Electrostatic protection structure and preparation method, electrostatic protection circuit

Abstract

The application provides an electrostatic protection structure and a preparation method and an electrostatic protection circuit. The electrostatic protection structure comprises a substrate, a well region with a second doping type formed on the substrate, a gate structure formed on the surface of the well region, and a drain region and a source region formed in the well region on both sides of the gate structure; the drain region comprises at least a first drift region with a first doping type, a first heavily doped region with the first doping type and a second heavily doped region with the second doping type which are formed in the first drift region; the source region comprises at least a second drift region with the first doping type and a third drift region with the second doping type which are arranged at intervals, a fourth heavily doped region with the first doping type formed on the second drift region, and a fourth heavily doped region with the second doping type formed on the third drift region. By forming a positive feedback loop in the electrostatic protection structure, the large ESD current is discharged.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor, and particularly relates to an electrostatic protection structure and a preparation method thereof, and an electrostatic protection circuit. BACKGROUND

[0002] ESD HVMOS device is an electrostatic discharge (ESD) protection device specially used for high voltage (HV) integrated circuit, and is widely applied in the fields of power management, display driving, automobile electronics, etc.

[0003] An ESD HVMOS device provided by the prior art is a gate-grounded NMOS (GGNMOS) device. Referring to FIG. 1, Figure 1 The ESD HVMOS device includes: a P-type substrate 10a, a P-type well region 11a formed on the P-type substrate 10a, a first N-type heavily doped region 12a located at a drain region, a second N-type heavily doped region 13a located at a source region, and a P-type heavily doped region 14a located at a base region in the P-type well region 11a; the first N-type heavily doped region 12a, the second N-type heavily doped region 13a, and the P-type heavily doped region 14a are separated by an isolation structure 15a; a first N-type drift region 121a, a second N-type drift region 131a, and a P-type drift region 141a are formed in the P-type well region 11a; a gate 16a is formed on a surface of the P-type well region 11a, and an oxide layer 161a is formed between the gate 16a and the P-type well region 11a; a contact layer 17a is formed on surfaces of the first N-type heavily doped region 12a, the second N-type heavily doped region 13a, the P-type heavily doped region 14a, and the gate 16a.

[0004] The principle of discharging ESD current by the ESD HVMOS device is as follows: when the ESD current flows into the first heavily doped region 12a and the first N-type drift region 121a through the anode, the PN junction formed by the first N-type drift region 121a and the P-type well region 11a is reversely broken down to form a large number of electron-hole pairs, and the generated holes flow into the P-type well region 11a to raise the potential of the P-type well region 11a. When the potential of the P-type well region 11a is higher than 0.7V, the PN junction formed by the second N-type heavily doped region 13a and the P-type well region 11a is forwardly conducted. Finally, the parasitic bipolar junction transistor (BJT) inside the ESD HVMOS device is conducted, that is, the NPN-type parasitic BJT formed between the first N-type heavily doped region 12a-first N-type drift region 121a / P-type heavily doped region 14a-P-type drift region 141a-P-type well region 11a / second N-type heavily doped region 13a-second N-type drift region 131a is conducted, thereby forming a low-resistance channel to discharge the ESD current.

[0005] However, the above-mentioned ESD HVMOS device can only discharge ESD current through the parasitic BJT turned on by the NPN, has a high trigger voltage (dependent on avalanche breakdown), and the current is relatively concentrated, the robustness of the device is poor, and can only discharge small ESD current, and cannot discharge large ESD current. SUMMARY

[0006] Therefore, one of the purposes of the present application is to provide an electrostatic protection structure and a preparation method, which aims to solve the technical problem that the ESD HVMOS device based on the GGNMOS structure in the related art cannot discharge large ESD current.

[0007] Another purpose of the present application is to provide an electrostatic protection circuit applying the above-mentioned electrostatic protection structure, which protects against static electricity through the above-mentioned electrostatic protection structure.

[0008] In a first aspect, the present application provides an electrostatic protection structure, comprising:

[0009] a substrate, a well region with a second doping type formed on the substrate, a gate structure formed on the surface of the well region, and a drain region and a source region formed in the well region on both sides of the gate structure;

[0010] The drain region at least includes a first drift region with a first doping type, a first heavily doped region with the first doping type and a second heavily doped region with the second doping type formed in the first drift region in a spaced manner.

[0011] The source region at least includes a second drift region with the first doping type and a third drift region with the second doping type arranged in a spaced manner, a third heavily doped region with the first doping type formed in the second drift region, and a fourth heavily doped region with the second doping type formed in the third drift region.

[0012] Optionally, one of the first doping type and the second doping type is N-type doping, and the other is P-type doping.

[0013] Optionally, the drain region further comprises:

[0014] a fifth heavily doped region with the first doping type, the fifth heavily doped region being in contact with the first drift region.

[0015] Optionally, the drain region further comprises a fourth drift region with the first doping type, the fourth drift region extending to below the gate structure and being in contact with the fifth heavily doped region.

[0016] Optionally, the depth of the fourth drift region is the same as the depth of the first drift region.

[0017] Optionally, the first drift region of the drain region is formed with a plurality of first isolation structures; the first isolation structures are formed between the first heavily doped region and the second heavily doped region, and between the second heavily doped region and the fifth heavily doped region.

[0018] Optionally, the first isolation structures have a depth lower than that of the first drift region, and the depth of the first isolation structures is greater than that of the first heavily doped region, the second heavily doped region, and the fifth heavily doped region, respectively.

[0019] In a second aspect, the present application provides a method for manufacturing an electrostatic protection structure, comprising:

[0020] providing a substrate;

[0021] forming a well region with a second doping type on the substrate;

[0022] forming an isolation structure on the well region, for isolating at least a first heavily doped region and a second heavily doped region in the well region of the drain region, and isolating a third heavily doped region and a fourth heavily doped region in the well region of the source region;

[0023] forming a plurality of drift regions in the well region by an ion implantation process, including at least a first drift region with a first doping type in the drain region, a second drift region with the first doping type in the source region, and a third drift region with the second doping type;

[0024] forming a gate structure on the well region between the first drift region and the second drift region;

[0025] forming the first to fourth heavily doped regions by an ion implantation process, the first heavily doped region and the third heavily doped region having the first doping type, and the second heavily doped region and the fourth heavily doped region having the second doping type.

[0026] Optionally, the method further comprises:

[0027] forming a fifth heavily doped region with the first doping type in the well region and the first drift region by an ion implantation process.

[0028] Optionally, the method further comprises:

[0029] forming a fourth drift region with the first doping type in the well region by an ion implantation process, the fourth drift region extending to below the gate structure;

[0030] forming a fifth heavily doped region with the first doping type in the fourth drift region, the well region, and the first drift region by an ion implantation process.

[0031] Optionally, the isolation structure of the drain region is a first isolation structure, a depth of the first isolation structure is lower than a depth of the first drift region, and the depth of the first isolation structure is greater than a depth of the first heavily doped region, a depth of the second heavily doped region, and a depth of the fifth heavily doped region, respectively.

[0032] Optionally, a depth of the fourth drift region is the same as a depth of the first drift region.

[0033] In a third aspect, the present application provides an electrostatic protection circuit formed by the electrostatic protection structure according to any one of the above or comprising the electrostatic protection structure prepared by the method according to any one of the above.

[0034] The technical scheme provided by the present application has the following unexpected technical effects:

[0035] The present application provides an electrostatic protection structure, a first drift region is formed at a source region of the electrostatic protection structure, a first heavily doped region and a second heavily doped region are formed at the first drift region. The unexpected technical effect is that the first heavily doped region, the first drift region, a well region, the second drift region, and a third heavily doped region form one of a first parasitic BJT triggered by NPN or a second parasitic BJT triggered by PNP, and a fourth heavily doped region, a third drift region, the well region, the first drift region, and the second heavily doped region form the other of the first parasitic BJT triggered by NPN or the second parasitic BJT triggered by PNP. The base of the first parasitic BJT triggered by NPN serves as the collector of the second parasitic BJT triggered by PNP, and the base of the second parasitic BJT triggered by PNP serves as the collector of the first parasitic BJT triggered by NPN. The collector current of the first parasitic BJT triggered by NPN directly drives the base of the second parasitic BJT triggered by PNP, and the collector current of the second parasitic BJT triggered by PNP drives the base of the first parasitic BJT triggered by NPN. Finally, a positive feedback loop is formed between the first parasitic BJT triggered by NPN and the second parasitic BJT triggered by PNP (the current amplification factor of the first parasitic BJT is , the current amplification factor of the second parasitic BJT is , and the current amplification factor of the positive feedback loop is ), the current amplification factor of the electrostatic protection structure is improved through the positive feedback loop, so that the electrostatic protection structure can discharge a large current.

[0036] The high current amplification factor can reduce the trigger voltage of the electrostatic protection structure, reduce the heat accumulation of the electrostatic protection structure, and further reduce the possibility of secondary breakdown of the electrostatic protection structure when discharging the ESD current. Moreover, the positive feedback loop can make the current uniformly distributed to the entire electrostatic protection structure, further avoiding local overheating of the electrostatic protection structure. At the same time, the positive feedback loop forces the current to be uniformly distributed in the electrostatic protection structure, improves the secondary breakdown voltage of the electrostatic protection structure ), so that the electrostatic protection structure can work in a higher voltage environment without secondary breakdown. Finally, the purpose of discharging the ESD current through the ESD HVMOS device based on the GGNMOS structure is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0038] Figure 1 A structure diagram of an ESD HVMOS device provided by the related art is shown.

[0039] Figure 2 A structure diagram of an electrostatic protection structure provided by an embodiment of the present application is shown.

[0040] Figure 3 A flowchart of a preparation method of an electrostatic protection structure provided by an embodiment of the present application is shown.

[0041] Figure 4 A structure diagram of an electrostatic protection structure in a preparation process provided by an embodiment of the present application is shown.

[0042] Figure 5 A structure diagram of an electrostatic protection structure in a preparation process provided by an embodiment of the present application is shown.

[0043] Figure 6 A structure diagram of an electrostatic protection structure in a preparation process provided by an embodiment of the present application is shown.

[0044] Figure 7 A structure diagram of an electrostatic protection structure in a preparation process provided by an embodiment of the present application is shown.

[0045] Figure 8 A structure diagram of an electrostatic protection structure in a preparation process provided by an embodiment of the present application is shown.

[0046] Figure 9A structural schematic diagram of the electrostatic protection structure provided by an embodiment of the present application in a preparation process is shown in FIG. 1.

[0047] Figure 10 A structural schematic diagram of the electrostatic protection structure provided by an embodiment of the present application in a preparation process is shown in FIG. 1.

[0048] Figure 11 A structural schematic diagram of the electrostatic protection structure provided by an embodiment of the present application in a preparation process is shown in FIG. 1.

[0049] Figure 12 A structural schematic diagram of the electrostatic protection structure provided by an embodiment of the present application in a preparation process is shown in FIG. 1.

[0050] Figure 13 A structural schematic diagram of the electrostatic protection structure provided by an embodiment of the present application in a preparation process is shown in FIG. 1.

[0051] Figure 14 A structural schematic diagram of the electrostatic protection structure provided by an embodiment of the present application in a preparation process is shown in FIG. 1.

[0052] Figure 15 A structural schematic diagram of the electrostatic protection structure provided by an embodiment of the present application in a preparation process is shown in FIG. 1.

[0053] The related art provides Figure 1 The reference signs of the drawings are as follows:

[0054] 10a: P-type substrate; 11a: P-type well region; 12a: first N-type heavily doped region; 121a: first N-type drift region; 13a: second N-type heavily doped region; 131a: second N-type drift region; 14a: P-type heavily doped region; 141a: P-type drift region; 15a: isolation structure; 16a: gate; 161a: oxide layer; 17a: contact layer.

[0055] The reference signs of the drawings are as follows: Figures 2 to 14 The reference signs of the drawings are as follows:

[0056] 10: substrate;

[0057] 21: well region; 22: drain region; 221: first drift region; 222: first heavily doped region; 223: second heavily doped region; 224: fifth heavily doped region; 225: fourth drift region; 226: first isolation structure; 23: source region; 231: second drift region; 232: third drift region; 233: third heavily doped region; 234: fourth heavily doped region; 235: second isolation structure;

[0058] 30: gate structure; 31: gate; 32: gate dielectric layer; 33: gate sidewall.

[0059] 40: ohmic contact layer. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0061] Related technologies provide ESD HVMOS devices based on GGNMOS structures that rely on the low-resistance discharge path formed by the parasitic BJT with NPN conduction to discharge ESD current, but the following problems exist:

[0062] In GGNMOS-based ESD HVMOS devices, the parasitic BJT with NPN conduction has a low current amplification factor (β value) (typically only 1~10). A low β value means that the avalanche injection current is insufficient to maintain large current conduction (i.e., insufficient to sustain large ESD current discharge), requiring a higher trigger voltage. and maintaining current This will further exacerbate the heat generation of the device.

[0063] The conduction of an NPN depends on avalanche breakdown (avalanche breakdown of the PN junction formed between the drain and well regions, or avalanche breakdown of the PN junction formed between the drift region connected to the drain and the well region), reaching [a certain value]. Previously, some of the ESD current had been dissipated within the device, exacerbating localized heating. A higher trigger voltage means higher power consumption, which will further exacerbate heat accumulation.

[0064] In a GGNMOS structure, the conduction of a parasitic BJT depends on avalanche breakdown (primary breakdown), but the secondary breakdown current of the parasitic BJT in a GGNMOS structure ( Generally small (in the mA to A range).

[0065] The base region of a parasitic BJT consists of a lightly doped P-type well with high resistivity (typically 10~100 Ω·cm). Under large ESD currents, the ohmic voltage drop in the base region is significant (due to the presence of base resistance, the base current ( The generation of an ohmic voltage drop in the base region leads to a weak base region conductivity modulation effect. In other words, the hole injection efficiency is low, making it difficult to conduct the entire device uniformly. The current is non-uniformly distributed and the local current density is high. The current will preferentially pass through low-resistance paths (such as the edge of the drain region), thus forming local hot spots.

[0066] The local density of current can cause Joule heating to make the temperature of the device rise, and the temperature rise can cause the intrinsic carrier concentration to exponentially increase. The increase of the intrinsic carrier concentration can further reduce the local resistivity, thereby causing the current to further concentrate, further causing the local current density to rise, and forming a thermal positive feedback. Ultimately, the thermal runaway of the device is caused, leading to the secondary breakdown of the device, and causing the device to be damaged.

[0067] According to the above analysis, it can be determined that the defects of the ESD HVMOS device based on the GGNMOS structure provided by the prior art are:

[0068] (1) The high trigger voltage caused by the low β value causes local overheating of the device.

[0069] (2) The thermal positive feedback formed by the non-uniform distribution of current, and the low secondary breakdown current of the device, which makes the device prone to secondary breakdown.

[0070] Figure 2 The structural diagram of the electrostatic protection structure provided by an embodiment of the present application is shown in Figure 2 , which comprises:

[0071] a substrate 10, a well region 21 with a second doping type formed on the substrate 10, a gate structure 30 formed on the surface of the well region 21, and a drain region 22 and a source region 23 formed in the well region 21 on both sides of the gate structure 30;

[0072] The drain region 22 at least comprises a first drift region 221 with a first doping type, a first heavily doped region 222 with the first doping type and a second heavily doped region 223 with the second doping type formed in the first drift region 221 in a spaced manner;

[0073] The source region 23 at least comprises a second drift region 231 with the first doping type and a third drift region 232 with the second doping type arranged in a spaced manner, a third heavily doped region 233 with the first doping type formed on the second drift region 231, and a fourth heavily doped region 234 with the second doping type formed on the third drift region 232.

[0074] It should be noted that when the electrostatic protection structure discharges the ESD current, the first heavily doped region 222 and the second heavily doped region 223 of the electrostatic protection structure are connected to the anode, and the third heavily doped region 233, the fourth heavily doped region 234, and the gate structure 30 of the electrostatic protection structure are connected to the cathode.

[0075] It should be noted that in the embodiment of the present application, the depths of all the drift regions are substantially the same, and are all greater than the heavily doped regions, the depths of all the heavily doped regions are substantially the same, and the depths of all the isolation structures are between the drift regions and the heavily doped regions.

[0076] In an example, the substrate 10 can be any one of a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, a silicon carbide (SiC) substrate, a silicon-on-sapphire (SOS) substrate, a gallium arsenide (GaAs) substrate, a gallium nitride (GaN) substrate, and a germanium (Ge) substrate.

[0077] For example, the substrate 10 can be a Si substrate.

[0078] In an example, the drain region 22 further includes:

[0079] a fifth heavily doped region 224 having the first doping type, the fifth heavily doped region 224 being in contact with the first drift region 221.

[0080] In the embodiment, the fifth heavily doped region 224 is further provided to connect the well region 21 and the first drift region 221, and since the doping concentration of the fifth heavily doped region 224 is higher than that of the first drift region 221, when the first heavily doped region 222 and the second heavily doped region 223 receive ESD current, the fifth heavily doped region 224 having a higher doping concentration is more likely to be avalanche breakdown (the higher the doping concentration, the lower the difficulty of avalanche breakdown) than the first drift region 221, thereby turning on the positive feedback loop formed by the NPN-type and PNP-type parasitic BJTs in the static protection structure.

[0081] In the embodiment, the fifth heavily doped region 224 is located between the gate structure 30 and the second heavily doped region 223.

[0082] In an example, the drain region 22 further includes:

[0083] a fourth drift region 225 having the first doping type, the fourth drift region 225 extending below the gate structure 30 and being in contact with the fifth heavily doped region 224, and the depth of the fourth drift region 225 being greater than that of the fifth heavily doped region 224.

[0084] In the embodiment, a fourth drift region 225 is additionally arranged between the fifth heavily doped region 224 and the gate structure 30. The fourth drift region 225 has a doping concentration higher than that of the well region 21, which can increase the flow path of the carriers, and the base region of the carrier movement is lengthened from the width of the original lateral first drift region 221 to the width of the lateral first drift region 221 and the depth of the fourth drift region 225, thereby facilitating further lifting of the secondary breakdown voltage of the electrostatic protection structure.

[0085] In an example, the depth of the fourth drift region 225 is the same as the depth of the first drift region 221.

[0086] In an example, a first isolation structure 226 is formed in the drain region 22, and the first isolation structure 226 is arranged between the first heavily doped region 222 and the second heavily doped region 223, and arranged between the second heavily doped region 223 and the fifth heavily doped region 224.

[0087] In an example, the depth of the first isolation structure 226 is lower than the depth of the first drift region 221, and the depth of the first isolation structure 226 is greater than the depth of the first heavily doped region 222, the depth of the second heavily doped region 223, and the depth of the fifth heavily doped region 224, respectively.

[0088] In an example, a second isolation structure 235 is formed in the source region 23, and the second isolation structure 235 is arranged between the third heavily doped region 233 and the fourth heavily doped region 234, and arranged between the third heavily doped region 233 and the gate structure 30.

[0089] As an example provided in the present application, the first isolation structure 226 and the second isolation structure 235 are shallow trench isolation (STI) structures.

[0090] In an example, one of the first doping type and the second doping type is N-type doping, and the other is P-type doping.

[0091] In an example, the N-type doping can be doping of a 5-valence element, and the P-type doping can be doping of a 3-valence element.

[0092] As an example, the N-type doping element can include phosphorus, arsenic, and the like.

[0093] As an example, the P-type doping element can include boron, indium, and the like.

[0094] As a first possible implementation manner provided in the present application, the first doping type is N-type doping, and the second doping type is P-type doping.

[0095] In a first possible implementation provided by the present application, the well region 21 is a P-type well region. In the drain region 22, the first drift region 221, the first heavily doped region 222, and the fifth heavily doped region 224 are N-type doped regions, and the second heavily doped region 223 is a P-type doped region. In the source region 23, the second drift region 231 and the third heavily doped region 233 are N-type doped regions, and the third drift region 232 and the fourth heavily doped region 234 are P-type doped regions.

[0096] In the first possible implementation provided by the present application, the first heavily doped region 222, the first drift region 221, the fifth heavily doped region 224, the well region 21, the second drift region 231, and the third heavily doped region 233 form a first parasitic BJT triggered by NPN. The fourth heavily doped region 234, the third drift region 232, the well region 21, the first drift region 221, and the second heavily doped region 223 form a second parasitic BJT triggered by PNP.

[0097] At this time, when the electrostatic protection structure encounters an ESD event, after avalanche breakdown occurs between the fifth heavily doped region 224 and the well region 21, a positive feedback loop formed by the first parasitic BJT triggered by NPN and the second parasitic BJT triggered by PNP is turned on, and ESD current flows from the fifth heavily doped region 224 after flowing from the anode to the first heavily doped region 222 and the first drift region 221, thereby discharging the ESD current from the cathode through a low-resistance discharge path formed by the positive feedback loop.

[0098] In the first possible implementation, the well region 21 is a high-voltage (HV) P-type well region, and the P-type doping concentration of the well region 21 is .

[0099] In the first possible implementation, the first drift region 221 is an N-type drift region, and the N-type doping concentration of the first drift region 221 is .

[0100] In the first possible implementation, the first heavily doped region 222 is an N+ type doped region, and the N-type doping concentration of the first heavily doped region 222 is .

[0101] In the first possible implementation, the second heavily doped region 223 is a P+ type doped region, and the P-type doping concentration of the second heavily doped region 223 is .

[0102] In the first possible implementation, the fifth heavily doped region 224 is an N+ type doped region, and the N-type doping concentration of the fifth heavily doped region 224 is .

[0103] In a first possible implementation, the fourth drift region 225 is an N-type drift region, and the N-type doping concentration of the fourth drift region 225 is .

[0104] In a first possible implementation, the second drift region 231 is an N-type drift region, and the N-type doping concentration of the second drift region 231 is .

[0105] In a first possible implementation, the third drift region 232 is a P-type drift region, and the P-type doping concentration of the third drift region 232 is .

[0106] In a first possible implementation, the third heavily doped region 233 is an N+ type doped region, and the N-type doping concentration of the third heavily doped region 233 is .

[0107] In a first possible implementation, the fourth heavily doped region 234 is a P+ type doped region, and the P-type doping concentration of the fourth heavily doped region 234 is .

[0108] In a second possible implementation provided in the present application, the first doping type is P-type doping, and the second doping type is N-type doping.

[0109] In the second possible implementation provided in the present application, the well region 21 is an N-type well region. In the drain region 22, the first drift region 221, the first heavily doped region 222, and the fifth heavily doped region 224 are P-type doped regions, and the second heavily doped region 223 is an N-type doped region. In the source region 23, the second drift region 231 and the third heavily doped region 233 are P-type doped regions, and the third drift region 232 and the fourth heavily doped region 234 are N-type doped regions.

[0110] In the second possible implementation provided in the present application, the first heavily doped region 222, the first drift region 221, the fifth heavily doped region 224, the well region 21, the second drift region 231, and the third heavily doped region 233 form a second parasitic BJT triggered by PNP. The fourth heavily doped region 234, the third drift region 232, the well region 21, the first drift region 221, and the second heavily doped region 223 form a first parasitic BJT triggered by NPN.

[0111] In the second possible implementation provided in the present application, the well region 21 is a High-Voltage Well N-type well region, and the N-type doping concentration of the well region 21 is .

[0112] In the second possible implementation provided in the present application, the first drift region 221 is a P-type drift region, and the P-type doping concentration of the first drift region 221 is .

[0113] In a second possible implementation provided by the present application, the first heavily doped region 222 is a P+ type doped region, and the P type doping concentration of the first heavily doped region 222 is .

[0114] In a second possible implementation provided by the present application, the second heavily doped region 223 is an N+ type doped region, and the N type doping concentration of the second heavily doped region 223 is .

[0115] In a second possible implementation provided by the present application, the fifth heavily doped region 224 is a P+ type doped region, and the P type doping concentration of the fifth heavily doped region is .

[0116] In a second possible implementation provided by the present application, the fourth drift region 225 is a P type drift region, and the P type doping concentration of the fourth drift region 225 is .

[0117] In a second possible implementation provided by the present application, the second drift region 231 is a P type drift region, and the P type doping concentration of the second drift region 231 is .

[0118] In a second possible implementation provided by the present application, the third drift region 232 is an N type drift region, and the N type doping concentration of the third drift region 232 is .

[0119] In a second possible implementation provided by the present application, the third heavily doped region 233 is a P+ type doped region, and the P type doping concentration of the third heavily doped region 233 is .

[0120] In a second possible implementation provided by the present application, the fourth heavily doped region 234 is an N+ type doped region, and the N type doping concentration of the fourth heavily doped region 234 is .

[0121] In an example provided by the present application, the gate structure 30 includes a gate 31, a gate dielectric layer 32, and a gate sidewall 33.

[0122] In an example, the material of the gate 31 can be polycrystalline silicon after ion implantation or a metal material, and the metal material includes TiN or W.

[0123] In an example, the material of the gate dielectric layer 32 includes any one of silicon dioxide (SiO2), silicon oxynitride (SiON), and a High-k material.

[0124] As an example, high-k materials include HfO2, HfSiO4, HfLaO, and the like.

[0125] In an example, the material of the gate side wall 33 includes Si3N4 or SiO2.

[0126] In an example, the first heavily doped region 222, the second heavily doped region 223 and the anode are connected through an ohmic contact layer 40, and the third heavily doped region 233, the fourth heavily doped region 234, the gate structure 30 and the cathode are connected through the ohmic contact layer 40.

[0127] In an example, the material of the ohmic contact layer 40 can be any one of Ti, TiN, Ni, and the like.

[0128] Figure 3 A flow chart of a method for manufacturing the electrostatic protection structure is provided for an embodiment of the present application. Referring to Figure 3 , the method comprises:

[0129] S101, providing a substrate.

[0130] The material of the substrate is described in the foregoing description of the electrostatic protection structure, which is not repeated here.

[0131] S102, forming a well region with a second doping type on the substrate.

[0132] In an example, the well region 21 can be formed by ion implantation on the substrate 10. If the well region 21 is a P-type well region, P-type doping elements are implanted. If the well region 21 is an N-type well region, N-type doping elements are implanted. The doping concentration range of the well region 21 is described in the foregoing description of the electrostatic protection structure, which is not repeated here.

[0133] Referring to Figure 4 , the well region 21 formed on the substrate 10 is shown.

[0134] S103, forming an isolation structure on the well region, for isolating at least the first heavily doped region and the second heavily doped region in the well region of the drain region, and isolating the third heavily doped region and the fourth heavily doped region in the well region of the source region.

[0135] In an example, the step S103 comprises:

[0136] A plurality of first isolation structures 226 are formed in the drain region, and a plurality of second isolation structures 235 are formed in the source region.

[0137] In an example, the isolation structure of the drain region 22 is a first isolation structure 226, the depth of the first isolation structure 226 is lower than the depth of the first drift region 221, and the depth of the first isolation structure 226 is greater than the depth of the first heavily doped region 222 (prepared in step S106), the depth of the second heavily doped region 223 (prepared in step S106), and the depth of the fifth heavily doped region 224 (prepared in step S106) respectively.

[0138] In an example, the first isolation structure 226 and the second isolation structure 235 are shallow trench isolation structures, which can be obtained by etching the well region 21 to form a shallow trench and filling the shallow trench with an insulating material. The insulating material can be silicon dioxide or the like.

[0139] Referring to Figure 5 , the first isolation structure 226 and the second isolation structure 235 prepared are shown.

[0140] S104, forming a plurality of spaced drift regions in the well region by an ion implantation process, at least including a first drift region with a first doping type located at the drain region and a second drift region with the first doping type located at the source region, and a third drift region with a second doping type.

[0141] In a first example provided in the present application, step S104 includes:

[0142] Firstly, forming a first drift region 221 with the first doping type at the drain region 22 and a second drift region 231 with the first doping type at the source region 23.

[0143] The first drift region 221 is located at the drain region 22, and the second drift region 231 is located at the source region 23.

[0144] Secondly, forming a third drift region 232 with the second doping type at the source region 23.

[0145] Referring to Figure 6 , the first drift region 221, the second drift region 231, and the third drift region 232 prepared are shown.

[0146] In a second example provided in the present application, a fourth drift region 225 is further prepared at the drain region 22, and step S104 includes:

[0147] Firstly, forming a first drift region 221, a fourth drift region 225, and a second drift region 231 with the first doping type at the drain region 22 and the source region 23 respectively.

[0148] The first drift region 221 and the fourth drift region 225 are located in the drain region 22, and the second drift region 231 is located in the source region 23.

[0149] In the second step, the third drift region 232 with the second doping type is formed in the source region 23.

[0150] Referring to Figure 7 The first drift region 221, the fourth drift region 225, the second drift region 231 and the third drift region 232 are shown in the second example.

[0151] In S105, the gate structure is formed on the well region between the first drift region and the second drift region.

[0152] In one example, S105 includes:

[0153] In the first step, the original gate dielectric layer and the gate material layer are sequentially formed on the surface of the well region.

[0154] In one example, the gate dielectric layer is a silicon dioxide layer, and the original gate dielectric layer can be formed by thermal oxidation.

[0155] In another example, the gate dielectric layer is a high-K dielectric layer, and the original gate dielectric layer can be formed by atomic layer deposition or physical vapor deposition.

[0156] In one example, the gate is a doped polysilicon, and the gate material layer is formed by chemical vapor deposition. The polysilicon can be doped with phosphorus or arsenic.

[0157] In another example, the gate is a metal gate, and the gate material layer is formed by physical vapor deposition or atomic layer deposition.

[0158] In the second step, the original gate dielectric layer and the gate material layer are etched by dry etching or wet etching to obtain the gate dielectric layer 32 and the gate 31.

[0159] The gate dielectric layer 32 is formed by etching the original gate dielectric layer, and the gate 31 is formed by etching the gate material layer.

[0160] In the third step, the side wall material layer is deposited.

[0161] As an example, the gate side wall is Si3N4 or SiO2, and the side wall material layer can be deposited by atomic layer deposition or plasma-enhanced chemical vapor deposition.

[0162] In the fourth step, the side wall material layer is etched by dry etching to form the gate side wall 33, and the gate structure 30 is obtained.

[0163] In Figure 6Based on the structure shown, the gate structure 30 prepared is described in detail below. Figure 8 .

[0164] exist Figure 7 Based on the structure shown, the gate structure 30 prepared is described in detail below. Figure 9 .

[0165] S106. First to fourth doped regions are formed by ion implantation process, wherein the first and third doped regions have a first doping type, and the second and fourth doped regions have a second doping type.

[0166] In the first example provided in this application, step S106 includes:

[0167] The first step is to prepare a first heavily doped region 222 and a third heavily doped region 233 with the first doping type in the drain region 22 and the source region 23, respectively.

[0168] The first doped region 222 is located in the drain region 22, and the third doped region 233 is located in the source region 23.

[0169] The second step involves preparing a second heavily doped region 223 and a fourth heavily doped region 234 with the second doping type in the drain region 22 and the source region 23, respectively.

[0170] The second doped region 223 is located in the drain region 22, and the fourth doped region 234 is located in the source region 23.

[0171] exist Figure 8 Based on the structure shown, the first to fourth doped regions prepared using the method in the first example provided in this application are described below. Figure 10 .

[0172] In the second example provided in this application, step S106 includes:

[0173] In the first step, a first heavily doped region 222, a third heavily doped region 233, and a fifth heavily doped region 224 with the first doping type are prepared in the drain region 22 and the source region 23, respectively.

[0174] Among them, the first doped region 222 and the fifth doped region 224 are located in the drain region 22, and the third doped region 233 is located in the source region 23.

[0175] The second step involves preparing a second heavily doped region 223 and a fourth heavily doped region 234 with the second doping type in the drain region 22 and the source region 23, respectively.

[0176] The second doped region 223 is located in the drain region 22, and the fourth doped region 234 is located in the source region 23.

[0177] In Figure 8 the structure shown in the first embodiment, the first to fifth heavily doped regions are prepared by the method provided in the second example of the present application. Figure 11 .

[0178] In Figure 9 the structure shown in the first embodiment, the first to fifth heavily doped regions are prepared by the method provided in the second example of the present application. Figure 12 .

[0179] After the gate structure 30 is prepared, an ohmic contact layer 40 is further prepared.

[0180] The ohmic contact layer 40 can be formed by forming a material layer through an atomic layer deposition or a magnetron sputtering process, and then etching the material layer through an etching process, and the remaining material layer forms the ohmic contact layer 40.

[0181] In Figure 10 the structure shown in the first embodiment, the ohmic contact layer 40 is further prepared, and the structure formed is shown in Figure 13 .

[0182] In Figure 11 the structure shown in the first embodiment, the ohmic contact layer 40 is further prepared, and the structure formed is shown in Figure 14 .

[0183] In Figure 12 the structure shown in the first embodiment, the ohmic contact layer 40 is further prepared, and the structure formed is shown in Figure 2 .

[0184] It should be noted that since the doping type, doping element, doping concentration, and material type of each region in the electrostatic protection structure have been described in the foregoing Figure 2 , they will not be described again in the preparation method shown in Figure 3 , and can be referred to the doping type, doping element, doping concentration, and material type in the foregoing Figure 2 .

[0185] Figure 15 The simulation result of the ESD HVMOS device provided in an embodiment of the present application is shown in the figure. Referring to Figure 15 , the devices in Figure 1 (the ESD HVMOS device provided by the related art) and Figure 2 (the electrostatic protection structure provided by the present application) are simulated by TCAD, and finally the transmission line pulse TCAD simulation result (TLP TCAD simulation result) shown in Figure 15 is obtained.

[0186] TCAD simulation is a semiconductor process and device simulation technology based on physical model, which is used to predict the electro-thermal behavior of a device in a transmission line pulse (TLP) test.

[0187] Analysis Figure 15 It can be known that, when the ESD HVMOS device provided by the present application and related technologies encounters an ESD event, as the drain voltage increases, the ESD HVMOS device provided by the related technology opens the parasitic NPN through avalanche breakdown, and the electrostatic protection structure provided by the present application opens the parasitic NPN and parasitic PNP, and then the drain voltage starts to drop. Subsequently, the electrostatic protection structure provided by the present application and the parasitic NPN in the ESD HVMOS device provided by the related technology start to discharge ESD current, and the device enters a maintenance state.

[0188] When the drain current of the ESD HVMOS device provided by the related technology rises to 7.90E-03 A / μm (i.e. A / μm), the ESD HVMOS device fails, and the electrostatic protection structure provided by the present application fails when the drain current rises to 0.90E-03 A / μm. That is, the failure current (also the secondary breakdown current ) of the ESD HVMOS device provided by the related technology is 7.90E-03 A / μm, and the failure current of the ESD HVMOS device provided by the present application is 0.90E-03 A / μm (i.e. A / μm). The failure current of the electrostatic protection structure provided by the present application is about 20% higher than that of the ESD HVMOS device provided by the related technology, and the robustness of the electrostatic protection structure is improved.

[0189] It should be noted that the electrostatic protection structure provided by the present application is based on the ESD HVMOS device of the GGNMOS structure.

[0190] Finally, it should be noted that the technical solutions provided by the present application have the following unexpected technical effects:

[0191] The application provides an electrostatic protection structure, a first drift region is formed in a source region of the electrostatic protection structure, a first heavily doped region and a second heavily doped region are formed in the first drift region. Unexpected technical effects are as follows: the first heavily doped region, the first drift region, a well region, the second drift region and a third heavily doped region form one of a first parasitic BJT triggered by NPN or a second parasitic BJT triggered by PNP, a fourth heavily doped region, a third drift region, the well region, the first drift region and the second heavily doped region form the other of the first parasitic BJT triggered by NPN or the second parasitic BJT triggered by PNP. The base of the first parasitic BJT triggered by NPN serves as the collector of the second parasitic BJT triggered by PNP, and the base of the second parasitic BJT triggered by PNP serves as the collector of the first parasitic BJT triggered by NPN. The collector current of the first parasitic BJT triggered by NPN directly drives the base of the second parasitic BJT triggered by PNP, and the collector current of the second parasitic BJT triggered by PNP drives the base of the first parasitic BJT triggered by NPN. Finally, a positive feedback loop is formed between the first parasitic BJT triggered by NPN and the second parasitic BJT triggered by PNP (the current amplification factor of the first parasitic BJT is , the current amplification factor of the second parasitic BJT is , and the current amplification factor of the positive feedback loop is ), the current amplification factor of the electrostatic protection structure is improved through the positive feedback loop, so that the electrostatic protection structure can discharge a large ESD current.

[0192] The high current amplification factor can reduce the trigger voltage of the electrostatic protection structure, reduce the heat accumulation of the electrostatic protection structure, and further reduce the possibility of secondary breakdown of the electrostatic protection structure when discharging a large ESD current. Moreover, the positive feedback loop can make the current uniformly distributed to the entire electrostatic protection structure, further avoiding local overheating of the electrostatic protection structure. At the same time, the positive feedback loop forces the current to be uniformly distributed in the electrostatic protection structure, improves the secondary breakdown voltage of the electrostatic protection structure (V ), so that the electrostatic protection structure can work in a higher voltage environment without secondary breakdown. Finally, the purpose of discharging a large ESD current through the ESD HVMOS device based on the GGNMOS structure is achieved.

[0193] A fifth heavily doped region is further provided, the fifth heavily doped region connects the well region and the first drift region, and since the doping concentration of the fifth heavily doped region is higher than that of the first drift region, when the first heavily doped region and the second heavily doped region receive an ESD current, the second heavily doped region with higher doping concentration is more prone to avalanche breakdown (the higher the doping concentration, the lower the difficulty of avalanche breakdown) than the first drift region, thereby turning on the positive feedback loop formed by the NPN-type and PNP-type parasitic BJTs in the electrostatic protection structure.

[0194] The fourth drift region is additionally arranged between the fifth doped region and the gate structure, and the fourth drift region has a higher doping concentration than the well region, which can increase the flow path of the carriers, and the base region of the carrier movement has the width of the original lateral first drift region, which is lengthened to the width of the lateral first drift region + the depth of the fourth drift region, thereby facilitating further lifting of the secondary breakdown voltage of the electrostatic protection structure.

[0195] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An electrostatic protection structure, characterized by, The application relates to a substrate, a well region with a second doping type formed on the substrate, a gate structure formed on the surface of the well region, and a drain region and a source region formed in the well region on both sides of the gate structure. The drain region comprises at least a first drift region with a first doping type, a first heavily doped region with the first doping type and a second heavily doped region with the second doping type which are formed in the first drift region. The source region comprises at least a second drift region with the first doping type and a third drift region with the second doping type which are arranged in intervals, a third heavily doped region with the first doping type formed in the second drift region, and a fourth heavily doped region with the second doping type formed in the third drift region. The drain region further comprises a fifth heavily doped region with the first doping type and a fourth drift region with the first doping type, the fifth heavily doped region is in contact with the first drift region, and the fourth drift region extends to below the gate structure and is in contact with the fifth heavily doped region. One of the first doping type and the second doping type is N-type doping, and the other is P-type doping.

2. The electrostatic protection structure of claim 1, wherein The first drift region of the drain region is formed with a plurality of first isolation structures, the first isolation structures are formed between the first heavily doped region and the second heavily doped region, and between the second heavily doped region and the fifth heavily doped region.

3. The electrostatic protection structure of claim 1, wherein, The depth of the first isolation structure is lower than the depth of the first drift region, and the depth of the first isolation structure is greater than the depth of the first heavily doped region, the depth of the second heavily doped region and the depth of the fifth heavily doped region respectively.

4. The electrostatic protection structure of claim 3, wherein, The application relates to a substrate, a well region with a second doping type formed on the substrate, a gate structure formed on the surface of the well region, and a drain region and a source region formed in the well region on both sides of the gate structure.

5. A method of producing an electrostatic protection structure, characterized by, The application relates to a substrate, a well region with a second doping type formed on the substrate, a gate structure formed on the surface of the well region, and a drain region and a source region formed in the well region on both sides of the gate structure. The application relates to a substrate, a well region with a second doping type formed on the substrate, a gate structure formed on the surface of the well region, and a drain region and a source region formed in the well region on both sides of the gate structure. The application relates to a substrate, a well region with a second doping type formed on the substrate, a gate structure formed on the surface of the well region, and a drain region and a source region formed in the well region on both sides of the gate structure. The first drift region and the second drift region are formed with a plurality of first isolation structures, the first isolation structures are formed between the first heavily doped region and the second heavily doped region, and between the second heavily doped region and the fifth heavily doped region. The depth of the first isolation structure is lower than the depth of the first drift region, and the depth of the first isolation structure is greater than the depth of the first heavily doped region, the depth of the second heavily doped region and the depth of the fifth heavily doped region respectively. ​ ​ 6. The method of claim 5, wherein the method further comprises: ​ 7. An electrostatic protection circuit, characterized by comprising: An electrostatic protection structure formed using any one of the electrostatic protection structures as claimed in claims 1 to 4, or an electrostatic protection structure prepared using the preparation method of the electrostatic protection structure as claimed in claim 5 or 6.

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