Packaging structure and forming method thereof

Abstract

The invention discloses a packaging structure and a forming method thereof. The packaging structure comprises a substrate, a semiconductor element, a wrapping layer, a cover layer and an electric connection structure. The semiconductor element is arranged on the substrate. The wrapping layer is arranged on the substrate, wraps the semiconductor element and exposes the top surface of the semiconductor element. The cap layer is disposed on the encapsulation layer and the semiconductor element, and includes a first portion and a second portion. The first portion covers and contacts a top surface of the semiconductor element. The second part covers and contacts the wrapping layer, and the ratio of the maximum intensity of the second part at a wave number of 1060 cm <-1 > to a wave number of 1080 cm <-1 > to the maximum intensity of the second part at a wave number of 780 cm <-1 > to a wave number of 800 cm <-1 > is greater than 0.65 in the measurement result of Fourier transform infrared spectroscopy. The electric connection structure is arranged on the substrate and penetrates through the substrate and the wrapping layer to be electrically connected with the semiconductor element.

Description

TECHNICAL FIELD

[0001] The present application relates to semiconductor technology, and particularly, to a packaging structure and a method of forming the same. BACKGROUND

[0002] As the size of semiconductor elements is scaled down, the number of semiconductor elements in a packaging structure is dramatically increased, which is a severe challenge to the manufacturing process. Among others, a mass transfer fabrication process can be used to transfer the semiconductor elements from a growth substrate to a carrier substrate, or from the carrier substrate to a circuit board, so as to facilitate the processing of the semiconductor elements. However, while existing packaging structures and methods of forming the same have generally met their established goals, they have not been without their drawbacks. Thus, there remains a need in the art for a packaging structure and a method of forming the same. SUMMARY

[0003] In some embodiments, a packaging structure is provided. The packaging structure includes a substrate, a semiconductor element, a cladding layer, a cap layer, and an electrical connection structure. The substrate has a first side and a second side opposite to each other. The semiconductor element is disposed on the first side of the substrate. The cladding layer is disposed on the first side of the substrate, and the cladding layer covers the semiconductor element and exposes a top surface of the semiconductor element. The cap layer is disposed on the cladding layer and the semiconductor element, and includes a first portion and a second portion. The first portion covers and contacts the top surface of the semiconductor element. The second portion covers and contacts the cladding layer, wherein a ratio between a maximum intensity of the second portion at a wave number of 1060 cm -1 to a wave number of 1080 cm -1 and a maximum intensity of the second portion at a wave number of 780 cm -1 to a wave number of 800 cm -1 is greater than 0.65. The electrical connection structure is disposed on the second side of the substrate, and passes through the substrate and the cladding layer to electrically connect with the semiconductor element.

[0004] In some embodiments, a method of forming a packaging structure is provided. The method of forming the packaging structure includes providing a cap layer, disposing a semiconductor element on the cap layer, wherein a top surface of the semiconductor element covers a portion of the cap layer, performing a surface treatment fabrication process on the semiconductor element and a portion of the cap layer not covered by the semiconductor element, disposing a cladding layer on the semiconductor element and the cap layer, disposing a connection portion in the cladding layer, wherein the connection portion is electrically connected with the semiconductor element, disposing a substrate on the cladding layer, and disposing a bonding pad on the substrate, wherein the bonding pad is electrically connected with the connection portion.

[0005] The package structure and the forming method thereof of the present application can be applied to various types of electronic devices. In order to make the features and advantages of the present application more apparent, various embodiments are described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0006] The concept of the embodiments of the present application can be better understood by the following detailed description with reference to the accompanying drawings. It is to be noted that some features can not be drawn to scale according to the standard practice in the industry. In fact, the sizes of different features can be increased or decreased in order to make the description clear.

[0007] Figures 1 to 3 are cross-sectional views showing the package structure at different stages in the forming method, respectively, of some embodiments of the present application;

[0008] Figure 4 are schematic diagrams showing the measurement results of Fourier-transform infrared spectroscopy (FTIR) of different portions of the cap layer, respectively, of some embodiments of the present application;

[0009] Figures 5 to 10 are cross-sectional views showing the package structure at different stages in the forming method, respectively, of some embodiments of the present application.

[0010] SYMBOL EXPLANATION

[0011] 1: package structure

[0012] 10: carrier plate

[0013] 11: adhesive layer

[0014] 12: cap layer

[0015] 121: first portion

[0016] 122: second portion

[0017] 123: third portion

[0018] 13: semiconductor element

[0019] 131: semiconductor stack

[0020] 132: electrode

[0021] 13A: top surface

[0022] 14: carrier plate

[0023] 15: adhesive layer

[0024] 15': adhesive layer

[0025] 16: Encapsulation layer

[0026] 17: Connecting part

[0027] 18: Base

[0028] 19: Joining pad

[0029] STP: Surface treatment process Detailed Implementation

[0030] The following disclosure provides numerous different embodiments or examples for implementing the provided apparatus. Specific examples of the components and their configurations are described below to simplify the embodiments of the invention and are not intended to limit the invention. For example, if the description refers to a first component being formed on a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, so that the first and second components are not in direct contact. Furthermore, the invention may repeat element symbols and / or characters in different embodiments or examples. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or examples discussed.

[0031] In some embodiments of the present invention, terms relating to setting or connection, such as "setting," "connection," and similar terms, may refer to two components in direct contact, or to two components not in direct contact, wherein an additional connecting component is located between the two structures, unless otherwise defined. Terms relating to setting or connection may also include cases where both structures are movable or both structures are fixed.

[0032] Furthermore, the terms "first," "second," and similar terms used in this specification or claims are used to name different components or to distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of components, nor to limit the manufacturing order or installation order of the components.

[0033] In this document, the terms "approximately," "about," "substantially" and variations thereof, generally mean within 10% of a given value or range, or within 5% of a given value or range, or within 3% of a given value or range, or within 2% of a given value or range, or within 1% of a given value or range, or within 0.5% of a given value or range. Given a quantity, the term "about" the quantity means that the quantity can also be "about" the quantity. The term "between a first value and a second value" means that the range includes the first value, the second value, and other values therebetween. Also, any two values or directions compared against each other can have some error. If a first value is equal to a second value, it is implied that the first value and the second value can have an error of about 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% therebetween. If a first direction is perpendicular to a second direction, the angle between the first direction and the second direction can be between 80 degrees and 100 degrees. If a first direction is parallel to a second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly idealized or formal sense unless expressly so defined herein.

[0035] It is understood that portions of the devices have been omitted from the figures for clarity and only some of the components of the devices are shown schematically. In some embodiments, additional components can be added to the devices described below. In other embodiments, some of the components of the devices described below can be replaced or omitted. It is understood that in some embodiments, additional operational steps can be provided before, during, and / or after the methods described below. In some embodiments, some of the operational steps described can be replaced or omitted, and the order of some of the operational steps described can be altered.

[0036] The present application can omit a moliding step, a flipping step, and a de-gluing step after the element transfer by reserving a catch material as a carrier in a transfer fabrication process. In this way, the package structure of the present application can greatly simplify the fabrication process, having the advantages of fewer forming steps and lower cost.

[0037] Reference is made to Figures 1 to 3 and Figures 5 to 10These are cross-sectional views showing different stages of the packaging structure formation method according to some embodiments of the present invention. To simplify the drawings, some figures only depict a single packaging structure 1 for clarity. In other embodiments, there may be multiple packaging structures 1. For example, there may be two, three, four, or more packaging structures 1, arranged in a matrix.

[0038] like Figure 1 As shown, a carrier plate 10 is provided for carrying components (e.g., semiconductor components 13) located thereon. In some embodiments, the carrier plate 10 may comprise a conductive material or a non-conductive material. For example, conductive materials may include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium phosphide (GaP), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), other suitable materials or combinations thereof, but the invention is not limited thereto; non-conductive materials may include glass, quartz, sapphire, diamond (C), ceramics, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials or combinations thereof, but the invention is not limited thereto.

[0039] like Figure 1 As shown, following the steps described above, an adhesive layer 11 is provided on the carrier plate 10, which is used to bond the carrier plate 10 to the supporting material (hereinafter referred to as "cover layer 12"). In some embodiments, the adhesive layer 11 may be a release film, such as thermal release, UV release, a combination thereof, or other suitable materials, but the invention is not limited thereto. By providing an adhesive layer 11 that can be decomposed by heat or light, the carrier plate 10, which serves as a temporary substrate, can be effectively removed in subsequent manufacturing processes.

[0040] like Figure 1As shown, after the above steps, a cover layer 12 is provided on the adhesive layer 11, which is used as a carrier in the transfer fabrication process. In some embodiments, the material of the cover layer 12 includes a high molecular silicon compound. For example, the high molecular silicon compound can include polydimethylsiloxane (PDMS), other suitable high molecular silicon compounds, or combinations thereof, but the present application is not limited thereto. In some embodiments, the material of the cover layer 12 can be selected according to requirements so that the cover layer 12 has a specific Young's modulus, viscosity, mechanical strength, chemical resistance, etc. For example, the cover layer 12 can be made to have a hardness or chemical resistance that can withstand subsequent photolithography and / or etching fabrication processes. Alternatively, the cover layer 12 can also be made to have a specific light transmittance so that light emitted by the semiconductor element 13, such as a micro light-emitted diode (μLED), can pass through. For example, the cover layer 12 can have a light transmittance greater than or equal to 95% in the visible light wavelength range. For example, the light transmittance of the cover layer 12 in the visible light wavelength range can be 95%, 96%, 97%, 98%, 99%, or any range of the above values.

[0041] In some embodiments, the cover layer 12 can be formed on the adhesive layer 11 by the following steps. First, a solution including a receiving material can be disposed on the adhesive layer 11. The solution can include a receiving material (e.g., dimethylsiloxane), a solvent, a dispersant, other suitable materials, or combinations thereof, but the present application is not limited thereto. Next, the solution can be uniformly distributed on the adhesive layer 11 by spinning. In some embodiments, the solution can be additionally heated to pre-cure the solution, but the present application is not limited thereto. Finally, the solution can be cured to form a fully cured or partially cured cover layer 12. The hardness of the cover layer 12 can be controlled by adjusting the curing conditions, such as adjusting the baking temperature, but the present application is not limited thereto. In this way, the cover layer 12 as described above can be obtained. It is worth mentioning that although the possible setting method of the cover layer 12 has been provided above, the present application is not limited thereto. In other embodiments, different setting methods or different formation sequences can be used to form the cover layer 12.

[0042] As shown, after the above steps, a cover layer 12 is provided on the adhesive layer 11, which is used as a carrier in the transfer fabrication process. In some embodiments, the material of the cover layer 12 includes a high molecular silicon compound. For example, the high molecular silicon compound can include polydimethylsiloxane (PDMS), other suitable high molecular silicon compounds, or combinations thereof, but the present application is not limited thereto. In some embodiments, the material of the cover layer 12 can be selected according to requirements so that the cover layer 12 has a specific Young's modulus, viscosity, mechanical strength, chemical resistance, etc. For example, the cover layer 12 can be made to have a hardness or chemical resistance that can withstand subsequent photolithography and / or etching fabrication processes. Alternatively, the cover layer 12 can also be made to have a specific light transmittance so that light emitted by the semiconductor element 13, such as a micro light-emitted diode (μLED), can pass through. For example, the cover layer 12 can have a light transmittance greater than or equal to 95% in the visible light wavelength range. For example, the light transmittance of the cover layer 12 in the visible light wavelength range can be 95%, 96%, 97%, 98%, 99%, or any range of the above values. Figure 1As shown, after the above step, the semiconductor element 13 is disposed on the cap layer 12, wherein a top surface 13A of the semiconductor element 13 faces the cap layer 12. In some embodiments, the semiconductor element 13 can include a light-emitting diode, a laser diode, a photodiode, a photodetector, an integrated circuit (IC), other suitable semiconductor elements, or a combination thereof, but the present disclosure is not limited thereto.

[0043] In some embodiments, the semiconductor element 13 can include a semiconductor stack 131 and a plurality of electrodes 132. In some embodiments in which the semiconductor element 13 is a micro light-emitting diode, the semiconductor stack 131 can include a first semiconductor layer, a light-emitting layer, and a second semiconductor layer, which are sequentially stacked. In some embodiments, the first semiconductor layer, the light-emitting layer, and the second semiconductor layer can be formed by an epitaxial growth process, but the present disclosure is not limited thereto. In some embodiments, the first semiconductor layer can be a P-type semiconductor layer, and the second semiconductor layer can be an N-type semiconductor layer. In other embodiments, the conductive types of the first semiconductor layer and the second semiconductor layer can be interchanged.

[0044] In some embodiments, the semiconductor stack 131 can include a II-VI material or a III-V material. For example, the II-VI material can include zinc selenide (ZnSe). For example, the III-V material can include gallium nitride (GaN), aluminum nitride (AIN), indium phosphide (InP), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), aluminum indium gallium nitride (AlInGaN), aluminum indium gallium phosphide (AlInGaP), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the light-emitting layer can include a quantum well (QW) or a multiple quantum well (MQW). In some embodiments, the P-type semiconductor layer can include a dopant, and the dopant such as magnesium (Mg) or carbon (C), but the present disclosure is not limited thereto. In some embodiments, the N-type semiconductor layer can include a dopant, and the dopant such as silicon (Si) or germanium (Ge), but the present disclosure is not limited thereto.

[0045] In some embodiments, the electrode 132 is disposed on a side of the semiconductor stack 131 opposite the top surface 13A. In some embodiments, the electrode 132 can include a first electrode and a second electrode, and the first electrode and the second electrode can be electrically connected with the semiconductor stack 131. The first electrode can be electrically connected with the first semiconductor layer, and the second electrode can be electrically connected with the second semiconductor layer. In some embodiments, the first electrode and the second electrode can include a conductive material. For example, the conductive material can include a metal, a conductive compound, other suitable conductive material, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the metal can be tin (Sn), copper (Cu), gold (Au), silver (Ag), nickel (Ni), indium (In), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), molybdenum (Mo), titanium (Ti), magnesium (Mg), zinc (Zn), an alloy thereof, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the conductive compound can include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), titanium nitride (TiN), other suitable conductive compound, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the first electrode and the second electrode can be formed by electroplating, chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, atomic layer deposition (ALD), other suitable manufacturing process, or a combination thereof, but the disclosure is not limited thereto.

[0046] As Figure 1As shown, in some embodiments, the step of placing the semiconductor element 13 on the capping layer 12 further includes: providing a carrier plate 14; placing an adhesive layer 15 on the carrier plate 14; forming (or placing) the semiconductor element 13 on the adhesive layer 15; and reducing the adhesion of the adhesive layer 15 to allow the semiconductor element 13 and a portion of the adhesive layer 15 to detach from the carrier plate 14 and transfer to the capping layer 12. The adhesive layer 15 can be weakened by heating, ultraviolet light irradiation, laser dissociation, other suitable methods, or combinations thereof; however, the invention is not limited thereto. Alternatively, the semiconductor element 13 can also be transferred to the capping layer 12 by a pick-up fabrication process. In some embodiments, the carrier plate 14 may comprise a conductive or non-conductive material. For example, conductive materials may include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium phosphide (GaP), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), other suitable materials or combinations thereof, but the invention is not limited thereto; non-conductive materials may include glass, quartz, sapphire, diamond (C), ceramics, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials or combinations thereof, but the invention is not limited thereto. In some embodiments, as shown in the figure... Figure 1 As shown, a single semiconductor element 13 is transferred at a time, but the invention is not limited thereto. In other embodiments, multiple semiconductor elements 13 may be transferred at a time, such as three, four, five or more semiconductor elements 13. In some embodiments, the adhesive layer 15 may be a release film, such as thermal release, UV release, laser release, a combination thereof or other suitable materials, but the invention is not limited thereto.

[0047] like Figure 2 As shown, in some embodiments where the semiconductor element 13 is a miniature light-emitting diode, three semiconductor elements 13 can be disposed onto the capping layer 12 by means such as laser dissociation. That is, each subsequently formed package structure 1 may include three semiconductor elements 13. It is worth mentioning that, Figure 2 The number of semiconductor elements 13 shown is merely an example, and the invention is not limited thereto. In other embodiments, each package structure 1 may include more than or less three semiconductor elements 13, such as one, two, four, or more than four.

[0048] In some embodiments, the three semiconductor elements 13 may respectively include a green LED chip, a red LED chip and a blue LED chip, wherein the green LED chip can emit green visible light with a wavelength between 510nm and 570nm, the red LED chip can emit red visible light with a wavelength between 610nm and 750nm, and the blue LED chip can emit blue visible light with a wavelength between 440nm and 470nm, but the present invention is not limited thereto.

[0049] In some embodiments, different color conversion layers can be disposed on multiple LED chips of the same type (e.g., the same color) to convert single-color light into different colors of light, thereby achieving the same effect as described above. For example, each of the three semiconductor elements 13 may include the same ultraviolet LED chip and respectively include a green conversion layer, a red conversion layer, and a blue conversion layer disposed on the ultraviolet LED chip. Alternatively, the present invention may also use blue LED chips or LED chips of other colors (wavelengths) as needed, and is not limited to the ultraviolet LED chips described above. By using the same LED chip, the types of LED chips can be simplified. In some embodiments, each color conversion layer may include materials such as phosphors and quantum dots to convert the single-color light emitted by each LED chip into light of a specific color. For example, when used with an ultraviolet LED chip, the red conversion layer or the green conversion layer may include CdSe, so that ultraviolet light can be converted into red visible light or green visible light. For example, when used with an ultraviolet LED chip, the blue conversion layer may include CdS / ZnS, so that ultraviolet light can be converted into blue visible light. The materials and combinations thereof described above are merely examples, and the present invention is not limited thereto.

[0050] like Figure 2 As shown, an adhesive layer 15' may remain on the semiconductor element 13 fabricated using a process such as laser dissociation, and the adhesive layer 15' covers the electrodes 132 of the semiconductor element 13. Figure 3 As shown, a surface treatment fabrication process (STP) can be performed to remove the adhesive layer 15' on the semiconductor element 13. After undergoing the STP, the remaining adhesive layer 15' is removed from the semiconductor element 13, thereby exposing the electrodes 132 of the semiconductor element 13. In some embodiments, the STP may include inductively coupled plasma clean (ICPclean), other suitable fabrication processes, or combinations thereof, but the invention is not limited thereto.

[0051] It is worth mentioning that surface treatment processes such as inductively coupled plasma (STP) cleaning, in addition to removing the adhesive layer 15', can also modify the capping layer 12. Specifically, the capping layer 12 can be divided into multiple parts, for example... Figure 3 The diagram shows a first portion 121, a second portion 122, and a third portion 123. In some embodiments, the first portion 121 and the second portion 122 are located on the side of the capping layer 12 adjacent to the semiconductor element 13, while the third portion 123 is located on the side of the capping layer 12 away from the semiconductor element 13. Specifically, the first portion 121 and the second portion 122 are arranged side by side on the third portion 123, with the first portion 121 located between the semiconductor element 13 and the third portion 123, and the third portion 123 located between the first portion 121 and the carrier plate 10, and between the second portion 122 and the carrier plate 10. The semiconductor element 13 covers and contacts the first portion 121 of the capping layer 12, exposing the second portion 122 of the capping layer 12. After undergoing a surface treatment fabrication process (STP), the second portion 122 of the capping layer 12 that is not covered by the semiconductor element 13 is modified. On the other hand, the first portion 121 of the capping layer 12 is not modified because it is covered by the semiconductor element 13. Similarly, the portion of the capping layer 12 that is far from the semiconductor element 13 (i.e., the third portion 123) is not modified.

[0052] In some embodiments, the thickness of the first portion 121 and the second portion 122 in the vertical direction (i.e., the normal direction of the carrier 10) may be between 0.5 μm and 2.5 μm. For example, the thickness of the first portion 121 and the second portion 122 in the vertical direction may be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, or any value or range between these values, but the invention is not limited thereto. In some embodiments, the thickness of the third portion 123 in the vertical direction may be between 5 μm and 150 μm. For example, the thickness of the third portion 123 in the vertical direction may be 5 μm, 10 μm, 15 μm, 40 μm, 60 μm, 80 μm, 100 μm, 125 μm, 150 μm, or any value or range between these values, but the invention is not limited thereto.

[0053] Refer to together Figure 4 This is based on some embodiments of the present invention, showing the measurement results of Fourier transform infrared spectra of different portions of the capping layer 12. For example... Figure 4 As shown, after undergoing a surface treatment fabrication process such as inductively coupled plasma cleaning (STP), the material structure of the capping layer 12 changes due to partial modification. Specifically, after performing the STP surface treatment fabrication process, the characteristic peaks of the network structure SiO2 in the modified portion of the capping layer 12 that underwent the STP surface treatment fabrication process (e.g., the second portion 122) (located at wavenumber 1070 cm⁻¹) change.-1 The portion of the capping layer 12 that has not undergone surface treatment process STP and has not been modified (e.g., the first portion 121 and the third portion 123) becomes more prominent, representing an increase in the proportion of SiO2 with a network structure. This makes the surface of the capping layer 12 (e.g., the modified second portion 122) denser, thereby improving its resistance to peeling.

[0054] In some embodiments, in the Fourier transform infrared spectroscopy measurement results, the second part 122 is at a wavenumber of 1060 cm⁻¹. -1 Up to wavenumber 1080cm -1 The maximum intensity of the characteristic peak (representing the network structure of SiO2) is similar to that of the second part 122 at wavenumber 780 cm⁻¹. -1 Up to wave number 800cm -1 The ratio between the maximum intensities (representing the characteristic peaks of Si-CH3) is greater than 0.65. For example, the ratio between the maximum intensities can be 0.65, 0.675, 0.7, 0.725, 0.75, 0.775, 0.8, 0.825, 0.85, any value or range between these values, but the invention is not limited thereto. Conversely, in some embodiments, in the Fourier transform infrared spectroscopy measurement results, the first portion 121 or the third portion 123 at a wavenumber of 1060 cm⁻¹... -1 Up to wavenumber 1080cm -1 The maximum intensity of the characteristic peaks (representing the network structure of SiO2) is similar to that of the first part 121 or the third part 123 at wavenumber 780 cm⁻¹. -1 Up to wave number 800cm -1 The ratio between the maximum intensities (representing the characteristic peaks of Si-CH3) is less than 0.65. For example, the ratio between the maximum intensities can be 0.65, 0.625, 0.6, 0.575, 0.55, 0.525, 0.5, 0.475, 0.45, any value or range between the above values, but the present invention is not limited thereto.

[0055] like Figure 5 As shown, a wrapping layer 16 may be disposed on the semiconductor element 13 and the capping layer 12. Specifically, the wrapping layer 16 covers and contacts the semiconductor element 13 and the second portion 122 of the capping layer 12. In some embodiments, the wrapping layer 16 may be or may include epoxy resin, polyimide (PI), polybenzoxazole (PBO), silicone resin, silicon dioxide, silicon nitride, or a combination thereof, but the invention is not limited thereto.

[0056] In some embodiments, the encapsulation layer 16 covers the side surfaces of the semiconductor element 13 and the electrodes 132, but does not contact the top surface 13A of the semiconductor element 13. In some embodiments where the top surface 13A of the semiconductor element 13 is used to emit light, in order to concentrate the light emitted by the light-emitting layer of the semiconductor element 13 toward the top surface 13A and to avoid crosstalk between the light emitted by adjacent semiconductor elements 13, the transmittance of the encapsulation layer 16 in the visible light wavelength range may be less than 5%. For example, the transmittance of the encapsulation layer 16 in the visible light wavelength range may be 5%, 4%, 3%, 2%, 1%, or any range of the above values. In some embodiments, the transmittance of the encapsulation layer 16 may be adjusted by including a material with a light reflectance greater than 90%. For example, the transmittance of the encapsulation layer 16 may be less than 5% by adding black dispersed particles such as carbon black to the encapsulation layer 16, thereby making the encapsulation layer 16 appear black.

[0057] like Figure 6 As shown, a connection portion 17 is provided on the encapsulation layer 16, wherein the connection portion 17 extends through the encapsulation layer 16 and is electrically connected to the electrode 132 of the semiconductor element 13. Specifically, a portion of the encapsulation layer 16 can be removed first to expose the electrode 132 of the semiconductor element 13, and then the connection portion 17 is formed on the exposed electrode 132 and the encapsulation layer 16. In some embodiments, the connection portion 17 may include a conductive material. For example, the conductive material may include metals, conductive compounds, other suitable conductive materials, or combinations thereof, but the present invention is not limited thereto. For example, metals may be tin (Sn), copper (Cu), gold (Au), silver (Ag), nickel (Ni), indium (In), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), molybdenum (Mo), titanium (Ti), magnesium (Mg), zinc (Zn), germanium (Ge), or alloys thereof. For example, conductive compounds may be tantalum nitride (TaN), titanium nitride (TiN), tungsten silicide (WSi2), indium tin oxide (ITO), etc. In some embodiments, a portion of the encapsulation layer 16 may be removed by a process such as photolithography etching, and the connection portion 17 may be formed by a process such as electroplating, sputtering, or vapor deposition, but the present invention is not limited thereto.

[0058] like Figure 7 As shown, a substrate 18 may be disposed on the encapsulation layer 16 and the connecting portion 17. Specifically, the substrate 18 covers the encapsulation layer 16 and the connecting portion 17. In some embodiments, the substrate 18 may include epoxy resin, polyimide (PI), polybenzoxazole (PBO), silicone resin, silicon oxide, silicon nitride, or a combination thereof, but the present invention is not limited thereto.

[0059] like Figure 8As shown, a bonding pad 19 can be disposed on a substrate 18, wherein the bonding pad 19 extends through the substrate 18 and is electrically connected to the semiconductor element 13 through a connection portion 17. Specifically, a portion of the substrate 18 can be removed first to expose a portion of the connection portion 17, and then the bonding pad 19 can be formed on the exposed connection portion 17 and the substrate 18. In some embodiments, the bonding pad 19 may include a conductive material. For example, the conductive material may include a metal, a conductive compound, other suitable conductive materials, or combinations thereof, but the invention is not limited thereto. In some embodiments, the material of the bonding pad 19 may be similar to or the same as the material of the connection portion 17, but the invention is not limited thereto. In some embodiments, a portion of the encapsulation layer 16 can be removed by a process such as photolithography etching, and the bonding pad 19 can be formed by a process such as electroplating, sputtering, or vapor deposition, but the invention is not limited thereto. In some embodiments, the bonding pad 19 and the connection portion 17 may be collectively referred to as an electrical connection structure or redistribution structure, which extends through the substrate 18 and the encapsulation layer 16 to be electrically connected to the semiconductor element 13.

[0060] like Figure 9 As shown, the removable carrier plate 10. For example, the carrier plate 10 can be removed by a laser lift-off process, other suitable processes, or a combination thereof, but the invention is not limited thereto.

[0061] like Figure 10 As shown, the structure obtained by the above steps is flipped over, and the adhesive layer 11 is removed to obtain the package structure 1. For example, the adhesive layer 11 can be removed by etching, heating, photolithography, other suitable processes or combinations thereof, but the present invention is not limited thereto.

[0062] In some embodiments, the adhesive layer 11 between the carrier plate 10 and the cover layer 12 can be removed simultaneously in the same manufacturing process. It is worth noting that the above methods are merely examples, and the invention is not limited thereto. In other embodiments, the adhesive layer 11 or a portion of the carrier plate 10 can be directly removed by physical destruction to separate it from the cover layer 12.

[0063] It is worth noting that, although not shown in the accompanying drawings, in some embodiments, multiple encapsulation structures 1 can be formed simultaneously through the steps described above. Therefore, before or after the fabrication process of removing the adhesive layer 11, a dicing process can be performed to separate the multiple encapsulation structures 1 from each other, forming a shape as shown in the diagram. Figure 10 The single package structure 1 is shown.

[0064] In summary, in the present application, by retaining the cap layer 12 as a carrier in the transfer manufacturing process, the molding step, the turning step and the glue removing step can be omitted after the element is transferred. In this way, the packaging structure 1 of the present application can greatly simplify the manufacturing process, so as to have the advantages of less forming steps and low cost.

[0065] The above-described embodiments are merely intended to illustrate the idea of the present application. Those skilled in the art should understand that other manufacturing processes and structures can be designed or modified based on the embodiments of the present application to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent manufacturing processes and structures do not deviate from the spirit and scope of the present application, and various changes, substitutions and replacements can be made without departing from the spirit and scope of the present application.

Claims

1. A package structure, comprising: a substrate having a first side and a second side opposite to each other; a semiconductor element disposed on the first side of the substrate; a cladding layer disposed on the first side of the substrate, the cladding layer covering the semiconductor element and exposing a top surface of the semiconductor element; a cap layer disposed on the cladding layer and the semiconductor element, and comprising: a first portion covering and contacting the top surface of the semiconductor element; a second portion covering and contacting the wrapping layer, wherein the second portion has a maximum intensity in a measurement of a Fourier transform infrared spectrum at a wavenumber of 1060 cm -1 to a wavenumber of 1080 cm -1 and a ratio between the maximum intensity of the second portion at a wavenumber of 780 cm -1 to a wavenumber of 800 cm -1 is greater than 0.65; and an electrical connection structure disposed on the second side of the substrate and penetrating through the substrate and the cladding layer to electrically connect with the semiconductor element.

2. The package structure according to claim 1, wherein in a measurement result of a Fourier transform infrared spectrum, a ratio between a maximum intensity of the first portion at a wave number 1060 cm"1 to a wave number 1080 cm"1 and a maximum intensity of the first portion at a wave number 780 cm"1 to a wave number 800 cm"1 is less than 0.

65. -1 -1 -1 -1 ​​​​ 3. The encapsulation structure as claimed in claim 1, wherein the cover layer further comprises a third portion, and the third portion is disposed on the first portion and the second portion, wherein in the Fourier transform infrared spectroscopy measurement results, the third portion is at a wavenumber of 1060 cm⁻¹. -1 Up to wavenumber 1080cm -1 The maximum intensity of the third part at wavenumber 780cm -1 Up to wave number 800cm -1 The ratio between their maximum strengths is less than 0.

65.

4. The package structure of claim 1, wherein a material of the cap layer comprises a high molecular silicon compound.

5. The package structure of claim 1, wherein a light transmittance of the cladding layer in a visible light wavelength range is less than 5%, and a light transmittance of the cap layer in the visible light wavelength range is greater than or equal to 95%.

6. The package structure of claim 1, wherein the electrical connection structure comprises a connecting portion and a bonding pad, the bonding pad is on the second side of the substrate, and the semiconductor element is electrically connected with the bonding pad through the connecting portion.

7. A method for forming a package structure, comprising: providing a cap layer; disposing a semiconductor element on the cap layer, wherein a top surface of the semiconductor element covers a portion of the cap layer; performing a surface treatment fabrication process on the semiconductor element and a portion of the cap layer not covered by the semiconductor element; disposing a cladding layer on the semiconductor element and the cap layer; disposing a connecting portion in the cladding layer, wherein the connecting portion is electrically connected with the semiconductor element; disposing a substrate on the cladding layer; and disposing a bonding pad on the substrate, wherein the bonding pad is electrically connected with the connecting portion.

8. The method for forming a package structure of claim 7, wherein the step of disposing a semiconductor element on the cap layer further comprises: providing a carrier; disposing an adhesive layer on the carrier; disposing the semiconductor element on the adhesive layer; and transferring the semiconductor element and the adhesive layer to the cap layer.

9. The method for forming a package structure of claim 8, wherein the surface treatment fabrication process removes the adhesive layer on the semiconductor element.

10. The method for forming a package structure of claim 7, wherein in the step of performing the surface treatment fabrication process, the portion of the cap layer covered by the semiconductor element is not subjected to the surface treatment fabrication process by using the semiconductor element as a mask. ​ ​

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