Chip test method, test board card and electronic equipment

Abstract

The embodiment of the invention discloses a chip test method, a test board card and electronic equipment, and the method comprises the steps: obtaining a target test vector, a test instruction and test information, determining a target execution frequency of the target test vector based on an operand in the test information, and when the test instruction indicates a result matching operation, controlling to cyclically execute the result matching operation, the number of times of cyclically executing the result matching operation does not exceed the target execution number of times, and each execution of the result matching operation comprises the following steps: collecting an actual vector output by the tested device, and determining the test result according to an expected vector in the actual vector and the target test vector. According to the method and the device, the matching operation is automatically executed for multiple times, the target test vector does not need to be acquired from the memory every time, the time delay of executing the target test vector is reduced, and the test efficiency is improved.

Description

Technical Field

[0001] This application relates to chip testing technology, and in particular to a chip testing method, test board, and electronic device. Background Technology

[0002] Test equipment is used to test Devices Under Test (DUTs) and detect their performance. Test equipment performs chip testing by executing multiple functional test vectors from a test vector file. For example, executing a functional test vector generates a stimulus signal to the DUT to perform a functional test. Therefore, the DUT occupies the bus and will not receive other stimulus signals. Only after the DUT occupies and releases the bus can it receive the next stimulus signal. The process of identifying the bus occupancy status of the DUT is called a match operation. During chip testing, a single target test vector often corresponds to multiple match operations. Each time a match operation is performed, the target test vector must be retrieved from the chip test equipment's memory. This results in a significant delay between two match operations, leading to low test efficiency. Summary of the Invention

[0003] To address the aforementioned technical problems, embodiments of this application provide a chip testing method, a test board, and an electronic device.

[0004] One aspect of this application provides a chip testing method applied to a testing device. The method includes: acquiring a target test vector, and test instructions and test information corresponding to the target test vector; determining a target execution count for the target test vector based on operands in the test information; and controlling the cyclic execution of a result matching operation in response to the test instruction to obtain a test result. The number of times the result matching operation is executed cyclically does not exceed the target execution count. Each execution of the result matching operation includes: acquiring an actual vector output by the device under test (DUT), and determining the test result based on the actual vector and an expected vector in the target test vector.

[0005] Another aspect of this application provides a test board for use in a testing device. The test board includes a cache module, a read module, a run module, and a result module connected sequentially. The cache module receives a target test vector, along with corresponding test instructions and test information. The read module retrieves the target test vector, along with corresponding test instructions and test information, from the cache module. Based on the operands in the test information, it determines the target execution count of the target test vector. When the test instruction indicates a result matching operation, it generates a continue execution signal and sends the target execution count, the test vector, the continue execution signal, and the test information to the run module. The module includes a running module, configured to control the cyclic execution of a result matching operation when the test instruction indicates a result matching operation, wherein the number of cyclic executions of the result matching operation does not exceed the target number of executions, and each execution of the result matching operation includes: acquiring the actual vector output by the device under test, determining the matching result based on the actual vector and the expected vector in the target test vector, wherein the matching result includes: the actual vector and the expected vector matching successfully, or the actual vector and the expected vector failing to match; and a result module, configured to count the number of times the result matching operation is executed, compare the current number of executions with the target number of executions, and determine the test result based on the matching result, wherein the test result includes successful matching and failed matching.

[0006] In another aspect of this application, an electronic device is provided, comprising: a memory for storing a computer program; and a processor for executing the computer program stored in the memory, wherein when the computer program is executed, it implements the chip testing method described above.

[0007] In another aspect of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the chip testing method described above.

[0008] In another aspect of the embodiments of this application, a computer program product is provided, including computer program instructions that, when executed by a processor, implement the chip testing method described above.

[0009] This application's embodiments include a chip testing method, a test board, and an electronic device. A target test vector, its corresponding test instructions, and test information are acquired. In response to the test instructions, a result matching operation is initiated to stimulate the test vector. The result matching operation is then executed cyclically to obtain a test result. The number of cyclic executions of the result matching operation does not exceed a target execution count. Each result matching operation includes: acquiring the actual vector output by the device under test (DUT), and determining the test result based on the actual vector and the expected vector in the target test vector. Therefore, in this application embodiment, multiple automatic executions of the result matching operation are achieved through test instructions and a target execution count, eliminating the need to retrieve the target test vector from memory each time, reducing the latency of executing the target test vector, and thus improving testing efficiency. Furthermore, when executing the test vector, the pins of the test device only need to perform opposite operations according to the test instructions, without needing to separately specify pins for the matching operation, thereby increasing the number of pins that can perform matching operations.

[0010] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0011] The accompanying drawings, which form part of this specification, illustrate embodiments of this application and, together with the description, serve to explain the principles of this application.

[0012] This application can be more clearly understood with reference to the accompanying drawings and the following detailed description, wherein:

[0013] Figure 1 This is a schematic flowchart of a chip testing method provided in an exemplary embodiment of this application;

[0014] Figure 2 This is a flowchart illustrating step S120 provided in an exemplary embodiment of this application;

[0015] Figure 3 This is a flowchart illustrating step S100 provided in an exemplary embodiment of this application;

[0016] Figure 4 This is a schematic flowchart of a chip testing method provided in another exemplary embodiment of this application;

[0017] Figure 5 This is a schematic flowchart of a chip testing method provided in another exemplary embodiment of this application;

[0018] Figure 6 This is a schematic diagram of a chip testing method provided in an application example of this application;

[0019] Figure 7 This is a schematic diagram of a test board provided in an exemplary embodiment of this application;

[0020] Figure 8 This is a schematic diagram of the structure of an application embodiment of the electronic device of this application. Detailed Implementation

[0021] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present application.

[0022] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this application are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0023] It should also be understood that in the embodiments of this application, "multiple" can refer to two or more, and "at least one" can refer to one, two or more.

[0024] It should also be understood that any component, data or structure mentioned in the embodiments of this application can generally be understood as one or more unless explicitly defined or given contrary guidance in the context.

[0025] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects have an "or" relationship.

[0026] It should also be understood that the description of the various embodiments in this application emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0027] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0028] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this application and its application or use.

[0029] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0030] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0031] The embodiments of this application can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Well-known examples of terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0032] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0033] In the process of implementing this application, it was found through research that during the testing of the device under test, the target test vector is usually obtained and multiple matching operations are performed. Specifically, the functional test vector needs to be obtained from the memory each time a matching operation is performed, which results in a large delay between the two matching operations, leading to low testing efficiency. In this embodiment, the device under test can be, for example, a chip.

[0034] Figure 1 This is a schematic flowchart of a chip testing method provided in an exemplary embodiment of this application. This embodiment can be applied to testing equipment, such as... Figure 1 As shown, the chip testing method may include the following steps:

[0035] Step S100: Obtain the target test vector, as well as the test instructions and test information corresponding to the target test vector.

[0036] The testing equipment is used to test the chip. For example, the testing equipment may include an Automatic Test Equipment (ATE). The testing equipment may include a host computer and a test head. The host computer communicates with the test head and controls the test head to test the device under test (DUT). In one embodiment, the testing equipment may pre-store multiple test vectors (patterns). These multiple test vectors (patterns) include stimulus test vectors and expected vectors. The stimulus test vectors and expected vectors are functional test vectors used to test the performance of the DUT. Specifically, the performance of the DUT pins is tested by executing the stimulus test vectors, such as reset and power-on. The expected vectors are used to perform multiple execution matching operations after executing the stimulus test vectors to detect the execution result of the stimulus test vectors. Based on the execution result of the stimulus test vectors, the next functional test vector is executed. Alternatively, the expected vectors are used to detect whether the functional pins of the DUT have reached the expected state, and can receive the next functional test vector. The target test vector is the selected test vector (pattern). Of course, multiple test vectors (patterns) can also include only the expected vector, which is used to detect whether the functional pins of the device under test (DUT) have reached the expected state, and can receive the next functional test vector.

[0037] Test instructions are used to indicate the operation type of the target test vector. In this embodiment, the test vector (pattern) is stored in memory, such as RAM, with one test vector stored in each row of addresses. For example, each row stores the test vector corresponding to one pin under test; however, those skilled in the art will know that it is not limited to storing one test vector per row, and the storage location of a test vector can be determined according to the start address and end address, and can be stored in one or more rows.

[0038] Test instructions are used to indicate result matching operations, normal operations, and loop operations. Test instructions may include, for example, a vector type (pattern type) and an operation instruction. For instance, the test instruction for retrieving the corresponding address line indicates a result matching operation. The test instruction includes `TYPE_MATCH` (vector type) and `TYPE_MATCH_IDLE` (operation instruction). `TYPE_MATCH` indicates that the test vector is for a result matching operation, and `TYPE_MATCH_IDLE` indicates that the result matching operation is executed repeatedly.

[0039] Test information is used to represent information about the execution of the target test vector. In this embodiment, test information includes operands, test vector execution data, microinstructions, etc.

[0040] Step S110: Based on the operands in the test information, determine the target number of executions for the target test vector.

[0041] The test information may include the operands corresponding to the target test vector. The target execution count can be an integer greater than or equal to zero. The operands can be used as the target execution count. In one implementation, the test information may also include the micro-instruction (Opcode) corresponding to the target test vector.

[0042] Step S120: In response to the test instruction indicating the result matching operation, control the loop to execute the result matching operation to obtain the test result.

[0043] The number of times the result matching operation is executed in a loop does not exceed the target number of executions. Each result matching operation includes: acquiring the actual vector output by the device under test, and determining the test result based on the actual vector and the expected vector in the target test vector.

[0044] In one implementation, the target test vector may include an activation test vector and a target vector. The test instruction instructs a result matching operation to indicate that a result matching operation is performed based on the target test vector. In one implementation, when the vector type in the test instruction is a result matching operation and the operation instruction is a loop execution of the result matching operation, the test instruction can be determined to be a result matching instruction.

[0045] Test results can include: successful match or failed match. A successful match indicates that the actual vector is the same as the expected vector, while a failed match indicates that the actual vector is different from the expected vector. The device under test can be, for example, a chip, integrated circuit, or wafer.

[0046] Test information can also include timing parameters, which can be used to generate timing information. Timing information can include, for example, the output timing of the excitation signal and the acquisition timing (input timing) of the actual vector values. Each time the target test vector is executed, the excitation signal can be sent and the actual vector values ​​can be acquired according to the timing information.

[0047] For example, each execution result matching operation includes: acquiring the actual vector output by the device under test according to the acquisition timing of the actual vector value, comparing the waveform corresponding to the actual vector with the waveform corresponding to the expected vector, and determining whether the actual vector and the expected vector are the same.

[0048] In this embodiment, the result matching operation is automatically executed repeatedly by using test instructions and target execution counts. This achieves multiple automatic executions of the result matching operation (collecting the actual vector value output by the device under test, and determining the test result based on the actual vector value and the expected vector value in the target test vector). It eliminates the need to retrieve the target test vector from the memory each time, reducing the latency of executing the target test vector and thus improving test efficiency.

[0049] In some optional embodiments, the channel information of the test device is obtained before obtaining the target test vector. For example, the test device contains 32 test channels, each occupying 1 bit. The channel information stores 32 bits of data, where 1 represents that the corresponding test channel is enabled, and 0 represents that the corresponding test channel is disabled. Of course, those skilled in the art will know that the test channels of the test device are connected one-to-one with the pins of the device under test (DUT). When a test channel is enabled, it means that the corresponding pin of the DUT is enabled; similarly, when a test channel is disabled, it means that the corresponding pin of the DUT is disabled.

[0050] Furthermore, when executing test vectors, the channels of the test equipment only need to determine the pins for the matching operation based on the test instructions, channel information, and expected vectors, and perform the corresponding operations, without needing to separately specify the pins for the matching operation. In this embodiment, the pins are the channels of the test equipment, which includes a test board, and the channels of the test board are the channels of the test equipment. In some optional embodiments, before controlling the loop to execute the result matching operation, the method further includes: outputting an excitation signal to the device under test based on the excitation test vector in the target test vector.

[0051] For example, the test equipment generates a corresponding excitation signal based on the excitation test vector in the target test vector, and inputs the excitation signal to the device under test. Then, it performs the result matching operation in a loop. Each result matching operation includes: acquiring the actual vector output by the device under test, comparing the waveform corresponding to the actual vector with the waveform corresponding to the expected vector, and determining whether the actual vector and the expected vector are the same.

[0052] In some optional implementations, the response to the test instruction indicating the result matching operation, controlling the cyclic execution of the result matching operation to obtain the test result may include:

[0053] Generate a signal to continue execution and perform the result matching operation repeatedly. Based on the target number of executions and the matching result between the actual vector and the expected vector obtained in each execution result matching operation, determine the test result. Based on the test result, obtain the next target test vector.

[0054] The generation of the continue execution signal is used to indicate that the result matching operation is executed cyclically until the next target test vector is obtained. After that, the continue execution signal is no longer generated, and the result matching operation is exited to execute the operation corresponding to the next target test vector.

[0055] Figure 2 This is a flowchart illustrating step S120 provided in an exemplary embodiment of this application. In some alternative embodiments, such as Figure 2 As shown, step S120 may include:

[0056] Step S121: Match the actual vector and the expected vector to obtain the matching result.

[0057] In one implementation, the waveform corresponding to the actual vector is compared with the waveform corresponding to the expected vector to determine the matching result. If the waveform corresponding to the actual vector is the same as the waveform corresponding to the expected vector, the matching result is determined to be a successful match between the actual vector and the expected vector; if the waveform corresponding to the actual vector is different from the waveform corresponding to the expected vector, the matching result is determined to be a failed match between the actual vector and the expected vector.

[0058] Step S122: In response to the matching result being a successful match between the actual vector and the expected vector, determine the test result as a successful match and stop executing the result matching operation.

[0059] In one implementation, when the matching result shows that the actual vector and the expected vector match successfully, the test result is determined to be a successful match (Match pass). At this point, the test device stops executing the result matching operation, thus completing the execution of the target test vector and allowing the next test vector to be executed. In the embodiment of the application, when the actual vector and the expected vector are the same, the test result is determined and the result matching operation is stopped, without continuing to execute the target test vector, thereby improving testing efficiency.

[0060] Step S123: In response to the matching result being a failure to match the actual vector and the expected vector, obtain the current execution count corresponding to the result matching operation.

[0061] The current execution count indicates the number of times the result matching operation has been executed.

[0062] It should be noted that there is no specific order of execution between steps S122 and S123 in the embodiments of this application.

[0063] Step S124: If the current execution count is not the last of the target execution count, perform the operation of acquiring the actual vector output by the device under test.

[0064] The test equipment compares the current execution count with the target execution count. If the current execution count is not the last execution count of the target execution count, a continue execution signal is generated. When the test equipment detects the continue execution signal, it performs the operation of acquiring the actual vector output by the device under test and determining the matching result based on the actual vector and the expected vector.

[0065] Step S125: If the current execution count is the last of the target execution count, determine that the test result is a matching failure and stop the result matching operation.

[0066] If the current execution count is the last of the target execution count, and the matching result is that the actual vector and the expected vector fail to match, then the test result is determined to be a match failure. At this time, the test device stops executing the result matching operation, thereby completing the execution of the target test vector.

[0067] In one implementation, the matching results obtained each time the target test vector is executed can be cached, and the test results can be stored and the matching results in the cache can be deleted when the test results are determined.

[0068] It should be noted that there is no specific order of execution between steps S124 and S125 in the embodiments of this application.

[0069] In the application embodiment, when the actual vector is different from the expected vector, it is determined whether to perform the result matching operation again based on the current execution count and the target execution count, thereby realizing automatic execution of the target test vector and improving testing efficiency.

[0070] In some optional implementations, the target test vector may include: an incentive test vector and / or an expected vector. Accordingly, after obtaining the target test vector and the corresponding test instructions and test information in the embodiments of this application, the process further includes:

[0071] In response to the target test vector, which includes the stimulus test vector and the expected vector, and with the test command instructing a result matching operation, the device under test (DUT) is cyclically output with stimulus signals based on the test command, channel information, stimulus test vector, and test information. The test information includes timing parameters and operands. Alternatively, the device under test is cyclically output with acquired signals based on the test command, channel information, expected vector, and test information.

[0072] In response to the target test vector including the expected vector and the test instruction indicating the result matching operation, the system cyclically outputs the acquired signal to the device under test based on the expected vector, test instruction, channel information and test information in the target test vector. The test information includes timing parameters and operands.

[0073] In this embodiment, in response to the target test vector including an excitation test vector and a target vector, based on the test command, channel information, and the corresponding excitation test vector and target vector, the operation pin is determined. The output timing of the excitation signal is obtained according to timing parameters, and the acquisition timing or input timing (timing information) of the actual vector value is obtained according to the timing parameters. After the timing information, pin information, and target test vector are confirmed, based on the operands in the test information, the excitation signal is cyclically output to the device under test (DUT), and the acquisition signal is cyclically output to the DUT, controlling the cyclic execution of the result matching operation; or...

[0074] In response to the target test vector, including the expected vector, the operation pin is determined based on the test command, channel information and the corresponding expected vector. The acquisition timing or input timing (timing information) of the actual vector value is obtained according to the timing parameters. After the timing information, pin information and target test vector are confirmed, the acquisition signal is cyclically output to the device under test based on the operand in the test information, and the result matching operation is controlled to be executed cyclically.

[0075] Figure 3 This is a flowchart illustrating step S100 provided in an exemplary embodiment of this application. In some alternative embodiments, such as Figure 3 As shown, step S100 may include the following steps:

[0076] Step S101: Obtain the target test vector and the corresponding microinstructions and operands from the memory.

[0077] The test equipment includes a memory, such as Random Access Memory (RAM). The memory stores multiple test vectors, each corresponding to a microinstruction and operands. Microinstructions can include: match instructions, normal instructions, or loop / endloop instructions. Match instructions are used to query the results of functional test vector execution or to check whether the functional pins of the DUT have reached the expected state. Normal instructions instruct the execution of the test vector corresponding to the next address. Loop / endloop instructions instruct the test vectors within the corresponding address range to perform a loop operation.

[0078] In one implementation, timing parameters and channel information corresponding to the target test vector can also be obtained from the memory.

[0079] Step S102: Determine test information based on microinstructions and operands.

[0080] The test information is constructed from microinstructions and operands; that is, the test information includes microinstructions and operands. In one embodiment, the test information can also be determined based on microinstructions, operands, and timing parameters, so that the test information can include microinstructions, operands, and timing parameters.

[0081] Step S103: Determine the test instructions based on the microinstructions.

[0082] The microinstructions include result matching instructions, ordinary instructions, or loop instructions. In one embodiment, when the microinstruction is a result matching instruction, a test instruction indicating a result matching operation can be generated; when the microinstruction is an ordinary instruction, a test instruction indicating an ordinary operation can be generated; and when the microinstruction is a loop instruction, a test instruction indicating a loop operation can be generated.

[0083] In one implementation, a buffer queue can be pre-configured, which can be a First-Input First-Out (FIFO) queue. The target test vector, corresponding test instructions, test information, and channel information are stored in the buffer queue.

[0084] In this embodiment, by generating corresponding test instructions and test information based on microinstructions and operands, the target test vector can be automatically executed based on the test instructions and test information. This eliminates the need to retrieve the target test vector from the storage device each time it is executed multiple times, thus improving testing efficiency.

[0085] Figure 4 This is a schematic flowchart of a chip testing method provided in another exemplary embodiment of this application. Figure 4 As shown, in Figure 1 Based on this, after step S110, the following may also be included:

[0086] Step S130: In response to the test instruction indicating normal or cyclic operation, control the target test vector to be executed a target number of times on the device under test.

[0087] When the test instruction indicates a normal operation, the test equipment executes the target test vector on the device under test (DUT) a target number of times. For example, when the test instruction indicates a normal operation, the microinstruction is a normal instruction (norm), and the target test vector includes a stimulus test vector, the target execution count is 1. A corresponding stimulus signal can be generated based on this stimulus test vector, and the stimulus signal is output to the DUT once to complete the execution of the target test vector. When the test instruction indicates a loop operation, and the target test vector includes a stimulus test vector, the microinstruction is a loop instruction (loop / endloop). Based on the loop instruction (loop / endloop), within the address range corresponding to the loop microinstruction and the endloop microinstruction, a corresponding stimulus signal can be generated based on the stimulus test vector, and the stimulus signal is output to the DUT. The execution is repeated cyclically based on the target execution count, for example, a target execution count of 10, to complete the execution of the target test vector.

[0088] It should be noted that there is no specific order of execution between steps S120 and S130 in this embodiment.

[0089] In the embodiments of this application, when the test instruction indicates a normal operation or a loop operation, that is, not a result matching operation, the target test vector of the target number of executions can be executed, thereby realizing the execution of the target test vector of various test instructions.

[0090] In some alternative implementations, in response to a test result of a match failure, the pin that executes the target test vector is set to a preset state the next time a new target test vector is executed.

[0091] Among them, the pin used to execute the result matching instruction corresponding to the target test vector can be called the match pin.

[0092] In one implementation, the preset state can be one of the first state, the second state, the third state, or the fourth state. The first state is to continue outputting the excitation signal of the target test vector, that is, to continue running the target test vector. The second state is to set the matching pin to high resistance and continuously output a high-impedance state or output 0. The third state is to output a low level (drive 0). The fourth state is to output a high level (drive 1).

[0093] In this embodiment, when the test result is a match failure, the pin that executes the target test vector is set to a preset state, thereby quickly finding the pin where the actual vector value and the predicted vector value fail to match.

[0094] Figure 5 This is a schematic flowchart of a chip testing method provided in another exemplary embodiment of this application. Figure 5 As shown, in some optional embodiments, the chip testing method may further include the following steps:

[0095] Step S200: Obtain the status of the pins of the target test vector.

[0096] The status of the pins can include normal operation status and preset status.

[0097] Specifically, based on the previous result matching operation's failure to match, the pins corresponding to the target test vector of the result matching instruction are set to a preset state and stored in the cache. After obtaining a new target test vector, the pins corresponding to the pins in the cache with preset states are set to the preset states. In other words, the state of the pins executing the target test vector is obtained.

[0098] In step S210, in response to the pin being in a preset state and the test command indicating a result matching operation, the pin is set to an operable state so that the target test vector can be executed through the pin.

[0099] Specifically, when the pin is in a preset state, the test command instructs a result matching operation, setting the pin to an operable state. Then, the test controls the cyclic execution of the result matching operation on the device under test. After a result matching operation, if the pin's state is confirmed to be operable again, it is set to a normal operating state, allowing the pin to continue executing the next target test vector. Conversely, if the pin is in a preset state after a result matching operation, it is set to the preset state. When the test command instructs a normal operation or a cyclic operation, the pin cannot continue executing the corresponding target test vector until the test command instructs a result matching operation, at which point the pin's state is confirmed again.

[0100] In step S220, in response to the pin being in a preset state and the test command not indicating a result matching operation, the pin does not execute the target test vector.

[0101] Specifically, when the pin is in a preset state and the test command does not indicate a result matching operation, the pin remains in the preset state and the target test vector is not executed. When the pin is in an operable state and the test command does not indicate a result matching command, the target test vector is executed directly on the device under test for the target number of executions through this pin.

[0102] In this embodiment, the test results of the test device pins are obtained through the result matching operation. If the test result is a matching failure, the corresponding pin is set to a preset state. The pin in the preset state is set as the target test vector that only executes the result matching instruction. The target vectors of other test instructions are not executed. This increases the flexibility of pin settings and ensures that the corresponding pin is in an operable state when executing non-result matching instructions, thus eliminating abnormal situations of the pin.

[0103] Figure 6 This is a schematic diagram of a chip testing method provided in an application example of this application. For example... Figure 6As shown, the test equipment includes a test board, which can be configured with a microinstruction module, a storage module (MCF), a buffer module (Vector_buffer), a read module (Vector_rd_ctrl), a run module (Drive), and a result module (Rx_result). The storage module can be RAM. The run module includes a run submodule and a PE module. The PE module can use a PE chip, which is connected to the pins of the device under test (DUT). In this application example, the microinstruction module uses the result matching instruction as an example. The microinstruction module retrieves the target test vector, the corresponding microinstruction, timing parameters, and operands, as well as preset status information and channel information from the RAM. Based on the microinstruction, it generates a test instruction including a result matching instruction. The target test vector, test instruction, test information, and channel information are sent to the buffer module for caching. The test information includes timing parameters and operands. The reading module reads the target test vector, test instructions, test information, and channel information from the cache module. When the test instructions indicate a result matching operation, it generates a param_vld signal (continue execution signal). The reading module uses the operands in the test information as the target execution count (UI cycle count) and sends the timing parameters, target execution count, continue execution signal, channel information, and target test vector from the test information to the running module. The running module generates timing information based on the timing parameters, sends the target execution count to the result module, and iteratively executes the result matching operation based on the target test vector, channel information, and timing information. The number of times the result matching operation is executed in the loop does not exceed the target execution count. Each execution of the result matching operation includes: acquiring the actual vector output by the device under test, determining the matching result based on the actual vector and the expected vector in the target test vector, and transmitting the matching result to the result module. The matching result includes: the actual vector and the expected vector match successfully, or the actual vector and the expected vector fail to match. The result module counts the number of times the result matching operation is executed, compares the current execution count with the target execution count, and determines the test result based on the matching result.

[0104] In this embodiment, the running module includes a running submodule and a PE module connected to each other. The running submodule is connected to the reading module and the result module, and the PE module is connected to the device under test. The running submodule is used to receive the target number of executions, the target test vector, the continue execution signal, and the test information, and transmits the target number of executions to the result module. It generates timing information based on timing parameters and transmits the target test vector and timing information to the PE module. The PE module performs a result matching operation cyclically based on the target test vector and timing information, and transmits the matching result to the result module via the running submodule.

[0105] Specifically, during each execution of the target test vector, when the target test vector includes an excitation test vector and a expected vector, the excitation test vector is an array composed of high and low levels of 0 and 1, and the expected vector is H or L. The excitation test vector and the expected vector determine the input and output. That is, based on the excitation test vector, the running submodule can transmit the excitation test vector, channel information, and timing information to the PE module. The PE module generates the corresponding excitation signal based on the excitation test vector and inputs the excitation signal to the corresponding pin of the device under test according to the timing information and channel information. The running submodule can transmit the expected vector to the PE chip. The PE chip, based on the timing information and channel information, acquires the actual vector output by the device under test and outputs A (peak), B (falling edge to the right of the peak), and C (rising edge to the left of the peak) of the waveform corresponding to the actual vector. The four edges of the actual vector and D (the rising edge to the right of the trough) are compared with the four edges of A, B, C, and D in the waveform corresponding to the expected vector (compare_result). If the waveform corresponding to the actual vector is the same as the waveform corresponding to the expected vector, the matching result is determined to be a successful match between the actual vector and the expected vector. If the waveform corresponding to the actual vector is different from the waveform corresponding to the expected vector, the matching result is determined to be a failed match between the actual vector and the expected vector, and the matching result is transmitted to the running submodule, which then transmits it to the result module. The result module receives the matching result and counts the number of times the result matching operation is performed (current execution count). When the matching result is a successful match, the test result is determined to be a successful match, and the successful match result is transmitted to the microinstruction module, which then reads the next target test vector. When the matching result is a failure, the result module compares the current execution count with the target execution count. If the current execution count is not the last execution count of the target count, the result module continues to receive the next matching result obtained by the running submodule and again determines whether the transmitted matching result is a successful match. If the current execution count is the last execution count of the target count, the result module determines that the test result is a failure and transmits the failure result to the microinstruction module. The microinstruction module stops executing the target test vector after determining the test result and reads the next target test vector. In one implementation, when the FE (functional daughterboard) includes multiple Match pins, each Match pin performs the above operation. When all Match pins are found to meet the requirements (successful matching), the match is determined to be successful. If, after a preset time, a Match pin still does not meet the requirements, the match is determined to be a failure. Simultaneously, the pin with the failed match is set to a preset state. The digital board (test board) can include multiple FEs, and each FE can include multiple PE chips.

[0106] Similarly, when the target test does not include the stimulus test vector, the execution submodule executes the expected vector. The execution submodule transmits the expected vector, channel information, and timing information to the PE module. The PE module, based on the specified matching pin in the channel information and the timing information, acquires the actual vector output by the device under test and performs the aforementioned result matching operation. The result module generates the corresponding ioctrl_mcf_match_en signal based on the test result. That is, when the test result is a successful match, an ioctrl_mcf_match_en signal with a value of 1 is generated; when the test result is a failed match, an ioctrl_mcf_match_en signal with a value of 0 is generated. The ioctrl_mcf_match_en signal is then marked on the test result, and the test result carrying the ioctrl_mcf_match_en signal is transmitted to the storage module. The storage module stores the test result carrying the ioctrl_mcf_match_en signal, thereby filtering out other intermediate results (matching results, etc.) and transmitting the test result to the microinstruction module so that the microinstruction module can obtain a new target test vector from RAM.

[0107] In one embodiment, when the test result is a match failure, the microinstruction module sets the pin of the target test vector corresponding to the result matching instruction to a preset state and transmits it to the cache module for storage. When executing the next target test vector, the microinstruction module transmits the channel information, target test vector, test instruction, and test information to the cache module. The cache module transmits the preset state of the pin, channel information, target test vector, test instruction, and test information to the execution module through the reading module. The execution module sets the state of the pin corresponding to the preset state in the cache module to the preset state. Based on this, the execution module obtains the pin state of the target test vector.

[0108] After the running module obtains the pin status of the target test vector, at least one pin is in a preset state. If the test instruction received by the running module indicates a result matching operation, the running module sets the state of the pin in the preset state to the runnable state so that the target test vector can be executed through the pin. If the test instruction received by the running module does not indicate a result matching operation, the pin in the preset state will not execute the target test vector.

[0109] In one embodiment, when the test board executes the target test vector corresponding to the test instruction indicating the result matching operation, it can control the device_cycle count value in the counter to remain unchanged each time the target test vector is executed. The counter is used to count cycles, and the device_cycle count value represents the number of cycles of operation.

[0110] Figure 7This is a schematic diagram of a test board provided in an exemplary embodiment of this application. The test board is used in testing equipment, such as... Figure 7 As shown, the test board is configured with the following modules connected in sequence: a cache module, a read module, a run module, and a result module.

[0111] The cache module is used to receive the target test vector, as well as the test instructions and test information corresponding to the target test vector;

[0112] The reading module is used to obtain the target test vector, the test instruction and test information corresponding to the target test vector from the cache module, determine the target number of executions of the target test vector based on the operands in the test information, generate a continue execution signal when the test instruction indicates a result matching operation, and send the target number of executions, the target test vector, the continue execution signal and the test information to the running module.

[0113] The running module is used to control the cyclic execution of the result matching operation when the test instruction indicates the result matching operation, wherein the number of times the result matching operation is executed in the loop does not exceed the target number of executions, and each execution of the result matching operation includes: acquiring the actual vector output by the device under test, and determining the matching result based on the actual vector and the expected vector in the target test vector, wherein the matching result includes: the actual vector and the expected vector are successfully matched, or the actual vector and the expected vector are not successfully matched;

[0114] The result module is used to count the number of times the result matching operation is performed, compare the current number of executions with the target number of executions, and determine the test result based on the matching result, wherein the test result includes successful matching and failed matching.

[0115] In some optional implementations, the test information includes timing parameters and operands, the running module includes a running submodule and a PE module connected to each other, the running submodule is connected to the reading module and the result module, and the PE module is connected to the device under test;

[0116] The running submodule is used to receive the target number of executions, the target test vector, the continue execution signal and the test information, and transmit the target number of executions to the result module, generate timing information based on the timing parameters, and transmit the target test vector and the timing information to the PE module;

[0117] The PE module performs a result matching operation cyclically based on the target test vector and the timing information, and transmits the matching result to the result module via the running submodule.

[0118] In some alternative implementations, the test board is also provided with a storage module;

[0119] The result module is also used to transmit the test results to the storage module;

[0120] The storage module is used to store the test results.

[0121] In some optional embodiments, the test board is further provided with a microinstruction module; the result module is connected to the microinstruction module, and the microinstruction module is connected to the cache module;

[0122] The microinstruction module is used to retrieve the target test vector and the corresponding microinstruction, timing parameters, channel information, and operands from the memory; determine the test information based on the timing parameters and the operands; determine the test instruction based on the microinstruction; and send the target test vector, the test instruction, the test information, and the channel information to the cache module. The microinstruction includes a result matching instruction, a normal instruction, or a loop instruction.

[0123] And when receiving the test results transmitted by the result module, stop performing the result matching operation and obtain the next target test vector.

[0124] In some optional implementations, the caching module is further configured to cache the preset state corresponding to the pin that executes the target test vector when the test result is determined to be a matching failure;

[0125] The running module is further configured to, upon receiving the next target test vector, set the corresponding pin of the next target test vector to the preset state based on the preset state of the pin stored in the cache module.

[0126] In some optional implementations, determining the test result based on the target number of executions and the matching result between the actual vector and the expected vector obtained from each execution result matching operation is further used for:

[0127] The actual vector and the expected vector are matched to obtain a matching result;

[0128] In response to the matching result indicating that the actual vector and the expected vector are successfully matched, the test result is determined to be a successful match, and the result matching operation is stopped;

[0129] In response to the matching result indicating that the actual vector and the expected vector failed to match, the current execution count corresponding to the result matching operation is obtained;

[0130] In response to the fact that the current execution count has not exceeded the target execution count, the operation of acquiring the actual vector output by the device under test is performed;

[0131] In response to the current number of executions exceeding the target number of executions, the test result is determined to be a matching failure, and the result matching operation is stopped.

[0132] In some optional implementations, after obtaining the target test vector and the corresponding test instructions and test information, the method further includes:

[0133] In response to the target test vector including an excitation test vector and an expected vector, and the test instruction indicating a result matching operation, an excitation signal is cyclically output to the device under test based on the test instruction, channel information, the excitation test vector, and the test information; an acquisition signal is cyclically output to the device under test based on the channel information, the expected vector, and the test information, wherein the test information includes timing parameters;

[0134] In response to the target test vector including the expected vector, and the test instruction indicating a result matching operation, the system cyclically outputs acquisition signals to the device under test based on the expected vector, the test instruction, channel information, and the test information, wherein the test information includes timing parameters.

[0135] In some alternative implementations, after determining the target number of executions for the target test vector, the method further includes:

[0136] In response to the test instruction indicating normal or cyclic operation, the target test vector is controlled to be executed on the device under test for the target number of times.

[0137] In some optional implementations, after obtaining the target test vector and the corresponding test instructions and test information, the method further includes:

[0138] Obtain the status of the pins that execute the target test vector;

[0139] In response to the pin being in a preset state and the test command indicating a result matching operation, the pin is set to an operable state so that the target test vector can be executed through the pin.

[0140] In response to the pin being in a preset state and the test command not indicating a result matching operation, the pin does not execute the target test vector.

[0141] The test board in this application corresponds to the chip testing method described above, and the relevant content can be referred to each other. It will not be repeated here.

[0142] The beneficial technical effects of the exemplary test board in this application can be found in the corresponding beneficial technical effects of the exemplary method section above, and will not be repeated here.

[0143] In addition, embodiments of this application also provide an electronic device, including:

[0144] Memory, used to store computer programs;

[0145] A processor is configured to execute a computer program stored in the memory, and when the computer program is executed, to implement the chip testing method described in any of the above embodiments of this application.

[0146] Figure 8 This is a schematic diagram illustrating the structure of an application embodiment of the electronic device of this application. Below, reference is made to… Figure 8 This application describes an electronic device according to embodiments thereof. The electronic device may be either or both of a first device and a second device, or a standalone device independent of them, which may communicate with the first device and the second device to receive acquired input signals from them.

[0147] like Figure 8 As shown, the electronic device includes one or more processors and memory.

[0148] A processor can be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and can control other components in an electronic device to perform desired functions.

[0149] The memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the program instructions to implement the chip testing methods of the various embodiments of this application described above and / or other desired functions.

[0150] In one example, the electronic device may also include input devices and output devices, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0151] In addition, the input device may include, for example, a keyboard, a mouse, etc.

[0152] This output device can output various information to the outside, including determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0153] Of course, for the sake of simplicity, Figure 8 Only some of the components of the electronic device relevant to this application are shown in this illustration; components such as buses, input / output interfaces, etc., are omitted. In addition, the electronic device may include any other suitable components depending on the specific application.

[0154] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the chip testing methods according to various embodiments of this application as described in the foregoing portion of this specification.

[0155] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0156] Furthermore, embodiments of this application may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the chip testing methods according to various embodiments of this application described in the foregoing portion of this specification.

[0157] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0158] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0159] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0160] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0161] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0162] The methods and apparatus of this application may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this application are not limited to the order specifically described above, unless otherwise specifically stated. Furthermore, in some embodiments, this application may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this application. Thus, this application also covers recording media storing programs for performing the methods according to this application.

[0163] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0164] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0165] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A chip testing method, characterized in that, Applied to a testing device, the method includes: Obtain the target test vector, as well as the test instructions and test information corresponding to the target test vector; Based on the operands in the test information, determine the target number of executions for the target test vector; In response to the test instruction indicating a result matching operation, the result matching operation is controlled to be executed cyclically to obtain a test result. The number of times the result matching operation is executed cyclically does not exceed the target number of executions. Each execution of the result matching operation includes: acquiring the actual vector output by the device under test, and determining the test result based on the actual vector and the expected vector in the target test vector.

2. The method according to claim 1, characterized in that, The response to the test instruction indicating the result matching operation, controlling the cyclic execution of the result matching operation to obtain the test result, includes: Generate a continuation signal and repeatedly perform the result matching operation; The test result is determined based on the target number of executions and the matching result between the actual vector and the expected vector obtained from the matching operation of each execution result; Based on the test results, obtain the next target test vector.

3. The method according to claim 2, characterized in that, The determination of the test result based on the target number of executions and the matching result between the actual vector and the expected vector obtained from each execution result matching operation includes: The actual vector and the expected vector are matched to obtain a matching result; In response to the matching result indicating that the actual vector and the expected vector are successfully matched, the test result is determined to be a successful match, and the result matching operation is stopped; In response to the matching result indicating that the actual vector and the expected vector failed to match, the current execution count corresponding to the result matching operation is obtained; If the current execution count is not the last of the target execution count, then the operation of acquiring the actual vector output by the device under test is performed; If the current execution count is the last of the target execution count, the test result is determined to be a matching failure, and the result matching operation is stopped.

4. The method according to claim 1, characterized in that, After obtaining the target test vector, and the corresponding test instructions and test information, the process further includes: In response to the target test vector including an excitation test vector and an expected vector, and the test instruction indicating a result matching operation, an excitation signal is cyclically output to the device under test based on the test instruction, channel information, the excitation test vector, and the test information; an acquisition signal is cyclically output to the device under test based on the test instruction, the channel information, the expected vector, and the test information, wherein the test information includes timing parameters; In response to the target test vector including the expected vector and the test instruction indicating a result matching operation, the system cyclically outputs acquisition signals to the device under test based on the expected vector, the test instruction, channel information, and the test information, wherein the test information includes timing parameters.

5. The method according to claim 1, characterized in that, The acquisition of the target test vector, and the corresponding test instructions and test information, includes: The target test vector and the corresponding microinstruction and operand are retrieved from the memory, wherein the microinstruction includes a result matching instruction, a normal instruction, or a loop instruction; The test information is determined based on the microinstruction and the operand; The test instruction is determined based on the microinstruction.

6. The method according to claim 1, characterized in that, After determining the target number of executions for the target test vector, the method further includes: In response to the test instruction indicating normal or cyclic operation, the target test vector is controlled to be executed on the device under test for the target number of times.

7. The method according to claim 1, characterized in that, After obtaining the test results, the process also includes: In response to the test result being a match failure, the pin that executes the target test vector will be set to a preset state the next time a new target test vector is executed.

8. The method according to claim 7, characterized in that, After obtaining the target test vector, and the corresponding test instructions and test information, the process further includes: Obtain the status of the pins that execute the target test vector; In response to the pin being in a preset state and the test command indicating a result matching operation, the pin is set to an operable state so that the target test vector can be executed through the pin. In response to the pin being in a preset state and the test command not indicating a result matching operation, the pin does not execute the target test vector.

9. A test board, characterized in that, Applied to testing equipment, the test board is equipped with: a cache module, a read module, a run module, and a result module connected in sequence; The cache module is used to receive the target test vector, as well as the test instructions and test information corresponding to the target test vector; The reading module is used to obtain the target test vector, the test instruction and test information corresponding to the target test vector from the cache module, determine the target number of executions of the target test vector based on the operands in the test information, generate a continue execution signal when the test instruction indicates a result matching operation, and send the target number of executions, the target test vector, the continue execution signal and the test information to the running module. The running module is used to control the cyclic execution of the result matching operation when the test instruction indicates the result matching operation, wherein the number of times the result matching operation is executed in the loop does not exceed the target number of executions, and each execution of the result matching operation includes: acquiring the actual vector output by the device under test, and determining the matching result based on the actual vector and the expected vector in the target test vector, wherein the matching result includes: the actual vector and the expected vector are successfully matched, or the actual vector and the expected vector are not successfully matched; The result module is used to count the number of times the result matching operation is performed, compare the current number of executions with the target number of executions, and determine the test result based on the matching result, wherein the test result includes successful matching and failed matching.

10. The test board according to claim 9, characterized in that, The test information includes timing parameters and operands. The running module includes a running sub-module and a PE module connected to each other. The running sub-module is connected to the reading module and the result module. The PE module is connected to the device under test. The running submodule is used to receive the target number of executions, the target test vector, the continue execution signal and the test information, and transmit the target number of executions to the result module, generate timing information based on the timing parameters, and transmit the target test vector and the timing information to the PE module; The PE module is used to perform result matching operations cyclically based on the target test vector and the timing information, and transmit the matching results to the result module via the running submodule.

11. The test board according to claim 9 or 10, characterized in that, The test board is also equipped with a storage module; The result module is also used to transmit the test results to the storage module; The storage module is used to store the test results.

12. The test board according to claim 9 or 10, characterized in that, The test board is also equipped with a microinstruction module; the result module is connected to the microinstruction module, and the microinstruction module is connected to the cache module; The microinstruction module is used to retrieve the target test vector and the corresponding microinstruction, timing parameters, channel information, and operands from the memory; determine the test information based on the timing parameters and the operands; determine the test instruction based on the microinstruction; and send the target test vector, the test instruction, the test information, and the channel information to the cache module. The microinstruction includes a result matching instruction, a normal instruction, or a loop instruction. And when receiving the test results transmitted by the result module, stop performing the result matching operation and obtain the next target test vector.

13. The test board according to claim 12, characterized in that, The caching module is also used to cache the preset state corresponding to the pin that executes the target test vector when the test result is determined to be a matching failure; The running module is further configured to, upon receiving the next target test vector, set the corresponding pin of the next target test vector to the preset state based on the preset state of the pin stored in the cache module.

14. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor is configured to execute a computer program stored in the memory, wherein when the computer program is executed, it implements the chip testing method according to any one of claims 1-8.

Images