Parallel acceleration method of multi-dominant-display-point self-focusing algorithm based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a parallel acceleration method for a multi-dominant-display-point self-focusing algorithm based on an FPGA (Field Programmable Gate Array), which is applied to the FPGA and comprises the following steps of: reading radar echo data according to an azimuth direction; after the normalized amplitude variance of each distance unit is calculated according to the radar echo data, a plurality of dominant display point units are screened based on the normalized amplitude variance of each distance unit; calculating the weight of each special display point unit; outputting complex phase history data according to the current azimuth unit data and the previous azimuth unit data in each distance unit based on the radar echo data; performing weighted summation on the complex phase history data along the distance direction according to all the dominant display point units and the weight of each dominant display point unit to obtain one-dimensional complex phase history data; calculating a compensation phase based on the one-dimensional complex phase history data; and the radar echo data is compensated by using the compensation phase, so that the multi-dominant-point self-focusing algorithm which is high in calculation efficiency, high in real-time performance and capable of effectively reducing the time complexity is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of radar, and particularly relates to a parallel acceleration method of a multi-characteristic-point self-focusing algorithm based on FPGA (Field Programmable Gate Array). BACKGROUND

[0002] Inverse Synthetic Aperture Radar (ISAR) imaging technology has an irreplaceable strategic value in target detection and identification in complex scenes due to its unique all-weather, all-day, long-range and high-resolution imaging characteristics. The improvement of ISAR imaging resolution is generally achieved by increasing the radar signal bandwidth and synthetic aperture time, for example, the bandwidth of the Haystack radar has been successfully upgraded to 8 GHz in 2010. These methods will cause a dramatic increase in radar echo data, reducing the signal processing speed and ISAR imaging efficiency. At present, ISAR is widely used for precise imaging of high-speed maneuvering targets, especially in scenes where the target motion trajectory is unknown or has non-cooperative motion. However, the complex motion of the target in such scenes will introduce phase errors, causing the final image to be blurred and seriously affecting the imaging quality. The key technology for phase error compensation, the self-focusing algorithm, mainly has two levels of bottlenecks: Firstly, at the algorithm level, the traditional characteristic-point self-focusing method usually relies on a single ideal isolated scattering point for phase estimation and compensation, but in actual applications, it is often difficult to find an ideal scattering point that meets the conditions in the target scene, resulting in limited applicability and low compensation accuracy of the traditional method.

[0003] Secondly, at the hardware implementation level, the existing self-focusing implementation based on general-purpose processors such as CPU (Central Processing Unit) or GPU (Graphics Processing Unit) and DSP (Digital Signal Processing) has high processing delay, large resource consumption, and difficulty in meeting real-time requirements, which limits its application in embedded or high-speed imaging systems.

[0004] Therefore, under the dual pressure of large data volume brought by high-resolution requirements and real-time requirements of high-speed maneuvering target scenes, how to break through the algorithm limitations and hardware bottlenecks and provide a multi-characteristic-point self-focusing algorithm parallel acceleration method with high computing efficiency, strong real-time performance and effective time complexity reduction has become a problem to be solved. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a parallel acceleration method of a multi-characteristic-point autofocusing algorithm based on FPGA.

[0006] The technical problem to be solved by the application is solved by the following technical scheme: In a first aspect, the application provides a parallel acceleration method of a multi-characteristic-point autofocusing algorithm based on FPGA, applied to FPGA, and comprising the following steps: reading radar echo data in the azimuth direction; After calculating the normalized amplitude variance of each range cell based on the radar echo data, screening a plurality of characteristic-point cells based on the normalized amplitude variance of each range cell, and calculating the weight of each characteristic-point cell; Based on the radar echo data, outputting complex phase history data according to the current azimuth cell data and the last azimuth cell data in each range cell; Performing weighted summation on the complex phase history data along the range direction according to all the characteristic-point cells and the weight of each characteristic-point cell, to obtain one-dimensional complex phase history data; Calculating compensation phase based on the one-dimensional complex phase history data; Compensating the radar echo data by using the compensation phase, to complete autofocusing processing.

[0007] Optionally, before reading the radar echo data in the azimuth direction, the parallel acceleration method further comprises: Performing envelope alignment processing on the radar echo data.

[0008] Optionally, performing weighted summation on the complex phase history data along the range direction according to all the characteristic-point cells and the weight of each characteristic-point cell, to obtain one-dimensional complex phase history data, comprises: Performing weighted summation on the complex phase history data along the range direction according to all the characteristic-point cells and the weight of each characteristic-point cell by using the weighted least square method, to obtain one-dimensional complex phase history data.

[0009] Optionally, calculating compensation phase based on one-dimensional complex phase history data, comprises: Calculating quasi-compensation phase history based on one-dimensional complex phase history data; Calculating the accumulation of quasi-compensation phase history, to obtain compensation phase.

[0010] Optionally, calculating quasi-compensation phase history based on one-dimensional complex phase history data, comprises: Performing modulus value operation on one-dimensional complex phase history data, to obtain one-dimensional complex modulus value; Dividing the one-dimensional complex phase history data by the one-dimensional complex modulus value, to obtain quasi-compensation phase history.

[0011] Optionally, the manner of calculating the weight of each salient point unit comprises: ; wherein, represents the weight of the i-th salient point unit; represents the normalized amplitude variance of the i-th salient point unit; represents the normalized amplitude variance of the i-th salient point unit; , represents the total number of salient point units.

[0012] In a second aspect, the present application provides a parallel acceleration device of a multi-salient point autofocusing algorithm based on FPGA, which is applied to FPGA, and the parallel acceleration device comprises: a reading module, configured to read radar echo data in an azimuth direction; a first calculation module, configured to filter a plurality of salient point units based on the normalized amplitude variance of each range cell after calculating the normalized amplitude variance of each range cell according to the radar echo data, and calculate the weight of each salient point unit; an output module, configured to output complex phase history data according to the current azimuth cell data and the last azimuth cell data in each range cell based on the radar echo data; a weighted summation module, configured to perform weighted summation on the complex phase history data along the range direction according to all salient point units and the weight of each salient point unit, to obtain one-dimensional complex phase history data; a second calculation module, configured to calculate a compensation phase based on the one-dimensional complex phase history data; a compensation module, configured to compensate the radar echo data by using the compensation phase, to complete autofocusing processing.

[0013] In a third aspect, the present application provides an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus; the memory, configured to store a computer program; the processor, configured to execute the computer program stored on the memory, to realize the method steps of any one of the parallel acceleration methods of the multi-salient point autofocusing algorithm based on FPGA.

[0014] In a fourth aspect, the present application provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the method steps of any one of the parallel acceleration methods of the multi-salient point autofocusing algorithm based on FPGA.

[0015] ​The parallel acceleration method for the multi-attribute point autofocusing algorithm based on FPGA provided by the application is applied to FPGA, a pipeline architecture based on FPGA and a multi-path parallel processing mechanism are used to divide a complex data processing task into multiple parallel execution stages, the hardware-level parallel computing capability and the timing controllable characteristics of FPGA are fully utilized, and the data throughput rate and processing efficiency of the system are significantly improved, so that the overall real-time response capability is effectively enhanced.

[0016] The screening of the attribute point unit and the weight calculation of the attribute point unit are synchronized, the compensation phase calculation can be completed through a single traversal of the imaging data, the time complexity is effectively reduced, and the real-time processing performance of the system is improved.

[0017] In addition, compared with the traditional CPU and GPU implementation mode, the FPGA has higher hardware resource utilization and energy efficiency ratio while meeting the high performance requirement, through reasonable design of logic resource allocation and data flow scheduling, the dependence on external high-speed storage and complex control unit is reduced, the system power consumption and hardware overhead are reduced, and the FPGA has higher cost performance and engineering application advantages.

[0018] The application will be further described in detail below with reference to the accompanying drawings and the application. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a flowchart of the parallel acceleration method for the multi-attribute point autofocusing algorithm based on FPGA provided by the embodiment of the application; Figure 2 is an algorithm implementation flowchart of the parallel acceleration method for the multi-attribute point autofocusing algorithm based on FPGA provided by the embodiment of the application; Figure 3 is a result comparison diagram of the autofocusing algorithm processing of different algorithm platforms; Figure 4 is a structural diagram of an electronic device provided by the embodiment of the application. DETAILED DESCRIPTION

[0020] The application will be further described in detail below with reference to the accompanying drawings and the application.

[0021] In order to solve the problems of low calculation efficiency, poor real-time performance and high time complexity of the existing autofocusing algorithm, the embodiment of the application provides a parallel acceleration method for a multi-attribute point autofocusing algorithm based on FPGA, as shown in Figure 1 , Figure 1 is a flowchart of the parallel acceleration method for the multi-attribute point autofocusing algorithm based on FPGA provided by the embodiment of the application, the parallel acceleration method for the multi-attribute point autofocusing algorithm is applied to FPGA, and specifically includes the following steps: Step S101: Read radar echo data according to azimuth.

[0022] Since there may be relative motion between the radar and the target, this can cause a time delay in the received echo signal. To address this issue, in this embodiment of the invention, before reading the radar echo data in the azimuth direction, the parallel acceleration method further includes: Envelope alignment is performed on the radar echo data.

[0023] In this embodiment of the invention, envelope alignment processing aims to compensate for signal variations caused by relative motion, ensuring that echoes received from different time periods are correctly aligned. Envelope alignment processing typically includes motion compensation, envelope extraction, and time delay correction.

[0024] In this embodiment of the invention, the radar echo data after envelope alignment processing, i.e., the unfocused HRRP (High Resolution Range Profile) data, can be stored in DDR4 (Double Data Rate), where DDR4 is a double data rate fourth-generation synchronous dynamic random access memory.

[0025] In this embodiment of the invention, the envelope-aligned radar echo data is as follows: ; in, Indicates the first Within the nth distance unit, the nth The envelope-aligned radar echo data under each azimuth cell is represented as the envelope-aligned radar echo transverse sequence. Indicates the first Scattering point coefficients per distance unit; Represents the imaginary unit; Indicates the first The initial phase of each distance unit; Indicates the first The horizontal spacing of each distance unit; Indicates the first Within the nth distance unit, the nth Phase modulation caused by noise in each azimuth unit; Indicates the first Each echo has a random initial phase value; , This indicates the azimuth unit, i.e., the total number of echoes.

[0026] Step S102: After calculating the normalized amplitude variance of each range cell based on the radar echo data, select multiple prominent point cells based on the normalized amplitude variance of each range cell; and calculate the weight of each prominent point cell.

[0027] Assumed distance unit For isolated scattering points, take them as the center of the turntable model, that is . The echo of the isolated scattering point can be expressed as: ; Wherein, represents the envelope-aligned radar echo data under the first th azimuth unit in the first th distance unit; represents the scattering point coefficient of the first th distance unit; represents the starting phase of the first th distance unit; represents the noise-induced phase modulation under the first th azimuth unit in the first th distance unit; , represents the azimuth unit, that is, the total number of echoes; The phase offset is: ; Obviously, the echo sequence amplitude of the feature point is only affected by the clutter and noise, and the amplitude fluctuation is small. Based on this feature, the feature point is found.

[0028] In the embodiment of the application, the feature point can be measured by normalizing the amplitude variance, which is defined as: ; Wherein, the horizontal line above the symbol in the formula represents taking the average value of each element in the distance unit; represents the normalized amplitude variance of the first th distance unit; represents the square of the mean value of the echo sequence amplitude of the first th distance unit; represents the mean square value of the first th distance unit.

[0029] Specifically, the envelope-aligned radar echo data in the DDR4 can be read in the azimuth direction, 16-way data is read in parallel, and the normalized amplitude variance is calculated.

[0030] In the embodiment of the application, a threshold is set, and when the normalized amplitude variance of a certain distance unit is less than the threshold, the distance unit is regarded as a feature point unit. Wherein, the threshold , the value can be set by the person skilled in the art according to experience, which is not limited here.

[0031] In the embodiment of the present application, it is assumed that, after screening by the special point unit, the first distance unit is the special point unit, and there are K special point units in total.

[0032] The weight of each special point unit is calculated according to the normalized amplitude variance of each special point unit, as follows: wherein, w k represents the weight of the kth special point unit; σ k represents the normalized amplitude variance of the kth special point unit; and K represents the total number of special point units.

[0033] In step S103, based on the radar echo data, the complex phase history data is output according to the current azimuth unit data and the previous azimuth unit data in each distance unit.

[0034] In view of the fact that it is difficult to obtain an ideal isolated scattering point in an actual scene, in the embodiment of the present application, a plurality of special points are screened and weighted, and the corresponding phase offset is jointly estimated, so as to realize effective phase compensation in the case of lacking a single ideal scattering point.

[0035] The radar echo data is read in parallel, the current azimuth unit under the first distance unit, i.e., the first azimuth unit data, is conjugated with the previous azimuth unit, i.e., the second azimuth unit data, to obtain complex phase history data

[0036] Specifically, the envelope-aligned radar echo data in the DDR4 is read in parallel in the azimuth direction, 16-way data is read in parallel, the previous data is conjugated (the high bit of the imaginary part is inverted), and the current data is multiplied by the previous data by using a Mult IP core. ​​​​​​​​​​​​​​​​​​​​​​​​multiplication of the conjugate of the complex phase history data .

[0037] In step S104, the complex phase history data is weighted and summed along the distance direction according to all the special point units and the weight of each special point unit, to obtain one-dimensional complex phase history data.

[0038] In the embodiment of the present application, the complex phase history data is weighted and summed along the distance direction according to all the special point units and the weight of each special point unit, to obtain one-dimensional complex phase history data, including: The complex phase history data is weighted and summed along the distance direction according to all the special point units and the weight of each special point unit by using the weighted least square method, to obtain one-dimensional complex phase history data.

[0039] The specific calculation method is as follows: ; wherein, the one-dimensional complex phase history data of the i th azimuth unit is represented as .

[0040] After obtaining the one-dimensional complex phase history data, the one-dimensional complex phase history data is continuously transmitted backward to perform the calculation in step S105, and is stored in the FIFO (First Input First Output) IP core.

[0041] In step S105, the compensation phase is calculated based on the one-dimensional complex phase history data.

[0042] In the embodiment of the present application, the compensation phase is calculated based on the one-dimensional complex phase history data, including: The quasi-compensation phase history is calculated based on the one-dimensional complex phase history data; The accumulation of the quasi-compensation phase history is calculated to obtain the compensation phase.

[0043] In one implementation, the quasi-compensation phase history is calculated based on the one-dimensional complex phase history data, including: The one-dimensional complex phase history data is subjected to a modulus operation to obtain one-dimensional complex modulus; The one-dimensional complex phase history data is divided by the one-dimensional complex modulus to obtain the quasi-compensation phase history.

[0044] In the embodiment of the present application, the one-dimensional complex phase history data can be subjected to the modulus operation by using the Cordic IP core to obtain the one-dimensional complex modulus.

[0045] ​​​Then, the one-dimensional complex phase history data in the FIFO IP core is divided by the one-dimensional complex modulus by using the Divder IP core to obtain the quasi-compensation phase history.

[0046] In the embodiment of the present application, the accumulation of the quasi-compensation phase history is calculated by using the Accumulator IP core to obtain the compensation phase.

[0047] In the embodiment of the present application, the compensation phase is: ; wherein, denotes the imaginary unit; denotes the azimuth index, , denotes the azimuth unit; In step S106, the radar echo data is compensated by using the compensation phase to complete the autofocusing processing.

[0048] In the embodiment of the present application, the in the DDR4 is read in parallel according to the azimuth direction, 16-way data is read in parallel, and the multiplication of and is calculated by using the Mult IP core to obtain the focusing data corresponding to the m-th azimuth unit, and the image autofocusing processing is completed. The specific calculation process is as follows: ; wherein, is the conjugate data obtained by taking the inverse of the highest bit of the imaginary part of the data.

[0049] In the embodiment of the present application, the multi-feature point autofocusing algorithm parallel acceleration method is applied to the FPGA. Based on the pipeline architecture and the multi-way parallel processing mechanism of the FPGA, the complex data processing task is divided into multiple parallel execution stages. The FPGA hardware level parallel computing capability and the timing controllable characteristics are fully utilized to significantly improve the data throughput rate and the processing efficiency of the system, thereby effectively enhancing the overall real-time response capability.

[0050] The screening of the feature point unit and the weight calculation of the feature point unit are obtained synchronously, the compensation phase calculation can be completed by single traversal of the imaging data, the time complexity is effectively reduced, and the real-time processing performance of the system is improved.

[0051] In addition, compared with traditional CPU and GPU implementation, FPGA has higher hardware resource utilization and energy efficiency ratio while meeting high performance requirements. By reasonably designing logical resource allocation and data flow scheduling, the dependence on external high-speed storage and complex control unit is reduced, and the system power consumption and hardware overhead are also reduced, so that the method has higher cost performance and engineering application advantages.

[0052] Referring to Figure 2 , Figure 2 is an algorithm implementation flowchart of a parallel acceleration method of a multi-echo-point self-focusing algorithm based on FPGA provided by the embodiment of the application, envelope-aligned radar echo data is input into a data distributor in the azimuth direction, 16-way data is read in paths 1, 2 and 3 in parallel, in path 1, the steps of calculating the normalized amplitude variance, marking the echo-point unit and calculating the weight of the echo-point unit are performed, in path 2, based on the radar echo data, the complex phase history data is output according to the current azimuth cell data and the previous azimuth cell data in each range cell, then the data of path 2 is weighted and summed along the range direction according to the echo-point unit in path 1 and the weight of the echo-point unit, one-dimensional complex phase history data is obtained, and the one-dimensional complex phase history data is subjected to a modulus value operation and stored in a FIFO in one way, in path 3, the one-dimensional complex phase history data in the FIFO IP core is divided by the one-dimensional complex modulus value to obtain the quasi-compensated phase history, and the quasi-compensated phase history is accumulated to obtain the compensated phase, then the radar echo data and the compensated phase subjected to a conjugate operation are subjected to a complex multiplication operation, and the focusing data is output, thereby completing the self-focusing processing.

[0053] In addition, the parallel acceleration method of the multi-echo-point self-focusing algorithm provided by the embodiment of the application can dynamically configure the number of parallel processing paths according to the actual available hardware resources on the basis of the hardware implementation based on FPGA. For example, when the resources are sufficient, the parallel degree is increased to improve the processing speed, and when the resources are limited, the number of parallel paths is reduced to optimize the area overhead, so that a flexible trade-off between performance and cost is realized.

[0054] The data flow of each processing stage can be uniformly organized into an azimuth direction continuous structure to support efficient pipeline operation; alternatively, the data flow can be uniformly arranged in the range direction, and the pipeline processing architecture is also realized. Both the above two methods can effectively improve the system throughput, and the optimal implementation form is selected according to the specific application scenario.

[0055] The simulation experiment of the parallel acceleration method of the multi-echo-point self-focusing algorithm based on FPGA provided by the embodiment of the application is as follows: Referring to Figure 3 , Figure 3 is a comparison diagram of the results of the self-focusing algorithm processing of different algorithm platforms, Figure 3(a) in FIG. 1 is an ISAR image without focusing processing, Figure 3 (b) in FIG. 1 is a result of FPGA platform processing, Figure 3 (c) in FIG. 1 is a result of CPU platform processing, Figure 3 (d) in FIG. 1 is a result of GPU platform processing. Comparison Figure 3 (a) in FIG. 1 and Figure 3 (b) in FIG. 1, it can be seen that the FPGA platform running the multi- feature point self-focusing algorithm can effectively realize image focusing, verifying the feasibility and correctness of the algorithm on the hardware platform.

[0056] Comparison Figure 3 (b), (c) and (d) in FIG. 1, it can be seen that the imaging results obtained by the multi- feature point self-focusing algorithm on different processing platforms such as FPGA, CPU and GPU are completely consistent, which further verifies the feasibility and correctness of the algorithm on the FPGA hardware platform.

[0057] Referring to Table 1, Table 1 shows the real-time comparison of different processing platforms such as FPGA, CPU and GPU: Table 1 Real-time comparison

[0058] The results shown in Table 1 show that, compared with the CPU and GPU platforms, the FPGA platform exhibits significant acceleration effect in algorithm running efficiency, highlighting its advantages in high-performance computing and real-time processing applications.

[0059] Based on the same inventive concept, the embodiments of the present application also provide a parallel acceleration device of a multi- feature point self-focusing algorithm based on FPGA, applied to FPGA, the parallel acceleration device of the multi- feature point self-focusing algorithm comprises: The reading module is configured to read radar echo data in an azimuth direction; The first calculation module is configured to calculate the normalized amplitude variance of each range cell based on the radar echo data, filter a plurality of feature point cells based on the normalized amplitude variance of each range cell, and calculate the weight of each feature point cell; The output module is configured to output complex phase history data based on the current azimuth cell data and the previous azimuth cell data in each range cell based on the radar echo data; The weighted summation module is configured to perform weighted summation on the complex phase history data along the range direction according to all feature point cells and the weight of each feature point cell, to obtain one-dimensional complex phase history data; The second calculation module is configured to calculate a compensation phase based on the one-dimensional complex phase history data; The compensation module is configured to compensate the radar echo data using the compensation phase to complete self-focusing processing.

[0060] In the embodiment of the present application, the multi-feature point self-focusing algorithm parallel acceleration method is applied to the FPGA. Based on the pipeline architecture and multi-path parallel processing mechanism of the FPGA, the complex data processing task is divided into multiple parallel execution stages. The FPGA hardware level parallel computing capability and timing controllable characteristics are fully utilized to significantly improve the data throughput rate and processing efficiency of the system, thereby effectively enhancing the overall real-time response capability.

[0061] The screening of the feature point unit and the weight calculation of the feature point unit are synchronized, and the compensation phase calculation can be completed by a single traversal of the imaging data, effectively reducing the time complexity and improving the real-time processing performance of the system.

[0062] In addition, compared with the traditional CPU and GPU implementation, the FPGA has higher hardware resource utilization and energy efficiency while meeting high performance requirements. By reasonably designing the logic resource allocation and data flow scheduling, the dependence on external high-speed storage and complex control units is reduced, and the system power consumption and hardware overhead are also reduced, which has higher cost performance and engineering application advantages.

[0063] Optionally, the multi-feature point self-focusing algorithm parallel acceleration device further comprises a processing module. The processing module is configured to perform envelope alignment processing on the radar echo data before reading the radar echo data in the direction.

[0064] Optionally, the weighted summation module is specifically configured to: The weighted least squares method is used to perform weighted summation on the complex phase history data along the distance direction according to all feature point units and the weights of the feature point units, to obtain one-dimensional complex phase history data.

[0065] Optionally, the second calculation module is specifically configured to: Calculate the quasi-compensation phase history based on the one-dimensional complex phase history data; and calculate the accumulation of the quasi-compensation phase history to obtain the compensation phase.

[0066] Optionally, the second calculation module calculates the quasi-compensation phase history based on the one-dimensional complex phase history data, and the calculation includes: Perform a modulo operation on the one-dimensional complex phase history data to obtain one-dimensional complex modulus; Divide the one-dimensional complex phase history data by the one-dimensional complex modulus to obtain the quasi-compensation phase history.

[0067] Optionally, the way of calculating the weight of each feature point unit includes: ; Wherein, represents the weight of the i-th feature point unit. a weight of the i-th feature point unit; a normalized amplitude variance of the i-th feature point unit; a normalized amplitude variance of the i-th feature point unit; a total number of the feature point units.

[0068] The embodiment of the present application further provides an electronic device, as shown in the figure, comprising a processor 401, a communication interface 402, a memory 403 and a communication bus 404, wherein the processor 401, the communication interface 402 and the memory 403 complete mutual communication through the communication bus 404, Figure 4 the memory 403 is used for storing a computer program; the processor 401 is used for executing the program stored in the memory 403, and realizing the method steps of the parallel acceleration method of the FPGA-based multi-feature point self-focusing algorithm.

[0069] The communication bus mentioned in the above electronic device can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used to represent in the figure, but it does not represent that there is only one bus or only one type of bus.

[0070] The communication interface is used for communication between the above electronic device and other devices.

[0071] The memory can comprise a random access memory (RAM) and can also comprise a non-volatile memory (NVM), for example at least one disk memory. Optionally, the memory can also be at least one storage device located away from the aforementioned processor.

[0072] ​​The processor described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0073] The application further provides a computer readable storage medium. The computer readable storage medium stores a computer program. When the computer program is executed by a processor, the method steps of the parallel acceleration method of the multi-point self-focusing algorithm based on FPGA are implemented.

[0074] Optionally, the computer readable storage medium can be a non-volatile memory (NVM), for example, at least one disk memory.

[0075] Optionally, the computer readable storage medium can also be at least one storage device located away from the processor.

[0076] In another embodiment of the application, a computer program product containing instructions, which, when run on a computer, causes the computer to perform the method steps of the parallel acceleration method of the multi-point self-focusing algorithm based on FPGA.

[0077] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the application. Rather, they are merely examples of devices and methods consistent with some aspects of the application.

[0078] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the description of the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in the specification.

[0079] Although the present application is described herein in conjunction with various embodiments, those skilled in the art, with reference to the drawings and the disclosure, can understand and implement other variations of the disclosed embodiments in the implementation of the claimed application. In the description of the present application, the word "comprising" does not exclude other components or steps, "one" or "an" does not exclude a plurality, and "plurality" means two or more, unless otherwise explicitly specified. In addition, some measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0080] The method provided by the embodiments of the present application can be applied to electronic devices. Specifically, the electronic device can be: desktop computer, portable computer, smart mobile terminal, server, etc. Herein, any electronic device that can implement the present application belongs to the protection scope of the present application.

[0081] For device / electronic device / storage medium embodiments, because they are basically similar to method embodiments, the description is relatively simple, and the relevant part can be referred to the part of the method embodiment.

[0082] It should be noted that the device, electronic device and storage medium of the embodiments of the present application are respectively the device, electronic device and storage medium of the above-mentioned one parallel acceleration method based on FPGA multi-attribute point self-focusing algorithm, and all embodiments of the above-mentioned one parallel acceleration method based on FPGA multi-attribute point self-focusing algorithm are applicable to the device, electronic device and storage medium, and can achieve the same or similar beneficial effects.

[0083] The above is a further detailed description of the present application in combination with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be regarded as falling within the protection scope of the present application.

Claims

1. A parallel acceleration method of a multi-point self-focusing algorithm based on FPGA, characterized in that, The parallel acceleration method comprises the following steps when applied to an FPGA: reading radar echo data in the azimuth direction; screening a plurality of significant point units based on the normalized amplitude variance of each distance unit after calculating the normalized amplitude variance of each distance unit according to the radar echo data; and calculating the weight of each significant point unit; outputting complex phase history data according to the current azimuth unit data and the previous azimuth unit data in each distance unit based on the radar echo data; performing weighted summation on the complex phase history data along the distance direction according to all significant point units and the weight of each significant point unit to obtain one-dimensional complex phase history data; calculating compensation phase based on the one-dimensional complex phase history data; compensating the radar echo data by using the compensation phase to complete self-focusing processing.

2. The parallel acceleration method of claim 1, wherein, Before reading the radar echo data in the azimuth direction, the parallel acceleration method further comprises the following steps: performing envelope alignment processing on the radar echo data.

3. The parallel acceleration method of claim 1, wherein, performing weighted summation on the complex phase history data along the distance direction according to all significant point units and the weight of each significant point unit to obtain one-dimensional complex phase history data, which comprises the following steps: performing weighted summation on the complex phase history data along the distance direction according to all significant point units and the weight of each significant point unit to obtain one-dimensional complex phase history data by using the weighted least square method.

4. The parallel acceleration method of claim 1, wherein, calculating compensation phase based on one-dimensional complex phase history data, which comprises the following steps: calculating a quasi-compensation phase history based on one-dimensional complex phase history data; calculating the accumulation of the quasi-compensation phase history to obtain the compensation phase.

5. The parallel acceleration method of claim 4, wherein, calculating a quasi-compensation phase history based on one-dimensional complex phase history data, which comprises the following steps: performing a modulo operation on the one-dimensional complex phase history data to obtain one-dimensional complex modulus; dividing the one-dimensional complex phase history data by the one-dimensional complex modulus to obtain the quasi-compensation phase history.

6. The parallel acceleration method of claim 1, wherein, The manner of calculating the weight of each significant point unit comprises the following steps: ； wherein, represents the weight of the i-th salient point unit; represents the normalized amplitude variance of the i-th salient point unit; , represents the total number of salient point units.​​ 7. A parallel acceleration device for multi-focal spot self-focusing algorithm based on FPGA, characterized in that, The parallel acceleration device comprises the following steps when applied to an FPGA: a reading module, configured to read radar echo data in the azimuth direction; a first calculation module, configured to screen a plurality of significant point units based on the normalized amplitude variance of each distance unit after calculating the normalized amplitude variance of each distance unit according to the radar echo data; and calculate the weight of each significant point unit; an output module, configured to output complex phase history data according to the current azimuth unit data and the previous azimuth unit data in each distance unit based on the radar echo data; a weighted summation module, configured to perform weighted summation on the complex phase history data along the distance direction according to all significant point units and the weight of each significant point unit to obtain one-dimensional complex phase history data; a second calculation module, configured to calculate compensation phase based on the one-dimensional complex phase history data; a compensation module, configured to compensate the radar echo data by using the compensation phase to complete self-focusing processing.

8. The parallel acceleration device of claim 7, wherein, The parallel acceleration device further comprises a processing module. The processing module is configured to perform envelope alignment processing on the radar echo data before reading the radar echo data in the azimuth direction.

9. An electronic device, comprising: The device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus. a memory for storing a computer program; a processor for implementing the parallel acceleration method of the multi-attribute point self-focusing algorithm based on FPGA according to any one of claims 1-6 when executing the computer program stored on the memory.

10. A computer-readable storage medium, characterized in that, The computer program is stored in the computer readable storage medium, and the computer program is executed by the processor to implement the parallel acceleration method of the multi-attribute point self-focusing algorithm based on FPGA according to any one of claims 1-6.

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