Fragment reassembly buffer storage method

Abstract

The application discloses a method for fragment reorganization buffer storage, which comprises the following steps: analyzing a link layer data frame to obtain sideband information in the link layer data frame, generating a write enable mask signal of at least one FLIT data packet based on the sideband information, and then writing the at least one FLIT data packet into a target buffer; determining a current data packet to be read out from the FLIT data packet and obtaining a write start address in the target buffer and a read pointer of the current data packet to be read out; and reading out the current data packet to be read out from the target buffer under the condition that a preset reading condition is satisfied. The method solves the problems of linear growth of resources with the number of accelerators, large consumption of hardware resources, increased communication delay of cache and shift output, and the like, and realizes instant splicing of data through a single buffer mechanism, a variable addressing pointer and parallel readout control logic, thereby saving storage resources and reducing link reorganization delay.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer and data processing, and particularly relates to a fragmentation reorganization buffer storage method. BACKGROUND

[0002] With the rapid development of artificial intelligence, big data analysis and other applications, the heterogeneous computing architecture of CPU (Central Processing Unit) and GPU (Graphics Processing Unit) and FPGA (Field-Programmable Gate Array) accelerator collaborative work has become the mainstream scheme to improve the computing power. FLIT (Flow Control Unit) is the basic unit of link layer flow control, which replaces the traditional variable-length data packet to reduce the protocol overhead. In order to improve the utilization rate of physical link, a FLIT packet is often split into multiple SLOTs (time slots) and transmitted through multiple logical channels.

[0003] In the related art, the "multi-buffer strategy" is generally used, that is, a dedicated buffer is set for each type of FLIT data packet. However, in the above scheme, when the number of interconnected accelerators increases, the required buffer resources increase exponentially, resulting in high manufacturing cost, and also increasing the communication delay of SLOT in the process of caching and shifting output in the buffer. It is urgent to solve. SUMMARY

[0004] The present application provides a fragmentation reorganization buffer storage method to at least solve the problems of linear growth of related art resources with the number of accelerators in the related art, resulting in huge hardware resource consumption, and increasing the communication delay of caching and shifting output.

[0005] The present application provides a fragmentation reorganization buffer storage method, comprising: receiving a link layer data frame and parsing the link layer data frame to obtain sideband information in the link layer data frame; generating a write enable mask signal of at least one FLIT data packet according to the sideband information in the link layer data frame, and writing the at least one FLIT data packet into a target buffer based on the write enable mask signal of the at least one FLIT data packet; determining a current data packet to be read out from the at least one FLIT data packet, obtaining a write start address in the target buffer, and determining a read pointer of the current data packet to be read out, and based on the write start address and the read pointer in the target buffer, determining whether the current data packet to be read out meets a preset reading condition, and reading out the current data packet to be read out from the target buffer when the preset reading condition is met.

[0006] The present application also provides a fragmentation reorganization buffer storage device, comprising:

[0007] receiving a link layer data frame, and parsing the link layer data frame to obtain sideband information in the link layer data frame;

[0008] generating a write enable mask signal of at least one FLIT data packet according to the sideband information in the link layer data frame, and writing the at least one FLIT data packet into a target buffer based on the write enable mask signal of the at least one FLIT data packet;

[0009] determining a current data packet to be read out from the at least one FLIT data packet, obtaining a write start address in the target buffer, determining a read pointer of the current data packet to be read out, and reading out the current data packet to be read out from the target buffer in a case that a preset reading condition is satisfied based on the write start address and the read pointer in the target buffer.

[0010] The application further provides an electronic device, comprising a memory for storing a computer program, and a processor for executing the computer program to implement the steps of any of the slice reorganization buffer storage methods.

[0011] The application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of any of the slice reorganization buffer storage methods.

[0012] The application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps of any of the slice reorganization buffer storage methods.

[0013] According to the application, the sideband information in the link layer data frame is obtained by parsing the link layer data frame, the write enable mask signal of at least one FLIT data packet is generated based on the sideband information, then the at least one FLIT data packet is written into a target buffer, the current data packet to be read out is determined from the FLIT data packet, the write start address in the target buffer and the read pointer of the current data packet to be read out are obtained, and then the current data packet to be read out is read out from the target buffer in a case that a preset reading condition is satisfied. The problems of linear growth of resources with the number of accelerators, large consumption of hardware resources, increased communication delay of cache and shift output, etc. are solved, the data is instantaneously spliced through the single-path buffer mechanism, the variable addressing pointer and the parallel readout control logic, the storage resources are saved, and the link reorganization delay is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following embodiments are only some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0015] Figure 1 The implementation block diagram of the FLIT fragmentation reorganization scheme of the related art;

[0016] Figure 2 The flowchart of the fragmentation reorganization buffer storage method provided by the embodiments of the present application;

[0017] Figure 3 The implementation block diagram of the FLIT fragmentation reorganization scheme according to an embodiment of the present application;

[0018] Figure 4 The relative position diagram of different cycle read-write pointers according to an embodiment of the present application;

[0019] Figure 5 The flowchart of the bit vector polling matching according to an embodiment of the present application;

[0020] Figure 6 The block diagram of the fragmentation reorganization buffer storage device according to the embodiments of the present application;

[0021] Figure 7 The structural diagram of the electronic device according to the embodiments of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the protection scope of the present application.

[0023] It should be noted that, in the description of the present application, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0024] In order to enable the person skilled in the art to better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0025] Embodiments of the present application provide a fragment reassembly buffer storage method. The method is described in detail in combination with the execution process of the fragment reassembly buffer storage method.

[0026] Specifically, before introducing the embodiments of the present application, first introduce the related technical background and the traditional FLIT fragment reassembly scheme. In the interconnection link, FLIT replaces the traditional variable-length data packet, effectively reduces the protocol processing overhead, and solves the timing convergence problem under high bandwidth. High-frequency physical links (such as PCIe (Peripheral Component Interconnect Express) 6.0 using PAM (Pulse Amplitude Modulation) 4 modulation) are limited by pin bandwidth and signal integrity. Therefore, a FLIT packet is usually split into multiple SLOTs for transmission, thereby dividing the physical link into multiple logical channels to achieve finer-grained data scheduling. At the same time, different SLOTs after fragmentation can reuse idle link resources, significantly improving throughput.

[0027] In the multi-accelerator interconnection scenario, the current reassembly of the SLOT after FLIT fragmentation generally adopts a multi-buffer strategy: first, a dedicated buffer is set for different types of FLIT packets. The system parses the effective data of the corresponding channel according to the sideband information carried by the SLOT and stores it in the corresponding buffer. Second, when it is detected that the data accumulation of a certain buffer reaches the total length of the FLIT packet, the complete FLIT packet is shifted out, for example, as shown in Figure 1 The link layer data frame is divided into 3 SLOTs, the FLIT data packet length may span multiple link layer data frames (such as D1 in Figure 1), and multiple FLIT data packets can share the same link layer data frame (such as B1 and C1 in Figure 1). The link layer data frame contains 3 SLOT data frames and related sideband information (such as channel ID (Identifier), valid signal, credit token number, etc.).

[0028] However, although the above method is efficient, when the number of interconnected accelerators increases, the required buffer resources will increase exponentially, and the process of SLOT caching and shifting out also increases the communication delay between accelerators to some extent.

[0029] Therefore, based on the problems in the related art, the embodiment of the present application proposes an efficient FLIT fragmentation reassembly buffer strategy based on an FPGA hardware platform, which discards the traditional multi-way cache mode, adopts a single-way shared dual-port ring buffer to manage all types of FLIT fragmentation data, and combines bit vector identification, variable base address addressing, and single-in multi-out control logic to realize parallel output management of multiple types of FLIT data packets, thereby saving FPGA on-chip storage resources, reducing link reassembly delay, and optimizing timing performance.

[0030] The core working principle is as follows: (1) storage management: based on the SLOT sideband information, the identification vector representing different data types is updated in real time; (2) addressing control: for different types of data streams, the read base address pointer is dynamically addressed and jumped according to the updated identification vector using the Round-Robin polling strategy; (3) state judgment: the effective data amount of the buffer is dynamically determined by real-time calculation of the read-write pointer difference, and whether the complete FLIT data packet has been cached is judged according to the effective data amount, and the corresponding read enable signal is generated, which will be described in detail in combination with specific embodiments.

[0031] Specifically, Figure 2 The fragmentation reassembly buffer storage method provided by the embodiment of the present application comprises the following steps:

[0032] In step S201, a link layer data frame is received, and the link layer data frame is parsed to obtain sideband information in the link layer data frame.

[0033] Specifically, in a high-speed interconnection link, each transmitted slot is accompanied by sideband information, which contains channel ID, valid signal, credit token number, etc. for distinguishing different data streams or data packets, wherein the channel ID represents which type of FLIT data packet the data belongs to, that is, the data type of the FLIT data packet in the link layer data can be obtained based on the sideband information in the link layer data frame, so that the corresponding vector identification can be generated based on the obtained data type of the FLIT data packet.

[0034] In step S202, a write enable mask signal of at least one FLIT data packet is generated according to the sideband information in the link layer data frame, and at least one FLIT data packet is written into a target buffer based on the write enable mask signal of the at least one FLIT data packet.

[0035] Specifically, after the sideband information in the link layer data frame is parsed, valid write enable mask signals can be generated based on the sideband information of the link layer data frame, i.e., the write enable mask signals of at least one FLIT data packet are obtained, the number of the write enable signals is consistent with the number of the corresponding SLOTs of the link layer data frame, then the system writes valid SLOT data into the target buffer according to the sideband information of the link layer data frame in sequence, and multiple SLOT valid data can be written in parallel at one time (for example, two A1s are written in parallel, the third SLOT corresponds to X invalid, and the write mask is not written).

[0036] wherein the number of valid slots can be calculated according to the formula (wptr-rptr_*+depth)%depth, wherein wptr indicates the current write link frame start position, rptr_* indicates the read start position of various types of data frames, and depth is the target buffer depth size.

[0037] In step S203, the current data packet to be read out is determined from the at least one FLIT data packet, the write start address in the target buffer is obtained, the read pointer of the current data packet to be read out is determined, and the current data packet to be read out is read out from the target buffer based on the write start address in the target buffer and the read pointer when the preset reading condition is met.

[0038] According to an embodiment of the present application, the read pointer of the current data packet to be read out is determined, including: obtaining the vector identifier of the current data packet to be read out, and generating the read enable base address of the current data packet to be read out and the position of the read enable base address based on the vector identifier of the current data packet to be read out; generating the mask field of the current data packet to be read out according to the read enable base address and the position of the read enable base address; obtaining the read pointer of the current data packet to be read out according to the mask field of the current data packet to be read out based on the preset bidirectional region matching search strategy.

[0039] According to an embodiment of the present application, the read enable base address of the current data packet to be read out and the position of the read enable base address are generated based on the vector identifier of the current data packet to be read out, including: determining the position of the first preset value as the position of the read enable base address according to a preset selection order based on the vector identifier of the current data packet to be read out; and taking the address of the position of the read enable base address as the read enable base address of the current data packet to be read out.

[0040] wherein the preset bidirectional region matching search strategy can be selected by those skilled in the art based on actual use requirements, which is not specifically limited here.

[0041] Specifically, after obtaining the data type of at least one FLIT data packet in the link layer data, the embodiment of the present application can set an independent vector identifier for different types of FLIT data packets in the link layer data, for example, the FLIT data packet of the embodiment of the present application can include Figure 2 four types of A, B, C and D, and the vector identifier corresponding to each type is Vec_A, Vec_B, Vec_C and Vec_D, the bit width of the vector identifier is equal to the depth of the ring buffer, and initially all the vector identifiers are all 0.

[0042] Further, when the first valid Slot of a FLIT data packet of a certain type is written into the target buffer, the bit position corresponding to the Slot write address in the vector identifier corresponding to the type is 1, that is, when the first Slot of a new FLIT data packet (for example, type B) is written into the target buffer address X, the module sets the Xth bit of Vec_B to '1', marking the beginning of a new packet here.

[0043] Wherein, the target buffer adopts a ring buffer, which is realized by a block memory of FPGA, and the read and write pointers are both extended by 1 bit as flip indication bits for judging whether the read and write operations are in the same cycle period, that is, in the embodiment of the present application, because the buffer is in a loop mode, the read and write pointers are both extended by 1 bit as flip indication bits, if the flip indication bits are the same, the read and write are in the same cycle, if the flip indication bits are different, the read and write are in different cycles.

[0044] Further, in the embodiment of the present application, the read address pointer management module sets an independent read address pointer for each type of FLIT data packet, which points to the starting position of the current FLIT data packet, that is, the read starting pointer of each type of FLIT follows the Round-Robin polling strategy according to the corresponding vector identifier, and the read address pointer management module periodically queries the vector identifier corresponding to each type of FLIT data packet and adopts the preset bidirectional region matching search strategy as shown in Figure 3 , to find the starting position of the next FLIT packet to be read, that is, whenever the FLIT data packet of this type is successfully read out, its read address pointer is updated, and the updating method is: according to the current position, sequentially find the next bit position of 1 from the vector identifier, and point the rptr_* to the position.

[0045] Wherein, the number of read enables of different types of FLIT data packets is consistent with the number of slots corresponding to the type of FLIT (for example, FLIT D corresponds to 5 slots, and the number of read enables corresponding to the type of FLIT is 5), and the address step corresponding to the read enable of the same type of FLIT is incremented.

[0046] Specifically, as shown in Figure 4

[0047] Thus, the "determining the read pointer of the current data packet to be read out" serves as a core bridge connecting the single-buffer shared storage and the efficient, low-latency, and fair scheduling of the multiple data streams. At this time, the system determines the read pointer position of the next FLIT packet to be read out through the query vector identifier and the polling strategy. This means that different types of FLIT packets can be alternately stored in the shared storage space without interfering with each other, and can be correctly positioned and taken out. Meanwhile, the read control module generates a set of continuous and step-incremental addresses based on the determined read pointer, thereby controlling the buffer to output multiple slots in parallel in one clock cycle, so as to realize accurate and on-demand parallel readout control.

[0048] According to an embodiment of the present application, after determining the read pointer of the current data packet to be read out, the method further includes: calculating a second difference value between the write start address in the target buffer and the read pointer; obtaining the number of valid slots of the current data packet to be read out based on the second difference value; determining whether the second difference value is greater than or equal to the number of valid slots of the current data packet to be read out; and determining that the preset read condition is met if the second difference value is greater than or equal to the number of valid slots of the current data packet to be read out.

[0049] According to an embodiment of the present application, the number of valid slots of the current data packet to be read out is obtained based on the second difference value, including: obtaining a buffer depth value of the target buffer; calculating a sum value of the second difference value and the buffer depth value; and performing a modulo operation on the sum value and the buffer depth value to obtain the number of valid slots of the current data packet to be read out.

[0050] Specifically, in the embodiment of the present application, one FLIT data packet can contain multiple slots, and the valid slot can be only a part of them, as shown in Figure 3

[0051] ​​Thus, by calculating the effective number of slots in real time and comparing it with the preset threshold (the total number of slots required by the FLIT type), the module can accurately know when a complete FLIT package is ready, thereby triggering the read operation in the first time, thereby eliminating the protocol overhead and uncertainty in the judgment logic, and realizing an extremely low-delay triggering mechanism.

[0052] According to one embodiment of the present application, the mask field of the current data packet to be read out is generated according to the read enable base address and the position of the read enable base address, comprising: obtaining an initial mask according to the read enable base address of the current data packet to be read out; determining a high-bit mask of the mask field of the current data packet to be read out and a low-bit mask of the current data packet to be read out according to the initial mask; and obtaining the mask field of the current data packet to be read out according to the high-bit mask of the mask field of the current data packet to be read out and the low-bit mask of the current data packet to be read out.

[0053] According to one embodiment of the present application, the high-bit mask of the mask field of the current data packet to be read out and the low-bit mask of the current data packet to be read out are determined according to the initial mask, comprising: judging whether the initial mask is all the second preset value; if the initial mask is not all the second preset value, calculating a first difference value between the low-bit mask of the initial mask and the fourth preset value, and taking the first difference value as the low-bit mask of the current data packet to be read out, and taking the complement of the high-bit mask of the initial mask as the high-bit mask of the current data packet to be read out.

[0054] According to one embodiment of the present application, after judging whether the initial mask is all the second preset value, further comprising: if the initial mask is not all the second preset value, calculating a first difference value between the low-bit mask of the initial mask and the fourth preset value, and taking the first difference value as the low-bit mask of the current data packet to be read out, and taking the complement of the high-bit mask of the initial mask as the high-bit mask of the current data packet to be read out.

[0055] Specifically, different types of vector identifiers Vec_* select the position of the first bit with value 1 from low bit to high bit, to generate the initial mask of the read enable base address, i.e. the mask field. For example, if Vec_B is 00100100, the first FLIT B read base address is 0010, and the second FLIT B read base address is 0101. The bit vector polling control flow is shown in Figure 5 According to the current read base address position, the corresponding mask field is generated, then a bidirectional region matching search strategy is adopted, and finally the integrated results are output, effectively improving the timing problem.

[0056] Specifically, first, it is judged whether the vector identifier is a second preset value, for example, 0. If it is 0, all low-bit masks are set to 0, and all high-bit masks are set to a third preset value, for example, 1. If the vector identifier is not 0, the low-bit mask is set to the current read index position minus 1, and the high-bit mask is set to the complement of the low-bit mask. For example, if the cache area depth is 8 and the start position of the current read index is start_vec = 00010000, the low-bit mask = 00001111, and the high-bit mask = 11110000.

[0057] Therefore, since the mask can accurately distinguish the valid SLOT from the invalid or idle SLOT in the link frame, only the SLOT enabled by the mask will be written into the buffer, and thus the invalid data can be prevented from occupying the buffer space by the mask calculation, so as to avoid the waste of storage resources, and also to reduce unnecessary memory write operations and power consumption.

[0058] According to one embodiment of the present application, based on a preset bidirectional region matching search strategy, a read pointer of a current to-be-read data packet is obtained according to a mask field of the current to-be-read data packet, including: determining a high-bit valid region interval and a low-bit valid region interval according to a vector identifier of the current to-be-read data packet and the mask field of the current to-be-read data packet; scanning in bit order in the high-bit valid region interval and the low-bit valid region interval respectively to obtain a first valid bit vector in the high-bit valid region interval to obtain a first one-hot code bit vector, and a first valid bit vector in the low-bit valid region interval to obtain a second one-hot code bit vector; and obtaining the read pointer of the current to-be-read data packet according to the first one-hot code bit vector and the second one-hot code bit vector.

[0059] According to one embodiment of the present application, the read pointer of the current to-be-read data packet is obtained according to the first one-hot code bit vector and the second one-hot code bit vector, including: obtaining a high-bit valid interval matching result according to the first one-hot code bit vector, and obtaining a low-bit valid interval matching result according to the second one-hot code bit vector; integrating the high-bit valid interval matching result and the low-bit valid interval matching result to obtain an integrated result, and determining the read pointer of the current to-be-read data packet according to the integrated result.

[0060] Specifically, based on the preset bidirectional region matching search strategy, the next bit of '1' can be quickly located in the vector identifier, which can directly relate to the key optimization of the entire system in terms of timing performance, throughput and fairness.

[0061] Specifically, as Figure 5As shown, the embodiment of the present application can determine the high significant region interval and the low significant region interval according to the vector identifier of the current data packet to be read out and the mask field of the current data packet to be read out, then scan in the bit order in the high significant region interval and the low significant region interval respectively, obtain the first valid bit vector in the high significant region interval to obtain the first one-hot code bit vector, and obtain the first valid bit vector in the low significant region interval to obtain the second one-hot code bit vector, then obtain the high significant region matching result according to the first one-hot code bit vector, and obtain the low significant region matching result according to the second one-hot code bit vector; integrate the high significant region matching result and the low significant region matching result to obtain the integrated result, and determine the read pointer of the current data packet to be read out according to the integrated result.

[0062] That is, according to the vector identifier of the current data packet to be read out and the mask field of the current data packet to be read out, the high significant region interval and the low significant region interval are determined, then the first valid bit vector found in the high significant region interval and the first valid bit vector found in the low significant region interval are generated after scanning in the bit order in the high significant region interval and the low significant region interval respectively, the one-hot code bit vector is generated, only one bit is 1 and the rest bits are 0 (one-hot code), and the matching result is output at the same time, and the one-hot code bit vector is generated after integration.

[0063] Further, after integrating the high significant region matching result and the low significant region matching result, the read index starting position is updated, the high significant region matching result is preferentially selected, and the low significant region matching result is secondly selected.

[0064] Therefore, the embodiment of the present application preferentially services the high region after the current pointer based on the rule of "high mask priority", then services the low region, simulates the standard Round-Robin scheduling, maintains the fairness of Round-Robin polling, realizes efficient and uninterrupted scheduling, ensures that the data stream can be continuously processed, and maximizes the buffer utilization rate and system throughput.

[0065] In summary, the embodiment of the present application adopts a single-path shared dual-port ring buffer architecture, dynamically manages the starting positions of different FLIT data packets in the shared buffer through vector identification, and efficiently and timing-optimized locates the next FLIT packet to be read through the combination of Round-Robin polling and bidirectional area matching search. The effective data amount is accurately calculated through the read-write pointer with a flip bit, and the multi-SLOT parallel lock-free readout is realized, so that the efficient concurrent reorganization of multi-type FLIT data packets is completed in a single buffer. Compared with the multi-buffer design mode, the problem of doubling of the buffer resource due to the surge in the number of accelerators is solved, and the multi-type slot parallel output effectively reduces the link delay. The bidirectional area matching strategy reduces the combination logic control, and the different bit widths and different starting positions improve the effect, thereby effectively improving the design timing, and the overall design is flexible, efficient, and can be transplanted on various platforms.

[0066] According to the fragmentation reorganization buffer storage method, the sideband information in the link layer data frame is obtained by analyzing the link layer data frame, and the write enable mask signal of at least one FLIT data packet is generated based on the sideband information, and then at least one FLIT data packet is written into the target buffer, the current data packet to be read out is determined from the FLIT data packet, and the write starting address in the target buffer and the read pointer of the current data packet to be read out are obtained, and then in the case where the preset reading condition is satisfied, the current data packet to be read out is read out from the target buffer. The problems of large hardware resource consumption, increased cache and shift output communication delay caused by linear growth of resources with the number of accelerators are solved, and the data is spliced in real time through the single-path buffer mechanism, variable addressing pointer and parallel readout control logic, thereby saving storage resources and reducing link reorganization delay.

[0067] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0068] The embodiment of the present application also provides a fragmentation reorganization buffer storage device.

[0069] Figure 6 is a block diagram of the fragmentation reorganization buffer storage device of the embodiment of the present application.

[0070] As shown in Figure 6 , the fragmentation reorganization buffer storage device 10 includes an analysis module 100, a generation module 200 and a data packet readout module 300.

[0071] The analysis module 100 is configured to receive the link layer data frame and analyze the link layer data frame to obtain the sideband information in the link layer data frame.

[0072] The generation module 200 is configured to generate a write enable mask signal of at least one FLIT data packet according to the sideband information in the link layer data frame, and write the at least one FLIT data packet into the target buffer according to the write enable mask signal of the at least one FLIT data packet.

[0073] The data packet reading module 300 is configured to determine a current data packet to be read from the at least one FLIT data packet, obtain a write start address in the target buffer, determine a read pointer of the current data packet to be read, and read the current data packet to be read from the target buffer when a preset reading condition is met according to the write start address in the target buffer and the read pointer.

[0074] The features of the embodiment of the slice recombination buffer storage device can refer to the related descriptions of the embodiment of the slice recombination buffer storage method, which will not be repeated here.

[0075] Figure 7 The electronic device provided by the embodiment of the present application is shown in the structure diagram. The electronic device can include:

[0076] The memory 701, the processor 702, and the computer program stored in the memory 701 and executable on the processor 702.

[0077] The processor 702 executes the program to implement the slice recombination buffer storage method provided in the above embodiments.

[0078] Further, the electronic device further includes:

[0079] The communication interface 703 is configured to communicate between the memory 701 and the processor 702.

[0080] The memory 701 is configured to store the computer program executable on the processor 702.

[0081] The memory 701 can include a high-speed RAM memory, and can also include a non-volatile memory, such as at least one disk memory.

[0082] If the memory 701, the processor 702 and the communication interface 703 are implemented independently, the communication interface 703, the memory 701 and the processor 702 can be connected with each other through a bus and complete communication between each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For convenience of representation, Figure 7 Only one thick line is used to represent the bus in the figure, but it does not mean that there is only one bus or only one type of bus.

[0083] Optionally, in a specific implementation, if the memory 701, the processor 702 and the communication interface 703 are integrated on a chip, the memory 701, the processor 702 and the communication interface 703 can complete communication between each other through an internal interface.

[0084] The processor 702 can be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present application.

[0085] Embodiments of the present application also provide a computer readable storage medium, which stores a computer program, and the computer program is configured to execute steps in any of the above-mentioned slice reorganization buffer storage method embodiments when running.

[0086] Embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program. The computer program is executed by a processor to implement steps in any of the above-mentioned slice reorganization buffer storage method embodiments.

[0087] Those skilled in the art will further realize that the mere concepts, teachings, and embodiments described herein are merely meant to provide an enabling description of the claimed invention and are not intended to limit the scope of the claimed invention to these embodiments. Accordingly, the claims are not intended to be limited to the embodiments described herein. Rather, the claims should be read to include any embodiment that falls within the scope of the claims and their equivalents.

[0088] The above describes in detail the method of the present application. The principles and implementation of the present application are described by using specific examples. The above description of the examples is only to help understand the method of the present application and its core idea. It should be pointed out that those skilled in the art can make some improvements and modifications to the present application without departing from the principles of the present application. These improvements and modifications also fall within the scope of the claims of the present application.

Claims

1. A fragmented reassembly buffer storage method, characterized in that, Includes the following steps: Receive link layer data frames and parse the link layer data frames to obtain the sideband information in the link layer data frames; Generate at least one write enable mask signal for a FLIT data packet based on the sideband information in the link layer data frame, and write the at least one FLIT data packet into the target buffer based on the write enable mask signal for the at least one FLIT data packet. The system determines the current data packet to be read from the at least one FLIT data packet, obtains the write start address in the target buffer, determines the read pointer of the current data packet to be read, and, based on the write start address and read pointer in the target buffer, reads the current data packet to be read from the target buffer if the preset reading conditions are met. The step of determining the read pointer of the current data packet to be read includes: obtaining the vector identifier of the current data packet to be read, and generating the read enable base address and the position of the read enable base address based on the vector identifier of the current data packet to be read; generating the mask field of the current data packet to be read according to the read enable base address and the position of the read enable base address; and obtaining the read pointer of the current data packet to be read according to the mask field of the current data packet to be read based on a preset bidirectional region matching search strategy. The step of generating the mask field of the current data packet to be read based on the read enable base address and the position of the read enable base address includes: obtaining an initial mask based on the read enable base address of the current data packet to be read; determining the high-order mask and the low-order mask of the current data packet to be read based on the initial mask; and obtaining the mask field of the current data packet to be read based on the high-order mask and the low-order mask of the current data packet to be read. The step of determining the high-order mask and low-order mask of the mask field of the current data packet to be read based on the initial mask includes: determining whether the initial mask is all of the second preset value; if the initial mask is not all of the second preset value, then setting the low-order mask of the mask field of the current data packet to be read to the second preset value, and setting the high-order mask of the mask field of the current data packet to be read to a third preset value.

2. The method according to claim 1, characterized in that, The step of generating the read enable base address and the position of the read enable base address based on the vector identifier of the current data packet to be read includes: Based on the vector identifier of the current data packet to be read, the first position with the first preset value is determined as the position of the read enable base address according to the preset selection order; The address of the read enable base address is used as the read enable base address of the current data packet to be read.

3. The method according to claim 1, characterized in that, After determining whether the initial mask is entirely composed of the second preset value, the process further includes: If the initial mask is not entirely the second preset value, then calculate the first difference between the low-order mask of the initial mask and the fourth preset value, and use the first difference as the low-order mask of the current data packet to be read, and use the complement of the high-order mask of the initial mask as the high-order mask of the current data packet to be read.

4. The method according to claim 3, characterized in that, The preset bidirectional region matching search strategy, which obtains the read pointer of the current data packet to be read based on the mask field of the current data packet to be read, includes: The high-order valid region interval and the low-order valid region interval are determined based on the vector identifier of the current data packet to be read and the mask field of the current data packet to be read. The first one-hot code bit vector is obtained by scanning the first valid bit vector in the high-bit valid region interval and the second one-hot code bit vector in the low-bit valid region interval respectively. The read pointer of the current data packet to be read is obtained by obtaining the first one-hot code bit vector and the second one-hot code bit vector.

5. The method according to claim 4, characterized in that, The step of obtaining the read pointer of the current data packet to be read based on the first one-hot code bit vector and the second one-hot code bit vector includes: The high-order valid interval matching result is obtained based on the first one-hot code bit vector, and the low-order valid interval matching result is obtained based on the second one-hot code bit vector; The high-order valid interval matching results and the low-order valid interval matching results are integrated to obtain an integrated result, and the read pointer of the current data packet to be read is determined based on the integrated result.

6. The method according to claim 1, characterized in that, After determining the read pointer of the current data packet to be read, the process also includes: Calculate the second difference between the write start address and the read pointer in the target buffer; Based on the second difference, the number of valid slots of the current data packet to be read is obtained; Determine whether the second difference is greater than or equal to the number of valid slots in the current data packet to be read; If the second difference is greater than or equal to the number of valid slots in the current data packet to be read, then the preset reading condition is satisfied.

7. The method according to claim 6, characterized in that, The step of obtaining the number of valid slots for the current data packet to be read based on the second difference includes: Obtain the buffer depth value of the target buffer; Calculate the sum of the second difference and the buffer depth value; The effective number of slots for the current data packet to be read is obtained by performing a modulo operation based on the sum and the buffer depth value.

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