Frequency adjustment method and electronic equipment
By dynamically adjusting the processor's target core and ring bus frequency, the performance bottleneck when using P-cores and E-cores interchangeably is resolved, enabling efficient operation and low power consumption of electronic devices, and improving processing speed and battery life.
Patent Information
- Application Number
- CN202510905138.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-01
- Publication Date
- 2025-11-28
Smart Images
Figure CN121029375A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of electronic equipment technology, and in particular to a frequency adjustment method and an electronic device. Background Technology
[0002] With the development of electronic devices, the performance requirements are becoming increasingly demanding, leading to higher processor core frequencies. However, in related technologies, although processor core frequencies are increasing, the ring bus can only operate at the maximum frequency of the energy-efficient E core. While the maximum frequency of the performance P core is higher than that of the energy-efficient E core, mixing the energy-efficient E core and the performance P core will affect the maximum overclocking performance of the performance P core, thus impacting the performance of the ring bus and resulting in a slower overall processing speed for the electronic device. Summary of the Invention
[0003] This disclosure provides a frequency adjustment method and an electronic device to at least solve the above-mentioned technical problems existing in the prior art.
[0004] According to a first aspect of this disclosure, a frequency adjustment method is provided, comprising:
[0005] Obtain core call instructions for applications running on electronic devices; the core call instructions are used to characterize the processor cores that the applications running on electronic devices need to call; wherein, the processor cores include a first core and a second core; the maximum operating frequency of the first core is greater than the maximum operating frequency of the second core;
[0006] In response to the core invocation instruction, a target core is determined; the target core is either a first core or a second core.
[0007] The operating frequency of the ring bus is adjusted according to the operating frequency of the target core to execute the application.
[0008] In one possible implementation, the electronic device runs multiple applications; determining the target core in response to the core invocation instruction includes:
[0009] Obtain the operating frequency required for each running application;
[0010] Sort the required operating frequencies of the applications in descending order;
[0011] The processor core that the application with the highest required operating frequency needs to call is identified as the target core.
[0012] In one possible implementation, it further includes:
[0013] In response to the target core being the first core, the working state of the second core is adjusted;
[0014] In response to the target core being the second core, the working state of the first core is adjusted.
[0015] In one possible implementation, adjusting the working state of the second core in response to the target core being a first core includes:
[0016] In response to the target core being the first core, the application running under the second core is identified;
[0017] The application running on the second core is executed by the first core, and the second core is switched to a non-working state.
[0018] In one possible implementation, adjusting the working state of the first core in response to the target core being a second core includes:
[0019] In response to the target core being the second core, the application running under the first core is identified;
[0020] The application running under the first core is executed by the second core, and the first core is switched to a non-working state.
[0021] In one possible implementation, adjusting the operating frequency of the ring bus to execute the application based on the operating frequency of the target core includes:
[0022] In response to the target core being the first core, the operating frequency of the ring bus is set based on the operating frequency of the second core;
[0023] In response to the target core being a second core, the operating frequency of the ring bus is set based on the operating frequency of the second core.
[0024] In one possible implementation, it further includes:
[0025] The first core and the second core operate simultaneously.
[0026] In one possible implementation, adjusting the operating frequency of the ring bus to execute the application based on the operating frequency of the target core further includes:
[0027] When the first core and the second core are running simultaneously, the operating frequency of the ring bus is set based on the operating frequency of the second core.
[0028] According to a second aspect of this disclosure, an electronic device is provided, comprising: a processor, the processor including a first core and a second core; the maximum operating frequency of the first core is greater than the maximum operating frequency of the second core;
[0029] The processor is used to obtain core call instructions for applications running on the electronic device; the core call instructions are used to identify the processor cores that the applications running on the electronic device need to call.
[0030] A core scheduler is used to determine a target core in response to the core invocation instruction; the target core is either a first core or a second core.
[0031] A ring bus controller is used to adjust the operating frequency of the ring bus according to the operating frequency of the target core to execute the application.
[0032] According to a third aspect of this disclosure, an electronic device is provided, comprising:
[0033] At least one processor; and
[0034] A memory communicatively connected to the at least one processor; wherein,
[0035] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the methods described in this disclosure.
[0036] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this disclosure.
[0037] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0038] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which:
[0039] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
[0040] Figure 1 This illustration shows the implementation flow of the frequency adjustment method according to an embodiment of the present disclosure. Figure 1 ;
[0041] Figure 2 This illustration shows the implementation flow of the frequency adjustment method according to an embodiment of the present disclosure. Figure 2 ;
[0042] Figure 3A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown;
[0043] Figure 4 A schematic diagram of the composition structure of another electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation
[0044] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0045] The following describes a frequency adjustment method provided in this application, with reference to the accompanying drawings, including:
[0046] S101, Obtain the core call instruction for the application running on the electronic device; the core call instruction is used to characterize the processor core that the application running on the electronic device needs to call; wherein, the processor core includes a first core and a second core; the maximum operating frequency of the first core is greater than the maximum operating frequency of the second core;
[0047] The electronic device provided in this application embodiment can be a smart terminal or a server; wherein, the smart terminal can be a mobile phone, a personal digital assistant (PDA), a tablet computer, a laptop computer, a desktop computer, or other devices. The server can be an independent physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery network (CDN) services, and big data and artificial intelligence platforms.
[0048] It's important to note that the processor core of an electronic device is responsible for processing instructions, performing calculations, and controlling the operation of the computer system. Processor cores include two types: performance cores (P-cores) and efficiency cores (E-cores). By differentiating the functional roles of each core, the processor dynamically allocates tasks to achieve a balance between high performance and low power consumption. P-cores handle tasks requiring high single-core performance, such as games, video editing, 3D rendering, and complex software compilation. E-cores handle background tasks or lightweight computing, such as system services (antivirus software, automatic backups), web browsing, multitasking, and standby power consumption control. The maximum operating frequency of P-cores is higher than the maximum operating frequency supported by E-cores.
[0049] In this application, the first core can be a P core and the second core can be an E core.
[0050] When an application in an electronic device is about to run, it generates kernel call instructions, which are generated based on the application type. For example, if the application type is a game, video editing, or 3D rendering, a P-core call instruction is generated. If the application type is web browsing, multitasking, or standby power consumption control, an E-core call instruction is generated.
[0051] S102, in response to the core call instruction, determine the target core; the target core is either a first core or a second core.
[0052] In this application, the processor dynamically allocates application tasks to a first core (such as a P-core, a performance core) or a second core (such as an E-core, an energy-efficient core) through core call instructions. If the core call instruction is a P-core call instruction, the target core is the P-core; if the core call instruction is an E-core call instruction, the target core is the E-core.
[0053] S103, adjust the operating frequency of the ring bus to execute the application based on the operating frequency of the target core.
[0054] In this application, if the target core is a P-core, the processor can adjust the operating state of the E-core to make it non-working. This allows the processor to operate with only the P-core running and determines the operating frequency of the P-core. If the target core is an E-core, the processor can adjust the operating state of the P-core to make it non-working. This allows the processor to operate with only the E-core running and determines the operating frequency of the E-core.
[0055] The P-core and E-core have different maximum operating frequencies, and their corresponding Ring bus operating frequencies also differ. The Ring bus frequency determines the speed of information transfer between various components within the processor, and it is also closely related to the operating frequencies of the cache and memory controller. Therefore, increasing the Ring frequency can improve memory performance. Synchronizing the Ring frequency with the target core's operating frequency allows the processor to operate at its optimal performance level, improving the overall speed of electronic devices.
[0056] The frequency adjustment method provided in this application, such as Figure 2 As shown, when an electronic device runs an application, the processor receives the core call instruction for the application and determines whether the application is running on the first or second core based on the instruction. If it is the first core, the processor adjusts the operating state of the second core; if it is the second core, the processor adjusts the operating state of the first core. Then, the operating frequency of the ring bus is adjusted according to the operating frequency of the first or second core to execute the application. The frequency adjustment method provided in this application can dynamically control the operating state of the P-core and E-core, thereby adjusting the ring bus, maximizing its performance, optimizing the operating state of the electronic device, and improving its processing speed.
[0057] In some embodiments, the electronic device runs multiple applications; determining the target core in response to the core invocation instruction includes:
[0058] Obtain the operating frequency required for each running application;
[0059] Sort the required operating frequencies of the applications in descending order;
[0060] The processor core that the application with the highest required operating frequency needs to call is identified as the target core.
[0061] It should be noted that different applications require different operating frequencies. For example, web browsing or social chatting are light-load tasks with low frequency requirements, typically handled by E cores, with frequencies ranging from approximately 0.8 to 3.0 GHz. Games, video decoding, rendering, and compilation, on the other hand, are heavy-load tasks with higher frequency requirements, typically handled by P cores, with frequencies ranging from approximately 2.0 to 6.0 GHz. Therefore, this application first determines the operating frequency required for the electronic device to run the application, and then determines whether a P core or an E core is needed to operate at that frequency. The core corresponding to the highest operating frequency required by the running application is then identified as the target core.
[0062] For example, the electronic device runs applications including web browsing, social chat, and games. Web browsing requires a frequency of 1.5 GHz, social chat requires 1.8 GHz, and games require 5 GHz. Therefore, the P-core corresponding to 5 GHz is determined as the target core. However, if the electronic device only runs web browsing and social chat, then the E-core corresponding to 1.8 GHz is determined as the target core.
[0063] In some embodiments, adjusting the operating state of another core based on the type of the target core and determining the operating frequency of the target core includes:
[0064] In response to the target core being the first core, the working state of the second core is adjusted;
[0065] In response to the target core being the second core, the working state of the first core is adjusted.
[0066] In this application, if the target core is the first core, the working state of the second core can be changed to a non-working state. If the target core is the second core, the working state of the first core can be changed to a non-working state. A non-working state could be, for example, a deep hibernation state or a paused state.
[0067] For example, if the target core is a P-core, the E-core's operating state is changed to a non-operating state. In this way, the processor runs at the P-core's operating frequency, improving the performance of the electronic device. If the target core is an E-core, the P-core's operating state is changed to a non-operating state. In this way, the processor runs at the E-core's operating frequency, reducing the electronic device's power consumption and extending its battery life.
[0068] In some embodiments, adjusting the working state of the second core in response to the target core being a first core includes:
[0069] In response to the target core being the first core, the application running under the second core is identified;
[0070] The application running on the second core is executed by the first core, and the second core is switched to a non-working state.
[0071] In this application, when the target core is the first core, the application running on the second core is identified, executed by the first core, and then the second core is switched to a non-working state. This allows applications in the electronic device to continue operating normally and also improves the performance of the electronic device.
[0072] For example, the electronic device runs applications including web browsing, social chat, and games. Web browsing and social chat run on the E core, while games run on the P core. After determining that the target core is the P core, web browsing and social chat are moved to run on the P core, and then the E core is switched to a non-working state.
[0073] In some embodiments, it also includes:
[0074] In response to the target core being the first core, the application running under the second core is identified;
[0075] The application running on the second core is executed by the first core, and the second core is switched to a non-working state.
[0076] In this application, such as Figure 2 As shown, when the target core is the first core, the application running on the second core is identified, executed by the first core, and then the second core is switched to a non-working state. This allows applications in the electronic device to continue operating normally and also improves the device's performance.
[0077] For example, the electronic device runs applications including web browsing, social chat, and games. Web browsing and social chat run on the E core, while games run on the P core. After determining that the target core is the P core, web browsing and social chat are moved to run on the P core, and then the E core is switched to a non-working state. In this way, not only can the stability of the game frame rate be improved, but compared with the E core and P core running simultaneously, the overall power consumption of the electronic device can also be reduced.
[0078] In some embodiments, adjusting the working state of the first core in response to the target core being a second core includes:
[0079] In response to the target core being the second core, the application running under the first core is identified;
[0080] The application running under the first core is executed by the second core, and the first core is switched to a non-working state.
[0081] In this application, when the target core is the second core, the application running on the first core is identified, and the second core executes the application running on the first core. Then, the first core is switched to a non-working state. This allows applications in the electronic device to continue operating normally and also improves the performance of the electronic device.
[0082] For example, the electronic device runs applications including web browsing, social chat, and system updates. Web browsing and social chat run on the E core, while system updates run on the P core. After determining that the target core is the E core, the system update is moved to the E core, and then the P core is switched to a non-working state. In this way, the processor's operating frequency is reduced, lowering the overall power consumption of the electronic device and extending its battery life.
[0083] In addition, this application keeps non-target cores in a low-frequency or sleep state for extended periods, reducing the number of times core transistors are switched on and off, and slowing down the aging process. For example, the average annual usage time of P-cores can be reduced by 30% to 50%, effectively extending the hardware lifespan by 1.5 to 2 times.
[0084] In some embodiments, adjusting the operating frequency of the ring bus to execute the application based on the operating frequency of the target core includes:
[0085] In response to the target core being the first core, the operating frequency of the ring bus is set based on the operating frequency of the second core;
[0086] In response to the target core being a second core, the operating frequency of the ring bus is set based on the operating frequency of the second core.
[0087] In this application, if the target core is a first core, the operating frequency of the ring bus is set according to the operating frequency of the first core. If the target core is a second core, the operating frequency of the ring bus is set according to the operating frequency of the second core. This synchronizes the operating frequency of the ring bus with either the operating frequency of the first core or the operating frequency of the second core, thereby improving processor performance.
[0088] It's important to note that when the P-core runs at 3.5GHz and the ring bus frequency is 2.0GHz, the core must wait for data transmission from the ring bus, creating a performance bottleneck. When the E-core runs at 1.0GHz, if the ring bus is still running at 2.0GHz, it will unnecessarily increase power consumption (bus power consumption ∝ frequency 2). Therefore, synchronizing the ring bus operating frequency with the target core's operating frequency can improve processor performance or reduce power consumption, extending the battery life of electronic devices.
[0089] For example, if the target core is a P-core, and the application running on the E-core is executed using the P-core, and then the E-core is switched to a non-working state, then if the P-core is running at 5GHz, the operating frequency of the ring bus is increased to accommodate the P-core. For example, the operating frequency of the ring bus is set to 4.7GHz. If the P-core is overclocked, the operating frequency of the ring bus can be increased accordingly. Similarly, if the target core is an E-core, and the application running on the P-core is executed using the E-core, and then the P-core is switched to a non-working state, then if the E-core is running at 2.4GHz, the operating frequency of the ring bus is adjusted to accommodate the E-core. For example, the operating frequency of the ring bus is set to 2.1GHz. If the E-core is overclocked, the operating frequency of the ring bus can be increased accordingly.
[0090] This application adjusts the operating frequency of the ring bus by regulating the operating frequency of the target core. Increasing the ring bus frequency based on the operating frequency of the first core ensures that the data transmission bandwidth matches the core's computing power. For example, during game execution, if the P core frequency is 3.5GHz, the ring bus frequency is increased to 2.8GHz. During video rendering, if all P cores operate at 5.0GHz, the ring bus frequency is increased to 4.0GHz. Decreasing the bus frequency based on the operating frequency of the second core reduces unnecessary power consumption. For example, in standby mode, if the E core frequency is 0.8GHz, the ring bus frequency drops to 0.5GHz; during background downloads, if the E core frequency is 1.5GHz, the ring bus frequency drops to 1.0GHz.
[0091] This application can also set a threshold protection for the operating frequency of the ring bus to prevent signal distortion when the operating frequency of the ring bus is too high, and communication interruption when the operating frequency of the ring bus is too low. For example, when the core frequency exceeds 4.0 GHz, the upper limit of the bus frequency is locked at 3.2 GHz (to prevent signal distortion). When the core frequency is below 1.0 GHz, the lower limit of the bus frequency is set at 0.6 GHz (to maintain basic communication).
[0092] In some embodiments, it also includes:
[0093] The first core and the second core operate simultaneously.
[0094] It should be noted that if there are multiple running applications, and these applications require both the P core and the E core to run, then the target cores are the first core and the second core.
[0095] For example, when a laptop is set to "Balanced Mode" and running medium-load tasks (such as simultaneously editing documents, playing 4K video, or conducting online meetings), the system disables the extreme state of all P cores going to sleep or all E cores being shut down, forcing both to retain at least some cores active. In battery mode, mobile workstations may limit the maximum frequency of P cores, but must retain E cores to handle background tasks to prevent a sharp drop in battery life caused by P cores running alone.
[0096] In some embodiments, adjusting the operating frequency of the ring bus to execute the application based on the operating frequency of the target core further includes:
[0097] When the first core and the second core are running simultaneously, the operating frequency of the ring bus is set based on the operating frequency of the second core.
[0098] In this application, when the first core and the second core are running simultaneously, the operating frequency of the ring bus can be set according to the operating frequency of the second core.
[0099] For example, when both the P-core and E-core are running simultaneously, the maximum operating frequency of the ring bus can be reduced. If the E-core is running at 2.4GHz, the operating frequency of the ring bus can be adjusted to accommodate the E-core. For instance, the operating frequency of the ring bus can be set to 2.1GHz. If the E-core is overclocked, the operating frequency of the ring bus can be increased accordingly.
[0100] The frequency adjustment method provided in this application, when the target core is the first core (such as the P core), eliminates the ring bus bandwidth bottleneck when cores are used interchangeably by shutting down the second core (E core) and simultaneously increasing the ring bus frequency. For example, in a gaming scenario, increasing the P core frequency from 3.5GHz to 5.0GHz and simultaneously increasing the ring bus frequency from 2.0GHz to 4.0GHz results in a 100% increase in data transfer rate, a 25% improvement in game frame rate stability, and a 30% reduction in rendering latency. This avoids the problem of P core performance being limited due to low-frequency operation of the E core, and actual measurements show a 40% increase in processing speed for heavy-load tasks (such as 4K video rendering). When the target core is the second core (E core), shutting down the P core and reducing the bus frequency significantly reduces power consumption in standby and light-load scenarios. For example, in standby mode, with the E core frequency at 0.8GHz and the bus frequency reduced to 0.5GHz, overall power consumption is reduced by 60% compared to traditional solutions, and battery life is extended by 35%. Hibernation of non-target cores reduces transistor switching losses; actual measurements show that the average annual usage time of the P core is reduced by 40%, effectively extending hardware lifespan by 1.8 times.
[0101] like Figure 3As shown in the figure, this application embodiment provides an electronic device, including: a processor, the processor including a first core and a second core; the maximum operating frequency of the first core is greater than the maximum operating frequency of the second core;
[0102] The processor is used to obtain core call instructions for applications running on the electronic device; the core call instructions are used to identify the processor cores that the applications running on the electronic device need to call.
[0103] A core scheduler is used to determine a target core in response to the core invocation instruction; the target core is either a first core or a second core.
[0104] A ring bus controller is used to adjust the operating frequency of the ring bus according to the operating frequency of the target core to execute the application.
[0105] The electronic device provided in this application includes a processor, which includes a first core and a second core; the maximum operating frequency of the first core is greater than the maximum operating frequency of the second core. The processor receives a core invocation instruction for running an application on the electronic device; a core scheduler responds to the core invocation instruction and determines a target core; the target core is either the first core or the second core; the processor adjusts the operating state of another core based on the type of the target core and determines the operating frequency of the target core; a ring bus controller adjusts the operating frequency of the ring bus according to the operating frequency of the target core to execute the application.
[0106] This application can select the appropriate target core based on the light or heavy load type of the application, and shut down another core based on the target core, thereby enabling the electronic device to operate at the working efficiency of the target core, and adjusting the working efficiency of the ring bus according to the working efficiency of the target core. This application avoids the inefficient state of "high-frequency core with low-frequency bus" or "low-frequency core with high-frequency bus" by synchronizing the ring bus frequency with the core frequency, thus improving the performance of the electronic device.
[0107] This application provides an electronic device, including:
[0108] At least one processor; and
[0109] A memory communicatively connected to the at least one processor; wherein,
[0110] The memory stores instructions that can be executed by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform...
[0111] Obtain core call instructions for applications running on electronic devices; the core call instructions are used to characterize the processor cores that the applications running on electronic devices need to call; wherein, the processor cores include a first core and a second core; the maximum operating frequency of the first core is greater than the maximum operating frequency of the second core;
[0112] In response to the core invocation instruction, a target core is determined; the target core is either a first core or a second core.
[0113] The operating frequency of the ring bus is adjusted according to the operating frequency of the target core to execute the application.
[0114] This application provides a non-transitory computer-readable storage medium storing computer instructions, which are used to cause a computer to perform the methods described in any of the above embodiments.
[0115] According to embodiments of this application, this application also provides an electronic device and a readable storage medium.
[0116] Figure 4 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.
[0117] like Figure 4 As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 802 or a computer program loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.
[0118] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0119] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the frequency adjustment method. For example, in some embodiments, the frequency adjustment method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the frequency adjustment method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the frequency adjustment method by any other suitable means (e.g., by means of firmware).
[0120] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0121] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0122] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0123] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).
[0124] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.
[0125] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.
[0126] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.
[0127] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.
[0128] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A frequency adjustment method, comprising: Obtain the core invocation instructions for applications running on electronic devices; The core call instruction is used to characterize the processor core that the electronic device needs to call to run the application; wherein, the processor core includes a first core and a second core; the maximum operating frequency of the first core is greater than the maximum operating frequency of the second core; In response to the core invocation instruction, a target core is determined; the target core is either a first core or a second core. The operating frequency of the ring bus is adjusted according to the operating frequency of the target core to execute the application.
2. The method according to claim 1, wherein the electronic device runs multiple applications; and the step of determining the target core in response to the core invocation instruction includes: Obtain the operating frequency required for each running application; Sort the required operating frequencies of the applications in descending order; The processor core that the application with the highest required operating frequency needs to call is identified as the target core.
3. The method according to claim 1, further comprising: In response to the target core being the first core, the working state of the second core is adjusted; In response to the target core being the second core, the working state of the first core is adjusted.
4. The method according to claim 3, wherein adjusting the working state of the second core in response to the target core being a first core includes: In response to the target core being the first core, the application running under the second core is identified; The application running on the second core is executed by the first core, and the second core is switched to a non-working state.
5. The method according to claim 3, wherein adjusting the working state of the first core in response to the target core being a second core includes: In response to the target core being the second core, the application running under the first core is identified; The application running under the first core is executed by the second core, and the first core is switched to a non-working state.
6. The method according to claim 1, wherein adjusting the operating frequency of the ring bus to execute the application based on the operating frequency of the target core includes: In response to the target core being the first core, the operating frequency of the ring bus is set based on the operating frequency of the second core; In response to the target core being a second core, the operating frequency of the ring bus is set based on the operating frequency of the second core.
7. The method according to claim 1, further comprising: The first core and the second core operate simultaneously.
8. The method according to claim 7, wherein adjusting the operating frequency of the ring bus to execute the application based on the operating frequency of the target core further comprises: When the first core and the second core are running simultaneously, the operating frequency of the ring bus is set based on the operating frequency of the second core.
9. An electronic device, comprising: The processor includes a first core and a second core; the maximum operating frequency of the first core is greater than the maximum operating frequency of the second core. The processor is used to obtain core call instructions for running applications on electronic devices; The core call instruction is used to characterize the processor core that the electronic device needs to call when running applications; The core scheduler is used to determine the target core in response to the core invocation instruction; The target core can be either the first core or the second core type; A ring bus controller is used to adjust the operating frequency of the ring bus according to the operating frequency of the target core to execute the application.
10. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform... Obtain core call instructions for applications running on electronic devices; the core call instructions are used to characterize the processor cores that the applications running on electronic devices need to call; wherein, the processor cores include a first core and a second core; the maximum operating frequency of the first core is greater than the maximum operating frequency of the second core; In response to the core invocation instruction, a target core is determined; the target core is either a first core or a second core. The operating frequency of the ring bus is adjusted according to the operating frequency of the target core to execute the application.