RS485 bus fault injection system and method
By designing an RS485 bus fault injection system, and using FPGA to parse and control the fault module to inject fault parameters at different levels, the problem of not being able to comprehensively evaluate RS485 bus faults in existing technologies is solved, achieving efficient system reliability assessment and simplified circuit design.
Patent Information
- Application Number
- CN202511060070.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-28
AI Technical Summary
Existing technologies make it difficult to comprehensively and effectively evaluate the performance of RS485 bus under various fault conditions in the aerospace field. Traditional test platforms and equipment cannot accurately simulate faults in the physical layer, electrical layer and protocol layer, which limits the improvement of system reliability.
Design an RS485 bus fault injection system, including a main control chip FPGA, a fault injection module, a host computer and an RS485 bus signal receiving device. The FPGA parses the fault injection instructions and controls the fault module to inject fault parameters of the protocol layer, electrical layer and physical layer to simulate faults in actual operation.
It achieves accurate simulation of RS485 bus under different fault conditions, simplifies circuit design, improves the efficiency and accuracy of system reliability assessment, and does not change the actual equipment.
Smart Images
Figure CN121029508A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the field of aerospace, and relates to bus signal fault diagnosis and injection technology, in particular to an RS485 bus fault injection system and method. BACKGROUND
[0002] In the field of aerospace, RS485 bus has become a key foundation for building system communication network due to its outstanding advantages such as simple protocol, flexible configuration, strong anti-interference, etc. It undertakes a large number of key tasks such as sensor data acquisition, device state monitoring, and control instruction transmission, and is widely used in avionics systems, spacecraft subsystems, and ground test equipment. It can provide reliable communication support for the stable operation of the system under complex electromagnetic environment and high reliability requirements. Therefore, whether it is the cooperative work between internal devices of the aircraft or the information exchange between the spacecraft and the ground control station, RS485 bus plays an indispensable role.
[0003] However, the current fault test system for RS485 bus has obvious defects. Existing general simulation test platforms focus on verifying the algorithm level and are difficult to accurately simulate the actual faults of RS485 bus at the physical layer, electrical layer and protocol layer. Traditional instruments rely on manual operation, which is not only inefficient, but also cannot fully reproduce various fault conditions under complex aerospace application scenarios. In addition, professional fault injection equipment on the market is mainly adapted to other types of buses, and there is a lack of special test solutions for RS485 bus. This situation makes it difficult to comprehensively and effectively evaluate the performance of RS485 bus under various fault conditions during the development and maintenance of aerospace systems, which seriously hinders the improvement and optimization of system reliability. SUMMARY
[0004] In order to solve the technical problem that the existing fault test system cannot comprehensively and effectively evaluate the performance of RS485 bus under various fault conditions, the present application discloses an RS485 bus fault injection system, which can simulate the faults occurring in the actual operation of hardware during RS485 bus communication. The fault injection system comprises a master chip FPGA, a fault injection module, a host computer and an RS485 bus signal receiving device.
[0005] The master chip FPGA is connected with the host computer and the RS485 bus signal receiving device, receives the fault injection instructions output by the host computer, and obtains any one of the protocol layer fault control instruction, the electrical layer fault control instruction and the physical layer fault control instruction by analyzing the fault injection instructions. According to the protocol layer fault control instruction, the protocol layer fault parameters are injected into the RS485 differential signal and then output to the RS485 bus signal receiving device. The fault injection module is connected with the main control chip FPGA and the RS485 bus signal receiving device, and outputs the RS485 differential signal to the RS485 bus signal receiving device after injecting the electrical layer fault parameter or the physical layer fault parameter into the RS485 differential signal according to the electrical layer fault control instruction.
[0006] Further, the fault injection system further comprises an RS485 bus signal sending device, an RS485 receiving module and a DA module, the RS485 bus signal sending device is connected with the main control chip FPGA through the RS485 receiving module, and the DA module is located between the main control chip FPGA and the fault injection module. The RS485 receiving module converts the RS485 differential signal output by the RS485 bus signal sending device into a TTL level signal and then outputs the TTL level signal to the main control chip FPGA. The DA module converts the TTL level signal received by the main control chip FPGA back into the RS485 differential signal and then outputs the RS485 differential signal to the fault injection module.
[0007] Still further, the RS485 receiving module comprises a TVS voltage stabilizing tube, a MAX3485 chip and an ADuM1301 digital isolation chip.
[0008] Further, the fault injection system further comprises a communication module, the communication module is located between the main control chip FPGA and the upper computer through the communication module, and the communication module comprises a wired communication module and / or a wireless communication module.
[0009] Further, the protocol layer fault parameter comprises a fault parameter of adjusting any one or more of a start bit, a data bit and a termination bit of the RS485 differential signal, inverting or delaying the RS485 differential signal.
[0010] Further, the fault injection module comprises an electrical layer fault module and a physical layer fault module, the electrical layer fault module is used to generate the electrical layer fault parameter, and the electrical layer fault parameter is injected into the RS485 differential signal and then output to the RS485 bus signal receiving device. The physical layer fault module is used to generate the physical layer fault parameter, and the physical layer fault parameter is injected into the RS485 differential signal and then output to the RS485 bus signal receiving device.
[0011] Further, the electrical layer fault module comprises a fault generating module and an adder module, the fault generating module generates the electrical layer fault parameter according to the electrical layer fault control instruction, and the adder module superimposes and injects the electrical layer fault parameter into the RS485 differential signal and outputs.
[0012] Preferably, the electrical layer fault parameter comprises a noise signal and / or a common-mode voltage, the fault generating module comprises a noise module for generating the noise signal and a common-mode voltage module for generating the common-mode voltage.
[0013] Further, the physical layer fault parameter comprises any one or more of a parallel impedance signal, a serial impedance signal, a short-circuit signal and an open-circuit signal, the physical layer fault module comprises a digital potentiometer module for generating the parallel impedance signal and the serial impedance signal, and an analog switch module for generating the short-circuit signal and the open-circuit signal.
[0014] The embodiment of the present application also provides an RS485 bus fault injection method, which adopts the above-mentioned RS485 bus fault injection system to perform fault injection, and the method comprises the following steps: S1, generating a fault injection instruction and an RS485 differential signal according to a fault injection test requirement; S2, the master control chip FPGA receives the fault injection instruction and the RS485 differential signal, and analyzes the fault injection instruction to obtain any one of a protocol layer fault control instruction, an electrical layer fault control instruction and a physical layer fault control instruction; S31, when the fault injection instruction is the protocol layer fault control instruction, the master control chip FPGA generates a protocol layer fault parameter, injects the protocol layer fault parameter into the received RS485 differential signal, and then outputs to the RS485 bus signal receiving device; S32, when the fault injection instruction is the electrical layer fault control instruction, the master control chip FPGA controls the fault injection module to generate an electrical layer fault parameter, superimposes and injects the electrical layer fault parameter into the RS485 differential signal, and then outputs to the RS485 bus signal receiving device; S33, when the fault injection instruction is the physical layer fault control instruction, the master control chip FPGA controls the fault injection module to generate a physical layer fault parameter, injects the physical layer fault parameter into the RS485 differential signal, and then outputs to the RS485 bus signal receiving device.
[0015] Compared with the prior art, the above at least one technical scheme adopted by the embodiment of the present application can achieve at least the following beneficial effects: 1) Through the cooperation of circuit and software, different faults are injected to simulate the influence in the transmission line caused by corresponding environmental changes, line aging and other factors, without changing any device in the actual situation; 2) Through the wired communication module and / or wireless communication module, the upper computer is connected and communicated, the fault injection instruction issued by the upper computer can be received in time, and the fault parameters and RS485 differential signals are uploaded to the upper computer, so that the user can observe and compare the waveform changes through the upper computer; 3) Through the direct control of FPGA on each module, the chip quantity in the physical layer circuit (fault injection module, DA module, signal generation device and receiving device, etc.) can be optimized, the circuit design is simplified and optimized, and the cost performance is high. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.
[0017] Figure 1 The architecture diagram of the RS485 bus fault injection system of the present application; Figure 2 The circuit diagram of the RS485 receiving module of the present application; Figure 3 The circuit diagram of the DA module of the present application; Figure 4 The circuit diagram of the noise module of the present application; Figure 5 The circuit diagram of the common mode voltage module of the present application; Figure 6 The circuit diagram of the Ethernet module of the present application; Figure 7 The principle diagram of the physical layer fault module of the present application; Figure 8 The flow chart of the RS485 bus fault injection method of the present application. DETAILED DESCRIPTION
[0018] The embodiments of the present application will be described in detail below with reference to the drawings.
[0019] Following, the embodiments of the present application are described through specific examples, and other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of the present specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and various modifications or changes can be made to the details in the present specification based on different views and applications, without departing from the spirit of the present application. It should be noted that the following embodiments and features of the embodiments can be combined with each other without conflict. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0020] The application discloses a RS485 bus fault injection system, as shown in Figure 1 The fault injection system comprises a master control chip FPGA, a fault injection module, a host computer and a RS485 bus signal receiving device.
[0021] The master control chip FPGA is connected with the host computer and the RS485 bus signal receiving device, receives a fault injection instruction output by the host computer, obtains any one of a protocol layer fault control instruction, an electrical layer fault control instruction and a physical layer fault control instruction by analyzing the fault injection instruction, and outputs the RS485 differential signal to the RS485 bus signal receiving device after injecting a protocol layer fault parameter into the RS485 differential signal according to the protocol layer fault control instruction. In addition, the master control chip FPGA is also used to report the received RS485 differential signal and the RS485 differential signal after fault injection to the host computer, and a user can observe and compare the waveform changes through the host computer.
[0022] The fault injection module is connected with the master control chip FPGA and the RS485 bus signal receiving device, and outputs the RS485 differential signal to the RS485 bus signal receiving device after injecting an electrical layer fault parameter or a physical layer fault parameter into the RS485 differential signal according to the electrical layer fault control instruction.
[0023] Further, as shown in Figure 1 The fault injection system further comprises a RS485 bus signal sending device, a RS485 receiving module and a DA module, the RS485 bus signal sending device is connected with the master control chip FPGA through the RS485 receiving module, and the DA module is located between the master control chip FPGA and the fault injection module. The circuit diagram of the DA module is shown in Figure 3As shown, the DA module adopts AD9744 chip of double-channel differential signal to complete digital-to-analog conversion, the FPGA controls the size of the output current of the AD9744 chip, the two differential signal output ends convert the differential current into differential voltage through resistance to complete voltage amplitude adjustment, and the FPGA controls the change of the voltage by controlling the size of the differential current output by the chip.
[0024] The RS485 bus signal sending device is used to generate RS485 differential signals, and the RS485 receiving module converts the RS485 differential signals into TTL level signals that can be received by the master control chip FPGA. Since the signal received by the RS485 bus signal receiving device is a differential signal, a DA module is connected to the master control chip FPGA, and the DA module converts the TTL level signal back into the RS485 differential signal and outputs it to the fault injection module.
[0025] Further, referring to Figure 2 As shown, the RS485 receiving module includes a TVS voltage stabilizing tube, a MAX3485 chip and an ADuM1301 digital isolation chip, wherein the TVS voltage stabilizing tube (i.e. SM712 chip) is used to protect the MAX3485 chip and the bus line from various transient overvoltages, the MAX3485 chip is used to convert the RS485 level into TTL level, and the ADuM1301 digital isolation chip is used to isolate the FPGA.
[0026] Further, the fault injection system further includes a communication module between the master control chip FPGA and the upper computer through the communication module, and the communication module includes a wired communication module and / or a wireless communication module. The wired communication includes serial communication, parallel communication, Ethernet, USB, optical fiber communication and the like, and the wireless communication includes Wi-Fi, Bluetooth, Zigbee (suitable for low-power and short-distance communication), LoRa (suitable for long-distance and low-power communication), 4G / 5G mobile communication network and the like. Referring to Figure 1 and Figure 6 As shown, the communication module can be an Ethernet module. The Ethernet module includes an SR8201F chip and an HR961160C chip, wherein the SR8201F chip is used as an Ethernet transceiver chip, and the HR961160C chip is used as an Ethernet connector. Figure 6The SR8201F chip is an external interface of the FPGA-controlled Ethernet module, the HR961160C is an Ethernet interface module, the upper computer and the lower computer are connected through the Ethernet interface module, the interface HR961160C transmits signals to the SR8201F, the SR8201F processes the signals to the FPGA, the FPGA receives the signals transmitted by the SR8201F and analyzes the signals, and the FPGA transmits the signals to the Ethernet interface through the SR8201F chip, and the upper computer receives the signals sent by the lower computer FPGA through the Ethernet module and displays the information to the corresponding upper computer interface.
[0027] Further, the protocol layer fault parameter includes a fault parameter of adjusting any one or more of a start bit, a data bit and a termination bit of the RS485 differential signal, and inverting or delaying the RS485 differential signal.
[0028] Further, the fault injection module includes an electrical layer fault module and a physical layer fault module, the electrical layer fault module is used to generate the electrical layer fault parameter, and the electrical layer fault parameter is injected into the RS485 differential signal and then output to the RS485 bus signal receiving device; and the physical layer fault module is used to generate the physical layer fault parameter, and the physical layer fault parameter is injected into the RS485 differential signal and then output to the RS485 bus signal receiving device.
[0029] Further, referring to Figure 1 , the electrical layer fault module includes a fault generation module and an adder module, the fault generation module generates the electrical layer fault parameter according to the electrical layer fault control instruction, and the adder module superimposes the electrical layer fault parameter on the RS485 differential signal and then outputs. The adder module can select an LM6132 operational amplifier chip, and the LM6132 operational amplifier chip is used to add the differential signal output by the DA module to a noise signal and a common-mode voltage signal.
[0030] Preferably, referring to Figure 1 , the electrical layer fault parameter includes a noise signal and / or a common-mode voltage, the fault generation module includes a noise module for generating the noise signal and a common-mode voltage module for generating the common-mode voltage, and the circuit diagram of the noise module is shown in Figure 4 , the AD9833 chip can generate different noise signals; and the circuit diagram of the common-mode voltage module is shown in Figure 5 , the AD5293 chip generates common-mode voltages with different amplitudes. In a specific implementation, the FPGA controls the noise module and the common-mode voltage module to generate different noise and different common-mode voltages, the adder module is used to superimpose the signals on the differential signal output by the DA module, and the electrical layer noise superimposition and common-mode voltage adjustment functions are completed.
[0031] Further, referring to Figure 1 As shown, the physical layer fault parameter includes any one or more of a parallel impedance signal, a serial impedance signal, a short circuit signal and an open circuit signal, the physical layer fault module includes a digital potentiometer module and an analog switch module, the digital potentiometer module is used to generate the parallel impedance signal and the serial impedance signal, and the analog switch module is used to generate the short circuit signal and the open circuit signal. In the application, the on-off of the analog switch can be controlled by the FPGA to realize the short circuit and the open circuit at the physical level, and the digital potentiometer can be controlled by the FPGA to realize the serial impedance and the parallel impedance change of the physical layer bus. Referring to Figure 7 As shown in the schematic diagram of the physical layer fault module, the digital potentiometer module can select AD5253 chip and AD8400 chip, and the analog switch module can select MAX4642 chip, the AD5253 chip and the AD8400 chip provide the serial impedance and the parallel impedance resistance value of the output signal, and the MAX4642 chip controls the short circuit, the ground short circuit and the open circuit of the differential signal.
[0032] The embodiment of the application also provides an RS485 bus fault injection method, which adopts the RS485 bus fault injection system to perform fault injection, and the method comprises the following steps: S1, generating a fault injection instruction and an RS485 differential signal according to fault injection test requirements; S2, the master control chip FPGA receives the fault injection instruction and the RS485 differential signal, and analyzes the fault injection instruction to obtain any one of a protocol layer fault control instruction, an electrical layer fault control instruction and a physical layer fault control instruction; S31, when the fault injection instruction is the protocol layer fault control instruction, the master control chip FPGA generates a protocol layer fault parameter, and outputs the protocol layer fault parameter to the RS485 bus signal receiving equipment after the protocol layer fault parameter is injected into the received RS485 differential signal; S32, when the fault injection instruction is the electrical layer fault control instruction, the master control chip FPGA controls the fault injection module to generate an electrical layer fault parameter, and outputs the electrical layer fault parameter to the RS485 bus signal receiving equipment after the electrical layer fault parameter is superimposed and injected into the RS485 differential signal; S33, when the fault injection instruction is the physical layer fault control instruction, the master control chip FPGA controls the fault injection module to generate a physical layer fault parameter, and outputs the physical layer fault parameter to the RS485 bus signal receiving equipment after the physical layer fault parameter is injected into the RS485 differential signal.
[0033] In implementation, referring to Figure 8As shown, the RS485 bus fault injection system includes two parts of host computer and lower computer, and the RS485 bus is a kind of serial communication. The user first selects the baud rate of the lower computer through the host computer, which is the same as the baud rate on the RS485 bus, and then selects different faults corresponding to different layers. The host computer and the lower computer are connected through an Ethernet module. The host computer selects information and transmits it to the main control chip FPGA of the lower computer through the Ethernet module. FPGA receives the fault injection instructions of the host computer through code control, analyzes them, generates corresponding fault signals through the control of different modules, and sends the RS485 differential signals after fault injection to the RS485 receiving device on the bus. Finally, FPGA transmits the corresponding information to the host computer through the Ethernet module, and the host computer can realize the corresponding waveform change.
[0034] The RS485 bus fault injection system and method of the application has at least the following advantages: 1) Different faults are injected by the cooperation of circuit and software to simulate the influence of corresponding environmental changes, line aging and other factors in the transmission line without changing any device in the actual situation. 2) The wired communication module and / or wireless communication module are connected with the host computer for communication, so that the fault injection instructions issued by the host computer can be received in time, and the fault parameters and RS485 differential signals are uploaded to the host computer, so that the user can observe and compare the waveform changes through the host computer. 3) FPGA directly controls each module, which can optimize the number of chips in the physical layer circuit (fault injection module, DA module, signal generating device and receiving device, etc.), simplifies and optimizes the circuit design, and has high cost performance.
[0035] Obviously, those skilled in the art should understand that each module or each step of the above-mentioned embodiments of the application can be realized by a general computing device, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Alternatively, they can be realized by program code executable by a computing device, so that they can be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described can be executed in different order, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps among them can be manufactured into a single integrated circuit module. Thus, the embodiments of the application are not limited to any specific hardware and software combination.
[0036] The above only describes the preferred embodiments of the application and is not intended to limit the application. For those skilled in the art, the embodiments of the application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the application shall be included in the protection scope of the application.
Claims
1. An RS485 bus fault injection system, characterized in that, include: The main control chip FPGA is connected to the host computer and the RS485 bus signal receiving device. It receives the fault injection command output by the host computer, parses the fault injection command to obtain any one of the protocol layer fault control command, electrical layer fault control command and physical layer fault control command, injects protocol layer fault parameters into the RS485 differential signal according to the protocol layer fault control command, and then outputs it to the RS485 bus signal receiving device. The fault injection module is connected to the main control chip FPGA and the RS485 bus signal receiving device. According to the electrical layer fault control command, it injects electrical layer fault parameters or physical layer fault parameters into the RS485 differential signal and then outputs them to the RS485 bus signal receiving device.
2. The RS485 bus fault injection system according to claim 1, characterized in that, It also includes an RS485 bus signal transmitting device, an RS485 receiving module, and a DA module. The RS485 bus signal transmitting device is connected to the main control chip FPGA via the RS485 receiving module, and the DA module is located between the main control chip FPGA and the fault injection module. The RS485 receiving module converts the RS485 differential signal output by the RS485 bus signal transmitting device into a TTL level signal and then outputs it to the main control chip FPGA. The DA module converts the TTL level signal received by the main control chip FPGA back into the RS485 differential signal and outputs it to the fault injection module.
3. The RS485 bus fault injection system according to claim 2, characterized in that, The RS485 receiver module includes a TVS voltage regulator, a MAX3485 chip, and an ADuM1301 digital isolation chip.
4. The RS485 bus fault injection system according to claim 1, characterized in that, It also includes a communication module, which is located between the main control chip FPGA and the host computer via the communication module. The communication module includes a wired communication module and / or a wireless communication module.
5. The RS485 bus fault injection system according to claim 1, characterized in that, The protocol layer fault parameters include any one or more fault parameters that adjust the start bit, data bit, and stop bit of the RS485 differential signal to flip or delay the RS485 differential signal.
6. The RS485 bus fault injection system according to claim 1, characterized in that, The fault injection module includes an electrical layer fault module and a physical layer fault module. The electrical layer fault module is used to generate electrical layer fault parameters, inject the electrical layer fault parameters into the RS485 differential signal, and then output them to the RS485 bus signal receiving device. The physical layer fault module is used to generate the physical layer fault parameters, inject the physical layer fault parameters into the RS485 differential signal, and then output them to the RS485 bus signal receiving device.
7. The RS485 bus fault injection system according to claim 6, characterized in that, The electrical layer fault module includes a fault generation module and an adder module. The fault generation module generates electrical layer fault parameters according to the electrical layer fault control command, and the adder module superimposes the electrical layer fault parameters onto the RS485 differential signal for output.
8. The RS485 bus fault injection system according to claim 7, characterized in that, The electrical layer fault parameters include noise signals and / or common-mode voltages, and the fault generation module includes a noise module that generates the noise signals and a common-mode voltage module that generates the common-mode voltages.
9. The RS485 bus fault injection system according to claim 6, characterized in that, The physical layer fault parameters include any one or more of parallel impedance signals, serial impedance signals, short-circuit signals, and open-circuit signals. The physical layer fault module includes a digital potentiometer module and an analog switch module. The digital potentiometer module is used to generate parallel impedance signals and serial impedance signals, and the analog switch module is used to generate short-circuit signals and open-circuit signals.
10. A method for injecting faults into an RS485 bus, characterized in that, Fault injection is performed using the RS485 bus fault injection system according to any one of claims 1 to 9, the method comprising: Based on the fault injection test requirements, generate fault injection commands and RS485 differential signals; The main control chip FPGA receives the fault injection command and the RS485 differential signal, and parses the fault injection command to obtain any one of the protocol layer fault control command, electrical layer fault control command and physical layer fault control command; When the fault injection instruction is the protocol layer fault control instruction, the main control chip FPGA generates protocol layer fault parameters, injects the protocol layer fault parameters into the received RS485 differential signal, and then outputs them to the RS485 bus signal receiving device. When the fault injection instruction is the electrical layer fault control instruction, the main control chip FPGA controls the fault injection module to generate electrical layer fault parameters, and then injects the electrical layer fault parameters into the RS485 differential signal and outputs them to the RS485 bus signal receiving device. When the fault injection instruction is the physical layer fault control instruction, the main control chip FPGA controls the fault injection module to generate physical layer fault parameters, injects the physical layer fault parameters into the RS485 differential signal, and then outputs them to the RS485 bus signal receiving device.