Code processing method and device, electronic equipment and readable medium

Abstract

The embodiment of the invention provides a code processing method and device, electronic equipment and a readable medium, and relates to the technical field of compilation, in the method, in the conversion process of source codes, any conditional branch statement contained in the source codes is detected. If it is detected that the code logic of the conditional branch statement conforms to the specified code logic, determining the conditional branch statement as a statement to be optimized; the code logic is used for representing the operation indicated by the conditional branch statement. And based on the related parameters defined by the to-be-optimized statement, converting the to-be-optimized statement into a non-branch instruction group for realizing code logic of the to-be-optimized statement. Compared with a mode of converting the conditional branch statements into the conditional branch instructions, the method and the device have the advantage that the statements to be optimized are converted into the non-branch instruction groups for realizing the code logic of the statements to be optimized. Therefore, the number of the generated branch instructions can be reduced under the condition of ensuring normal implementation of code logic, so that the subsequent execution performance can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of compiling, in particular to a code processing method and device, electronic equipment and readable medium. BACKGROUND

[0002] At present, with the continuous development of compiling technology, the application of the compiler is more and more widely. When using the compiler for compiling, the source code can be converted to obtain executable code. Specifically, the executable code can be assembly code, and the assembly code can include an instruction sequence, which can be executed in subsequent execution.

[0003] In the prior art, in the conversion process, the compiler directly converts the conditional branch statement corresponding to the source code into a conditional branch instruction. In this way, the subsequent execution performance is affected. SUMMARY

[0004] The code processing method, device, electronic equipment and readable medium provided by the embodiments of the present application can improve the execution performance.

[0005] In order to solve the above problems, the present application discloses a code processing method, which comprises:

[0006] In the conversion process of the source code, any conditional branch statement contained in the source code is detected;

[0007] If the code logic of the conditional branch statement meets the specified code logic, the conditional branch statement is determined as a to-be-optimized statement; the code logic is used to represent the operation indicated by the conditional branch statement;

[0008] Based on the related parameters defined based on the to-be-optimized statement, the to-be-optimized statement is converted into a non-branch instruction group for implementing the code logic of the to-be-optimized statement.

[0009] Optionally, the detection of any conditional branch statement contained in the source code comprises:

[0010] For any conditional branch statement contained in the source code, it is detected whether the code logic of the conditional branch statement is to compare the to-be-compared parameters according to the comparison condition, and to select one from the to-be-selected parameters as the result parameter according to the comparison result;

[0011] If yes, it is determined that the code logic of the conditional branch statement meets the specified code logic;

[0012] If no, it is determined that the code logic of the conditional branch statement does not meet the specified code logic.

[0013] Optionally, the converting the to-be-optimized statement into the non-branch instruction set for implementing the code logic of the to-be-optimized statement based on the related parameters defined by the to-be-optimized statement comprises:

[0014] extracting the to-be-compared parameter, the comparison condition, the to-be-selected parameter and the result parameter defined by the to-be-optimized statement as the target to-be-compared parameter, the target condition, the target to-be-selected parameter and the target result parameter;

[0015] generating the non-branch instruction set based on the target to-be-compared parameter, the target condition, the target to-be-selected parameter and the target result parameter; the non-branch instruction set is used for comparing the target to-be-compared parameter according to the target condition and selecting one from the target to-be-selected parameter as the target result parameter according to the comparison result.

[0016] Optionally, the generating the non-branch instruction set based on the target to-be-compared parameter, the target condition, the target to-be-selected parameter and the target result parameter comprises:

[0017] generating a comparison instruction based on the target to-be-compared parameter and the target condition; the comparison instruction sets a destination register as a first preset value if the target to-be-compared parameter meets the target condition, or sets the destination register as a second preset value; the destination register is used for storing the comparison result of the comparison instruction;

[0018] generating at least two conditional assignment instructions based on the target to-be-selected parameter; one of the conditional assignment instructions is used for assigning an intermediate variable as one of the target to-be-selected parameter if a result register is the first preset value, or assigning the intermediate variable as 0; the result register has the same value as the destination register; the result register is used for providing a value representing the comparison result for the conditional assignment instruction;

[0019] generating an OR instruction based on the target result parameter and the intermediate variables of the conditional assignment instructions; the OR instruction performs OR operation on the intermediate variables of the conditional assignment instructions and takes the result as the value of the target result parameter; the non-branch instruction set comprises the comparison instruction, the conditional assignment instructions and the OR instruction.

[0020] Optionally, the to-be-compared parameter is a real number, the to-be-selected parameter is an integer, the destination register is a condition flag register and the result register is a fixed-point register; the method further comprises:

[0021] generating a register value transfer instruction based on the condition flag register and the fixed-point register;

[0022] The register value transfer instruction transfers the value of the condition flag register to the fixed-point register.

[0023] Optionally, the method further comprises:

[0024] In the instruction sequence converted from the source code, the comparison instruction, the register value transfer instruction, the first conditional assignment instruction, the second conditional assignment instruction and the or instruction in the non-branch instruction group are sequentially added.

[0025] In another aspect, an embodiment of the present application discloses a code processing apparatus, the apparatus comprising:

[0026] A detection module is configured to detect any conditional branch statement contained in the source code during the conversion of the source code;

[0027] A determination module is configured to determine the conditional branch statement as an optimized statement if the code logic of the conditional branch statement conforms to the specified code logic; the code logic is used to represent the operation indicated by the conditional branch statement.

[0028] A conversion module is configured to convert the optimized statement into a non-branch instruction group for implementing the code logic of the optimized statement based on the related parameters defined by the optimized statement.

[0029] Optionally, the detection module is specifically configured to:

[0030] For any conditional branch statement contained in the source code, detect whether the code logic of the conditional branch statement is to compare the comparison parameters according to the comparison condition and select one from the candidate parameters as the result parameter according to the comparison result;

[0031] If yes, determine that the code logic of the conditional branch statement conforms to the specified code logic;

[0032] If no, determine that the code logic of the conditional branch statement does not conform to the specified code logic.

[0033] Optionally, the conversion module is specifically configured to:

[0034] Extract the comparison parameters, the comparison condition, the candidate parameters and the result parameter defined by the optimized statement as the target comparison parameters, the target condition, the target candidate parameters and the target result parameter;

[0035] Generate the non-branch instruction group based on the target comparison parameters, the target condition, the target candidate parameters and the target result parameter; the non-branch instruction group is used to implement the comparison of the target comparison parameters according to the target condition and select one from the target candidate parameters as the target result parameter according to the comparison result.

[0036] Optionally, the conversion module is further configured to:

[0037] generate a comparison instruction based on the target parameter to be compared and the target condition; the comparison instruction sets a destination register to a first preset value if the target parameter to be compared meets the target condition, and sets the destination register to a second preset value otherwise; the destination register is used to store a comparison result of the comparison instruction;

[0038] generate at least two conditional assignment instructions based on the target candidate parameter; one of the conditional assignment instructions is configured to assign an intermediate variable to the target candidate parameter if a result register is the first preset value, and assign the intermediate variable to 0 otherwise; the result register has the same value as the destination register; the result register is used to provide a value representing the comparison result for the conditional assignment instruction;

[0039] generate an or instruction based on the target result parameter and the intermediate variables of the conditional assignment instructions; the or instruction performs an or operation on the intermediate variables of the conditional assignment instructions to obtain a value of the target result parameter; the non-branch instruction group includes the comparison instruction, the conditional assignment instructions, and the or instruction.

[0040] Optionally, the parameter to be compared is a real number, the candidate parameter is an integer, the destination register is a condition flag register, and the result register is a fixed-point register; the conversion module is further configured to:

[0041] generate a register value transfer instruction based on the condition flag register and the fixed-point register;

[0042] The register value transfer instruction transfers a value of the condition flag register to the fixed-point register.

[0043] Optionally, the apparatus further includes:

[0044] a joining module configured to sequentially join the comparison instruction, the register value transfer instruction, the first conditional assignment instruction, the second conditional assignment instruction, and the or instruction in the non-branch instruction group in the instruction sequence obtained by converting the source code.

[0045] In another aspect, an electronic device is disclosed, which includes a processor, a memory, a communication interface, and a communication bus; the processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is configured to store at least one executable instruction; the executable instruction causes the processor to execute the method described above.

[0046] The embodiment of the present application also discloses a machine readable medium having instructions stored thereon that, when executed by one or more processors, cause the processors to perform the method described above.

[0047] The embodiment of the present application has the following advantages: in the conversion process of the source code, any conditional branch statement contained in the source code is detected. If the code logic of the conditional branch statement is consistent with the specified code logic, the conditional branch statement is determined as a to-be-optimized statement; the code logic is used to represent the operation indicated by the conditional branch statement. Based on the related parameters defined based on the to-be-optimized statement, the to-be-optimized statement is converted into a non-branch instruction group for implementing the code logic of the to-be-optimized statement. Compared with the way of converting the conditional branch statement into a conditional branch instruction, in the embodiment of the present application, the to-be-optimized statement is converted into a non-branch instruction group for implementing the code logic of the to-be-optimized statement. In this way, the number of generated branch instructions can be reduced while ensuring that the code logic is normally implemented, and thus the subsequent execution performance can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0049] Figure 1 is a step flow chart of a code processing method provided by the embodiment of the present application;

[0050] Figure 2 is a block diagram of a code processing device provided by the embodiment of the present application;

[0051] Figure 3 is a structural schematic diagram of an electronic device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0053] Figure 1 is a step flow chart of a code processing method provided by the embodiment of the present application, as shown in Figure 1 the code processing method can include the following steps:

[0054] Step 101, in the conversion process of the source code, any conditional branch statement contained in the source code is detected.

[0055] Step 102, if the code logic of the conditional branch statement is consistent with the specified code logic, the conditional branch statement is determined as a to-be-optimized statement; the code logic is used to represent the operation indicated by the conditional branch statement.

[0056] Step 103, based on the related parameters defined by the to-be-optimized statement, the to-be-optimized statement is converted into a non-branch instruction group for implementing the code logic of the to-be-optimized statement.

[0057] The code processing method provided by the embodiment of the application can be applied to an electronic device, and in particular can be applied to a compiler in the electronic device. The code processing method can be applied to the field of compiler optimization, and realizes branch optimization of assembly code, reduces the number of branch instructions in the instruction sequence finally obtained after the source code is converted, and further improves subsequent execution performance and execution efficiency.

[0058] Specifically, the source code can be the source code of any program, a statement refers to a code unit for completing a logical operation or action, and one statement can be composed of one or more expressions. Accordingly, the conditional branch statement refers to a statement in the source code for controlling the program flow. The conditional branch statement causes the program to select different objects according to a specific condition, and then causes the program to go to different execution paths. The conditional branch statement can also be regarded as a conditional branch instruction in the source code.

[0059] The source code can include multiple conditional branch statements. Accordingly, the detection operation can be performed once for any conditional branch statement. If the code logic of the conditional branch statement is consistent with the specified code logic, the conditional branch statement can be determined as a to-be-optimized statement. The related parameters defined by the to-be-optimized statement can be parameters related to the code logic of the to-be-optimized statement, for example, the operands and comparison conditions defined in the to-be-optimized statement. The specified code logic can be set in advance according to actual requirements, and the embodiment of the application does not limit this. That is, in the embodiment of the application, the conditional branch statement that meets the specified code logic is optimized, avoiding converting the conditional branch statement that meets the specified code logic into a conditional branch instruction in the assembly code, thereby reducing the total number of conditional branch instructions in the assembly code, and further improving the subsequent execution performance and execution efficiency.

[0060] Further, the process of the compiler converting the source code can include: lexical analysis and syntax analysis, semantic analysis, intermediate code generation, assembly code generation. The lexical analysis and syntax analysis refer to lexical analysis of the source code, decomposing the source code into a series of tokens, and then performing syntax analysis to convert the tokens into an abstract syntax tree. Semantic analysis refers to the compiler checking semantic errors in the abstract syntax tree, such as type mismatch, undefined variable, and the like. Intermediate code generation refers to the compiler converting the abstract syntax tree after semantic analysis into an intermediate representation (IR). The IR representation is a platform-independent low-level representation that provides convenience for subsequent optimization and code generation. For conditional branch statements in the source code, the intermediate code generation node will be converted into an IR representation of the conditional branch structure. In the assembly code generation stage, the compiler converts the IR representation into machine instructions conforming to the preset architecture to obtain the instruction sequence. The preset architecture can be an architecture supported by the electronic device, and the preset architecture can be Loongson architecture, for example, and the embodiments of the present application are not limited thereto.

[0061] Correspondingly, when converting the to-be-optimized statement into a non-branch instruction set for implementing the code logic of the to-be-optimized statement, the to-be-optimized statement can be converted into an IR representation first, and then in the assembly code generation stage, the to-be-optimized statement in the form of the IR representation is converted into a non-branch instruction set for implementing the code logic of the to-be-optimized statement, that is, the non-branch instruction set is generated for the to-be-optimized statement in the form of the IR representation. The instructions included in the non-branch instruction set are all non-conditional branch instructions, and the instructions included in the non-branch instruction set are all machine instructions conforming to the preset architecture. Compared with the prior art, in which the to-be-optimized statement in the form of the IR representation is directly converted into a conditional branch instruction, this way can reduce the number of conditional branch instructions in the finally generated instruction sequence.

[0062] Conditional branch instructions in assembly code are used to control the flow of a program, which allows the program to execute different code paths based on conditions. Processors usually employ pipeline technology to execute instructions. When a conditional branch instruction is encountered, the pipeline needs to wait for the branch result, which can cause multiple stages in the pipeline to stall until the branch result is determined, thus affecting the execution performance and efficiency. That is, in a computer, the processor does not know the direction of the branch until the last moment. In a related art, branch prediction is performed. Branch prediction is a technique used in processors to predict the code path of a branch instruction in a program. By guessing the direction of the branch, branch prediction allows the processor to execute instructions on the predicted path in advance, thus reducing the waiting time and improving overall performance. Specifically, branch prediction determines a recognition pattern based on a large number of historical branch behaviors, and makes a prediction based on the recognition pattern. However, when facing unpredictable branches without a recognition pattern, branch prediction cannot actually optimize. If the prediction is wrong, the processor will re-execute, thus reducing the execution efficiency. In the embodiments of the present application, by reducing the number of conditional branch instructions in the finally generated instruction sequence, the need for branch prediction can be reduced, thus reducing the occurrence of branch prediction errors and the inability to perform branch prediction, improving the execution efficiency of the processor and improving the execution performance.

[0063] In summary, in the code processing method provided by the embodiments of the present application, any conditional branch statement contained in the source code is detected during the conversion of the source code. If the code logic of the conditional branch statement meets the specified code logic, the conditional branch statement is determined as a to-be-optimized statement. Based on the related parameters defined for the to-be-optimized statement, the to-be-optimized statement is converted into a non-branch instruction group for implementing the code logic of the to-be-optimized statement. Compared with the way of converting the conditional branch statement into a conditional branch instruction, in the embodiments of the present application, the to-be-optimized statement is converted into a non-branch instruction group for implementing the code logic of the to-be-optimized statement. In this way, the number of generated branch instructions can be reduced while ensuring that the code logic is normally implemented, and thus the subsequent execution performance can be improved.

[0064] Optionally, the step of detecting any conditional branch statement contained in the source code in the embodiments of the present application can specifically include:

[0065] Step 1011: For any conditional branch statement contained in the source code, it is detected whether the code logic of the conditional branch statement is to compare to-be-compared parameters according to a comparison condition and to select one from the to-be-selected parameters as a result parameter according to the comparison result.

[0066] Step 1012: If yes, it is determined that the code logic of the conditional branch statement meets the specified code logic.

[0067] Step 1013, if no, it is determined that the code logic of the conditional branch statement does not conform to the specified code logic.

[0068] In the embodiment of the present application, the specified code logic can be that the comparison condition is used to compare the to-be-compared parameters, and one of the to-be-selected parameters is selected as the result parameter according to the comparison result. Correspondingly, it can be detected whether the code logic of the conditional branch statement is that the comparison condition is used to compare the to-be-compared parameters, and one of the to-be-selected parameters is selected as the result parameter according to the comparison result. That is, it is judged whether the operation corresponding to the conditional branch statement is an optimizable operation, if yes, it is determined that the code logic of the conditional branch statement conforms to the specified code logic. Correspondingly, the conditional branch statement can be determined as the to-be-optimized statement. On the contrary, if no, it is determined that the code logic of the conditional branch statement does not conform to the specified code logic. Correspondingly, the optimization process can be exited, and the conditional branch statement can be directly converted into the conditional branch instruction.

[0069] Specifically, the conditional branch statement in the source code can be recognized, for example, the if-else statement included therein is recognized. Then it is detected whether the to-be-compared parameter, the comparison condition, the to-be-selected parameter and the result parameter are included in the related parameters included in the conditional branch statement. If yes, it is determined that the code logic of the conditional branch statement conforms to the specified code logic. Alternatively, in some embodiments, the to-be-compared parameter is a real number, and the to-be-selected parameter is an integer, that is, integer data. Correspondingly, the specified code logic can be that the comparison condition is used to compare the to-be-compared real number, and one of the to-be-selected integers is selected as the result parameter according to the comparison result. It can be determined that the code logic of the conditional branch statement conforms to the specified code logic in the case that the to-be-compared real number, the comparison condition, the to-be-selected integer and the result parameter are included in the related parameters included in the conditional branch statement. Specifically, the to-be-compared parameter can be a floating point number, and the to-be-selected parameter can be a fixed point number. Correspondingly, the embodiment of the present application can be specifically to optimize the conditional branch statement in which one of the fixed point numbers is selected as the result parameter according to the comparison result of the floating point numbers.

[0070] The conditional branch statement can be further parsed. If the parsing result indicates that the conditional branch statement compares the real numbers to be compared according to the comparison condition, and selects one from the candidate integers as the result parameter according to the comparison result, and the code logic of the conditional branch statement is determined to comply with the specified code logic, the accuracy of the identification is ensured to a greater extent. For example, the compiler analyzes whether the conditional expression of the conditional branch statement complies with a preset expression structure. If it complies, it is determined that the parsing result indicates that the conditional branch statement compares the real numbers to be compared according to the comparison condition, and selects one from the candidate integers as the result parameter according to the comparison result. The preset expression structure is an expression structure possessed by a statement that compares the real numbers to be compared according to the comparison condition, and selects one from the candidate integers as the result parameter.

[0071] In the embodiment of the present application, the conditional branch statement that complies with the specific condition (i.e., the conditional branch statement whose code logic complies with the specified code logic) is optimized, thereby reducing the generation of branch instructions. In the embodiment of the present application, detecting whether the code logic of the conditional branch statement is to compare the parameters to be compared according to the comparison condition, and to select one from the candidate parameters as the result parameter according to the comparison result, can enable the subsequent conditional branch statement to be used as the statement to be optimized, and accordingly, the statement to be optimized is converted into a non-branch instruction set, which can reduce the number of conditional branch instructions, and further reduce the branches in the control flow, and improve the execution efficiency of the instruction sequence obtained by compiling.

[0072] Optionally, the step of converting the statement to be optimized into a non-branch instruction set for implementing the code logic of the statement to be optimized based on the related parameters defined by the statement to be optimized can specifically include:

[0073] Step 1031: Extracting the parameters to be compared, the comparison condition, the candidate parameters, and the result parameter defined by the statement to be optimized as the target parameters to be compared, the target condition, the target candidate parameters, and the target result parameter.

[0074] Step 1032: Generating the non-branch instruction set based on the target parameters to be compared, the target condition, the target candidate parameters, and the target result parameter; the non-branch instruction set is used to compare the target parameters to be compared according to the target condition, and to select one from the target candidate parameters as the target result parameter according to the comparison result.

[0075] Specifically, the number of the to-be-compared parameters and the to-be-selected parameters is not less than 2, the to-be-compared parameters in the to-be-optimized statement can be extracted as target to-be-compared parameters, the comparison condition in the to-be-optimized statement can be extracted as a target condition, the to-be-selected parameters in the to-be-optimized statement can be extracted as target to-be-selected parameters, and the result parameter in the to-be-optimized statement can be extracted as a target result parameter. The order of extracting the to-be-compared parameters in the to-be-optimized statement, extracting the comparison condition in the to-be-optimized statement, extracting the to-be-selected parameters in the to-be-optimized statement, and extracting the result parameter in the to-be-optimized statement is not unique, and the embodiments of the present application do not limit this. For example, a regular expression constructed for a statement of a specified code logic can be used to perform regular matching on the to-be-optimized statement, to obtain the to-be-compared parameters, the comparison condition, the to-be-selected parameters, and the result parameter in the to-be-optimized statement.

[0076] For example, in an application scenario, the number of the to-be-compared parameters and the to-be-selected parameters is 2. It is assumed that the to-be-optimized statement is as follows:

[0077] if(real0>real1)

[0078] next=int0;

[0079] else next=int1;

[0080] Correspondingly, two to-be-compared parameters real0 and real1, a comparison condition real0>real1, two to-be-selected parameters int0 and int1, and a result parameter next can be extracted. The operation that can be implemented by the to-be-optimized statement is to select one of two integers int0 and int1 by comparing the sizes of two real numbers real0 and real1. Specifically, if real0 fcondreal1 is true (that is, (real0>real1), the result next is int0, otherwise the result next is int1. The code processing method in the embodiments of the present application can make this kind of operation no longer generate a conditional branch instruction, but use a non-branch instruction set to implement this kind of operation.

[0081] For example, it is assumed that the to-be-optimized statement is as follows:

[0082] if(real1>real2)

[0083] if(real0, real2>0)

[0084] next=int0;

[0085] else next=int1;

[0086] else next=int2;

[0087] Correspondingly, three to-be-compared parameters, real0, real1, real2, three comparison conditions, real1>real2 and real0, real2>0, real1>real2 and real0, real2≤0, real1<real2, three to-be-selected parameters, int0, int1, int2, and a result parameter, next, can be extracted. The operation that can be implemented by the to-be-optimized statement is: by comparing the sizes of two real numbers, real1 and real2, and the sizes of real0 and real2 and 0, one of three integers, int0, int1, and int2, is selected. Specifically, if real1>real2 and real0, real2>0 are true, the result next is int0; if real1>real2 and real0, real2≤0 are true, the result next is int1; otherwise, the result next is int2. The code processing method in the embodiment of the present application can make this kind of operation no longer generate conditional branch instructions, but use a non-branch instruction group to implement this kind of operation.

[0088] Further, based on the target to-be-compared parameter, the target condition, the target to-be-selected parameter, and the target result parameter, a plurality of non-branch instructions can be generated to obtain a non-branch instruction group. The target to-be-compared parameter, the target condition, the target to-be-selected parameter, and the target result parameter can be used as parameters of instructions in the non-branch instruction group, so that the non-branch instruction group can implement comparison of the target to-be-compared parameter according to the target condition, and selection of one of the target to-be-selected parameters as the target result parameter according to the comparison result.

[0089] In the embodiment of the present application, the to-be-compared parameter, the comparison condition, the to-be-selected parameter, and the result parameter defined by the to-be-optimized statement are extracted as the target to-be-compared parameter, the target condition, the target to-be-selected parameter, and the target result parameter. Then, based on the target to-be-compared parameter, the target condition, the target to-be-selected parameter, and the target result parameter, a non-branch instruction group is generated. The non-branch instruction group can implement comparison of the target to-be-compared parameter according to the target condition, and selection of one of the target to-be-selected parameters as the target result parameter according to the comparison result. In this way, it can be ensured that the to-be-optimized statement is converted into a non-branch instruction group, and the subsequent execution logic is correct.

[0090] Optionally, the step of generating the non-branch instruction group based on the target to-be-compared parameter, the target condition, the target to-be-selected parameter, and the target result parameter can specifically include:

[0091] Step 1032a, generating a comparison instruction based on the target parameter to be compared and the target condition; the comparison instruction sets a destination register to a first preset value if the target parameter to be compared meets the target condition, otherwise sets the destination register to a second preset value; the destination register is used to store a comparison result of the comparison instruction.

[0092] Step 1032b, generating at least two conditional assignment instructions based on the target parameter to be selected; one of the conditional assignment instructions is used to assign an intermediate variable to one of the target parameter to be selected if a result register is the first preset value, otherwise assign the intermediate variable to 0; the result register has the same value as the destination register; the result register is used to provide a value representing the comparison result for the conditional assignment instruction.

[0093] Step 1032c, generating an or instruction based on the target result parameter and the intermediate variable of each conditional assignment instruction; the or instruction performs an or operation on the intermediate variable of each conditional assignment instruction and takes the result as the value of the target result parameter; the non-branch instruction set includes the comparison instruction, the conditional assignment instruction and the or instruction.

[0094] In the embodiments of the present application, the target parameter to be compared can be a real number, and accordingly, the comparison instruction can be a real number comparison instruction. Specifically, a real number comparison instruction including the target parameter to be compared and the target condition can be generated. The comparison result of the real number comparison instruction can be stored in a specific register, which can be regarded as the destination register of the real number comparison instruction. Alternatively, in some embodiments, the destination register can be a condition flag register. The parameter to be compared can be a floating point number, and accordingly, the source operand of the real number comparison instruction can be saved in a floating point register. When the real number comparison instruction is executed, the sizes of the compared real numbers in the target parameter to be compared are compared according to the target condition, and the comparison result can be stored in the condition flag register.

[0095] The comparison result can be a first preset value or a second preset value. The first preset value indicates that the target parameter to be compared meets the target condition, i.e., the comparison result is true. The second preset value indicates that the target parameter to be compared does not meet the target condition, i.e., the comparison result is false. The specific forms of the first preset value and the second preset value can be set according to actual requirements. For example, the first preset value and the second preset value can be 1 and 0, respectively. Since there can be multiple target conditions, one real number comparison instruction can be generated for one target condition. For example, for the scenario in which the target condition in the foregoing example only includes real0>real1, one real number comparison instruction can be generated. If real0 and real1 in the target parameter to be compared meet real0>real1, the condition flag register is set to 1 by executing the real number comparison instruction. If real0 and real1 in the target parameter to be compared do not meet real0>real1, the condition flag register is set to 0 by executing the real number comparison instruction. In an application scenario, the instruction format of the real number comparison instruction can be: instruction name.comparison condition, source operand. Accordingly, the target condition can be used as the comparison condition of the instruction, and the parameters to be compared in the target parameter to be compared can be used as the source operand. Accordingly, for the example, one real number comparison instruction can be obtained: instruction name.real0>real1 flag, real0, real1. The instruction name can be a mnemonic representing the comparison function.

[0096] For the scenario in which the target condition in the foregoing example includes real1>real2 and real0, real2>0, real1>real2 and real0, real2≤0, and real1<real2, three real number comparison instructions can be generated. One real number comparison instruction corresponds to one target condition, and one real number comparison instruction is used to set the destination register to the first preset value if the target parameter to be compared meets the target condition corresponding to the real number comparison instruction, or to set the destination register to the second preset value. The target condition corresponding to the real number comparison instruction is defined in the real number comparison instruction. The target parameter to be selected corresponding to the real number comparison instruction is the target parameter to be selected corresponding to the target condition corresponding to the real number comparison instruction.

[0097] Accordingly, for the example, three real number comparison instructions can be obtained:

[0098] Compare instruction 1: instruction name.real1 > real2 and real0, real2 > 0 flag, real0, real1, real2 Compare instruction 2: instruction name.real1 > real2 and real0, real2 < 0 flag, real0, real1, real2 Compare instruction 3: instruction name.real1 < real2 flag, real0, real1, real2

[0099] The number of conditional assignment instructions is the same as the number of target parameters. The parameters can be integers, and the specific parameters can be fixed-point numbers. Correspondingly, a conditional assignment instruction can be a conditional assignment instruction with two integers. The two integers can include one of the target parameters and a default value of 0. One of the target parameters can be used as a source operand of a conditional assignment instruction. The result register is specifically a comparison result register, and the result register can be the destination register of the aforementioned real number comparison instruction, i.e., the aforementioned conditional flag register. Alternatively, the result register can be a register value same as the value of the conditional flag register. Alternatively, the result register can be a fixed-point register.

[0100] Exemplarily, the instruction format of the conditional assignment instruction can be represented as: instruction name rd, rj, rk. Correspondingly, in the case that there are two target candidate parameters, for the scenario that the target candidate parameters in the foregoing example include int0 and int1, two conditional assignment instructions can be generated: a first conditional assignment instruction and a second conditional assignment instruction. The first conditional assignment instruction can be represented as instruction name 0 rd, rj, rk, and the second conditional assignment instruction can be represented as instruction name 1 rd, rj, rk. Wherein, rd represents the destination register of the conditional assignment instruction, specifically, the first variable is stored in the rd of the first conditional assignment instruction, and the second variable is stored in the rd of the second conditional assignment instruction. rk represents the comparison result register, and rj represents the source operand, wherein the first variable and the second variable are intermediate variables of the first conditional assignment instruction and the second conditional assignment instruction respectively. Specifically, the rj of the first conditional assignment instruction is the first candidate parameter, and the rj of the second conditional assignment instruction is the second candidate parameter. For the foregoing example, tpm0 represents the rd storing the first variable, tpm1 represents the rd storing the second variable, and the comparison result: flag is stored in rk. The first conditional assignment instruction: instruction name 0 tpm0, int0, flag can be generated, and the second conditional assignment instruction: instruction name 1 tpm1, int1, flag can be generated. Wherein, the first candidate parameter can be the candidate parameter corresponding to the true comparison result, and the second candidate parameter can be the candidate parameter corresponding to the false comparison result, accordingly, when the first conditional assignment instruction is executed, if the value of flag is 1, that is, the comparison result is true, the value of rj int0 is written into tmp0, otherwise 0 is written into tmp0. When the second conditional assignment instruction is executed, if the value of flag is 0, that is, the comparison result is false, the value of rj int1 is written into tmp1, otherwise 0 is written into tmp1. That is, in the case that the target comparison parameter meets the target condition, the value of flag is 1, accordingly, tmp0 = int0, tmp1 = 0. In the case that the target comparison parameter does not meet the target condition, the value of flag is 0, accordingly, tmp0 = 0, tmp1 = int1. Wherein, the instruction name can be a mnemonic representing the assignment function, such as it can represent the conditional transfer assignment function.

[0101] In the case that there are more than two target candidate parameters, for example, in the case that the target candidate parameters include int0, int1 and int2 in the foregoing example, three conditional assignment instructions can be generated: one conditional assignment instruction is specifically used for assigning the intermediate variable to the target candidate parameter corresponding to the target condition of the comparison instruction in the case that the result register corresponding to the comparison instruction is the first preset value. The result register corresponding to the comparison instruction refers to the result register whose value is the same as the target register of the comparison instruction. The target candidate parameter corresponding to the target condition refers to the target candidate parameter selected for the result parameter when the target condition is met, and the target candidate parameter corresponding to the target condition is used as the source operand of the conditional assignment instruction. For example, the three conditional assignment instructions: conditional assignment instruction 1, conditional assignment instruction 2 and conditional assignment instruction 3 can be used to assign the intermediate variable to int0 in the case that the result register corresponding to comparison instruction 1 is the first preset value, to int1 in the case that the result register corresponding to comparison instruction 2 is the first preset value, and to int2 in the case that the result register corresponding to comparison instruction 3 is the first preset value.

[0102] Further, the target result parameter and the intermediate variable of all conditional assignment instructions can be used as the instruction parameters of the OR instruction. For example, the instruction format of the OR instruction can be represented as OR rd rs1 rs2. Accordingly, the first variable can be used as rs1, the second variable can be used as rs2, and the target result parameter can be used as rd to obtain an OR instruction. For example, for the foregoing example, the generated OR instruction can be represented as OR next tmp0 tmp1. Accordingly, in the case that the target comparison parameter meets the target condition, tmp0=int0 and tmp1=0, and finally next=int0. In the case that the target comparison parameter does not meet the target condition, tmp0=0 and tmp1=int1, and finally next=int1. This is the same as the code logic implemented by the to-be-optimized statement.

[0103] In the embodiment of the present application, the comparison instruction is generated based on the target comparison parameter and the target condition, the conditional assignment instruction is generated based on the target candidate parameter, and the OR instruction is generated based on the target result parameter and the intermediate variable of the conditional assignment instruction. In this way, the comparison instruction, the conditional assignment instruction and the OR instruction can constitute a non-branch instruction group capable of implementing the code logic of the to-be-optimized statement, and the conversion efficiency is high.

[0104] Alternatively, in the embodiment of the present application, the comparison parameter is a real number, the candidate parameter is an integer, the target register is a condition flag register, and the result register is a fixed-point register. Accordingly, the embodiment of the present application can further include the following steps:

[0105] In step S21, a register value transfer instruction is generated based on the condition flag register and the fixed-point register; wherein the register value transfer instruction transfers the value of the condition flag register to the fixed-point register.

[0106] Specifically, by further generating the register value transfer instruction, it can be ensured that the value in the fixed-point register is the same as the value in the condition flag register when the non-branch instruction group is executed, i.e., it is ensured that the result register and the destination register have the same value, and the result register provides a value representing the comparison result for the conditional assignment instruction, wherein the value representing the comparison result is the first preset value and the second preset value. The instruction format of the register value transfer instruction can be represented as: MOV rd rs. Specifically, the condition flag register can be set as rs of the register value transfer instruction, and the fixed-point register can be set as rd of the register value transfer instruction, and then the register value transfer instruction is obtained. For a conditional assignment instruction, a register value transfer instruction for transferring the value of the condition flag register of the comparison instruction corresponding to the conditional assignment instruction to the fixed-point register of the conditional assignment instruction can be generated, and rd and rs of the register value transfer instruction are the destination register of the comparison instruction corresponding to the conditional assignment instruction and the result register of the conditional assignment instruction, respectively. The comparison instruction corresponding to the conditional assignment instruction refers to the comparison instruction corresponding to the target candidate parameter defined in the source operand of the conditional assignment instruction. For example, for the conditional assignment instruction 1, the conditional assignment instruction 2, and the conditional assignment instruction 3, the register value transfer instruction 1, the register value transfer instruction 2, and the register value transfer instruction 3 can be generated, respectively, and the three register value transfer instructions are used to transfer the value of the condition flag register of the comparison instruction 1 to the result register of the conditional assignment instruction 1, the value of the condition flag register of the comparison instruction 2 to the result register of the conditional assignment instruction 2, and the value of the condition flag register of the comparison instruction 3 to the result register of the conditional assignment instruction 3, respectively.

[0107] In the embodiment of the present application, in the preset architecture supported by the electronic device, the non-branch instruction can be used to implement the logic of comparing the real numbers to be compared according to the comparison condition and selecting one from the candidate integers as the result parameter according to the comparison result. Therefore, by setting the parameter to be compared as a real number and the candidate parameter as an integer, it can be ensured that the finally generated instruction can be supported by the architecture.

[0108] Further, since the first conditional assignment instruction and the second conditional assignment instruction support operations on the fixed-point register, the register value transfer instruction is generated based on the condition flag register and the fixed-point register, so that when the register value transfer instruction is executed, the value of the condition flag register can be transferred to the fixed-point register, ensuring that the first conditional assignment instruction and the second conditional assignment instruction can normally obtain the first preset value or the second preset value, thereby ensuring that the instructions in the non-branch instruction group can implement the code logic of the to-be-optimized statement.

[0109] It should be noted that the code processing method provided by the embodiment of the present application can be applied to an electronic device supporting a preset architecture that meets a constraint condition, wherein the constraint condition can include: an existence of a real number comparison instruction, a conditional assignment instruction for an integer, a register value transfer instruction, and an or instruction. In this way, it can be ensured that the to-be-optimized statement can be normally converted into the non-branch instruction group.

[0110] Optionally, the embodiment of the present application can further include the following steps:

[0111] In step S31, the comparison instruction, the register value transfer instruction, the first conditional assignment instruction, the second conditional assignment instruction, and the or instruction in the non-branch instruction group are sequentially added to the instruction sequence converted from the source code.

[0112] Specifically, when the comparison instruction is executed, the target destination register can be set to the first preset value if the target to-be-compared parameter meets the target condition, and the target destination register can be set to the second preset value if the target to-be-compared parameter does not meet the target condition, that is, a comparison result is generated. When the register value transfer instruction is executed, the value of the condition flag register can be transferred to the fixed-point register, that is, the value of the destination flag register of the comparison instruction can be transferred to the result register, so that the first conditional assignment instruction and the second conditional assignment instruction can obtain the comparison result. Further, when the first conditional assignment instruction is executed, the first variable can be assigned to the first selected parameter if the result register is the first preset value, and the first variable can be assigned to 0 if the result register is the second preset value. When the second conditional assignment instruction is executed, the second variable can be assigned to the second selected parameter if the result register is the second preset value, and the second variable can be assigned to 0 if the result register is the first preset value. In this way, the target result parameter can be obtained by performing an or operation on the first variable and the second variable.

[0113] Correspondingly, the instructions in the non-branch instruction group can be arranged in sequence as: the comparison instruction, the register value transfer instruction, the first conditional assignment instruction, the second conditional assignment instruction, or the instruction, so that the non-branch instruction group is added to the instruction sequence obtained by converting the source code. Further, when the subsequent instructions are executed, the comparison instruction, the register value transfer instruction, the first conditional assignment instruction, the second conditional assignment instruction, or the instruction are executed in sequence, so that the code logic of the to-be-optimized statement can be normally implemented, and the accuracy of instruction execution is ensured. It should be noted that the instructions in the instruction sequence can be underlying commands executable by a central processing unit (CPU). The instruction sequence can also include other instructions, which are not limited by the embodiments of the present application. Further, the order of the first conditional assignment instruction and the second conditional assignment instruction can be adjusted, for example, the second conditional assignment instruction is arranged before the first conditional assignment instruction, that is, the instructions in the non-branch instruction group can be arranged in sequence as: the comparison instruction, the register value transfer instruction, the second conditional assignment instruction, the first conditional assignment instruction, or the instruction. The embodiments of the present application do not limit this.

[0114] With reference to Figure 2 , a block diagram of a code processing apparatus provided by an embodiment of the present application is shown, as shown in Figure 2 , the code processing apparatus can specifically include:

[0115] The detection module 201 is configured to detect any conditional branch statement included in the source code during the conversion of the source code.

[0116] The determination module 202 is configured to determine the conditional branch statement as a to-be-optimized statement if the code logic of the conditional branch statement meets the specified code logic; the code logic is used to represent the operation indicated by the conditional branch statement.

[0117] The conversion module 203 is configured to convert the to-be-optimized statement into a non-branch instruction group for implementing the code logic of the to-be-optimized statement based on the related parameters defined by the to-be-optimized statement.

[0118] Optionally, the detection module 201 is specifically configured to:

[0119] For any conditional branch statement included in the source code, detect whether the code logic of the conditional branch statement is to compare the to-be-compared parameters according to the comparison condition, and select one from the to-be-selected parameters as the result parameter according to the comparison result;

[0120] If yes, it is determined that the code logic of the conditional branch statement meets the specified code logic;

[0121] If not, it is determined that the code logic of the conditional branch statement does not conform to the specified code logic.

[0122] Optionally, the conversion module 203 is specifically used for:

[0123] extracting the to-be-optimized statement definition, the to-be-compared parameter, the comparison condition, the to-be-selected parameter, and the result parameter as the target to-be-compared parameter, the target condition, the target to-be-selected parameter, and the target result parameter;

[0124] generating the non-branch instruction group based on the target to-be-compared parameter, the target condition, the target to-be-selected parameter, and the target result parameter; the non-branch instruction group is used to compare the target to-be-compared parameter according to the target condition, and select one of the target to-be-selected parameters as the target result parameter according to the comparison result.

[0125] Optionally, the conversion module 203 is specifically used for:

[0126] generating a comparison instruction based on the target to-be-compared parameter and the target condition; the comparison instruction sets a destination register to a first preset value in a case where the target to-be-compared parameter meets the target condition, and sets the destination register to a second preset value in a case where the target to-be-compared parameter does not meet the target condition; the destination register is used to store a comparison result of the comparison instruction;

[0127] generating at least two conditional assignment instructions based on the target to-be-selected parameter; one of the conditional assignment instructions is used to assign an intermediate variable to one of the target to-be-selected parameters in a case where a result register is the first preset value, and is used to assign the intermediate variable to 0 in a case where the result register is not the first preset value; the result register has the same value as the destination register; the result register is used to provide a value representing the comparison result for the conditional assignment instruction;

[0128] generating an or instruction based on the target result parameter and the intermediate variables of the conditional assignment instructions; the or instruction performs an or operation on the intermediate variables of the conditional assignment instructions to obtain a value of the target result parameter; the non-branch instruction group includes the comparison instruction, the conditional assignment instructions, and the or instruction.

[0129] Optionally, the to-be-compared parameter is a real number, the to-be-selected parameter is an integer, the destination register is a condition flag register, and the result register is a fixed-point register; the conversion module 203 is specifically used for:

[0130] generating a register value transfer instruction based on the condition flag register and the fixed-point register;

[0131] The register value transfer instruction transfers a value of the condition flag register to the fixed-point register.

[0132] Optionally, the apparatus further comprises:

[0133] a joining module, configured to sequentially join the comparison instruction, the register value transfer instruction, the first conditional assignment instruction, the second conditional assignment instruction and the or instruction in the non-branch instruction group in the instruction sequence converted from the source code.

[0134] In summary, in the code processing apparatus provided by the embodiments of the present application, any conditional branch statement contained in the source code is detected in the conversion process of the source code. If the code logic of the conditional branch statement is consistent with the specified code logic, the conditional branch statement is determined as a to-be-optimized statement; the code logic is used to represent the operation indicated by the conditional branch statement. Based on the related parameters defined according to the to-be-optimized statement, the to-be-optimized statement is converted into a non-branch instruction group for implementing the code logic of the to-be-optimized statement. Compared with the way of converting the conditional branch statement into a conditional branch instruction, the to-be-optimized statement is converted into a non-branch instruction group for implementing the code logic of the to-be-optimized statement in the embodiments of the present application. In this way, the number of generated branch instructions can be reduced while ensuring the normal implementation of the code logic, and thus the subsequent execution performance can be improved.

[0135] Reference Figure 3 is a structural schematic diagram of an electronic device provided by the embodiments of the present application. As Figure 3 shown, the electronic device comprises a processor, a memory, a communication interface and a communication bus.

[0136] The processor, the memory and the communication interface complete the communication among each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction makes the processor execute the code processing method of the foregoing embodiments. The executable instruction can constitute a program.

[0137] The embodiments of the present application provide a machine readable medium having instructions stored thereon, which, when executed by one or more processors, enable the processors to execute the code processing method of the foregoing embodiments.

[0138] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0139] Those skilled in the art will appreciate that embodiments of the present application can be provided as methods, apparatus, or computer program products. Accordingly, embodiments of the present application can be embodied in a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application can be embodied in a computer program product on one or more computer readable storage media (including, but not limited to, disk memory, CD-ROMs, optical storage media, etc.) having computer usable program code embodied thereon.

[0140] It is noted that all actions of obtaining signals, information, or data in this application are performed in compliance with the corresponding data protection regulations of the country where the corresponding device is located, and with the authorization given by the owner of the corresponding device.

[0141] Embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate an apparatus that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in the flowcharts and / or block diagrams.

[0142] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal devices to work in a predictive manner, so that the instructions stored in the computer readable memory produce a manufactured product including instruction apparatus that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in the flowcharts and / or block diagrams.

[0143] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are performed on the computer or other programmable terminal device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable terminal device provide a process for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in the flowcharts and / or block diagrams.

[0144] While the preferred embodiments of the application have been described above, it should be understood that many modifications and adaptations will occur to those skilled in the art upon reading the foregoing description. Accordingly, the appended claims are intended to cover all such modifications and adaptations as fall within the true spirit and scope of the application.

[0145] Finally, it should be noted that the terminology used herein, such as first and second, is merely used for the convenience of the reader and is not intended to limit the scope of the application nor is it intended to imply that there is any actual relationship or order between the entities or actions so designated.

[0146] Moreover, the terms "comprise", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0147] The code processing method, code processing device, electronic device and one or more readable media provided by the application are described in detail above, the principles and implementation manners of the application are described by applying specific examples in the present text, the above description of the embodiments is only used to help understand the method of the application and its core idea; meanwhile, for the general skilled person in the art, according to the idea of the application, there will be changes in the specific implementation manners and application scope, and the above description of the content of the present text should not be understood as a limitation of the application.

Claims

1. A code processing method, characterized in that, The method includes: During the conversion of the source code, any conditional branch statement contained in the source code is detected; If the code logic of the conditional branch statement is detected to conform to the specified code logic, then the conditional branch statement is identified as a statement to be optimized; the code logic is used to characterize the operation indicated by the conditional branch statement. Based on the relevant parameters defined in the statement to be optimized, the statement to be optimized is converted into a non-branching instruction set for implementing the code logic of the statement to be optimized.

2. The method according to claim 1, characterized in that, The detection of any conditional branch statement contained in the source code includes: For any conditional branch statement contained in the source code, detect whether the code logic of the conditional branch statement is to compare the parameters to be compared according to the comparison conditions, and select one from the candidate parameters as the result parameter based on the comparison result. If so, then it is determined that the code logic of the conditional branch statement conforms to the specified code logic; If not, then it is determined that the code logic of the conditional branch statement does not conform to the specified code logic.

3. The method according to claim 1, characterized in that, The step of converting the statement to be optimized into a non-branching instruction set for implementing the code logic of the statement to be optimized, based on the relevant parameters defined in the statement to be optimized, includes: Extract the comparison parameters, comparison conditions, candidate parameters, and result parameters defined in the statement to be optimized, and use them as the target comparison parameters, target conditions, target candidate parameters, and target result parameters. Based on the target comparison parameter, target conditions, target candidate parameters, and target result parameter, the non-branch instruction group is generated; the non-branch instruction group is used to compare the target comparison parameter according to the target conditions, and select one from the target candidate parameters as the target result parameter based on the comparison result.

4. The method according to claim 3, characterized in that, The step of generating the non-branch instruction group based on the target comparison parameters, target conditions, target candidate parameters, and target result parameters includes: A comparison instruction is generated based on the target comparison parameter and the target condition; if the target comparison parameter meets the target condition, the comparison instruction sets the destination register to a first preset value, otherwise sets the destination register to a second preset value; the destination register is used to store the comparison result of the comparison instruction. At least two conditional assignment instructions are generated based on the target candidate parameters; wherein, one of the conditional assignment instructions is used to assign an intermediate variable to a target candidate parameter if the result register is the first preset value, otherwise assign it to 0; the result register has the same value as the destination register; the result register is used to provide a value representing the comparison result for the conditional assignment instructions; Based on the target result parameter and the intermediate variables of each conditional assignment instruction, an OR instruction is generated; the OR instruction performs an OR operation on the intermediate variables of each conditional assignment instruction and uses the result as the value of the target result parameter; the non-branch instruction group includes the comparison instruction, the conditional assignment instruction, and the OR instruction.

5. The method according to claim 4, characterized in that, The parameter to be compared is a real number, the parameter to be selected is an integer, the destination register is a condition flag register, and the result register is a fixed-point register; the method further includes: Generate a register value transfer instruction based on the condition flag register and the fixed-point register; The register value transfer instruction transfers the value of the condition flag register to the fixed-point register.

6. The method according to claim 5, characterized in that, The method further includes: In the instruction sequence obtained from the source code conversion, the comparison instruction, the register value transfer instruction, the first conditional assignment instruction, the second conditional assignment instruction, and the OR instruction from the non-branch instruction group are added in sequence.

7. A code processing device, characterized in that, The device includes: The detection module is used to detect any conditional branch statements contained in the source code during the conversion process. The determination module is used to determine the conditional branch statement as a statement to be optimized if the code logic of the conditional branch statement is detected to conform to the specified code logic; the code logic is used to characterize the operation indicated by the conditional branch statement. The conversion module is used to convert the statement to be optimized into a non-branching instruction set for implementing the code logic of the statement to be optimized, based on the relevant parameters defined in the statement to be optimized.

8. The apparatus according to claim 7, characterized in that, The detection module is specifically used for: For any conditional branch statement contained in the source code, detect whether the code logic of the conditional branch statement is to compare the parameters to be compared according to the comparison conditions, and select one from the candidate parameters as the result parameter based on the comparison result. If so, then it is determined that the code logic of the conditional branch statement conforms to the specified code logic; If not, then it is determined that the code logic of the conditional branch statement does not conform to the specified code logic.

9. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store executable instructions that cause the processor to perform the method as described in any one of claims 1 to 6.

10. One or more machine-readable media, characterized in that, It stores instructions that, when executed by one or more processors, cause the processors to perform the method as described in any one of claims 1-6.

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