Memory allocation methods and devices for direct access to memory devices

Abstract

This application discloses a memory allocation method and apparatus for direct access to memory devices, relating to the field of server technology. The method includes: in response to a memory access request from a user process, allocating virtual address information to the user process; obtaining the physical address range of the direct access memory device, the physical address range including physical address sub-regions corresponding to multiple memory channels; establishing an interleaving mapping relationship between the virtual address information and the physical address sub-regions corresponding to the multiple memory channels; writing the interleaving mapping relationship between the virtual address information and the multiple physical address sub-regions into a page table, and processing the user process's memory access request according to the interleaving mapping relationship in the page table. This method can improve the memory access speed of the server.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a memory allocation method and device for directly accessing memory devices. Background Technology

[0002] With the rapid development of server technology, users have increasingly higher requirements for server memory access speed. Direct access devices can bypass the traditional page-cached data copying path, enabling direct, zero-overhead memory access.

[0003] In related technologies, when an application accesses this contiguous physical address in a linear fashion, memory access requests are concentrated on a single memory channel until that channel's resources are exhausted before switching to the next channel. This access pattern cannot fully utilize the multi-channel parallel characteristics of memory, limiting the actual effective bandwidth to the bandwidth of a single memory channel rather than the sum of the bandwidths of all channels, thus reducing the server's memory access speed. Summary of the Invention

[0004] This application provides a memory allocation method and apparatus for directly accessing memory devices, so as to at least solve the problem of low memory access speed of servers in related technologies.

[0005] On the one hand, this application provides a memory allocation method for directly accessing memory devices, including:

[0006] In response to memory access requests from user processes, virtual address information is allocated to the user processes;

[0007] Obtain the physical address range of the memory device that is directly accessed. The physical address range includes the physical address sub-regions corresponding to each of the multiple memory channels.

[0008] Establish an interleaved mapping relationship between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels;

[0009] The interleaving mapping relationship between virtual address information and multiple physical address sub-regions is written into the page table, and the memory access requests of user processes are processed according to the interleaving mapping relationship in the page table.

[0010] On the other hand, this application provides a memory allocation apparatus for direct access to memory devices, comprising:

[0011] The allocation unit is used to allocate virtual address information to user processes in response to their memory access requests.

[0012] The acquisition unit is used to acquire the physical address range of the memory device that is directly accessed. The physical address range includes the physical address sub-regions corresponding to each of the multiple memory channels.

[0013] The establishment unit is used to establish the interleaving mapping relationship between virtual address information and the physical address sub-regions corresponding to multiple memory channels;

[0014] The processing unit is used to write the interleaving mapping relationship between virtual address information and multiple physical address sub-regions into the page table, and to process the memory access requests of user processes according to the interleaving mapping relationship in the page table.

[0015] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the memory allocation method of any of the above-described direct access memory devices when executing the computer program.

[0016] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described direct access memory device memory allocation methods.

[0017] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described direct access memory device memory allocation methods.

[0018] This application provides a memory allocation method and apparatus for direct access memory devices. The method includes: allocating virtual address information to the user process in response to a memory access request from a user process; obtaining the physical address range of the direct access memory device, the physical address range including physical address sub-regions corresponding to multiple memory channels; establishing an interleaving mapping relationship between the virtual address information and the physical address sub-regions corresponding to the multiple memory channels; writing the interleaving mapping relationship between the virtual address information and the multiple physical address sub-regions into a page table, and processing the memory access request of the user process according to the interleaving mapping relationship in the page table. In the embodiments of this application, by establishing an interleaving mapping relationship between the virtual address information and the physical address sub-regions corresponding to the multiple memory channels, when processing the memory access request of the user process, consecutive physical address access requests can be evenly distributed across multiple memory channels, making full use of the bandwidth of multiple memory channels, thereby improving the parallel bandwidth utilization of multiple memory channels, and thus improving the memory access speed of the server. Attached Figure Description

[0019] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1A schematic diagram of a prior art memory allocation method provided for embodiments of this application;

[0021] Figure 2 The flow chart of the memory allocation method for direct access to memory devices provided in the embodiments of this application Figure 1 ;

[0022] Figure 3 A schematic diagram of a memory allocation method for direct access memory devices provided in this application embodiment. Figure 1 ;

[0023] Figure 4 A schematic diagram of a memory allocation method for direct access memory devices provided in this application embodiment. Figure 2 ;

[0024] Figure 5 A schematic diagram of the memory allocation apparatus for direct access to memory devices provided in this application embodiment. Figure 1 ;

[0025] Figure 6 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0027] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0028] With the rapid development of server technology, users have increasingly higher requirements for server memory access speed. Direct access devices can bypass the traditional page-cached data copying path, enabling direct, zero-overhead memory access.

[0029] In related technologies, when an application accesses this contiguous physical address in a linear fashion, memory access requests are concentrated on a single memory channel until that channel's resources are exhausted before switching to the next channel. This access pattern cannot fully utilize the multi-channel parallel characteristics of memory, limiting the actual effective bandwidth to the bandwidth of a single memory channel rather than the sum of the bandwidths of all channels, thus reducing the server's memory access speed.

[0030] For example, such as Figure 1 As shown, DAX (Direct Access) memory devices provide memory to the host in a linear mapping manner. In this case, the physical address received by the host corresponds one-to-one with the memory region. If the total bandwidth of the direct access memory device link is 64G, with memory region 1 and memory region 2 each providing 32G of bandwidth, when an application accesses this contiguous physical address in a linear manner, memory access requests will be concentrated on a single memory channel. Therefore, the actual effective bandwidth is limited by the bandwidth of a single memory channel, rather than the sum of the bandwidths of all channels, thus reducing the server's memory access speed.

[0031] Therefore, how to fully utilize the bandwidth of multiple memory channels to improve the memory access speed of servers is a technical problem that urgently needs to be solved.

[0032] To address the aforementioned technical issues, this application proposes a memory allocation method for direct access to memory devices. This method remaps the physical address access of DAX devices at the kernel level, enabling the system's memory access to DAX devices to be automatically and evenly distributed across multiple memory channels, thereby significantly improving the parallelism and effective bandwidth of memory access.

[0033] Optionally, the specific steps include: First, in response to a user process's memory access request, allocating virtual address information to the user process; obtaining the physical address range of the directly accessed memory device, which includes the physical address sub-regions corresponding to each of the multiple memory channels. Then, establishing an interleaving mapping relationship between the virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels. Finally, writing the interleaving mapping relationship between the virtual address information and the multiple physical address sub-regions into a page table, and processing the user process's memory access request according to the interleaving mapping relationship in the page table.

[0034] In this embodiment, by establishing an interleaved mapping relationship between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels, when processing the memory access requests of user processes, continuous physical address access requests can be evenly distributed across multiple memory channels, making full use of the bandwidth of multiple memory channels, thereby improving the parallel bandwidth utilization of multiple memory channels and thus improving the memory access speed of the server.

[0035] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] The specific application environment architecture or specific hardware architecture on which the execution of the memory allocation method that directly accesses memory devices depends is described here.

[0037] Figure 2 The flow chart of the memory allocation method for direct access to memory devices provided in the embodiments of this application Figure 1 The execution entity for this memory allocation method that directly accesses memory devices can be a server. For example... Figure 2 As shown, the method includes:

[0038] S201. In response to a user process's memory access request, allocate virtual address information to the user process.

[0039] In this embodiment of the disclosure, a user process is a program instance that runs to process a specific task. When processing a task, the user process can initiate a memory access request to the server to allocate virtual address information.

[0040] Optionally, virtual address information is used to indicate a virtual memory region and may include a starting virtual address and an ending virtual address. The size of the virtual memory region allocated varies depending on the memory access requests of different user processes.

[0041] S202. Obtain the physical address range of the directly accessed memory device. The physical address range includes the physical address sub-regions corresponding to each of the multiple memory channels.

[0042] In this embodiment of the disclosure, the user can specify the direct access memory device to be split and the corresponding number of memory regions to be split.

[0043] Optionally, the physical address range of the directly accessed memory device can be identified first, and then the physical address range can be divided into multiple physical address sub-regions based on the number of memory region partitions. Accordingly, this step may include: obtaining the physical address range of the directly accessed memory device and the number of memory channels; and dividing the physical address range into multiple physical address sub-regions based on the number of memory channels.

[0044] Optionally, the user can pre-configure the number of direct memory access devices to be split and the corresponding number of memory channels. Accordingly, obtaining the physical address range and the number of memory channels of the direct memory access devices includes: obtaining the device identifier of the direct memory access device corresponding to the memory access request; and obtaining the physical address range and the number of memory channels of the direct memory access devices from the pre-stored correspondence between device identifiers, physical address ranges, and the number of memory channels based on the device identifier.

[0045] For example, the kernel identifies the physical address range of directly accessed memory devices. For instance, for a 4GB directly accessed memory device, the first 2GB (0x1000000000-0x107FFFFFFF) and the last 2GB (0x1080000000-0x10FFFFFFFF) correspond to two different memory modules. Normally, the kernel cannot obtain the characteristics of a memory region; the identified physical address range is a continuous segment of addresses within the directly accessed memory device (e.g., 0x1000000000-0x10FFFFFFFF). In this case, the user can specify the directly accessed memory device to be split and the corresponding number of memory region splits (e.g., 2). The system can then split the continuous memory address into two physical address sub-regions of the same size: 0x1000000000-0x107FFFFFFF and 0x1080000000-0x10FFFFFFFF.

[0046] In some embodiments, the physical address range for direct access to the memory device can also be obtained through a preset interface. This preset interface may be ACPI (Advanced Configuration and Power Interface).

[0047] For example, the physical address range is stored in the current resource setting (CRS), and the physical address range for direct access to the memory device can be obtained by reading the current resource setting through the ACPI interface.

[0048] S203. Establish the interleaving mapping relationship between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels.

[0049] In this embodiment of the disclosure, an interleaving mapping relationship between virtual address information and the corresponding physical address sub-regions of multiple memory channels can be established according to the interleaving mapping granularity. Accordingly, this step may include: obtaining the interleaving mapping granularity between virtual address information and the corresponding physical address sub-regions of multiple memory channels; wherein, the interleaving mapping granularity is used to represent the memory size of the interleaving mapping; and establishing the interleaving mapping relationship between virtual address information and the corresponding physical address sub-regions of multiple memory channels according to the interleaving mapping granularity.

[0050] In some embodiments, the memory interleaving granularity can be dynamically adjusted to adapt to memory access patterns of different workloads. Accordingly, obtaining the interleaving mapping granularity between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels includes: obtaining the memory access pattern corresponding to the memory access request, and determining the interleaving mapping granularity between the virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels from the correspondence between the memory access pattern and the interleaving mapping granularity.

[0051] Optionally, the memory access mode may include a contiguous address access mode and a discrete address access mode. Accordingly, determining the interleaving mapping granularity between virtual address information and the corresponding physical address sub-regions of the multiple memory channels from the correspondence between memory access modes and interleaving mapping granularities includes: if the memory access mode is a contiguous address access mode, then determining the interleaving mapping granularity between virtual address information and the corresponding physical address sub-regions of the multiple memory channels as a first interleaving mapping granularity from the correspondence between memory access modes and interleaving mapping granularities; if the memory access mode is a discrete address access mode, then determining the interleaving mapping granularity between virtual address information and the corresponding physical address sub-regions of the multiple memory channels as a second interleaving mapping granularity from the correspondence between memory access modes and interleaving mapping granularities; wherein the first interleaving mapping granularity is greater than the second interleaving mapping granularity.

[0052] For example, the first interleaving mapping granularity is 2MB, and the second interleaving mapping granularity is 4KB. For contiguous address access patterns, the interleaving mapping granularity is 2MB; for discrete address access patterns, the interleaving mapping granularity is 4KB. It should be noted that for small-block random access loads (such as database queries), a 4KB granularity can be used to achieve fine-grained interleaving; for large-block sequential access loads (such as video processing), a 2MB granularity can be selected to reduce address translation overhead.

[0053] In the embodiments of this disclosure, the memory interleaving granularity can be dynamically adjusted to adapt to memory access patterns of different workloads. For contiguous address access patterns, appropriately increasing the interleaving mapping granularity can allow contiguous addresses to fall into the same channel, improving access efficiency. For discrete address access patterns, appropriately reducing the interleaving mapping granularity can evenly distribute discrete addresses to multiple memory channels, enabling parallel access and making full use of multi-channel bandwidth.

[0054] In this embodiment of the disclosure, an interleaved mapping relationship between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels can be established in various ways.

[0055] In some embodiments, when allocating physical pages, multiple physical address sub-regions corresponding to each memory channel can be alternately selected according to the user-specified memory interleaving granularity. Accordingly, establishing an interleaving mapping relationship between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels according to the interleaving mapping granularity includes: dividing the virtual address information into multiple virtual address sub-regions according to the interleaving mapping granularity; and establishing an interleaving mapping relationship between the multiple virtual address sub-regions and the physical address sub-regions corresponding to each of the multiple memory channels.

[0056] Optionally, an interleaved mapping relationship is established between multiple virtual address sub-regions and their respective physical address sub-regions for multiple memory channels, including: for multiple virtual address sub-regions, alternately determining the physical address sub-regions corresponding to each of the multiple virtual address sub-regions from the physical address sub-regions corresponding to each of the multiple memory channels; and establishing a mapping relationship between the virtual address sub-regions and their corresponding physical address sub-regions.

[0057] For example, such as Figure 3 As shown, based on the interleaving mapping granularity, the virtual address information is divided into multiple virtual address sub-regions. Memory region 1 and memory region 2 are selected alternately to establish the interleaving mapping relationship between the multiple virtual address sub-regions and the physical address sub-regions corresponding to the multiple memory channels.

[0058] In other embodiments, when the kernel memory module is initialized, the kernel divides physical memory into page frames, initializes the page frames, and then hands over free page frames to the buddy system for management. During this process, the translation from physical address to kernel virtual address is completed. At this point, remapping is required to linearly map the kernel virtual address to a pseudo-physical address (i.e., intermediate physical address information) based on the physical address. When actually filling the page table, the real physical address is filled in through remapping. It should be noted that, alternatively, after the kernel completes the page table mapping based on the pseudo-physical address, it can readjust the pseudo-physical address to the interleaved real physical address based on the remapping table.

[0059] Optionally, based on the interleaving mapping granularity, an interleaving mapping relationship is established between virtual address information and the corresponding physical address sub-regions of multiple memory channels, including: based on the interleaving mapping granularity, an interleaving mapping relationship is established between intermediate physical address information and the corresponding physical address sub-regions of multiple memory channels; a mapping relationship is established between virtual address information and intermediate physical address information to obtain the interleaving mapping relationship between virtual address information and the corresponding physical address sub-regions of multiple memory channels.

[0060] For example, such as Figure 4As shown, based on the interleaving mapping granularity, an interleaving mapping relationship is established between intermediate physical address information and the corresponding physical address sub-regions of multiple memory channels, including: dividing the intermediate physical address information into multiple intermediate physical address sub-regions according to the interleaving mapping granularity; and establishing an interleaving mapping relationship between the multiple intermediate physical address sub-regions and the corresponding physical address sub-regions of multiple memory channels.

[0061] S204. Write the interleaving mapping relationship between virtual address information and multiple physical address sub-regions into the page table, and process the memory access requests of user processes according to the interleaving mapping relationship in the page table.

[0062] In this embodiment, when a user process requests memory, it triggers kernel page frame allocation. At this time, in the kernel's page frame management, the physical address is already interleaved and mapped. The system allocates page frames and page tables through the existing call interface, automatically achieving memory interleaving from virtual address to physical address. Therefore, when processing memory access requests from user processes, consecutive physical address access requests can be evenly distributed across multiple memory channels, fully utilizing the bandwidth of multiple memory channels and improving the parallel bandwidth utilization of multiple memory channels, thus increasing the server's memory access speed.

[0063] In some embodiments, retaining the identification information corresponding to the directly accessed memory device in the page table can avoid triggering page caching or exceptions.

[0064] This application proposes a memory allocation method for direct access memory devices: In response to a user process's memory access request, virtual address information is allocated to the user process; the physical address range of the direct access memory device is obtained, the physical address range including physical address sub-regions corresponding to multiple memory channels; an interleaving mapping relationship is established between the virtual address information and the physical address sub-regions corresponding to the multiple memory channels; the interleaving mapping relationship between the virtual address information and the multiple physical address sub-regions is written into a page table, and the user process's memory access request is processed according to the interleaving mapping relationship in the page table. In this embodiment, by establishing an interleaving mapping relationship between the virtual address information and the physical address sub-regions corresponding to the multiple memory channels, continuous physical address access requests can be evenly distributed across multiple memory channels when processing user process memory access requests, fully utilizing the bandwidth of multiple memory channels, thereby improving the parallel bandwidth utilization of multiple memory channels and thus increasing the server's memory access speed.

[0065] Figure 5 This is a schematic diagram of the memory allocation device for direct access to memory devices provided in an embodiment of this application. Figure 5 As shown, the device includes:

[0066] The allocation unit 501 is used to allocate virtual address information to the user process in response to the user process's memory access request;

[0067] The acquisition unit 502 is used to acquire the physical address range of the directly accessed memory device. The physical address range includes the physical address sub-regions corresponding to each of the multiple memory channels.

[0068] Establishment unit 503 is used to establish the interleaving mapping relationship between virtual address information and the physical address sub-regions corresponding to multiple memory channels;

[0069] The processing unit 504 is used to write the interleaving mapping relationship between virtual address information and multiple physical address sub-regions into a page table, and to process the memory access request of the user process according to the interleaving mapping relationship in the page table.

[0070] In some embodiments, the establishment unit 503 establishes an interleaving mapping relationship between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels, including: obtaining the interleaving mapping granularity between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels; wherein the interleaving mapping granularity is used to represent the memory size of the interleaving mapping; and establishing the interleaving mapping relationship between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels according to the interleaving mapping granularity.

[0071] In some embodiments, the establishment unit 503 obtains the interleaving mapping granularity between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels, including: obtaining the memory access mode corresponding to the memory access request, and determining the interleaving mapping granularity between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels from the correspondence between the memory access mode and the interleaving mapping granularity.

[0072] In some embodiments, the memory access modes include a contiguous address access mode and a discrete address access mode. Accordingly, the establishment unit 503 determines the interleaving mapping granularity between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels from the correspondence between memory access modes and interleaving mapping granularity, including: if the memory access mode is a contiguous address access mode, then the interleaving mapping granularity between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels is determined as a first interleaving mapping granularity from the correspondence between memory access modes and interleaving mapping granularity; if the memory access mode is a discrete address access mode, then the interleaving mapping granularity between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels is determined as a second interleaving mapping granularity from the correspondence between memory access modes and interleaving mapping granularity; wherein the first interleaving mapping granularity is greater than the second interleaving mapping granularity.

[0073] In some embodiments, the establishing unit 503 establishes an interleaving mapping relationship between virtual address information and the physical address sub-regions corresponding to the multiple memory channels according to the interleaving mapping granularity, including: dividing the virtual address information into multiple virtual address sub-regions according to the interleaving mapping granularity; and establishing an interleaving mapping relationship between the multiple virtual address sub-regions and the physical address sub-regions corresponding to the multiple memory channels.

[0074] In some embodiments, the establishment unit 503 establishes an interleaved mapping relationship between multiple virtual address sub-regions and the physical address sub-regions corresponding to each of the multiple memory channels, including: for multiple virtual address sub-regions, alternately determining the physical address sub-regions corresponding to each of the multiple virtual address sub-regions from the physical address sub-regions corresponding to each of the multiple memory channels; and establishing a mapping relationship between the virtual address sub-regions and the physical address sub-regions corresponding to the virtual address sub-regions.

[0075] In some embodiments, the establishing unit 503 establishes an interleaving mapping relationship between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels according to the interleaving mapping granularity, including: establishing an interleaving mapping relationship between intermediate physical address information and the physical address sub-regions corresponding to each of the multiple memory channels according to the interleaving mapping granularity; establishing a mapping relationship between virtual address information and intermediate physical address information to obtain the interleaving mapping relationship between virtual address information and the physical address sub-regions corresponding to each of the multiple memory channels.

[0076] In some embodiments, the establishing unit 503 establishes an interleaving mapping relationship between intermediate physical address information and the physical address sub-regions corresponding to the multiple memory channels according to the interleaving mapping granularity, including: dividing the intermediate physical address information into multiple intermediate physical address sub-regions according to the interleaving mapping granularity; and establishing an interleaving mapping relationship between the multiple intermediate physical address sub-regions and the physical address sub-regions corresponding to the multiple memory channels.

[0077] In some embodiments, the acquisition unit 502 acquires the physical address range of the directly accessed memory device, including: acquiring the physical address range of the directly accessed memory device and the number of memory channels; and dividing the physical address range into multiple physical address sub-regions according to the number of memory channels.

[0078] In some embodiments, the acquisition unit 502 acquires the physical address range and the number of memory channels of the directly accessed memory device, including: acquiring the device identifier of the directly accessed memory device corresponding to the memory access request; and acquiring the physical address range and the number of memory channels of the directly accessed memory device from a pre-stored correspondence between the device identifier, the physical address range, and the number of memory channels based on the device identifier.

[0079] This application provides a memory allocation device for direct access to memory devices. By establishing an interleaved mapping relationship between virtual address information and the corresponding physical address sub-regions of multiple memory channels, when processing memory access requests from user processes, continuous physical address access requests can be evenly distributed across multiple memory channels, making full use of the bandwidth of multiple memory channels, thereby improving the parallel bandwidth utilization of multiple memory channels and thus increasing the memory access speed of the server.

[0080] The description of the features of the memory allocation device for direct access to memory devices provided in this application can be found in the relevant description of the memory allocation method for direct access to memory devices, and will not be repeated here.

[0081] Figure 6 A schematic diagram of the structure of the electronic device provided in this application. Figure 6 As shown, the electronic device 60 provided in this embodiment includes at least one processor 601 and a memory 602. Optionally, the electronic device 60 further includes a communication component 603. The processor 601, memory 602, and communication component 603 are connected via a bus.

[0082] In a specific implementation, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to execute the memory allocation method embodiment described above for directly accessing memory devices.

[0083] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0084] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0085] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0086] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0087] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the memory allocation method for direct access to memory devices when it is run.

[0088] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0089] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the memory allocation method for directly accessing memory devices.

[0090] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the memory allocation method for directly accessing memory devices.

[0091] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0092] The foregoing has provided a detailed description of a memory allocation method and apparatus for directly accessing memory devices provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A memory allocation method for a direct access memory device, characterized by, The method comprises: allocating virtual address information for a user process in response to a memory access request of the user process; obtaining a physical address range of a direct access memory device, the physical address range comprising a plurality of physical address sub-regions corresponding to a plurality of memory channels respectively; obtaining a memory access mode corresponding to the memory access request, and determining an interleaving mapping granularity between the virtual address information and the plurality of physical address sub-regions corresponding to the plurality of memory channels respectively from a correspondence relationship between memory access modes and interleaving mapping granularities, wherein the interleaving mapping granularity represents a memory size of interleaving mapping; establishing an interleaving mapping relationship between the virtual address information and the plurality of physical address sub-regions corresponding to the plurality of memory channels respectively according to the interleaving mapping granularity; and writing the interleaving mapping relationship between the virtual address information and the plurality of physical address sub-regions into a page table, and processing the memory access request of the user process according to the interleaving mapping relationship in the page table.

2. The memory allocation method of claim 1, wherein, The memory access mode comprises a continuous address access mode and a discrete address access mode. Correspondingly, determining the interleaving mapping granularity between the virtual address information and the plurality of physical address sub-regions corresponding to the plurality of memory channels respectively from the correspondence relationship between memory access modes and interleaving mapping granularities comprises: if the memory access mode is the continuous address access mode, determining the interleaving mapping granularity between the virtual address information and the plurality of physical address sub-regions corresponding to the plurality of memory channels respectively from the correspondence relationship between memory access modes and interleaving mapping granularities as a first interleaving mapping granularity; if the memory access mode is the discrete address access mode, determining the interleaving mapping granularity between the virtual address information and the plurality of physical address sub-regions corresponding to the plurality of memory channels respectively from the correspondence relationship between memory access modes and interleaving mapping granularities as a second interleaving mapping granularity; wherein the first interleaving mapping granularity is greater than the second interleaving mapping granularity.

3. The memory allocation method of claim 1, wherein, The method further comprises: dividing the virtual address information into a plurality of virtual address sub-regions according to the interleaving mapping granularity; and establishing an interleaving mapping relationship between the plurality of virtual address sub-regions and the plurality of physical address sub-regions corresponding to the plurality of memory channels respectively.

4. The memory allocation method of claim 3, wherein, The method further comprises: alternately determining a plurality of physical address sub-regions corresponding to the plurality of virtual address sub-regions from the plurality of physical address sub-regions corresponding to the plurality of memory channels respectively; and establishing a mapping relationship between the virtual address sub-regions and the physical address sub-regions corresponding to the virtual address sub-regions.

5. The memory allocation method of claim 1, wherein, The method further comprises: dividing intermediate physical address information into a plurality of intermediate physical address sub-regions according to the interleaving mapping granularity; and establishing an interleaving mapping relationship between the plurality of intermediate physical address sub-regions and the plurality of memory channel corresponding physical address sub-regions; establishing a mapping relationship between the virtual address information and the intermediate physical address information, and obtaining an interleaving mapping relationship between the virtual address information and the plurality of memory channel corresponding physical address sub-regions.

6. The memory allocation method of claim 1, wherein, The method further includes: obtaining a physical address range of the direct access memory device and a memory channel number; splitting the physical address range into a plurality of physical address sub-regions according to the memory channel number.

7. The memory allocation method of claim 6, wherein, The method further includes: obtaining a device identifier of the direct access memory device corresponding to the memory access request; obtaining the physical address range and the memory channel number of the direct access memory device from a pre-stored corresponding relationship among device identifiers, physical address ranges and memory channel numbers according to the device identifier.

8. An electronic device, comprising: The method further includes: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the memory allocation method of the direct access memory device according to any one of claims 1 to 7.

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