A bus link, a circuit board, a server and a bus link configuration method

Abstract

The application discloses a bus link, a circuit board, a server and a bus link configuration method, and relates to the technical field of computers. The bus link comprises backboard circuit and mainboard circuit. The mainboard circuit comprises switching device and first buffer. The backboard circuit comprises backboard buffer and floating port. The floating port is connected with the mainboard circuit, and the backboard buffer is connected with the second type mainboard. When the mainboard circuit is configured as the first type mainboard, the first buffer is connected with one end of any backboard buffer, and the switching device is connected with the corresponding floating port. When the mainboard circuit is configured as the second type mainboard, the first buffer is connected with the corresponding floating port, and the switching device is connected with the other end of the corresponding backboard buffer. The first type mainboard accesses the corresponding second type mainboard through the backboard buffer. The mainboard circuit structure is unified, and the bus device is convenient to access.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a bus link, a circuit board, a server and a bus link configuration method. BACKGROUND

[0002] In order to improve the computing performance of the server, a multi-path server system is usually composed of multiple mainboards. Each mainboard is equipped with a processor and a plurality of I 2 C bus devices. For a multi-path server, in order to avoid bus conflicts, only the master processor is allowed to access and manage the I 2 C bus devices. Usually, for a multi-path server system, the mainboard equipped with the master processor and the mainboard equipped with the slave processor are connected in series to build a server topology architecture. This will cause the circuit structure of the mainboard equipped with the master processor to be different from the circuit structure of the mainboard equipped with the slave processor; and when the master processor accesses the I 2 C bus devices on other mainboards, the link is too long and the link control is complex. SUMMARY

[0003] The present application provides a bus link, a circuit board, a server and a bus link configuration method, which at least solves the problem of consistency of circuit design of the mainboard equipped with the master processor and the slave processor in a multi-path server with multiple mainboards interconnected, and the problem of low access efficiency of the master processor to the slave device caused by the multi-path topology structure.

[0004] In a first aspect, the present application provides a bus link, comprising: a backboard circuit and a mainboard circuit;

[0005] The mainboard circuit comprises a switching device and a first buffer;

[0006] The type of the mainboard circuit comprises a first type of mainboard and a second type of mainboard; the bus link comprises the first type of mainboard and at least one second type of mainboard;

[0007] The backboard circuit comprises a backboard buffer and a floating port;

[0008] The floating port is connected to the mainboard circuit, and the backboard buffer is connected to the second type of mainboard;

[0009] When the mainboard circuit is configured as the first type of mainboard, the first buffer is connected to one end of any backboard buffer, and the switching device is connected to the corresponding floating port;

[0010] When the mainboard circuit is configured as the second type of mainboard, the first buffer is connected to the corresponding floating port, and the switching device is connected to the other end of the corresponding backboard buffer;

[0011] The first type of mainboard accesses the corresponding second type of mainboard through the backplane buffer.

[0012] In a second aspect, the application provides a circuit board, comprising a backplane and a mainboard;

[0013] The backplane is provided with the backplane circuit in the bus link of the first aspect;

[0014] The mainboard is provided with the mainboard circuit in the bus link of the first aspect.

[0015] In a third aspect, the application provides a server, comprising the circuit board of the second aspect.

[0016] In a fourth aspect, the application provides a bus link configuration method, applicable to the server of the third aspect, wherein the mainboard of the server is provided with a controller, and the controller executes the bus link configuration method in response to the power-on of the server, comprising:

[0017] In response to the power-on of the server, the controller is activated;

[0018] The address of the corresponding mainboard is obtained, and the switch device address of the mainboard is configured with the address;

[0019] In response to the access instruction of the processor in the first type of mainboard to the bus device carried by the mainboard, the access path of the corresponding bus device is opened.

[0020] The technical scheme provided by the embodiments of the application has the beneficial effects that: by implementing the bus link, the circuit board, the server and the bus link configuration method provided by the embodiments of the application, the circuit structures of the main processor mainboard and the slave processor mainboard can be unified; in the topological structure, the mainboard carrying the slave processor is connected to the backplane in parallel, the link of the main processor accessing the slave device is shortened, and the control of the device on the access link of the slave device is simplified. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0022] Figure 1 is a conventional single-mainboard server I 2 C topological schematic diagram;

[0023] Figure 2 is a conventional multi-mainboard server I 2 C topological schematic diagram;

[0024] Figure 3 is a bus link schematic diagram provided by an embodiment of the present application;

[0025] Figure 4 is another bus link schematic diagram provided by an embodiment of the present application;

[0026] Figure 5 is another bus link schematic diagram provided by an embodiment of the present application;

[0027] Figure 6 is a bus link configuration method schematic diagram provided by an embodiment of the present application;

[0028] Figure 7 is a switch device address information configuration schematic diagram of a mainboard provided by an embodiment of the present application;

[0029] Figure 8 is an access path opening schematic diagram of a corresponding bus device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0031] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms “one”, “an” or “the” and similar terms do not indicate a quantity limitation, but indicate the presence of at least one. The numbers in the drawings of the specification only represent the distinction of the respective functional components or modules, and do not represent the logical relationship between the components or modules. The terms “include” or “contain” and similar terms mean that the elements or objects before the terms cover the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “up”, “down”, “left”, “right” and the like only represent relative positional relationships, which may change accordingly when the absolute position of the described object changes.

[0032] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.

[0033] With the development of semiconductor technology, the integration of processors and controllers has exploded. For servers, the number of bus devices they incorporate is increasing to meet the demands of intelligent scenarios. This trend typically leads to the adoption of bus-based architectures (such as I / O). 2 Devices can be interconnected using C-bus, eSPI bus, etc., and different peripherals can be distinguished by device addresses. This solves the problem of increased device packaging costs and increased hardware design complexity caused by the increase in the number of discrete GPIO (General Purpose Input / Output) pins.

[0034] In terms of bus link topology, it consists of a single motherboard server (such as...) Figure 1 As shown), it gradually evolved into a multi-motherboard server (such as...). Figure 2 (as shown), to accommodate the needs of bus device expansion.

[0035] In a single-motherboard server topology, the processor's I... 2 After level conversion by the buffer, the C bus accesses I... 2 C-type switching device. The channels of the switching device carry multiple I-type switches with different addresses. 2 C devices (e.g., EEPROM memory, temperature sensors, I / O expanders, etc.) have their buffers enabled. The addresses of the switching devices are set to fixed values ​​using static pull-up and pull-down switches, and the reset signals for the switching devices are directly pulled up without additional control. While this topology allows for processor bus and I / O expansion in a single-motherboard system, expanding the processor requires at least one additional independent motherboard to achieve a multi-processor system. In a multi-processor system, only the main processor's I / O... 2 The C bus has functionality, which will prevent the main processor from interacting with other I / O devices on the motherboard. 2 C-bus device communication.

[0036] To overcome the above-mentioned shortcomings, the following evolved: Figure 2 The multi-processor server system shown. The main processor's I... 2 C accesses I through the buffer. 2 The C-type switching device has one channel connected to a second motherboard via a backplane. The second motherboard then uses the switching device to expand its bus functionality to include more devices. It should be noted that... Figure 2The two mainboards are schematically illustrated. If the mainboard is expanded, the newly expanded mainboard is cascaded on the switch device channel of the previous mainboard. This architecture effectively solves the problem that the main processor cannot access the slave device, but its defects are also obvious: the mainboard circuit carrying the main processor is designed differently from other mainboard circuits, and multiple mainboards need to be developed to achieve this architecture, increasing the development workload and development cost; the multi-level cascaded switch device affects the I 2 C communication efficiency. Unless otherwise specified, the master device in this application refers to the bus device expanded by the switch device on the mainboard carrying the main processor; the slave device refers to the bus device expanded by the switch device on the mainboard carrying the main processor.

[0037] In view of the problem that the mainboard circuit carrying the main processor and the mainboard circuit carrying the slave processor are designed differently in the bus link of the multi-path server with multi-mainboard interconnection in the prior art, and the problem of low access efficiency of the main processor to the slave device caused by the multi-path topology structure, the following embodiments are provided:

[0038] In some embodiments, as shown in FIG. 1, a bus link includes a backboard circuit 000 and a mainboard circuit 100. Figure 3

[0039] The mainboard circuit 100 includes a switch device 110 and a first buffer 120.

[0040] The type of the mainboard circuit 100 includes a first type mainboard 100a and a second type mainboard 100b; the bus link includes the first type mainboard 100a and at least one second type mainboard 100b.

[0041] The backboard circuit 000 includes a backboard buffer 010 and a floating port 000a.

[0042] The floating port 000a corresponds to the connection of the mainboard circuit 100, and the backboard buffer 010 corresponds to the connection of the second type mainboard 100b.

[0043] When the mainboard circuit 100 is configured as the first type mainboard 100a, the first buffer 120 is connected to one end of any backboard buffer 010, and the switch device 110 is connected to the corresponding floating port 000a.

[0044] When the mainboard circuit 100 is configured as the second type mainboard 100b, the first buffer 120 is connected to the corresponding floating port 000a, and the switch device 110 is connected to the other end of the corresponding backboard buffer 010.

[0045] The first type mainboard 100a accesses the corresponding second type mainboard 100b through the backboard buffer 010.

[0046] ​Preferably, a bus link refers to I 2 C bus link.

[0047] Preferably, the switching device is an analog switch with high bandwidth, and the switching on or off of the analog switch is controlled by an enable signal.

[0048] A buffer is used to isolate input signals from output signals. Typically, a buffer amplifies the input signal before outputting it; a buffer can also convert the level of an input signal to another level before outputting it. In this application, the first buffer, the second buffer, and the backplane buffer are all buffers.

[0049] Both the first type and the second type of motherboard have the same circuit structure. The difference between them lies in the connection method with the backplane: the first buffer of the first type motherboard is connected to one end of any backplane buffer, and its switching device is connected to the floating port on the backplane corresponding to the motherboard; the first buffer of the second type motherboard is connected to the floating port on the backplane corresponding to the motherboard, and its switching device is connected to the other end of the backplane buffer corresponding to the motherboard.

[0050] Typically, the processor is located on the motherboard. The processor on the first type of motherboard is the main processor, because I... 2 The C bus link is used by the main processor to access bus devices. On a Type 1 motherboard, can the main processor access any bus device on the motherboard via this bus link?

[0051] The floating port is designed to ensure structural consistency between the first type of motherboard and the second type of motherboard, so that the first buffer and switching device on the first type of motherboard and the first buffer and switching device on the second type of motherboard are both connected to the backplane.

[0052] Therefore, the circuit structure of the first type of motherboard with a main processor and the second type of motherboard with a slave processor are unified; the second type of motherboard forms a "parallel" connection with the first type of motherboard through a backplane buffer, shortening the link for the main processor to access the slave device and simplifying the control of devices on the slave device access link. The specific access method will be described below.

[0053] like Figure 4 As shown, the motherboard circuit 100 also includes: a second buffer 130, a switching device 140, and a processor 190.

[0054] The processor 190 is connected to the second buffer 130, which is connected to the switching device 110 and the first buffer 120, and then to the switching device 140.

[0055] Switching device 140 is used to carry bus device 900.

[0056] The processor 190 on the first type of motherboard 100a is configured to access the bus device 900 connected to the switching device 140.

[0057] The above-mentioned motherboard topology realizes the access path of the processor on the motherboard to the bus device.

[0058] For the first type of motherboard, the processor can access not only the bus device carried on the motherboard, but also the bus device carried on other motherboards.

[0059] Specifically, the switching device 110 has a switching device first port 110a and a switching device second port 110b.

[0060] The first buffer 120 has a first buffer first port 120a and a first buffer second port 120b.

[0061] The second buffer 130 has a second buffer first port 130a and a second buffer second port 130b.

[0062] The switching device 140 has a switching device bus transmission port 140a and at least one switching device device channel 140b.

[0063] The processor 190 is connected to the second buffer first port 130a, and after the second buffer second port 130b is connected to the switching device first port 110a and the first buffer first port 120a, it is connected to the switching device bus transmission port 140a, and the switching device device channel 140b is used to connect the bus device 900.

[0064] Preferably, the bus link further comprises an expander 150.

[0065] The expander 150 is connected to the switching device 140 and is used to expand the bus device 900 carried on the motherboard.

[0066] The expander refers to an I / O expander. Preferably, the I / O expander is an I 2 C I / O expander, which can convert an I 2 C bus into multiple GPIOs, so that the motherboard can carry more bus devices.

[0067] The expander 150 has an expander bus transmission port 150a and a plurality of expander device channels 150b.

[0068] The expander bus transmission port 150a is connected to the switching device device channel 140b of the switching device 140, and the plurality of expander device channels 150b are used to carry the bus device 900.

[0069] Preferably, asFigure 5 As shown, the motherboard circuit 100 also includes a controller 160.

[0070] The controller 160 is connected to the switching device 110, the first buffer 120, the second buffer 130 and the switching device 140, and is used to configure the enable state of the switching device 110, the first buffer 120 and the second buffer 130, and to configure the address information and reset command of the switching device 140.

[0071] The controller has the functions of setting enable signals; receiving and sending address information; and sending reset commands. Preferably, a CPLD (Complex Programmable Logic Device) is used as the controller. The controller is at least used to send enable signals to the first buffer, the second buffer, and the switching device; receive address signals from the backplane; configure the address information of the switching device; and configure the reset command of the switching device.

[0072] Specifically, the controller 160 has: a first control port 160a, a second control port 160b, a third control port 160c, an address configuration port 160d, and a reset configuration port 160e.

[0073] Switching device 110 also has: switching device enable port 110c.

[0074] The first buffer 120 also has: a first buffer enable port 120c.

[0075] The second buffer 130 also has: a second buffer enable port 130c.

[0076] The switching device 140 also has: an address setting port 140c and a reset setting port 140d.

[0077] The first control port 160a is connected to the switch device enable port 110c and is used to transmit the enable signal sent by the controller 160 to the switch device 110.

[0078] The second control port 160b is connected to the first buffer enable port 120c and is used to transmit the enable signal sent by the controller 160 to the first buffer 120.

[0079] The third control port 160c is connected to the second buffer enable port 130c and is used to transmit the enable signal sent by the controller 160 to the second buffer 130.

[0080] Address configuration port 160d is connected to address setting port 140c and is used to configure the address information of switching device 140.

[0081] The reset configuration port 160e is connected to the reset setting port 140d and is used to configure the reset command of the switching device 140.

[0082] Preferably, the controller 160 also has an address receiving port 160f.

[0083] Address receiving port 160f is connected to backplane circuit 000 and is used to obtain the address information of switching device 140 in the corresponding motherboard circuit 100.

[0084] Address information for configuring switching devices can be obtained from the backplane via address receive port 160f.

[0085] Address information is typically represented using at least one binary digit. To illustrate, a two-motherboard system uses one binary digit to represent address information; a four-motherboard system uses two binary digits; and an eight-motherboard system uses three binary digits.

[0086] Accordingly, for a two-motherboard system, address configuration port 160d has one pin to receive address information; for a four-motherboard system, address configuration port 160d has two pins to receive address information; and for an eight-motherboard system, address configuration port 160d has three pins to receive address information.

[0087] For example, in a system with four motherboards, "00" represents the first type of motherboard, and "01", "10" and "11" represent the three second type motherboards respectively.

[0088] Preferably, the first buffer 120 further includes: a first power port 120c and a second power port 120d.

[0089] The second buffer 130 also has: a first power port 130d for the second buffer and a second power port 130e for the second buffer.

[0090] The first power supply port 120c, the second power supply port 120d, and the second power supply port 130e of the first buffer are used to connect to the first power supply Vcc1.

[0091] The first power port 130d of the second buffer is used to connect to the second power supply Vcc2.

[0092] Indicatively, the voltage of the first power supply Vcc1 is 3.3V, and the voltage of the second power supply Vcc2 is 1.8V.

[0093] The buffer isolates the input and output signals. The second buffer also converts the signal level between 1.8V and 3.3V.

[0094] By implementing the bus link provided in the embodiments of this application, the circuit structure of the motherboard equipped with the main processor and the motherboard equipped with the slave processor can be unified. In terms of topology, the motherboard equipped with the slave processor is connected to the backplane in parallel, which shortens the link for the main processor to access the slave device. After the bus link is configured, the control of the devices on the slave device access link can be simplified.

[0095] In other embodiments, a circuit board includes a backplane and a motherboard; the backplane is provided with the backplane circuitry in the bus link described above; and the motherboard is provided with the motherboard circuitry in the bus link described above.

[0096] The motherboard circuit 100 includes a switching device 110 and a first buffer 120.

[0097] The motherboard circuit 100 includes: a first type motherboard 100a and a second type motherboard 100b; the bus link includes: a first type motherboard 100a and at least one second type motherboard 100b.

[0098] The backplane circuit 000 includes: a backplane buffer 010 and a floating port 000a.

[0099] The floating port 000a is connected to the motherboard circuit 100, and the backplane buffer 010 is connected to the second type of motherboard 100b.

[0100] When the motherboard circuit 100 is configured as a first type motherboard 100a, the first buffer 120 is connected to one end of any backplane buffer 010, and the switching device 110 is connected to the corresponding floating port 000a; when the motherboard circuit 100 is configured as a second type motherboard 100b, the first buffer 120 is connected to the corresponding floating port 000a, and the switching device 110 is connected to the other end of the corresponding backplane buffer 010.

[0101] The first type motherboard 100a accesses the corresponding second type motherboard 100b through the backplane buffer 010.

[0102] The motherboard circuit 100 also includes: a second buffer 130, a switching device 140, and a processor 190;

[0103] The processor 190 is connected to the second buffer 130, and the second buffer 130 is connected to the switching device 110 and the first buffer 120, and then connected to the switching device 140.

[0104] Switching device 140 is used to carry bus device 900;

[0105] The processor 190 on the first type motherboard 100a is used to access the bus device 900 connected to the switching device 140.

[0106] The switching device 110 has: a first port 110a and a second port 110b.

[0107] The first buffer 120 has: a first buffer first port 120a and a first buffer second port 120b;

[0108] The second buffer 130 has: a second buffer first port 130a and a second buffer second port 130b;

[0109] Switching device 140 has: a switching device bus transmission port 140a and at least one switching device device channel 140b;

[0110] The processor 190 is connected to the first port 130a of the second buffer. The second port 130b of the second buffer is connected to the first port 110a of the switching device and the first port 120a of the first buffer, and then connected to the bus transmission port 140a of the switching device. The device channel 140b of the switching device is used to connect to the bus device 900.

[0111] The bus link also includes extender 150;

[0112] The expander 150 is connected to the switching device 140 and is used to expand the bus device 900 on the motherboard.

[0113] The expander 150 has: an expander bus transmission port 150a and several expander device channels 150b;

[0114] The extender bus transmission port 150a is connected to the switching device device channel 140b of the switching device 140, and carries the bus device 900 through several extender device channels 150b.

[0115] The motherboard circuit 100 also includes a controller 160;

[0116] The controller 160 is connected to the switching device 110, the first buffer 120, the second buffer 130 and the switching device 140, and is used to configure the enable state of the switching device 110, the first buffer 120 and the second buffer 130, and to configure the address information and reset command of the switching device 140.

[0117] The controller 160 has: a first control port 160a, a second control port 160b, a third control port 160c, an address configuration port 160d, and a reset configuration port 160e;

[0118] The switching device 110 also has: a switching device enable port 110c;

[0119] The first buffer 120 also has: a first buffer enable port 120c;

[0120] The second buffer 130 also has: a second buffer enable port 130c;

[0121] Switching device 140 also includes: address setting port 140c and reset setting port 140d;

[0122] The first control port 160a is connected to the switch device enable port 110c and is used to transmit the enable signal sent by the controller 160 to the switch device 110.

[0123] The second control port 160b is connected to the first buffer enable port 120c and is used to transmit the enable signal sent by the controller 160 to the first buffer 120.

[0124] The third control port 160c is connected to the second buffer enable port 130c and is used to transmit the enable signal sent by the controller 160 to the second buffer 130.

[0125] Address configuration port 160d is connected to address setting port 140c and is used to configure the address information of switching device 140;

[0126] The reset configuration port 160e is connected to the reset setting port 140d and is used to configure the reset command of the switching device 140.

[0127] Controller 160 also has an address receiving port 160f;

[0128] Address receiving port 160f is connected to backplane circuit 000 and is used to obtain the address information of switching device 140 in the corresponding motherboard circuit 100.

[0129] The first buffer 120 also includes: a first power port 120c and a second power port 120d of the first buffer;

[0130] The second buffer 130 also includes: a first power port 130d for the second buffer and a second power port 130e for the second buffer;

[0131] The first power supply port 120c, the second power supply port 120d, and the second power supply port 130e of the first buffer are used to connect to the first power supply Vcc1.

[0132] The first power port 130d of the second buffer is used to connect to the second power supply Vcc2.

[0133] Preferably, the spacing between adjacent backplate buffers on the backplate is less than a spacing threshold;

[0134] The distance between the first buffer on the motherboard and the switching device is less than the distance threshold;

[0135] The distance between the switching device on the motherboard and the second buffer is less than the distance threshold.

[0136] Preferably, the spacing threshold is 2 inches. Using 2 inches as the spacing threshold for the above-mentioned circuit components is to place the components as close as possible to improve signal transmission quality.

[0137] The circuit board provided in this application serves as the carrier for the aforementioned bus link, enabling a unified circuit structure for both the main processor motherboard and the slave processor motherboard. In terms of topology, the motherboard carrying the slave processor is connected to the backplane in parallel, shortening the link for the main processor to access the slave device. After bus link configuration, the control of devices accessing the slave device's link is simplified. By setting a spacing threshold, signal transmission quality is improved.

[0138] In other embodiments, a server includes the circuit board described above.

[0139] The circuit board includes a backplate and a motherboard.

[0140] The backplane circuitry of the bus link described above is installed on the backplane.

[0141] The motherboard contains the motherboard circuitry in the bus link described above.

[0142] The motherboard circuit 100 includes: a switching device 110 and a first buffer 120;

[0143] The motherboard circuit 100 includes: a first type motherboard 100a and a second type motherboard 100b; the bus link includes: a first type motherboard 100a and at least one second type motherboard 100b;

[0144] The backplane circuit 000 includes: a backplane buffer 010 and a floating port 000a;

[0145] The floating port 000a is connected to the main board circuit 100, and the backplane buffer 010 is connected to the second type of main board 100b.

[0146] When the motherboard circuit 100 is configured as the first type motherboard 100a, the first buffer 120 is connected to one end of any backplane buffer 010, and the switching device 110 is connected to the corresponding floating port 000a.

[0147] When the motherboard circuit 100 is configured as the second type motherboard 100b, the first buffer 120 is connected to the corresponding floating port 000a, and the switching device 110 is connected to the other end of the corresponding backplane buffer 010.

[0148] The first type motherboard 100a accesses the corresponding second type motherboard 100b through the backplane buffer 010.

[0149] The motherboard circuit 100 also includes: a second buffer 130, a switching device 140, and a processor 190;

[0150] The processor 190 is connected to the second buffer 130, and the second buffer 130 is connected to the switching device 110 and the first buffer 120, and then connected to the switching device 140.

[0151] Switching device 140 is used to carry bus device 900;

[0152] The processor 190 on the first type motherboard 100a is used to access the bus device 900 connected to the switching device 140.

[0153] The switching device 110 has: a first port 110a and a second port 110b.

[0154] The first buffer 120 has: a first buffer first port 120a and a first buffer second port 120b;

[0155] The second buffer 130 has: a second buffer first port 130a and a second buffer second port 130b;

[0156] Switching device 140 has: a switching device bus transmission port 140a and at least one switching device device channel 140b;

[0157] The processor 190 is connected to the first port 130a of the second buffer. The second port 130b of the second buffer is connected to the first port 110a of the switching device and the first port 120a of the first buffer, and then connected to the bus transmission port 140a of the switching device. The device channel 140b of the switching device is used to connect to the bus device 900.

[0158] The bus link also includes extender 150;

[0159] The expander 150 is connected to the switching device 140 and is used to expand the bus device 900 on the motherboard.

[0160] The expander 150 has: an expander bus transmission port 150a and several expander device channels 150b;

[0161] The extender bus transmission port 150a is connected to the switching device device channel 140b of the switching device 140, and carries the bus device 900 through several extender device channels 150b.

[0162] The motherboard circuit 100 also includes a controller 160;

[0163] The controller 160 is connected to the switching device 110, the first buffer 120, the second buffer 130 and the switching device 140, and is used to configure the enable state of the switching device 110, the first buffer 120 and the second buffer 130, and to configure the address information and reset command of the switching device 140.

[0164] The controller 160 has: a first control port 160a, a second control port 160b, a third control port 160c, an address configuration port 160d, and a reset configuration port 160e;

[0165] The switching device 110 also has: a switching device enable port 110c;

[0166] The first buffer 120 also has: a first buffer enable port 120c;

[0167] The second buffer 130 also has: a second buffer enable port 130c;

[0168] Switching device 140 also includes: address setting port 140c and reset setting port 140d;

[0169] The first control port 160a is connected to the switch device enable port 110c and is used to transmit the enable signal sent by the controller 160 to the switch device 110.

[0170] The second control port 160b is connected to the first buffer enable port 120c and is used to transmit the enable signal sent by the controller 160 to the first buffer 120.

[0171] The third control port 160c is connected to the second buffer enable port 130c and is used to transmit the enable signal sent by the controller 160 to the second buffer 130.

[0172] Address configuration port 160d is connected to address setting port 140c and is used to configure the address information of switching device 140;

[0173] The reset configuration port 160e is connected to the reset setting port 140d and is used to configure the reset command of the switching device 140.

[0174] Controller 160 also has an address receiving port 160f;

[0175] Address receiving port 160f is connected to backplane circuit 000 and is used to obtain the address information of switching device 140 in the corresponding motherboard circuit 100.

[0176] The first buffer 120 also includes: a first power port 120c and a second power port 120d of the first buffer;

[0177] The second buffer 130 also includes: a first power port 130d for the second buffer and a second power port 130e for the second buffer;

[0178] The first power supply port 120c, the second power supply port 120d, and the second power supply port 130e of the first buffer are used to connect to the first power supply Vcc1.

[0179] The first power port 130d of the second buffer is used to connect to the second power supply Vcc2.

[0180] Preferably, the spacing between adjacent backplate buffers on the backplate is less than a spacing threshold;

[0181] The distance between the first buffer on the motherboard and the switching device is less than the distance threshold;

[0182] The distance between the switching device on the motherboard and the second buffer is less than the distance threshold.

[0183] By implementing the server provided in this application embodiment, the circuit structure of the main processor motherboard and the slave processor motherboard can be uniformly installed when designing and manufacturing the server; in terms of topology, the motherboard with the slave processor is connected to the backplane in parallel, which shortens the link for the main processor to access the slave device, and the control of the devices on the slave device access link can be simplified by configuring the bus link; and the signal transmission quality is guaranteed.

[0184] In other embodiments, such as Figure 6 As shown, a bus link configuration method is applicable to the server described above. The server's motherboard has a controller. In response to the server powering on, the controller executes the bus link configuration method, including:

[0185] S100: Activates the controller in response to the server power-on.

[0186] S200: Obtain the address information of the corresponding motherboard and configure the address information of the motherboard's switching device using the address information.

[0187] S300: In response to the processor's access command for the bus device on the motherboard in the first type of motherboard, open the access path of the corresponding bus device.

[0188] After the server powers on, the controller will be activated. The activated controller will then obtain the address information of the corresponding motherboard from the backplane and use this address information to configure the address information of the switching devices on that motherboard. Once the switch address information takes effect, the switching devices on the motherboard will have unique addresses.

[0189] Address information is typically represented using at least one binary digit. To illustrate, a two-motherboard system uses one binary digit to represent address information; a four-motherboard system uses two binary digits; and an eight-motherboard system uses three binary digits.

[0190] For example, in a system with four motherboards, "00" represents the first type of motherboard, and "01", "10" and "11" represent the three second type motherboards respectively.

[0191] Specifically, such as Figure 7 As shown, the address information of the corresponding motherboard is obtained, and the address information of the motherboard's switching device is configured using the address information, including:

[0192] S210: Obtains address information corresponding to the motherboard through the address receiving port;

[0193] S220: Configure the switching device address information according to the address information;

[0194] S230: In response to the switching device completing the address information configuration, a reset command is sent to the reset setting port through the reset configuration port to make the address information of the switching device effective.

[0195] When a motherboard is powered on, the address information of its switching devices is set to the default value. After the controller configures the address information, the address information will replace the default value and be stored in the storage unit within the switching device. The configuration will take effect after a reset command is executed, giving the corresponding switching device a unique address.

[0196] Specifically, such as Figure 8 As shown, in response to the processor's access command for a bus device on the motherboard in the first type of motherboard, the access path for the corresponding bus device is opened, including:

[0197] S310: Receives access commands to bus devices.

[0198] S320a: In response to the access command, if the target device is a bus device mounted on the first type of motherboard, the second buffer in the first type of motherboard is enabled, and the target device is accessed through the corresponding device channel in the switching device of the first type of motherboard.

[0199] S320b: In response to the access command, if the target device is a bus device on the second type motherboard, the first buffer and the second buffer in the first type motherboard are enabled, and the corresponding switching device of the second type motherboard is enabled, and the target device is accessed through the corresponding device channel in the switching device of the second type motherboard.

[0200] Specifically, S320a: In response to the access command's target device being a bus device mounted on the first type of motherboard, the second buffer in the first type of motherboard is enabled, and the target device is accessed through the corresponding device channel in the switching device of the first type of motherboard, including:

[0201] An enable signal is sent to the second buffer in the first type of motherboard, causing the second buffer to turn on.

[0202] Configure the device channel corresponding to the target device, so that the main controller can access the target device through the device channel corresponding to the target device via the second buffer.

[0203] Specifically, S320b: In response to the target device of the access command being a bus device mounted on the second type of motherboard, the first buffer and the second buffer in the first type of motherboard are enabled, and the corresponding switching device of the second type of motherboard is enabled. Access to the target device is then performed through the corresponding device channel in the switching device of the second type of motherboard, including:

[0204] Enable signals are sent to the first buffer and the second buffer in the first type of motherboard to turn on the first buffer and the second buffer in the first type of motherboard.

[0205] Send an enable signal to the backplane buffer and switching devices corresponding to the second type of motherboard where the target device is located, so that the backplane buffer and switching devices corresponding to the target device are turned on.

[0206] A shutdown signal is sent to the second buffer of the second type of motherboard where the target device is located, causing the second buffer to shut down.

[0207] Configure the device channel corresponding to the target device, so that the main controller accesses the target device through the second buffer of the first type of motherboard, the first buffer of the first type of motherboard, the backplane buffer corresponding to the target device, and the switching device corresponding to the target device, via the device channel corresponding to the target device.

[0208] It should be understood that, although Figures 6-8 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 6-8 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0209] By implementing the bus link configuration method provided in the embodiments of this application, the device access link of the motherboard equipped with the slave processor, which is connected to the backplane in parallel, can be shortened based on the unified circuit structure of the motherboard equipped with the master processor and the motherboard equipped with the slave processor, thereby simplifying the control of devices on the slave device access link.

[0210] By implementing the bus link, circuit board, server, and bus link configuration method provided in this application embodiment, the circuit structure of the main processor motherboard and the slave processor motherboard can be unified, simplifying the design difficulty of the motherboard circuit and saving the design cost of the motherboard circuit. In terms of topology, the motherboard with the slave processor is connected to the backplane in parallel, shortening the link for the main processor to access the slave device and simplifying the control of the devices on the slave device access link. Furthermore, the arrangement of electronic components on the circuit board ensures the quality of signal transmission. The configuration method of the motherboard is flexible.

[0211] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0212] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as steps controlled by a computer software program. For example, embodiments of this application include a computer program product comprising a computer program loaded on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from memory, or installed from ROM. When the computer program is executed by an external processor, it performs the functions defined in the methods of embodiments of this application.

[0213] It should be noted that the computer-readable medium in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the embodiments of this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the embodiments of this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (Radio Frequency), etc., or any suitable combination thereof.

[0214] The aforementioned computer-readable medium may be included in the aforementioned server; or it may exist independently and not assembled into the server. The aforementioned computer-readable medium carries one or more programs that, when executed by the server, cause the server to: in response to detecting that the peripheral mode of the terminal is not activated, acquire the frame rate of the application on the terminal; when the frame rate meets the screen-off condition, determine whether the user is acquiring the terminal's screen information; and in response to the determination that the user is not acquiring the terminal's screen information, control the screen to enter an immediate dimming mode.

[0215] Computer program code for performing the operations of the embodiments of this application can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages—such as Java, Smalltalk, and C++—and conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0216] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0217] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

[0218] The foregoing has provided a detailed description of a bus link, circuit board, server, and bus link configuration method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. These embodiments are merely preferred embodiments of this application, used to help understand the method and core ideas of this application, and are not intended to limit this application. It should be noted that for those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application without departing from its principles are also within the protection scope of this application.

Claims

1. A bus link, characterized in that, include: The backplane circuit (000) and the motherboard circuit (100) include the following types of motherboard circuit (100): a first type motherboard (100a) and a second type motherboard (100b). The bus link includes the first type motherboard (100a) and at least one second type motherboard (100b). The motherboard circuit (100) includes: a switching device (110) and a first buffer (120); The backplane circuit (000) includes: a backplane buffer (010) and a floating port (000a); The floating port (000a) is connected to the motherboard circuit (100), and the backplane buffer (010) is connected to the second type of motherboard (100b). When the motherboard circuit (100) is configured as the first type motherboard (100a), the first buffer (120) is connected to one end of any backplane buffer (010), and the switching device (110) is connected to the corresponding floating port (000a). When the motherboard circuit (100) is configured as the second type motherboard (100b), the first buffer (120) is connected to the corresponding floating port (000a), and the switching device (110) is connected to the other end of the corresponding backplane buffer (010). The first type of motherboard (100a) accesses the corresponding second type of motherboard (100b) through the backplane buffer (010).

2. The bus link according to claim 1, characterized in that, The motherboard circuit (100) also includes: a second buffer (130), a switching device (140), and a processor (190). The processor (190) is connected to the second buffer (130), and the second buffer (130) is connected to the switching device (110) and the first buffer (120) and then to the switching device (140); The switching device (140) is used to carry the bus device (900). The processor (190) on the first type of motherboard (100a) is used to access the bus device (900) connected to the switching device (140).

3. The bus link according to claim 2, characterized in that, The switching device (110) has: a first port (110a) and a second port (110b). The first buffer (120) has: a first buffer first port (120a) and a first buffer second port (120b); The second buffer (130) has: a second buffer first port (130a) and a second buffer second port (130b); The switching device (140) has: a switching device bus transmission port (140a) and at least one switching device device channel (140b). The processor (190) is connected to the first port (130a) of the second buffer. The second port (130b) of the second buffer is connected to the first port (110a) of the switching device and the first port (120a) of the first buffer, and then connected to the bus transmission port (140a) of the switching device. The device channel (140b) of the switching device is used to connect to the bus device (900).

4. The bus link according to claim 2, characterized in that, The bus link also includes an extender (150). The expander (150) is connected to the switching device (140) and is used to expand the bus device (900) on the motherboard.

5. The bus link according to claim 4, characterized in that, The extender (150) has: an extender bus transmission port (150a) and a plurality of extender device channels (150b). The extender bus transmission port (150a) is connected to the switching device device channel (140b) of the switching device (140), and the bus device (900) is carried through the plurality of extender device channels (150b).

6. The bus link according to claim 2, characterized in that, The motherboard circuit (100) also includes a controller (160). The controller (160) is connected to the switching device (110), the first buffer (120), the second buffer (130) and the switching device (140), and is used to configure the enable state of the switching device (110), the first buffer (120) and the second buffer (130), and to configure the address information and reset command of the switching device (140).

7. The bus link according to claim 6, characterized in that, The controller (160) has: a first control port (160a), a second control port (160b), a third control port (160c), an address configuration port (160d), and a reset configuration port (160e). The switching device (110) also has: a switching device enable port (110c); The first buffer (120) also has: a first buffer enable port (120c); The second buffer (130) also has: a second buffer enable port (130c); The switching device (140) also has: an address setting port (140c) and a reset setting port (140d). The first control port (160a) is connected to the switch device enable port (110c) and is used to transmit the enable signal sent by the controller (160) to the switch device (110); The second control port (160b) is connected to the first buffer enable port (120c) and is used to transmit the enable signal sent by the controller (160) to the first buffer (120); The third control port (160c) is connected to the second buffer enable port (130c) and is used to transmit the enable signal sent by the controller (160) to the second buffer (130); The address configuration port (160d) is connected to the address setting port (140c) and is used to configure the address information of the switching device (140); The reset configuration port (160e) is connected to the reset setting port (140d) and is used to configure the reset command of the switching device (140).

8. The bus link according to claim 6, characterized in that, The controller (160) also has an address receiving port (160f); The address receiving port (160f) is connected to the backplane circuit (000) and is used to obtain the address information of the switching device (140) in the corresponding motherboard circuit (100).

9. The bus link according to claim 2, characterized in that, The first buffer (120) further includes: a first power port (120c) and a second power port (120d) of the first buffer. The second buffer (130) also has: a first power port (130d) for the second buffer and a second power port (130e) for the second buffer. The first power supply port (120c), the second power supply port (120d) of the first buffer, and the second power supply port (130e) of the second buffer are used to connect to the first power supply Vcc1; The first power port (130d) of the second buffer is used to connect to the second power supply Vcc2.

10. A circuit board, characterized in that, Including the backplate and motherboard; The backplane is provided with the backplane circuit of the bus link as described in any one of claims 1-9; The motherboard is provided with the motherboard circuit of the bus link as described in any one of claims 1-9.

11. The circuit board according to claim 10, characterized in that, The spacing between adjacent backplate buffers on the backplate is less than the spacing threshold. The distance between the first buffer on the motherboard and the switching device is less than the distance threshold. The distance between the switching device on the motherboard and the second buffer is less than the distance threshold.

12. A server, characterized in that, Includes the circuit board as described in claim 10 or 11.

13. A bus link configuration method, characterized in that, Applicable to the server of claim 12, wherein a controller is provided on the motherboard of the server, and in response to the server being powered on, the controller executes the bus link configuration method, including: S100: In response to the server being powered on, activate the controller; S200: Obtain the address of the corresponding motherboard and configure the switching device address of the motherboard using the address; S300: In response to a processor's access command for a bus device on the motherboard in the first type of motherboard, open the access path for the corresponding bus device.

14. The bus link configuration method according to claim 13, characterized in that, S200: Obtain the address of the corresponding motherboard and configure the switching device address of the motherboard using the address, including: S210: Obtains address information corresponding to the motherboard through the address receiving port; S220: Configure the address of the switching device according to the address information; S230: In response to the completion of address configuration of the switching device, a reset command is sent to the reset setting port through the reset configuration port to make the address of the switching device effective.

15. The bus link configuration method according to claim 13, characterized in that, S300: In response to a processor's access command for a bus device on the motherboard in the first type of motherboard, opens an access path for the corresponding bus device, including: S310: Receive an access command for the bus device; S320a: In response to the target device of the access command being a bus device mounted on the first type of motherboard, the second buffer in the first type of motherboard is enabled, and the target device is accessed through the corresponding device channel in the switching device of the first type of motherboard. S320b: In response to the target device of the access command being a bus device mounted on a second type of motherboard, the first buffer and the second buffer in the first type of motherboard are enabled, and the corresponding switching device of the second type of motherboard is enabled, and the target device is accessed through the corresponding device channel in the switching device of the second type of motherboard.

Images