Data transmission device and data transmission method for network-on-chip

Abstract

The invention provides a network-on-chip data transmission device and a data transmission method. The network-on-chip data transmission device comprises at least one network interface and at least one storage control node, the network interface comprises a first-stage compression and decompression module, and the first-stage compression and decompression module is used for performing first-stage compression on received transmission data sent by the computing node or performing first-stage decompression on received transmission data sent by the network node; the storage control node comprises a secondary compression and decompression module, and the secondary compression and decompression module is used for performing secondary compression on the received primary compression data sent by the network node or performing secondary decompression on the storage data acquired from the off-chip memory. According to the invention, transmission in the network-on-chip in the form of the first-level compressed data format is realized, transmission between the computing node and the off-chip memory in the form of the second-level compressed data format is realized, occupation of network bandwidth can be effectively reduced, and data transmission efficiency and performance of the whole network-on-chip are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of network-on-chip communication technology, and in particular to a data transmission device and a data transmission method of a network-on-chip. BACKGROUND

[0002] With the development of integrated circuit technology, the number of processor cores, memory units and other functional modules integrated in a system-on-chip is increasing, and the network-on-chip (NoC) as the core infrastructure for data interaction is facing increasingly severe bandwidth pressure and energy efficiency challenges.

[0003] The existing data transmission method of the network-on-chip occupies a large amount of NoC bandwidth when transmitting large-scale data, resulting in limited data throughput, especially in the multi-node parallel computing scenario, the network congestion problem is significant. How to reduce the network congestion of the network-on-chip data transmission and improve the data transmission efficiency of the network-on-chip is an important issue that needs to be solved in the industry at present. SUMMARY

[0004] The present application provides a data transmission device and a data transmission method of a network-on-chip to reduce the network congestion of the network-on-chip data transmission and improve the data transmission efficiency of the network-on-chip.

[0005] The present application provides a data transmission device of a network-on-chip, comprising at least one network interface and at least one storage control node; The first end of the network interface is connected to a network node of the network-on-chip, and the second end of the network interface is used to connect a computing node, the network interface comprises a first-level compression and decompression module, the first-level compression and decompression module is used to perform first-level compression on the transmission data sent by the computing node received, or perform first-level decompression on the transmission data sent by the network node received; The first end of the storage control node is connected to a network node of the network-on-chip, and the second end of the storage control node is used to connect an off-chip memory, the storage control node comprises a second-level compression and decompression module, the second-level compression and decompression module is used to perform second-level compression on the first-level compressed data sent by the network node received, or perform second-level decompression on the storage data obtained from the off-chip memory.

[0006] According to the data transmission device of the network-on-chip provided by the present application, the first-level compression and decompression module comprises a first-level compression unit, a first-level decompression unit, a first interface bus and a second interface bus; The first end of the first interface bus is used as the first end of the network interface, and the second end of the first interface bus is connected to the first end of the first-level compression unit and the first end of the first-level decompression unit, respectively; The first end of the second interface bus is the second end of the network interface, and the second end of the second interface bus is connected to the second end of the primary compression unit and the second end of the primary decompression unit respectively. The primary compression unit is configured to perform primary compression on the received transmission data sent by the computing node based on a Varint coding algorithm in a pipeline manner. The primary decompression unit is configured to perform primary decompression on the received transmission data sent by the network node based on a Varint coding algorithm in a pipeline manner.

[0007] According to the data transmission device of the network-on-chip provided by the application, the secondary compression and decompression module comprises a secondary compression unit, a secondary decompression unit, an Xbar bus, an external interaction bus and a storage controller. The first end of the external interaction bus is the first end of the storage control node, and the second end of the external interaction bus is connected to the first end of the secondary compression unit and the first end of the secondary decompression unit respectively. The first end of the Xbar bus is connected to the first end of the storage controller, and the second end of the Xbar bus is connected to the second end of the secondary compression unit and the second end of the secondary decompression unit respectively. The second end of the storage controller is the second end of the storage control node, and is configured to obtain storage data from an off-chip storage. The secondary compression unit is configured to perform secondary compression on the received primary compressed data sent by the network node based on a run-length compression algorithm in a pipeline manner. The secondary decompression unit is configured to perform secondary decompression on the storage data obtained from the off-chip storage by the storage controller based on a run-length compression algorithm in a pipeline manner.

[0008] According to the data transmission device of the network-on-chip provided by the application, the storage control node further comprises an address mapping table. The address mapping table is configured to record storage address information and data length information of the transmission data before secondary compression.

[0009] According to the data transmission device of the network-on-chip provided by the application, the network interface further comprises a bypass control unit. The bypass control unit is configured to directly transmit the transmission data bypassing the primary compression and decompression module when it is determined that the transmission data does not need to be compressed.

[0010] The application further provides a data transmission method of a network-on-chip, which is applied to the data transmission device of the network-on-chip. The network interface receives data to be stored sent by the computing node; The network interface is based on a primary compression and decompression module, which performs primary compression on the data to be stored and transmits the resulting primary compressed data to the network node. The storage control node receives the first-level compressed data sent by the network node, performs second-level compression on the first-level compressed data based on the second-level compression and decompression module, and sends the resulting second-level compressed data to the off-chip memory, so that the off-chip memory performs off-chip storage of the second-level compressed data.

[0011] According to a data transmission method for an on-chip network provided by the present invention, the first-level compression of the data to be stored includes: Based on the Varint encoding and decoding algorithm, the data to be stored is compressed in a pipelined manner.

[0012] According to a data transmission method for an on-chip network provided by the present invention, the step of performing secondary compression on the primary compressed data includes: Based on the run-length compression algorithm, the first-level compressed data is subjected to second-level compression in a pipelined execution manner.

[0013] According to a data transmission method for an on-chip network provided by the present invention, before performing secondary compression on the primary compressed data, the method further includes: Obtain the storage address information and data length information of the data to be stored, and store the storage address information and data length information in the address mapping table in the storage control node.

[0014] The data transmission method for an on-chip network provided by the present invention further includes: Receive a data read request from a computing node, and query the address mapping table based on the data read request to determine the target storage address of the data to be acquired; Based on the storage control node, target data is obtained from the target storage address of the off-chip memory, and the target data is decompressed in two stages based on the two-stage compression and decompression module in the storage control node to obtain two-stage decompressed data; The storage control node transmits the secondary decompression data to the network node; The network interface receives the secondary decompressed data sent by the network node, performs primary decompression on the secondary decompressed data based on the primary compression and decompression module, and sends the resulting primary decompressed data to the computing node.

[0015] The data transmission device and method for on-chip networks provided by this invention, by setting a primary compression / decompression module in the network interface and a secondary compression / decompression module in the storage control node, enables data transmission between different computing nodes in the on-chip network to be transmitted in a primary compressed data format. Data storage and retrieval operations between computing nodes and off-chip memory are transmitted in a secondary compressed data format, effectively reducing network bandwidth usage, shortening data transmission and storage time, and improving the overall data transmission efficiency and performance of the on-chip network. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the data transmission device of the on-chip network provided by the present invention.

[0018] Figure 2 This is a schematic diagram of the network interface provided by the present invention.

[0019] Figure 3 This is a schematic diagram of the structure of the storage control node provided by the present invention.

[0020] Figure 4 This is a flowchart illustrating the data transmission method of the on-chip network provided by the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0022] Figure 1 This is a schematic diagram of the data transmission device for the on-chip network provided by the present invention, as shown below. Figure 1As shown, the device specifically includes at least one network interface 101 and at least one storage control node 102. Each computing node is connected to the on-chip network via the network interface 101, enabling on-chip network communication among multiple computing nodes. Some network nodes are connected to the storage control node 102, enabling network communication between each computing node and the storage. Solid lines between network nodes represent direct connections, while dashed lines represent indirect connections involving multiple network nodes.

[0023] Network-on-a-chip (NAT) is a network architecture that enables communication between multiple processor cores or other computing components on a single chip. It borrows the concept of computer networks, connecting various functional modules on the chip (such as processor cores, memory, I / O interfaces, etc.) through network nodes to form a complex communication network. Computing nodes such as CPUs or GPUs can connect to the NAT network nodes through network interfaces, while storage units such as off-chip memory can connect to the NAT network nodes through storage control nodes. Based on the NAT network nodes, data communication between all computing nodes and storage units is achieved.

[0024] Specifically, the on-chip network interface has two connection ends. The first end connects to the network node of the on-chip network, and the second end connects to the compute node. This connection method enables the compute node to interact with other nodes (other compute nodes or off-chip memory, etc.) in the on-chip network through the network interface, serving as a bridge for the compute node to access the on-chip network.

[0025] The two data transmission methods that can be implemented by computing nodes based on on-chip networks include: One approach is to implement data transmission between computing nodes through an on-chip network; the other approach is to use an on-chip network to store data from computing nodes to off-chip memory.

[0026] Specifically, the network interface includes a primary compression and decompression module, which is used for data compression and decompression.

[0027] When the network interface receives transmission data from the compute node, the first-level compression and decompression module performs primary compression on the data, ensuring that the data is transmitted in compressed form within the on-chip network. Compression removes redundant information, reduces data size, and improves transmission efficiency within the on-chip network. By converting the data into a more compact form using compression algorithms, the amount of data subsequently transmitted over the network is reduced, thus lowering network bandwidth usage.

[0028] When the network interface receives transmitted data from a network node, the primary compression / decompression module performs primary decompression on the data. It can be understood that the data received by the network interface from the network node originates from compute node A and has undergone primary compression. This primary compressed data can be transmitted from compute node A to compute node B via the on-chip network. Before the network interface transmits the primary compressed data to compute node B, the primary compression / decompression module within the network interface decompresses the data, restoring the original data for transmission to compute node B. This ensures that compute node B can correctly identify and process the data.

[0029] The primary compression / decompression module in the network interface helps improve the transmission efficiency of data between computing nodes via on-chip networks. By compressing data, the transmission time of data in the network is reduced, enabling computing nodes to obtain the required data or send data to the network more quickly, thereby improving response speed and throughput.

[0030] The storage control node also has two connection points: the first connects to the network node on the on-chip network, and the second connects to the off-chip memory. This allows the network node on the on-chip network to interact with the off-chip memory through the storage control node, enabling access to and management of off-chip storage resources.

[0031] It should be noted that the storage control node receives first-level compressed data sent by the network node that requires off-chip storage. This first-level compressed data is obtained by the compute node sending the transmitted data to the network interface, where the network interface performs first-level compression on the transmitted data.

[0032] When the storage control node receives the first-level compressed data from the network node, the second-level compression and decompression module performs further second-level compression on the first-level compressed data. Since off-chip memory access speeds are relatively slow and storage bandwidth is limited, second-level compression can further reduce data volume and improve data storage efficiency. For example, for data that requires long-term storage but has a large volume (such as log information, historical data, etc.), second-level compression can save storage space on off-chip memory while reducing data write and read times.

[0033] It should be noted that data is stored in off-chip memory using a two-stage compression method. When the storage control node retrieves data from off-chip memory, the data has undergone first-stage compression followed by second-stage compression. The second-stage compression / decompression module performs second-stage decompression on the retrieved data. Only after restoring the compressed data to the first-stage compression format and further performing first-stage decompression via the network interface can it be used by the compute nodes.

[0034] The secondary compression and decompression module in the storage control node optimizes the data transfer and storage process between the on-chip network and off-chip memory. It not only reduces the time overhead during data storage and retrieval but also improves the utilization of off-chip memory, enabling the on-chip network to utilize external storage resources more efficiently and meet the system's needs for large data storage and access.

[0035] The on-chip network data transmission device provided by this invention incorporates a primary compression / decompression module in the network interface and a secondary compression / decompression module in the storage control node. This enables data transmission between different computing nodes within the on-chip network, transmitting data in a primary compressed data format. Data storage and retrieval operations between computing nodes and off-chip memory are transmitted in a secondary compressed data format, effectively reducing network bandwidth usage, decreasing data transmission and storage time, and improving the overall data transmission efficiency and performance of the on-chip network.

[0036] In one embodiment, the primary compression / decompression module includes a primary compression unit, a primary decompression unit, a first interface bus, and a second interface bus; a first end of the first interface bus serves as a first end of the network interface, and a second end of the first interface bus is connected to both the first end of the primary compression unit and the first end of the primary decompression unit; a first end of the second interface bus serves as a second end of the network interface, and a second end of the second interface bus is connected to both the second end of the primary compression unit and the second end of the primary decompression unit; the primary compression unit is used to perform primary compression on the transmitted data sent by the received computing node in a pipelined manner based on the Varint encoding / decoding algorithm; the primary decompression unit is used to perform primary decompression on the transmitted data sent by the received network node in a pipelined manner based on the Varint encoding / decoding algorithm.

[0037] A schematic diagram of the network interface based on the primary compression / decompression module can be seen as follows: Figure 2 The structural diagram of the network interface provided by this invention is shown.

[0038] The network interface of the primary compression and decompression module includes a primary compression unit, a primary decompression unit, a first interface bus, and a second interface bus.

[0039] The first-level compression unit is a hardware compression acceleration unit that uses the Varint (Variable-length Integer) encoding algorithm. It can encode 32-bit and 64-bit data based on a five-stage pipeline. For data compression that supports a 128-bit wide bus, the 128-bit data can be split into two 64-bit data sets and sent to the data splitting unit of the first-stage pipeline.

[0040] In the first-stage pipeline, the data width to be compressed is identified based on the register configuration. When the data width is 32 bits, the first splitting unit extracts the lower 32 bits, and the second splitting unit extracts the higher 32 bits; when the data width is 64 bits, the first splitting unit extracts the lower 35 bits, and the second splitting unit extracts the higher 29 bits. The splitting unit continues to split the data into five 7-bit data segments.

[0041] In the second-stage pipeline, the last byte is determined according to the Varint encoding algorithm, a continuation bit is inserted in the high-order bits, and the number of bytes after encoding is recorded.

[0042] In the third-stage pipeline, based on the register configuration, the current data width to be compressed is identified, and the results of the two split units are merged. When the data width is 32 bits, it directly enters the next stage of the pipeline. When the data width is 64 bits, it is determined whether the data in the second split unit is zero. If it is zero, the number of bytes in the second split unit is marked as 0; if it is not zero, the number of bytes in the first split unit is marked as 5, and all continuation bits of the output byte of the first split unit are marked as 1.

[0043] In the fourth-level pipeline, based on the number of bytes in the first and second splitting units, the encoded valid bit data is extracted, sequentially rearranged and reassembled, and then cached. In the fifth-stage pipeline, the cached data is reordered and reassembled to form 128-bit wide data, which is then sent to the routing node.

[0044] The first-stage decompression unit is a hardware compression acceleration unit that supports the Varint decoding algorithm and employs a four-stage pipeline, capable of decoding 32-bit and 64-bit data. For example, it supports data decompression on a 128-bit wide bus and buffering of received data. Data received from the routing node is buffered into a FIFO. When the FIFO is not empty, 128 bits of data are sequentially extracted and sent to the first-stage pipeline.

[0045] In the first-stage pipeline, the length of the current valid data bits is determined in real time. When the valid data is no more than 128 bits, the 128 bits of data sent by the FIFO are received and inserted to the right of the valid data to form a combined data of more than 128 bits. At the same time, the continuation bits in the high 20 bytes are checked to determine the position of the byte where the continuation bit is zero.

[0046] In the second-stage pipeline, the data bit width to be compressed is identified based on the register configuration. When the bit width is 64 bits, the most significant byte is truncated to the first byte with consecutive zeros, and the first byte after the first byte with consecutive zeros is truncated to the second byte with consecutive zeros, and then sent to the next-stage data decoding unit. When the bit width is 32 bits, the most significant byte is truncated to the second byte with consecutive zeros, and the first byte after the second byte with consecutive zeros is truncated to the fourth byte with consecutive zeros. At the same time, the position of the byte with consecutive zeros is marked, and then sent to the next-stage data decoding unit.

[0047] At the same time, the combined data is shifted left to eliminate the truncated data, and the process jumps to the first-stage pipeline to check the effective bit length of the combined data again.

[0048] In the third-stage pipeline, based on the register configuration, the current data bit width to be compressed is identified, and the continuation bits of each byte are detected. When the bit width is 64 bits, the Varint decoding algorithm extracts the 7 bits of data excluding the continuation bits from each byte, and pads the high-order bits with zeros according to the number of valid bytes, forming 64 bits of valid data. When the bit width is 32 bits, based on the positions of the two bytes with zero continuation bits, the 7 bits of data excluding the continuation bits from each byte are extracted, and padding with zeros according to the number of valid bytes, forming two 32-bit valid data.

[0049] In the fourth stage of the pipeline, the received 32-bit or 64-bit data is sequentially concatenated into 128-bit data and sent to the local compute / storage node.

[0050] In one embodiment, the network interface further includes a bypass control unit, which is used to bypass the primary compression / decompression module and transmit the transmitted data directly if it is determined that the transmitted data does not need to be compressed.

[0051] Understandably, when the data is in a non-32-bit or non-64-bit format and does not require compression or decompression, bypass control can be used to bypass the first-level compression and decompression module and allow direct data communication between the local computing / storage node and the routing node.

[0052] Optionally, the bus width is configurable. Depending on the actual needs, it can be configured to different widths such as 256, 512, and 1024, and different numbers of first-level compression and decompression modules can be configured according to the width.

[0053] In one embodiment, the secondary compression / decompression module includes a secondary compression unit, a secondary decompression unit, an Xbar bus, an external interaction bus, and a storage controller. The first end of the external interaction bus serves as the first end of the storage control node, and the second end of the external interaction bus is connected to both the first end of the secondary compression unit and the first end of the secondary decompression unit. The first end of the Xbar bus is connected to the first end of the storage controller, and the second end of the Xbar bus is connected to both the second end of the secondary compression unit and the second end of the secondary decompression unit. The second end of the storage controller serves as the second end of the storage control node and is used to obtain storage data from external memory. The secondary compression unit performs secondary compression on the primary compressed data sent by the network node using a run-length compression algorithm and a pipelined execution method. The secondary decompression unit performs secondary decompression on the storage data obtained by the storage controller from external memory using a run-length compression algorithm and a pipelined execution method.

[0054] Optionally, the structural diagram of the storage control node based on the two-level compression and decompression module can be as follows: Figure 3 The structural diagram of the storage control node provided by this invention is shown.

[0055] The storage control node may also include an address mapping table, which records the storage address information and data length information of the transmitted data before secondary compression. The address mapping table can be maintained by the RISC-V processor in the storage control node.

[0056] The Xbar bus can be specifically composed of the Xbar bus and the secondary Xbar bus.

[0057] The storage control node receives data from other nodes via an external interaction bus. After compression by the secondary compression unit, the data is transferred to off-chip memory (which can be an off-chip DDR chip) via the storage controller (specifically, the DDR controller) and the address mapping table is updated. Upon receiving data read requests from other nodes, the RISC-V processor queries the address mapping table to confirm the size and storage address of the compressed data. It then controls the DDR controller to read the data from the off-chip memory chip, decompresses it via the secondary decompression unit, and forwards it to the corresponding node. Multiple off-chip memories are interconnected to maintain single-cycle read / write of 128-bit data. The RISC-V processor, address mapping table, secondary compression unit, and secondary decompression unit are interconnected via a primary Xbar bus, configured and started by the processor control register. The DDR controller is interconnected via a secondary Xbar bus to maintain data storage consistency.

[0058] It interconnects with the RISC-V processor via the bus, receiving system control and status access from the processor; it interconnects with the local cache via the data bus, transferring compressed data to local off-chip memory, and decompressing data from local off-chip memory.

[0059] The secondary compression unit is a hardware compression acceleration unit that uses run-length encoding (RLE) based on a five-stage pipeline, enabling compression encoding of arbitrary bit data. The secondary compression unit can contain five sub-compression modules. After receiving stored data from other nodes, it is cyclically placed into these five sub-compression modules in preparation for secondary compression.

[0060] Each sub-compression module can complete data compression and caching after five pipeline cycles.

[0061] In the first-stage pipeline, after receiving 128 bits of data, it is split into two 64-bit data sets. Starting with the most significant and least significant byte (8 bytes each), each set is compared with its adjacent byte to check for equality. For the most significant byte, if the 8th byte is not equal to the 7th byte, the 8th byte is output directly; otherwise, the number of equal bytes is counted, and the process proceeds to the second-stage pipeline, where it is compared with the 6th byte. For the least significant byte, the first and second bytes are compared, and a decision is made whether to output the data.

[0062] In the second and third pipelines, the high-order byte is compared with the 6th and 5th bytes, and the low-order byte is compared with the 3rd and 4th bytes, and it is determined whether to output.

[0063] In the fourth pipeline, the last output byte of the high-order bit and the last output byte of the low-order bit are compared to see if they are equal. If they are equal, the counters of the two bytes are added together and output; if they are not equal, they are output directly.

[0064] In the fifth pipeline, the last byte of the first 64-bit data output is compared with the last byte of the first 64-bit data output. If they are equal, the corresponding counters are incremented and the result is output; otherwise, the result is output directly.

[0065] The output result is cached in a temporary buffer, concatenated with the data output from the subsequent sub-compression module to form 128 bits of data, and sent to the local buffer, waiting to be transferred to the off-chip memory.

[0066] The secondary decompression unit is a hardware compression acceleration unit that supports run-length extraction (RLE) decompression algorithm and adopts a four-stage pipeline, enabling the decompression and encoding of arbitrary bit data. The secondary decompression unit reads 128 bits of data from external memory and then begins decompression.

[0067] In the first-level pipeline, data is sent to 8 data generation units in units of two bytes; the high byte is a counter and the low byte is valid data.

[0068] In the second-stage pipeline, in the data generation unit, 128 bits of data are generated according to the counter, and the valid bits of the data are marked.

[0069] In the third-stage pipeline, the generated valid data is sequentially concatenated into 128 bits. When the valid data exceeds 128 bits, a loop concatenation process is initiated to continue concatenating 128 bits of valid data.

[0070] In the fourth-level pipeline, subsequent data cannot be concatenated into 128 bits. The remaining valid data is placed in the data buffer and continues to wait for new data sent from the previous pipeline before being concatenated.

[0071] A handshake blocking mechanism is used between different pipelines. When the next pipeline is blocked, the previous pipeline enters a waiting mode.

[0072] This invention also provides a data transmission method for an on-chip network, such as... Figure 4 The flowchart of the data transmission method for an on-chip network provided by the present invention is shown. This data transmission method for an on-chip network is applied to the data transmission device of the on-chip network as described above. The method includes: Step 410: The network interface receives the data to be stored sent by the computing node; Step 420: The network interface performs primary compression on the data to be stored based on the primary compression and decompression module, and transmits the resulting primary compressed data to the network node. Step 430: The storage control node receives the first-level compressed data sent by the network node, performs second-level compression on the first-level compressed data based on the second-level compression and decompression module, and sends the resulting second-level compressed data to the off-chip memory, so that the off-chip memory performs off-chip storage of the second-level compressed data.

[0073] Specifically, in an on-chip network system, after completing its computational tasks, a compute node may generate data that needs to be stored long-term or used by other components later; this data is called data to be stored. The compute node sends the data to be stored to the network interface it is connected to.

[0074] The network interface acts as a bridge between the compute nodes and the on-chip network. It receives the data to be stored from the compute nodes and passes it to the first-level compression / decompression module. The first-level compression / decompression module uses a compression algorithm to compress the data. After first-level compression, the data size is significantly reduced, resulting in first-level compressed data.

[0075] The network interface transmits first-level compressed data to the connected network node. During transmission, the network interface encapsulates the data according to the on-chip network's communication protocol, adding necessary headers and checksums to ensure the data arrives at the network node accurately. The network node, acting as a relay station in the on-chip network, is responsible for further forwarding or processing the received data.

[0076] After receiving the primary compressed data from the network node, the storage control node forwards it to the internal secondary compression and decompression module. The secondary compression and decompression module can then use compression algorithms to further compress the data.

[0077] The storage control node sends the secondary compressed data to the off-chip memory. After receiving the data, the off-chip memory stores it in the designated storage location.

[0078] The data transmission method for on-chip networks provided by this invention establishes a primary compression / decompression module in the network interface and a secondary compression / decompression module in the storage control node. This enables data transmission between different computing nodes within the on-chip network to be performed in a primary compressed data format. Data storage and retrieval operations between computing nodes and off-chip memory are performed in a secondary compressed data format, effectively reducing network bandwidth usage, decreasing data transmission and storage time, and improving the overall data transmission efficiency and performance of the on-chip network.

[0079] In one embodiment, performing primary compression on the data to be stored includes: performing primary compression on the data to be stored in a pipelined manner based on the Varint encoding / decoding algorithm.

[0080] During the first-level compression, a five-stage pipeline approach can be used to encode 32-bit and 64-bit data.

[0081] Varint is a variable-length integer encoding algorithm that improves storage and transmission efficiency by dynamically adjusting the number of bytes required to represent an integer.

[0082] In one embodiment, performing secondary compression on the primary compressed data includes: performing secondary compression on the primary compressed data in a pipelined execution manner based on a run-length compression algorithm.

[0083] When performing a second-level compression on the first-level compressed data, a run-length compression algorithm is adopted. Based on a five-level pipeline approach, it is possible to compress and encode data of any number of bits.

[0084] Among them, the run-length compression algorithm is a lossless data compression algorithm that reduces the amount of data by identifying and encoding continuously repeating data.

[0085] In one embodiment, before performing secondary compression on the first-level compressed data, the method further includes: obtaining the storage address information and data length information of the data to be stored, and storing the storage address information and the data length information in the address mapping table in the storage control node.

[0086] The storage control node may also include an address mapping table, which records the storage address information and data length information of the transmitted data before secondary compression. The address mapping table can be maintained by the RISC-V processor in the storage control node.

[0087] Understandably, after two levels of compression, the storage location cannot be directly determined. The storage address information can be obtained before the second level of compression to facilitate data retrieval. The stored data length information can be used for verification after data retrieval.

[0088] In one embodiment, the method further includes: receiving a data read request from a computing node; querying the address mapping table based on the data read request to determine the target storage address of the data to be acquired; acquiring the target data from the target storage address of the off-chip memory based on a storage control node; performing secondary decompression on the target data based on a secondary compression and decompression module in the storage control node to obtain secondary decompressed data; the storage control node transmitting the secondary decompressed data to a network node; the network interface receiving the secondary decompressed data sent by the network node; performing primary decompression on the secondary decompressed data based on a primary compression and decompression module; and sending the obtained primary decompressed data to the computing node.

[0089] In the data reading process of on-chip network, when a data reading request is received from a computing node, the address mapping table is first queried based on the request to determine the target storage address of the data to be acquired in the off-chip memory.

[0090] The storage control node retrieves the target data from the off-chip memory based on the determined target storage address. Since two-stage compression was performed during storage, the two-stage compression / decompression module in the storage control node needs to perform two-stage decompression on the target data to obtain decompressed data. Subsequently, the storage control node transmits the decompressed data to the network node.

[0091] After receiving the secondary decompressed data from the network node, the network interface performs primary decompression on it through the primary compression and decompression module, ultimately restoring the original primary decompressed data and sending it to the computing node to complete the entire data reading process, ensuring that the computing node can obtain the required original data.

[0092] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0093] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data transmission device for an on-chip network, characterized in that, include: At least one network interface and at least one storage control node; The first end of the network interface is connected to the network node of the on-chip network, and the second end of the network interface is used to connect to the computing node. The network interface includes a first-level compression and decompression module, which is used to perform first-level compression on the transmitted data sent by the computing node or to perform first-level decompression on the transmitted data sent by the network node. The first end of the storage control node is connected to the network node of the on-chip network, and the second end of the storage control node is used to connect to the off-chip memory. The storage control node includes a two-level compression and decompression module, which is used to perform two-level compression on the first-level compressed data sent by the network node, or to perform two-level decompression on the storage data obtained from the off-chip memory.

2. The data transmission device for an on-chip network according to claim 1, characterized in that, The primary compression and decompression module includes a primary compression unit, a primary decompression unit, a first interface bus, and a second interface bus; The first end of the first interface bus serves as the first end of the network interface, and the second end of the first interface bus is respectively connected to the first end of the first-level compression unit and the first end of the first-level decompression unit. The first end of the second interface bus serves as the second end of the network interface, and the second end of the second interface bus is connected to the second end of the first-level compression unit and the second end of the first-level decompression unit, respectively. The first-level compression unit is used to perform first-level compression on the transmitted data sent by the received computing node based on the Varint encoding and decoding algorithm in a pipelined execution manner. The first-level decompression unit is used to perform first-level decompression on the transmitted data sent by the network node based on the Varint encoding and decoding algorithm in a pipelined execution manner.

3. The data transmission device for an on-chip network according to claim 1, characterized in that, The two-level compression and decompression module includes a two-level compression unit, a two-level decompression unit, an Xbar bus, an external interaction bus, and a storage controller; The first end of the external interaction bus serves as the first end of the storage control node, and the second end of the external interaction bus is connected to the first end of the secondary compression unit and the first end of the secondary decompression unit, respectively. The first end of the Xbar bus is connected to the first end of the storage controller, and the second end of the Xbar bus is connected to the second end of the secondary compression unit and the second end of the secondary decompression unit, respectively. The second terminal of the storage controller serves as the second terminal of the storage control node, used to obtain storage data from off-chip memory; The secondary compression unit is used to perform secondary compression on the primary compressed data sent by the network node based on the run-length compression algorithm in a pipelined execution manner. The secondary decompression unit is used to perform secondary decompression on the storage data obtained by the storage controller from the off-chip memory based on the run-length compression algorithm in a pipelined execution manner.

4. The data transmission device for an on-chip network according to claim 3, characterized in that, The storage control node also includes: an address mapping table; The address mapping table is used to record the storage address information and data length information of the transmitted data before it undergoes secondary compression.

5. The data transmission device for an on-chip network according to claim 1, characterized in that, The network interface also includes a bypass control unit; The bypass control unit is used to bypass the first-level compression and decompression module and transmit the data directly when it is determined that the transmitted data does not need to be compressed.

6. A data transmission method for an on-chip network, characterized in that, The method, applied to a data transmission device for an on-chip network as described in any one of claims 1-5, comprises: The network interface receives data to be stored sent by the computing node; The network interface is based on a primary compression and decompression module, which performs primary compression on the data to be stored and transmits the resulting primary compressed data to the network node. The storage control node receives the first-level compressed data sent by the network node, performs second-level compression on the first-level compressed data based on the second-level compression and decompression module, and sends the resulting second-level compressed data to the off-chip memory, so that the off-chip memory performs off-chip storage of the second-level compressed data.

7. The data transmission method for an on-chip network according to claim 6, characterized in that, The first-level compression of the data to be stored includes: Based on the Varint encoding and decoding algorithm, the data to be stored is compressed in a pipelined manner.

8. The data transmission method for an on-chip network according to claim 6, characterized in that, The step of performing secondary compression on the first-level compressed data includes: Based on the run-length compression algorithm, the first-level compressed data is subjected to second-level compression in a pipelined execution manner.

9. The data transmission method for an on-chip network according to claim 6, characterized in that, Before performing secondary compression on the first-level compressed data, the method further includes: Obtain the storage address information and data length information of the data to be stored, and store the storage address information and data length information in the address mapping table in the storage control node.

10. The data transmission method for an on-chip network according to claim 9, characterized in that, Also includes: Receive a data read request from a computing node, and query the address mapping table based on the data read request to determine the target storage address of the data to be acquired; Based on the storage control node, target data is obtained from the target storage address of the off-chip memory, and the target data is decompressed in two stages based on the two-stage compression and decompression module in the storage control node to obtain two-stage decompressed data; The storage control node transmits the secondary decompression data to the network node; The network interface receives the secondary decompressed data sent by the network node, performs primary decompression on the secondary decompressed data based on the primary compression and decompression module, and sends the resulting primary decompressed data to the computing node.

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