Configuration method and device compatible with multi-topological structure GPU server and storage medium

Abstract

The invention relates to a configuration method and device compatible with a multi-topological structure GPU server and a storage medium, and the method comprises the steps: controlling a first programmable logic chip of a GPU node to obtain topological structure information of the GPU server, setting the gating of a total multiplexer based on the topological structure information of the GPU server and a gating truth table, and according to the gating of the total multiplexer, carrying out the configuration of the GPU server. And determining the gating type of the total nonvolatile memory, and loading the corresponding firmware file from the corresponding total nonvolatile memory through the serial peripheral interface of the switching chip according to the gating type of the total nonvolatile memory so as to configure the PCIe port of the switching chip, thereby configuring the GPU server, and a serial peripheral interface of the switching chip is connected with a plurality of total nonvolatile memories. According to the scheme provided by the invention, the firmware file required by an actual topological structure can be adaptively switched to start and complete configuration in the whole process from server assembly completion, power-on to startup, so that the production efficiency is improved, and the development cost is saved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a configuration method, apparatus, and storage medium for GPU servers compatible with multiple topologies. Background Technology

[0002] In the information age, artificial intelligence is developing rapidly, and GPU servers have become the darling of the AI ​​industry, providing powerful computing power for training and inference. Computing power relies on the server's internal PCIe bus resources, but the CPU's PCIe resources and processing capabilities are no longer sufficient to meet the ever-increasing demand for computing power. Therefore, the application of PCIe switching chips and GPUs in servers has emerged: GPUs provide computing power, while PCIe switching chips are used to expand PCIe resources and enable high-speed point-to-point communication between GPUs.

[0003] Based on different GPU server application scenarios and the need for minimal data interaction latency, the market has gradually developed typical topologies such as Common mode (including single uplink and dual uplink), Balanced mode (including single uplink and dual uplink), and Cascade mode. Each topology requires a corresponding firmware file to configure the PCIe port resources of the switching chip.

[0004] For GPU servers with different topologies, the firmware file of the switching chip usually needs to be re-flashed according to the actual topology during production. After the flashing is completed, the server is restarted so that the switching chip loads the new firmware file and configures resources such as PCIe ports accordingly.

[0005] Due to differences in topology, PCIe switching chips in GPU servers require different firmware files to boot and configure PCIe port resources. When a single server needs to support three topologies—dual uplink (including Balanced and Common), single uplink (including Balanced and Common), and cascade—the corresponding firmware files are typically manually flashed to the switching chips according to the application scenario. This process is cumbersome, error-prone, and leads to low production efficiency, hindering large-scale production. Furthermore, flashing requires the software to support online firmware upgrades for the switching chips; if this is not supported, re-flashing is impossible. This incurs development and maintenance costs for the software functionality. Summary of the Invention

[0006] This invention provides a configuration method, apparatus, and storage medium for GPU servers compatible with multiple topologies, aiming to solve at least one of the technical problems existing in the prior art.

[0007] The technical solution of this invention is a configuration method for GPU servers compatible with multiple topologies, comprising the following steps: S100: The first programmable logic chip that controls the GPU node obtains the topology information of the GPU server; S200. Based on the topology information of the GPU server and the gating truth table, set the gating of the total multiplexer; S300. Determine the selection type of the total nonvolatile memory based on the selection of the total multiplexer; S400. According to the selection type of the total non-volatile memory, load the corresponding firmware file from the corresponding total non-volatile memory through the serial peripheral interface of the switching chip to configure the PCIe port of the switching chip, thereby configuring the GPU server. The serial peripheral interface of the switching chip is connected to a plurality of total non-volatile memories.

[0008] According to some embodiments of the present invention, prior to step S100, the configuration method of the multi-topology compatible GPU server further includes the following steps: A. The second programmable logic chip controlling the CPU node acquires the electrical signals of the MCIO cable on the CPU node, and combines the electrical signals into the topology information of the GPU server according to a preset rule; B. Control the second programmable logic chip to transmit the topology information of the GPU server to the NVM register inside the first programmable logic chip via the I2C bus.

[0009] According to some embodiments of the present invention, the GPU node includes a first programmable logic chip, a switching chip, a first non-volatile memory, a second non-volatile memory, a third non-volatile memory, a first multiplexer, and a second multiplexer; the first programmable logic chip includes a select1 pin, an e#1 pin, a select2 pin, and an e#2 pin; The GPU node is configured such that: the serial peripheral interface of the switching chip is connected to port A of the first multiplexer; port B1 of the first multiplexer is connected to the first non-volatile memory; port B2 of the first multiplexer is connected to port A of the second multiplexer; port B1 of the second multiplexer is connected to the second non-volatile memory; port B2 of the second multiplexer is connected to the third non-volatile memory; port S of the first multiplexer is connected to the select1 pin; port E0# of the first multiplexer is connected to the E0#1 pin; port S of the second multiplexer is connected to the select2 pin; and port E0# of the second multiplexer is connected to the E0#2 pin.

[0010] According to some embodiments of the present invention, in steps S200 and S300, the topology type is obtained based on the topology information of the GPU server, and the selection of the total multiplexer is set through the select1 pin, the oe#1 pin, the select2 pin and the oe#2 pin of the first programmable logic chip of the GPU node; Based on the selection of the total multiplexer, the selection type of the total non-volatile memory is determined, wherein the selection type of the total non-volatile memory includes the first non-volatile memory, the second non-volatile memory, and the third non-volatile memory.

[0011] According to some embodiments of the present invention, in steps S200 and S300, when the topology type is a dual-uplink topology, the selection of the total multiplexer is set according to the selection truth table, wherein the select1 pin is set to "0", the select2 pin is set to "0", the oe#1 pin is set to "0", and the oe#2 pin is set to "1" to disable the second multiplexer and enable the first non-volatile memory.

[0012] According to some embodiments of the present invention, in steps S200 and S300, when the topology type is a single uplink topology, the selection of the total multiplexer is set according to the selection truth table, wherein the select1 pin is set to "1", the select2 pin is set to "0", the oe#1 pin is set to "0", and the oe#2 pin is set to "0" to enable the first multiplexer and the second multiplexer, and to select the second non-volatile memory.

[0013] According to some embodiments of the present invention, in steps S200 and S300, when the topology type is a cascaded topology, the selection of the total multiplexer is set according to the selection truth table, wherein the select1 pin is set to "1", the select2 pin is set to "1", the oe#1 pin is set to "0", and the oe#2 pin is set to "0" to enable the first multiplexer and the second multiplexer, and to select the third non-volatile memory.

[0014] According to some embodiments of the present invention, in step S400, the firmware file includes a firmware file for a dual-uplink topology, a firmware file for a single-uplink topology, and a firmware file for a cascaded topology; the first non-volatile memory is controlled to burn the firmware file for the dual-uplink topology, the second non-volatile memory is controlled to burn the firmware file for the single-uplink topology, and the third non-volatile memory is controlled to burn the firmware file for the cascaded topology.

[0015] The present invention also relates to a computer device, including a memory and a processor, wherein the processor executes the method described above when executing a computer program stored in the memory.

[0016] The present invention also relates to a computer-readable storage medium having program instructions stored thereon, which, when executed by a processor, implement the method described above.

[0017] The beneficial effects of this invention include: the first programmable logic chip controlling the GPU node acquires the topology information of the GPU server; based on the GPU server's topology information and a gating truth table, it sets the gating of the total multiplexer; based on the gating of the total multiplexer, it determines the gating type of the total non-volatile memory; based on the gating type of the total non-volatile memory, it loads the corresponding firmware file from the corresponding total non-volatile memory through the serial peripheral interface of the switching chip to configure the PCIe port of the switching chip, thereby configuring the GPU server. The serial peripheral interface of the switching chip is connected to multiple total non-volatile memories. The solution proposed above can adaptively switch to the firmware file required by the actual topology throughout the entire process from server assembly and power-on to startup, thereby improving production efficiency and saving development costs.

[0018] Furthermore, additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] Figure 1 This is an optional flowchart of a configuration method for a GPU server compatible with multiple topologies in an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of the Balanced dual-uplink topology in an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of the Common dual-uplink topology in an embodiment of the present invention.

[0022] Figure 4This is a schematic diagram of the Balanced single uplink topology in an embodiment of the present invention.

[0023] Figure 5 This is a schematic diagram of the Common single uplink topology in an embodiment of the present invention.

[0024] Figure 6 This is a schematic diagram of the Cascade topology in an embodiment of the present invention.

[0025] Figure 7 This is a schematic diagram of a Balanced dual-uplink topology in an embodiment of the present invention without the connection relationship between the first programmable logic chip, the switching chip, and the total non-volatile memory.

[0026] Figure 8 This is a schematic diagram of a Common dual-uplink topology in an embodiment of the present invention without the connection relationship between the first programmable logic chip, the switching chip, and the total nonvolatile memory.

[0027] Figure 9 This is a schematic diagram of a Balanced single-uplink topology in an embodiment of the present invention without the connection relationship between the first programmable logic chip, the switching chip, and the total non-volatile memory.

[0028] Figure 10 This is a schematic diagram of a Common single uplink topology in an embodiment of the present invention without the connection relationship between the first programmable logic chip, the switching chip, and the total nonvolatile memory.

[0029] Figure 11 This is a schematic diagram of a Cascade topology in an embodiment of the present invention without the connection relationship between the first programmable logic chip, the switching chip, and the total nonvolatile memory.

[0030] Figure 12 This is a schematic diagram showing the connection relationship between the first programmable logic chip, the switching chip, the total multiplexer, and the total non-volatile memory in the dual uplink topology of this invention.

[0031] Figure 13 This is a schematic diagram of the connection relationship between the first programmable logic chip, the switching chip, the total multiplexer, and the total non-volatile memory in a single uplink topology according to an embodiment of the present invention.

[0032] Figure 14 This is a schematic diagram showing the connection relationship between the first programmable logic chip, the switching chip, the total multiplexer, and the total non-volatile memory in the cascaded topology structure of this invention. Detailed Implementation

[0033] The following will provide a clear and complete description of the concept, specific structure, and technical effects of the present invention in conjunction with the embodiments and accompanying drawings, so as to fully understand the purpose, solution, and effects of the present invention. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0034] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. Furthermore, the descriptions of "upper," "lower," "left," "right," "top," and "bottom" used in this invention are only relative to the relative positional relationships of the various components of the invention in the accompanying drawings.

[0035] Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and not for limiting the invention. The term "and / or" as used herein includes any combination of one or more of the associated listed items.

[0036] It should be understood that although the terms first, second, third, etc., may be used to describe various elements in this invention, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, a first element may also be referred to as a second element without departing from the scope of this invention, and similarly, a second element may also be referred to as a first element.

[0037] To facilitate understanding of the technical solutions provided in the embodiments of the present invention, some key terms used in the embodiments of the present invention will be explained here first: CPU: Central Processing Unit, is the core unit in a personal computer and server responsible for interpreting instructions, performing general-purpose calculations, and controlling the overall operation of the machine.

[0038] PCIe: Peripheral Component Interface Express is a high-speed serial computer expansion bus standard used to connect devices such as CPUs, GPUs, SSDs, and network cards into a unified I / O system.

[0039] CPLD: Complex Programmable Logic Device. It is a medium-scale programmable hardware based on product term arrays and programmable interconnects. It is often used to implement board-level management functions such as glue logic, power timing, port protection, and hot-swap control. It can operate when power is off and has a fixed delay.

[0040] GPU: Graphics Processing Unit, is a processor designed for high-parallelism floating-point and vector computation. It is now widely used in graphics rendering, deep learning training / inference, and scientific computing, and is usually connected to the main CPU via the PCIe bus.

[0041] PCIe Switch: A switching chip suitable for the PCIe bus, used to expand PCIe bus resources.

[0042] MCIO: Mini Cool Edge IO is an interface that combines multiple physical channels into a single high-speed data stream, widely used for data transmission on high-speed computer buses such as PCIe.

[0043] NVMe: Non-Volatile Memory Express, is a high-speed storage protocol designed specifically for solid-state drives (SSDs).

[0044] SPI: Serial Peripheral Interface, a high-speed, full-duplex, synchronous communication bus protocol.

[0045] MUX (Multiplexer) is a general term for a class of high-speed / low-speed signal selection switches.

[0046] Reference Figures 1 to 14 In some embodiments, the configuration method of the GPU server compatible with multiple topologies according to the present invention includes at least the following steps: S100: The first programmable logic chip that controls the GPU node obtains the topology information of the GPU server; S200, based on the topology information and gating truth table of the GPU server, sets the gating of the total multiplexer; S300. Determine the selection type of the total nonvolatile memory based on the selection of the total multiplexer; S400: Based on the strobe type of the total nonvolatile memory, load the corresponding firmware file from the corresponding total nonvolatile memory through the serial peripheral interface of the switching chip to configure the PCIe port of the switching chip, thereby configuring the GPU server. The serial peripheral interface of the switching chip is connected to multiple non-volatile memories.

[0047] As can be seen, the solution proposed above by the present invention can adaptively switch to the firmware file required by the actual topology to start and complete the configuration throughout the entire process from server assembly to power-on, thereby improving production efficiency and saving development costs.

[0048] It's important to note that a GPU server primarily consists of two nodes: CPU nodes and GPU nodes. The GPU nodes and CPU nodes are connected via multiple MCIO cables to transmit PCIe bus signals. Each GPU node has two switching chips that expand the PCIe bus resources from the CPU node to support the needs of multiple GPU cards, network cards, NVMe SSDs, and other components. Typically, after power-on, the switching chip loads firmware files from an external Flash chip via its SPI interface to configure the chip's PCIe ports and other resources.

[0049] Specifically, in this invention, see [reference needed]. Figure 2 and Figure 7 In the Balanced dual-uplink mode: the uplink port S0 of switch chip 1 is connected to the PE0 port of CPU0 via two MCIO cables; the uplink port S1 of switch chip 1 is connected to the PE1 port of CPU0 via two MCIO cables; the uplink port S0 of switch chip 2 is connected to the PE0 port of CPU1 via two MCIO cables; the uplink port S1 of switch chip 2 is connected to the PE1 port of CPU1 via two MCIO cables; the CPLD (i.e., the aforementioned first programmable logic chip) of the GPU node is used to control the power-on and power-off timing of the node and to perform some data interaction with the CPU node. In this topology, after power-on, switch chip 1 and switch chip 2 load firmware files from the external Flash chip through the SPI interface (i.e., the aforementioned serial peripheral interface) of switch chip 1 and the SPI interface of switch chip 2 to complete the configuration of resources such as the chip PCIe ports. The downstream devices of each switch chip are evenly distributed and connected to its two uplink ports.

[0050] In this invention, see Figure 3 and Figure 8Common Dual Uplink Mode: In this structure, both switching chips are connected to ports on CPU0. Uplink port S0 of switching chip 1 is connected to CPU0's PE0 port via two MCIO cables; uplink port S1 of switching chip 1 is connected to CPU0's PE1 port via two MCIO cables; uplink port S0 of switching chip 2 is connected to CPU0's PE3 port via two MCIO cables; uplink port S1 of switching chip 2 is connected to CPU0's PE4 port via two MCIO cables. The GPU node's CPLD is used to control the node's power-on / off timing and to perform some data interaction with the CPU node. In this topology, after power-on, the switching chip loads firmware files from an external Flash chip via its SPI interface to configure resources such as the chip's PCIe ports. Downstream devices for each switching chip are evenly distributed and connected to its two uplink ports. In this topology, because the port resource configuration of its switching chip is completely consistent with that of Balanced dual uplink, the firmware file information of the switching chip is consistent with that of Balanced dual uplink.

[0051] In this invention, see Figure 4 and Figure 9 In the Balanced single-uplink mode: the uplink port S0 of switch chip 1 is connected to the PE0 port of CPU 0 via two MCIO cables; the uplink port S0 of switch chip 2 is connected to the PE0 port of CPU 1 via two MCIO cables. In this topology, during power-up, the switch chip loads firmware files from an external Flash chip via its SPI interface to configure resources such as the chip's PCIe ports. Downstream devices of each switch chip are connected to the same uplink port. The GPU node's CPLD is used to control the node's power-up / down timing and to perform some data interaction with the CPU node. In this topology, the firmware file information of the switch chips is inconsistent with that in the dual-uplink configuration.

[0052] In this invention, see Figure 5 and Figure 10Common Single Uplink Mode: In this structure, both switching chips are connected to ports on CPU0. Uplink port S0 of switching chip 1 is connected to the PE0 port of CPU0 via two MCIO cables; uplink port S0 of switching chip 2 is connected to the PE1 port of CPU0 via two MCIO cables. In this topology, during power-up, the switching chips load firmware files from an external Flash chip via their SPI interface to configure resources such as the chip's PCIe ports. Downstream devices of each switching chip are connected to the same uplink port. The GPU node's CPLD is used to control the node's power-up / down timing and to perform some data interaction with the CPU node. In this topology, the firmware file information of the switching chips is inconsistent with that of the dual uplink configuration but consistent with the Balanced Single Uplink configuration.

[0053] In this invention, see Figure 6 and Figure 11 Cascade Mode: In this structure, only switch chip 1 is directly connected to the port of CPU0, and switch chip 2 is connected to switch chip 1, achieving a cascaded structure. The uplink port S0 of switch chip 1 is connected to the PE0 port of CPU0 via two MCIO cables; the uplink port S0 of switch chip 2 is connected to the interface at port S8 of switch chip 1 via two MCIO cables. In this topology, during power-up, the switch chips load firmware files from an external Flash chip via their SPI interface to configure resources such as the chip's PCIe ports. Downstream devices of each switch chip are connected to the same uplink port. The CPLD of the GPU node is used to control the power-up / down timing of the node and to perform some data interaction with the CPU node. In this topology, the firmware file information of the switch chips is different from all the previous structures.

[0054] It should be noted that in existing technologies, when a GPU server switches topologies, the firmware file of the switching chip cannot be automatically adapted, requiring manual re-flashing of the corresponding firmware file. This flashing process relies on online software upgrade functionality, which cannot be completed if the software does not support it. This process incurs software development and maintenance costs, and its cumbersome, error-prone, and inefficient nature hinders mass production, further increasing production costs.

[0055] This invention can automatically match and load the firmware file of the corresponding switching chip after the GPU server completes the topology assembly and switching, without the need to re-burn the firmware file or develop additional software functions, thereby saving development investment, simplifying the whole machine production process, improving production efficiency, and reducing production costs.

[0056] Specifically, the term "switch chip" refers to a PCIe switch chip. A PCIe switch chip is an application-specific integrated circuit (ASIC) designed for expanding, aggregating, and scheduling high-speed PCIe channels. Flash chips are a type of non-volatile semiconductor memory that utilizes a floating-gate tunnel oxide (MOSFET) transistor to store charge.

[0057] The specific implementation method of step S100 is as follows:

[0058] The method of this embodiment controls the first programmable logic chip of the GPU node to obtain the topology information of the GPU server.

[0059] In some embodiments, prior to step S100, the configuration method for a multi-topology compatible GPU server further includes the following steps: A. The second programmable logic chip controlling the CPU node acquires the electrical signals of the MCIO cable on the CPU node and combines the electrical signals into the topology information of the GPU server according to preset rules. B. Control the second programmable logic chip to transmit the topology information of the GPU server to the NVM register inside the first programmable logic chip via the I2C bus.

[0060] Specifically, the second programmable logic chip is connected to the first programmable logic chip via an I2C bus.

[0061] It's important to note that MCIO cable stands for "Mini-Cool-Edge IO" cable. Based on the SFF-TA-1016 standard, it's a high-density, low-profile, high-speed internal copper cable assembly used to transmit high-speed differential signals such as PCIe 5.0 / 6.0, CXL, or UCIe between devices like servers, GPU accelerator cards, and storage backplanes. The I2C bus, also known as the IIC bus, is a two-wire, half-duplex, synchronous, multi-master, multi-slave, board-level serial bus. It connects the MCU to various low-speed peripheral chips (EEPROM, RTC, temperature sensors, PMIC, LED drivers, touchscreens, battery management, DDR SPD, etc.) with a minimal number of pins, earning it the nickname "serial USB between chips." The NVM register is a non-volatile memory unit within a programmable logic chip used for "power-down configuration saving." It allows the chip to restore user settings after a restart, making it a key technology for achieving "reconfigurable, no external configuration chip required."

[0062] The specific implementation methods of steps S200 and S300 are as follows:

[0063] The method of this invention sets the gating of the total multiplexer based on the topology information of the GPU server and the gating truth table, and determines the gating type of the total nonvolatile memory based on the gating of the total multiplexer.

[0064] In some embodiments, the GPU node includes a first programmable logic chip, a switching chip, a first non-volatile memory, a second non-volatile memory, a third non-volatile memory, a first multiplexer, and a second multiplexer; the first programmable logic chip includes a select1 pin, an e#1 pin, a select2 pin, and an e#2 pin. The GPU node is configured such that: the serial peripheral interface of the switching chip is connected to port A of the first multiplexer; port B1 of the first multiplexer is connected to the first non-volatile memory; port B2 of the first multiplexer is connected to port A of the second multiplexer; port B1 of the second multiplexer is connected to the second non-volatile memory; port B2 of the second multiplexer is connected to the third non-volatile memory; port S of the first multiplexer is connected to the select1 pin; port E0# of the first multiplexer is connected to the E0#1 pin; port S of the second multiplexer is connected to the select2 pin; and port E0# of the second multiplexer is connected to the E0#2 pin.

[0065] In some embodiments, in steps S200 and S300, the topology type is obtained based on the topology information of the GPU server, and the selection of the total multiplexer is set through the select1 pin, oe#1 pin, select2 pin and oe#2 pin of the first programmable logic chip of the GPU node; Based on the selection of the total multiplexer, the selection type of the total non-volatile memory is determined, wherein the selection type of the total non-volatile memory includes a first non-volatile memory, a second non-volatile memory, and a third non-volatile memory.

[0066] In some embodiments, during steps S200 and S300, when the topology type is a dual-uplink topology, the selection of the total multiplexer is set according to the selection truth table, wherein the select1 pin is set to "0", the select2 pin is set to "0", the oe#1 pin is set to "0", and the oe#2 pin is set to "1" to disable the second multiplexer and enable the first non-volatile memory.

[0067] In some embodiments, during steps S200 and S300, when the topology type is a single uplink topology, the selection of the total multiplexer is set according to the selection truth table, wherein the select1 pin is set to "1", the select2 pin is set to "0", the oe#1 pin is set to "0", and the oe#2 pin is set to "0" to enable the first multiplexer and the second multiplexer, and the second non-volatile memory is selected.

[0068] In some embodiments, during steps S200 and S300, when the topology type is a cascaded topology, the selection of the total multiplexer is set according to the selection truth table, wherein the select1 pin is set to "1", the select2 pin is set to "1", the oe#1 pin is set to "0", and the oe#2 pin is set to "0" to enable the first multiplexer and the second multiplexer, and to select the third non-volatile memory.

[0069] Specifically, see Figures 2 to 6 When designing the external circuitry of the switching chip on the GPU node, each switching chip's SPI interface is simultaneously connected to three Flash chips (i.e., the aforementioned first non-volatile memory, second non-volatile memory, and third non-volatile memory). Flash1 (the aforementioned first non-volatile memory) is programmed with a dual-uplink (Balanced and Common) topology firmware file by default during hardware circuit board manufacturing. Flash2 (the aforementioned second non-volatile memory) is programmed with a single-uplink (Balanced and Common) topology firmware file by default during hardware circuit board manufacturing. Flash3 (the aforementioned third non-volatile memory) is programmed with a Cascade topology firmware file by default during circuit board manufacturing. Two high-speed MUX (the aforementioned first and second multiplexers) switching chips (SN74CBTLV3257) are introduced into the SPI bus of each switching chip to select a specific Flash chip (i.e., the aforementioned first, second, or third non-volatile memory) to enable the switching chip to boot and complete configuration from that Flash. The two MUX chips under the switching chip are respectively connected to the CPLD (i.e., the aforementioned first programmable logic chip) on the GPU node. The CPLD (i.e., the aforementioned first programmable logic chip) controls the switching of MUX1 (i.e., the aforementioned first multiplexer) and MUX2 (i.e., the aforementioned second multiplexer) through select1, oe#1, select2, and oe#2. The CPLD (i.e., the aforementioned second programmable logic chip) of the CPU node communicates with the CPLD (i.e., the aforementioned first programmable logic chip) of the GPU node through the I2C bus to transmit the topology information to the CPLD (i.e., the aforementioned first programmable logic chip) of the GPU node.

[0070] The truth tables for gating MUX1 and MUX2 are shown in Table 1: Table 1: Truth Tables for Gating MUX1 and MUX2: Serial Number Select1 Select2 Oe#1 Oe#2 Select Flash# Topology Remark 1 0 0 0 1 Flash1 Dual uplink topology Turn off MUX2 2 1 0 0 0 Flash2 Single uplink topology Open MUX1 / 2 3 1 1 0 0 Flash3 Cascaded topology Open MUX1 / 2 Before the GPU node's CPLD (i.e., the aforementioned first programmable logic chip) initializes and sets MUX1 and MUX2, the CPU node's CPLD (i.e., the aforementioned second programmable logic chip) needs to write the corresponding current server topology information via the I2C bus. This topology information is closely related to the connection status of the uplink port of the switching chip and the MCIO cable connecting the CPU node. After obtaining this topology information, the GPU node's CPLD sets the MUX strobes according to the aforementioned strobe truth table. If the GPU server malfunctions, causing the CPU node's CPLD to be unable to send valid topology information to the GPU node's CPLD, the GPU node's CPLD will default to setting MUX1 and MUX2 to strobe Flash1, meaning the switching chip will start with a dual uplink topology by default.

[0071] Specific implementation method of step S400:

[0072] According to the method of this invention, based on the strobe type of the total non-volatile memory, the corresponding firmware file is loaded from the corresponding total non-volatile memory through the serial peripheral interface of the switching chip to configure the PCIe port of the switching chip, thereby configuring the GPU server.

[0073] In some embodiments, in step S400, the firmware file includes a firmware file for a dual uplink topology, a firmware file for a single uplink topology, and a firmware file for a cascaded topology. Control the first non-volatile memory to burn firmware files for a dual-uplink topology, control the second non-volatile memory to burn firmware files for a single-uplink topology, and control the third non-volatile memory to burn firmware files for a cascaded topology.

[0074] Understandably, the GPU node is configured as follows: the serial peripheral interface of the main switching chip is connected to port A of the first multiplexer; port B1 of the first multiplexer is connected to the first non-volatile memory; port B2 of the first multiplexer is connected to port A of the second multiplexer; port B1 of the second multiplexer is connected to the second non-volatile memory; port B2 of the second multiplexer is connected to the third non-volatile memory; port S of the first multiplexer is connected to the select1 pin; port E0# of the first multiplexer is connected to the E0#1 pin; port S of the second multiplexer is connected to the select2 pin; and port E0# of the second multiplexer is connected to the E0#2 pin. The main switching chip includes a first switching chip (i.e., switching chip 1) and a second switching chip (i.e., switching chip 2).

[0075] See Figure 12The dual-uplink topology (including Balanced and Common) involves two switching chips booting from their respective Flash1 (the aforementioned first non-volatile memory). The A ports of the two MUX1s are connected to the SPI ports of switching chip 1 and switching chip 2, respectively. The Flash1 of switching chip 1 and switching chip 2 are connected to the B1 ports of their respective MUX1s. The CPLD (the aforementioned first programmable logic chip) controls the operation of the two MUX1s via the select1 and e#1 pins. In this structure, the B2 ports of the two MUX1s and MUX2 do not need to participate in operation.

[0076] The serial peripheral interface of switch chip 1 is connected to port A of the first multiplexer of switch chip 1, and the serial peripheral interface of switch chip 2 is connected to port A of the first multiplexer of switch chip 2; port B1 of the first multiplexer of switch chip 1 is connected to the first non-volatile memory of switch chip 1, and port B1 of the first multiplexer of switch chip 2 is connected to the first non-volatile memory of switch chip 2; port S of the first multiplexer of switch chip 1 is connected to the select1 pin, port E0# of the first multiplexer of switch chip 1 is connected to the E0#1 pin, port S of the first multiplexer of switch chip 2 is connected to the select1 pin, and port E0# of the first multiplexer of switch chip 2 is connected to the E0#1 pin.

[0077] See Figure 13 In a single-uplink topology (including Balanced and Common), both switching chips boot from their respective Flash2 ports. The A ports of the two MUX1s are connected to the SPI ports of switching chip 1 and switching chip 2, respectively. The A ports of the two MUX2s are connected to the B2 ports of the two MUX1s, respectively. The Flash2 ports of switching chip 1 and switching chip 2 are connected to the B1 ports of their respective MUX2s. The CPLD (i.e., the aforementioned first programmable logic chip) controls the operation of the four MUXs through the select1, e1#1, select2, and e2#2 pins. In this structure, the B1 ports of the two MUX1s and the B2 ports of the two MUX2s do not need to participate in operation.

[0078] The serial peripheral interface of switch chip 1 is connected to port A of the first multiplexer of switch chip 1, and the serial peripheral interface of switch chip 2 is connected to port A of the first multiplexer of switch chip 2; port B2 of the first multiplexer of switch chip 1 is connected to port A of the second multiplexer of switch chip 1, and port B2 of the first multiplexer of switch chip 2 is connected to port A of the second multiplexer of switch chip 2; port B1 of the second multiplexer of switch chip 1 is connected to the second non-volatile memory of switch chip 1, and port B1 of the second multiplexer of switch chip 2 is connected to the second non-volatile memory of switch chip 2; the first multiplexer of switch chip 1... The S port of the selector is connected to the select1 pin; the oe# port of the first multiplexer of the switching chip 1 is connected to the oe#1 pin; the S port of the second multiplexer of the switching chip 1 is connected to the select2 pin; the oe# port of the second multiplexer of the switching chip 1 is connected to the oe#2 pin; the S port of the first multiplexer of the switching chip 2 is connected to the select1 pin; the oe# port of the first multiplexer of the switching chip 2 is connected to the oe#1 pin; the S port of the second multiplexer of the switching chip 2 is connected to the select2 pin; the oe# port of the second multiplexer of the switching chip 2 is connected to the oe#2 pin.

[0079] See Figure 14 Cascaded topology (including Cascade): Both switching chips boot from their respective Flash3. The A ports of the two MUX1s are connected to the SPI ports of switching chip 1 and switching chip 2, respectively. The A ports of the two MUX2s are connected to the B2 ports of the two MUX1s, respectively. The Flash3 of switching chip 1 and switching chip 2 are connected to the B2 ports of their respective MUX2s. The CPLD (i.e., the aforementioned first programmable logic chip) controls the operation of the four MUXs through the select1, e1#1, select2, and e2#2 pins. In this structure, the B1 ports of the two MUX1s and the two MUX2s do not need to participate in operation.

[0080] The serial peripheral interface of switch chip 1 is connected to port A of the first multiplexer of switch chip 1, and the serial peripheral interface of switch chip 2 is connected to port A of the first multiplexer of switch chip 2; port B2 of the first multiplexer of switch chip 1 is connected to port A of the second multiplexer of switch chip 1, and port B2 of the first multiplexer of switch chip 2 is connected to port A of the second multiplexer of switch chip 2; port B2 of the second multiplexer of switch chip 1 is connected to the third non-volatile memory of switch chip 1, and port B2 of the second multiplexer of switch chip 2 is connected to the third non-volatile memory of switch chip 2; the first multiplexer of switch chip 1... The S port of the selector is connected to the select1 pin; the oe# port of the first multiplexer of the switching chip 1 is connected to the oe#1 pin; the S port of the second multiplexer of the switching chip 1 is connected to the select2 pin; the oe# port of the second multiplexer of the switching chip 1 is connected to the oe#2 pin; the S port of the first multiplexer of the switching chip 2 is connected to the select1 pin; the oe# port of the first multiplexer of the switching chip 2 is connected to the oe#1 pin; the S port of the second multiplexer of the switching chip 2 is connected to the select2 pin; the oe# port of the second multiplexer of the switching chip 2 is connected to the oe#2 pin.

[0081] In one specific embodiment, the configuration method for a GPU server compatible with multiple topologies includes the following steps: When designing the GPU node side, each switching chip's SPI interface simultaneously connects to 3 Flash chips, and two high-speed MUX switching chips SN74CBTLV3257 are introduced to select the switching chip to a specific Flash chip. Because the firmware files used by the switching chips are the same for both Balanced dual uplink and Common dual uplink, and the firmware files for the switching chips are the same for both Balanced single uplink and Common single uplink, the standard procedure for manufacturing the circuit boards on the GPU node side is to program the firmware files for dual uplink on the Flash1 chip, the firmware files for single uplink on the Flash2 chip, and the firmware files for the cascade structure on the Flash3 chip. The CPLD (i.e. the aforementioned second programmable logic chip) on the CPU node acquires the electrical signals from each MCIO connector on the node, and then combines the electrical signals into configuration information of the server topology according to predetermined rules. The CPU node's CPLD (i.e., the aforementioned second programmable logic chip) transmits topology configuration information to the GPU node's CPLD (i.e., the aforementioned first programmable logic chip) internal NVM register via the I2C bus. The CPLD (i.e., the first programmable logic chip mentioned above) of the GPU node controls the selection of MUX1 and MUX2 under the SPI interface of the two switching chips through four signals oe#1, select1, oe#2 and select2 according to the received topology configuration information. After the CPLD initialization and strobe settings of MUX1 and MUX2 are completed, the server receives the power-on signal, the switching chip powers on, and then loads the firmware configuration file from its respective Flash1, Flash2 or Flash3 to complete the initialization of the PCIe port resources of the switching chip. Due to server topology limitations, the two switching chips can only load firmware configuration files from their respective Flash1, Flash2, or Flash3 simultaneously in one of three scenarios; there are no other combinations.

[0082] Specifically, after selecting the MUX according to the actual topology, during the normal boot process of the server, the two switching chips load the configuration file from their respective Flash1, Flash2 or Flash3 to complete the startup.

[0083] It is understood that this invention supports intelligent and automatic switching of the switching chip firmware configuration file after the GPU server has completed the assembly and switching of the topology; it does not require re-burning the firmware of the new topology switching chip; it does not require additional software development investment, saving development costs; it simplifies and improves the overall production process of the server, improves production efficiency, and saves production costs; and it makes the server products more adaptable, flexible, and more competitive in the market.

[0084] This invention also provides a computer device including a memory and a processor, wherein the processor performs the above-described method when executing a computer program stored in the memory.

[0085] This invention also provides a computer-readable storage medium storing program instructions thereon, which, when executed by a processor, implement the method described above.

[0086] It should be understood that the method steps in the embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The method can use standard programming techniques. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if necessary, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0087] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program comprises a plurality of instructions executable by one or more processors.

[0088] Furthermore, the method can be implemented in any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices, etc. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. When programmed according to the methods and techniques described in the invention, the invention may also include the computer itself.

[0089] A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects generated on the display.

[0090] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, as long as they achieve the technical effects of the present invention by the same means, should be included within the scope of protection of the present invention. Within the scope of protection of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A configuration method for GPU servers compatible with multiple topologies, characterized in that, Includes the following steps: S100: The first programmable logic chip that controls the GPU node obtains the topology information of the GPU server; S200. Based on the topology information of the GPU server and the gating truth table, set the gating of the total multiplexer; S300. Determine the selection type of the total nonvolatile memory based on the selection of the total multiplexer; S400. According to the selection type of the total non-volatile memory, load the corresponding firmware file from the corresponding total non-volatile memory through the serial peripheral interface of the switching chip to configure the PCIe port of the switching chip, thereby configuring the GPU server. The serial peripheral interface of the switching chip is connected to multiple non-volatile memories.

2. The configuration method for a GPU server compatible with multiple topologies according to claim 1, characterized in that, Before step S100, the configuration method for the multi-topology compatible GPU server further includes the following steps: A. The second programmable logic chip controlling the CPU node acquires the electrical signals of the MCIO cable on the CPU node, and combines the electrical signals into the topology information of the GPU server according to a preset rule; B. Control the second programmable logic chip to transmit the topology information of the GPU server to the NVM register inside the first programmable logic chip via the I2C bus.

3. The configuration method for a GPU server compatible with multiple topologies according to claim 1, characterized in that, The GPU node includes a first programmable logic chip, a switching chip, a first non-volatile memory, a second non-volatile memory, a third non-volatile memory, a first multiplexer, and a second multiplexer; the first programmable logic chip includes select1 pin, eE#1 pin, select2 pin, and eE#2 pin; The GPU node is configured such that: the serial peripheral interface of the switching chip is connected to port A of the first multiplexer; port B1 of the first multiplexer is connected to the first non-volatile memory; port B2 of the first multiplexer is connected to port A of the second multiplexer; port B1 of the second multiplexer is connected to the second non-volatile memory; port B2 of the second multiplexer is connected to the third non-volatile memory; port S of the first multiplexer is connected to the select1 pin; port E0# of the first multiplexer is connected to the E0#1 pin; port S of the second multiplexer is connected to the select2 pin; and port E0# of the second multiplexer is connected to the E0#2 pin.

4. The configuration method for a GPU server compatible with multiple topologies according to claim 3, characterized in that, In steps S200 and S300, The topology type is obtained based on the topology information of the GPU server, and the selection of the total multiplexer is set through the select1 pin, oe#1 pin, select2 pin and oe#2 pin of the first programmable logic chip of the GPU node; Based on the selection of the total multiplexer, the selection type of the total non-volatile memory is determined, wherein the selection type of the total non-volatile memory includes the first non-volatile memory, the second non-volatile memory, and the third non-volatile memory.

5. The configuration method for a multi-topology compatible GPU server according to claim 4, characterized in that, In steps S200 and S300, When the topology type is a dual-uplink topology, the selection of the total multiplexer is set according to the selection truth table, wherein the select1 pin is set to "0", the select2 pin is set to "0", the oe#1 pin is set to "0", and the oe#2 pin is set to "1" to disable the second multiplexer and enable the first non-volatile memory.

6. The configuration method for a GPU server compatible with multiple topologies according to claim 4, characterized in that, In steps S200 and S300, When the topology type is a single uplink topology, the selection of the total multiplexer is set according to the selection truth table, wherein the select1 pin is set to "1", the select2 pin is set to "0", the oe#1 pin is set to "0", and the oe#2 pin is set to "0" to enable the first multiplexer and the second multiplexer, and to select the second non-volatile memory.

7. The configuration method for a multi-topology compatible GPU server according to claim 4, characterized in that, In steps S200 and S300, When the topology type is a cascaded topology, the selection of the total multiplexer is set according to the selection truth table, wherein the select1 pin is set to "1", the select2 pin is set to "1", the oe#1 pin is set to "0", and the oe#2 pin is set to "0" to enable the first multiplexer and the second multiplexer, and to select the third non-volatile memory.

8. The configuration method for a GPU server compatible with multiple topologies according to claim 4, characterized in that, In step S400 The firmware files include firmware files for dual uplink topology, single uplink topology, and cascaded topology; The system controls the first non-volatile memory to burn the firmware file of the dual uplink topology, controls the second non-volatile memory to burn the firmware file of the single uplink topology, and controls the third non-volatile memory to burn the firmware file of the cascaded topology.

9. A computer device comprising a memory and a processor, characterized in that, When the processor executes a computer program stored in the memory, it performs the method as described in any one of claims 1 to 8.

10. A computer-readable storage medium having program instructions stored thereon, characterized in that, When the program instructions are executed by the processor, they perform the method as described in any one of claims 1 to 8.

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