A method and system for automatic calibration of behavioral level models of stacked chips

Abstract

The application provides a behavior level model automatic calibration method and system for stacked chips, which comprises the following steps: constructing a behavior level model library, the behavior level model library storing a plurality of behavior level models with different precisions, the precisions of the plurality of behavior level models from high to low including a cycle accurate model, a cycle approximate model and a transaction level model; establishing an identification for each behavior level model, the identification of each behavior level model comprising a model identification number, a precision level and a model performance of the behavior level model; obtaining a conversion index of a target chip in current simulation, and judging whether the type of the behavior level model of the target chip in current simulation needs to be converted according to the conversion index of the target chip; if the type of the behavior level model of the target chip in current simulation needs to be converted, the type of the behavior level model of the target chip in current simulation is converted to a behavior level model with matched precision. The application also provides a system for implementing the above method. The application can automatically convert the behavior level model during chip simulation to meet the requirements of simulation efficiency and simulation accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, in particular to a stacked chip behavior level model automatic calibration method and a stacked chip behavior level model automatic calibration system implementing the method. BACKGROUND

[0002] With the development of chip technology, three-dimensional stacked chips have been widely used, and the design efficiency of three-dimensional stacked chips has been paid more and more attention by researchers. With the development of technology, three-dimensional stacked chip design is also carried out in an automated manner. In the design process of three-dimensional stacked chips of heterogeneous integration, since multiple chips of different processes and different functions need to be combined for complex interconnection and packaging, any error will cause the entire chip to malfunction. Therefore, a lot of time is spent on verifying and iterating the chip during the design of three-dimensional stacked chips, and early high-level modeling simulation is needed before three-dimensional stacked chip integration.

[0003] In the high-level modeling simulation process of three-dimensional stacked chips, a suitable behavior level model needs to be selected for the current chip for verification. Currently, the behavior level models used in the simulation process of three-dimensional stacked chips include cycle-accurate models, cycle-approximate models, and transaction-level models from high to low in precision. When simulating, an engineer needs to select one of the models for simulation. Once the behavior level model is selected, the entire simulation process cannot be modified. For example, to improve simulation efficiency, an engineer will choose the transaction-level model with the lowest precision for simulation. However, if it is found during simulation that the precision of the currently selected behavior level model is not sufficient, the existing method is to interrupt the simulation and manually select a higher-precision behavior level model before performing high-precision simulation. However, this method cannot automatically switch and match to a model with appropriate precision according to the problem found during the current verification run, resulting in inflexible chip simulation and difficulty in balancing simulation performance and efficiency.

[0004] A current multi-simulation-precision switchable test method is to create a test system containing multiple simulation-precision functional block models, switch to a simulation-precision functional block model suitable for the current simulation process scenario in the multiple simulation-precision functional block models during simulation, and perform simulation testing using the switched simulation-precision functional block model. The precision of the model includes behavior level and cycle level. However, in this way, the switching of the model relies on user-preset static configuration or manually selected dynamic switching points, and is not automatically switched according to actual conditions during simulation, which cannot meet the needs of three-dimensional stacked chip design automation. SUMMARY

[0005] The first object of the present application is to provide a stacked chip behavior level model automatic calibration method capable of automatically realizing behavior level model conversion of different precisions.

[0006] The second object of the present application is to provide a stacked chip behavior level model automatic calibration system capable of balancing design flexibility and design efficiency.

[0007] To realize the first object of the present application, the stacked chip behavior level model automatic calibration method provided by the present application comprises: constructing a behavior level model library, the behavior level model library storing behavior level models of multiple precisions, the precisions of the multiple behavior level models including, from high to low, a cycle accurate model, a cycle approximate model and a transaction level model; establishing an identification for each behavior level model, the identification of each behavior level model including a model identification number, a precision level and a model performance of the behavior level model; obtaining a conversion index of a target chip currently simulated, and judging whether the type of the behavior level model of the target chip currently simulated needs to be converted according to the conversion index of the target chip, and if so, converting the type of the behavior level model of the target chip currently simulated to a behavior level model of a matching precision.

[0008] As can be seen from the above scheme, the present application realizes automatic conversion of behavior level models of different precisions by automatically obtaining a conversion index of a target chip currently simulated and determining whether the type of the behavior level model of the target chip currently simulated needs to be converted according to the conversion index of the target chip, so that the automatic conversion of behavior level models of different precisions can be realized according to actual conditions in the process of simulation, balancing simulation efficiency and accuracy.

[0009] A preferred scheme is that the conversion index comprises one of the following: a chip performance index, a chip usage index, a chip function verification index, a chip power consumption and temperature index.

[0010] As can be seen from the above scheme, the chip simulation process can flexibly convert behavior level models of different precisions according to multiple conditions such as a chip performance index, a chip usage index, a chip function verification index, a chip power consumption and temperature index.

[0011] A further scheme is that determining whether the type of the behavior level model of the target chip currently simulated needs to be converted according to the chip performance index of the target chip comprises: if the interconnection bandwidth between two target chips exceeds a pre-set bandwidth threshold, converting the behavior level model of the target chip to a behavior level model of a higher precision; if the mutual access time between two target chips exceeds a pre-set time threshold, converting the behavior level model of the target chip to a behavior level model of a higher precision; if the cache hit rate of the target chip is less than a pre-set cache threshold, converting the behavior level model of the target chip to a behavior level model of a higher precision.

[0012] Therefore, by presetting the conversion rules of the chip under different chip performance index conditions, the conversion of the behavior level model can be realized in real time according to the chip performance index of the target chip during the simulation process.

[0013] Another scheme is that whether the type of the current behavior level model of the target chip needs to be converted is judged according to a chip function verification index of the target chip, including: if the unverified function module of the target chip needs to be verified or a new state machine state needs to be triggered, the behavior level model of the target chip is converted into a cycle accurate model; if the coverage area of a key boundary case in the simulation process is not hit for a long time, the behavior level model of the target chip is converted into a cycle accurate model in the corresponding time node in the test sequence.

[0014] Therefore, the behavior level model can be automatically converted according to the actual chip use index during the simulation process by presetting the behavior level model conversion rules of the target chip under different chip use index conditions.

[0015] Another scheme is that whether the type of the current behavior level model of the target chip needs to be converted is judged according to a chip function verification index of the target chip, including: if the unverified function module of the target chip needs to be verified or a new state machine state needs to be triggered, the behavior level model of the target chip is converted into a cycle accurate model; if the coverage area of a key boundary case in the simulation process is not hit for a long time, the behavior level model of the target chip is converted into a cycle accurate model in the corresponding time node in the test sequence.

[0016] Therefore, the behavior level model can be automatically converted according to the actual chip use index during the simulation process by presetting the behavior level model conversion rules of the target chip under different chip use index conditions.

[0017] Another scheme is that whether the type of the current behavior level model of the target chip needs to be converted is judged according to a chip function verification index of the target chip, including: if the unverified function module of the target chip needs to be verified or a new state machine state needs to be triggered, the behavior level model of the target chip is converted into a cycle accurate model; if the coverage area of a key boundary case in the simulation process is not hit for a long time, the behavior level model of the target chip is converted into a cycle accurate model in the corresponding time node in the test sequence.

[0018] Therefore, in the simulation process of the chip, the precision conversion of the behavior level model can be automatically realized according to the actual chip power consumption and temperature index.

[0019] Further, the simulation system simulates a plurality of modules containing a plurality of chips, and when it is determined that the type of the behavior level model of the target chip needs to be converted, only the behavior level model of the target chip is converted to a behavior level model with matching precision.

[0020] Therefore, the present application does not need to convert the behavior level model of all chips in the entire module being simulated, but only converts the behavior level model of the target chip that needs to be processed, thereby reducing the problem of low conversion efficiency caused by conversion of the entire module, and when the behavior level model with high precision needs to be converted, the above method can avoid the problem of excessive calculation caused by converting the entire module into a behavior level model with high precision.

[0021] Further, the model performance includes the estimated simulation speed and / or power consumption estimation error information of the model.

[0022] To achieve the above-mentioned second object, the behavior level model automatic calibration system for stacked chips provided by the present application includes a model library, a behavior level model library storing a plurality of precision behavior level models, the precision of the plurality of behavior level models from high to low includes: cycle accurate model, cycle approximate model and transaction level model; a model identification library module for establishing an identification for each behavior level model, the identification of each behavior level model includes the model identification number, precision level and model performance of the behavior level model; an intelligent detection module for obtaining the conversion index of the target chip currently simulated, determining whether the type of the current behavior level model of the target chip needs to be converted according to the conversion index of the target chip, and if the type of the current behavior level model of the target chip needs to be converted, converting the type of the current behavior level model of the target chip to a behavior level model with matching precision by the intelligent calibration module.

[0023] A preferred scheme is that the behavior level model library stores the behavior level models of the computing core, the storage core and the interconnection interposer.

[0024] Therefore, the present application stores a plurality of precision behavior level models of the computing core, the storage core and the interconnection interposer, and can meet the simulation requirements of the computing core, the storage core and the interconnection interposer. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a structural block diagram of an embodiment of the behavior level model automatic calibration system for stacked chips of the present application.

[0026] Figure 2 is a flowchart of an embodiment of the behavior level model automatic calibration method for stacked chips of the present application.

[0027] The application will be further described in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0028] The behavior level model automatic calibration system of the stacked chip is used for automatically converting the precision of the behavior level model of the target chip according to actual simulation needs in the chip simulation process, which can be converted into a higher precision model to more accurately find out the problems of the chip, or can be converted into a lower precision model to improve the simulation efficiency. Therefore, the application can flexibly and automatically realize the conversion of the behavior level model, and takes into account the simulation efficiency and accuracy.

[0029] Embodiment of the behavior level model automatic calibration system of the stacked chip:

[0030] Referring to Figure 1 The embodiment has a behavior level model library module 11, a model identification library module 12, an intelligent detection module 13 and an intelligent calibration module 14. The above-mentioned multiple modules can run in the simulation system of the stacked chip, and the intelligent detection module 13 can detect the real-time situation of the currently simulated chip, such as the performance index, power consumption, temperature and the like of the chip.

[0031] The behavior level model library module 11 is used for constructing a behavior level model library, and the constructed behavior level model library stores multiple precision behavior level models, such as multiple precision behavior level models including cycle accurate model, cycle approximate model and transaction level model. The multiple behavior level models have different precisions, and specifically, the precisions of the multiple behavior level models from high to low are cycle accurate model, cycle approximate model and transaction level model. It can be seen that the precision of the transaction level model is the lowest, the transactions between the transaction level models communicate through “transaction”, which refers to a complete “memory read-write request” or “data packet transmission” event, and the simulation speed of this type of behavior level model is the fastest. The precision of the cycle approximate model is higher than that of the transaction level model, and this model can reflect the approximate clock cycle required by the chip at present, but does not need to be accurate to the signal change in each cycle. The precision of the cycle accurate model is the highest, which can accurately simulate the behavior and output of the digital circuit in each clock cycle, and is completely consistent with the RTL (Register-Transfer Level) model. Further, the behavior level model library stores multiple different models, such as the behavior level models of the computing chip, the storage chip and the interconnection interlayer. The computing chip can be a CPU, GPU and the like, and the storage chip can be an HBM or a DDR and the like.

[0032] The model identifier library module 12 is used to establish identifiers for each behavioral-level model. The identifier for each behavioral-level model includes information such as the model identifier number, accuracy level, and model performance. Among them, model performance includes the estimated simulation speed and / or power consumption estimation error information of the corresponding behavioral-level model.

[0033] The intelligent detection module 13 is used to acquire the conversion index of the target chip being simulated during the simulation process, and to determine whether it is necessary to convert the type of the current behavioral-level model of the target chip based on the conversion index. In other words, it determines whether the accuracy of the behavioral-level model of the currently simulated chip needs to be adjusted, such as using a higher-precision model or a lower-precision model for simulation. If it is not necessary to adjust the accuracy of the behavioral-level model of the target chip, the current model accuracy is maintained.

[0034] If the accuracy of the behavioral-level model of the target chip in the current simulation needs to be adjusted, the intelligent calibration module 14 will convert the type of the current behavioral-level model of the target chip to a behavioral-level model with matching accuracy. Specifically, the intelligent calibration module 14 stores preset adjustment rules and converts the model to a behavioral-level model with matching accuracy based on the preset adjustment rules and the current situation of the simulated chip.

[0035] Example of an automatic calibration method for behavioral-level models of stacked chips:

[0036] The following is combined Figure 2 This document describes the working method of the aforementioned automatic calibration system for behavioral-level models of stacked chips. In this embodiment, step S1 is first executed to construct a behavioral-level model library. Specifically, three different levels of behavioral-level models with varying precision are established for computing chips, storage chips, and interconnect intermediary layers. These three levels of models are: periodic precise model, periodic approximation model, and transaction-level model, with the precision of each model ranging from highest to lowest as follows: periodic precise model, periodic approximation model, and transaction-level model.

[0037] Then, step S2 is executed to establish an identifier for each level of behavioral model. Specifically, for the multiple behavioral models created in step S1, a model identifier, accuracy level, and model performance information are set for each behavioral model. The model performance includes the estimated simulation speed and / or power consumption estimation error information of the corresponding behavioral model.

[0038] Then, step S4 is performed to determine whether the target chip currently being simulated meets the pre-set conversion condition. If no conversion is needed, step S5 is performed to maintain the behavior level model of the current precision. If the conversion condition is met, step S6 is performed to convert the behavior level model of the target chip currently being simulated to a behavior level model of a precision that matches the current condition.

[0039] Then, step S4 is performed to determine whether the target chip currently being simulated meets the pre-set conversion condition. If no conversion is needed, step S5 is performed to maintain the behavior level model of the current precision. If the conversion condition is met, step S6 is performed to convert the behavior level model of the target chip currently being simulated to a behavior level model of a precision that matches the current condition.

[0040] Specifically, the conversion can be determined based on the chip performance index, chip usage index, chip function verification index, chip power consumption and temperature index, and other aspects of the target chip currently being simulated. For example, the chip performance index of the target chip can be used to determine whether the type of the behavior level model of the target chip currently being simulated needs to be converted. If the interconnection bandwidth between the two target chips exceeds the pre-set bandwidth threshold, the behavior level model of the target chip is converted to a behavior level model of a higher precision. Preferably, the pre-set bandwidth threshold is 80%, so when the interconnection bandwidth between the two target chips exceeds 80%, the simulation system will need to issue a prompt message indicating that the two target chips will experience communication congestion and data transmission may be stalled. If the simulation models of the two target chips are both transaction level models, they need to be immediately converted to cycle approximation models or cycle accurate models, so that the clock cycle in which the congestion occurs and why the congestion occurs can be analyzed.

[0041] Preferably, since the module currently being simulated usually includes multiple chips, if only the communication bandwidth between two of the multiple chips exceeds the pre-set bandwidth threshold, the simulation models of only the two target chips need to be converted, while the simulation models of the other chips remain at the current precision. In this case, different chips use behavior level models of different precisions, which is referred to as mixed simulation. In this case, the chips with smooth communication are simulated using behavior level models of a lower precision to ensure the efficiency of the simulation, while the target chips with communication congestion are simulated using behavior level models of a higher precision to accurately analyze the cause of the problem and improve the accuracy of the simulation.

[0042] In addition, if the mutual access time between the two target chips exceeds a preset time threshold, the behavior level model of the target chip is converted into a higher-precision behavior level model. Therefore, a delay threshold of the mutual access time between the two chips needs to be set, which can be several clock cycles. If the mutual access time between the two chips exceeds the preset clock cycle, the behavior level model of the two chips needs to be converted into a higher-precision behavior level model, so as to analyze the specific cycle and the corresponding path that causes the delay.

[0043] In addition, if the cache hit rate of the target chip is less than a preset cache threshold, the behavior level model of the target chip is converted into a higher-precision behavior level model. For example, if the hit rate of the last level cache of a chip is less than 60%, it indicates that the cache hit rate of the chip is less than the preset cache threshold. At this time, the behavior level model of the target chip needs to be converted into a higher-precision behavior level model, so as to analyze whether there is a problem in the behavior or the coherence protocol.

[0044] When the chip usage index of the target chip is set, it can be judged whether the currently debugged target chip is a key debug chip. If it is a key debug chip, the behavior level model of the target chip needs to be converted into a cycle-accurate model. In addition, it is also judged whether the target chip is a verified mature chip. If it is, the behavior level model of the target chip is converted into a low-precision behavior level model, for example, the cycle-accurate model is converted into a transaction-level model. If the target chip is a chip that only needs to verify data flow information, the behavior level model of the target chip is converted into a low-precision behavior level model. If the target chip is a chip in the early stage of design, the behavior level model of the target chip is converted into a transaction-level model. If the target chip is a chip in the middle stage of design, the behavior level model of the target chip is converted into a cycle-approximate model, reflecting the approximate time concept. If the target chip is a chip in the late stage of verification, the behavior level model of the target chip is converted into a cycle-accurate model.

[0045] Through the above settings, the behavior level model conversion rules of the target chip under various different chip usage index conditions are applied, so that the automatic conversion of the behavior level model can be performed according to the actual chip usage index condition in the simulation process. In addition, the conversion of each behavior level model is not only converted into a higher-precision behavior level model, but also reduces the precision of the behavior level model according to the actual situation.

[0046] When judging whether the type of the current behavior level model of the target chip needs to be converted according to the chip function verification index of the target chip, two cases of triggering a specific function and a low-coverage area hit situation can be set. For the case of triggering a specific function, if the current simulation needs to verify an unverified function module of the target chip or needs to trigger a new state machine state, the simulation system will automatically convert the behavior level model of the target chip into a cycle-accurate model, that is, into a behavior level model with the highest precision, so as to be able to more accurately simulate the new function and new module.

[0047] For the low-coverage area hit situation, if the coverage area of a key boundary case is not hit for a long time during the simulation process, the behavior level model of the target chip will be converted into a cycle-accurate model at the corresponding time node in the test sequence, so that more accurate debugging information can be obtained when the boundary case is triggered.

[0048] Finally, the embodiment also judges whether the type of the current behavior level model of the target chip needs to be converted according to the chip power consumption and temperature index of the target chip. Specifically, a power consumption threshold and a temperature threshold can be set respectively to determine whether the behavior level model needs to be converted from two dimensions of power consumption and temperature. For example, for a preset rule of power consumption, if the power consumption of a certain module of the target chip exceeds the preset power consumption threshold, the behavior level model of the module and its adjacent modules will be converted into a behavior level model with higher precision, so as to analyze the power consumption of the target chip in detail. For the temperature management case, if the simulation system predicts that the temperature of a certain region will exceed the preset temperature threshold, the behavior level models of all chips in the region will be converted into behavior level models with higher precision, and a dynamic voltage and frequency scaling strategy is started to test whether it can effectively reduce the temperature of the region.

[0049] It can be seen that the simulation information is obtained in real time during the simulation running of the stacked chip, and the conditions for converting the behavior level model are preset. Once the target chip meets the conversion condition during the simulation process, the behavior level model of the target chip is automatically converted according to the preset rule. For example, in order to improve the simulation efficiency, a behavior level model with lower precision can be selected for simulation, but a behavior level model with higher precision is used for simulation for a chip that appears abnormal or may appear abnormal, or a chip that needs to be focused on or is in a key debugging stage.

[0050] Based on the above rules, during simulation, the system can run on a fast low-precision behavior level model most of the time, and only when potential problems occur, the precision of the behavior level model is automatically improved for deep analysis in a local and specific time period, so that the huge time cost caused by running a high-precision model from beginning to end can be avoided, and the best balance between simulation speed and depth is achieved. Moreover, the present application can also automatically capture occasional complex problems that are ignored in low-precision simulation, and through conversion into a high-precision model, in-depth analysis is carried out, and the effect of simulation is improved.

[0051] Finally, it should be emphasized that the above is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An automatic calibration method for behavioral-level models of stacked chips, characterized in that, include: A behavioral-level model library is constructed, which stores behavioral-level models of various accuracies. The accuracies of the various behavioral-level models, from high to low, include: periodic exact models, periodic approximate models, and transaction-level models. An identifier is established for each row-level model. The identifier for each row-level model includes the model identifier number, accuracy level, and model performance. Obtain the conversion index of the target chip in the current simulation, and determine whether it is necessary to convert the type of the current behavioral level model of the target chip based on the conversion index of the target chip. If conversion is required, convert the type of the current behavioral level model of the target chip to a behavioral level model with matching accuracy. The conversion metrics include one of the following: chip performance metrics, chip usage metrics, chip functional verification metrics, and chip power consumption and temperature metrics. The types of decisions made based on the target chip's chip performance metrics to determine whether the current behavioral-level model of the target chip needs to be converted include: If the interconnect bandwidth between two target chips exceeds a preset bandwidth threshold, the behavioral-level model of the target chip will be converted into a higher-precision behavioral-level model. If the mutual access time between two target chips exceeds a preset time threshold, the behavioral-level model of the target chip will be converted into a higher-precision behavioral-level model. If the cache hit rate of the target chip is less than the preset cache threshold, the behavioral model of the target chip will be converted into a higher-precision behavioral model.

2. The automatic calibration method for behavioral-level models of stacked chips according to claim 1, characterized in that: The types of decisions made based on the target chip's usage metrics to determine whether the current behavioral-level model of the target chip needs to be changed include: If the target chip is a key chip for debugging, then the behavioral-level model of the target chip is converted into a periodic accurate model; If the target chip is a proven and mature chip, then the behavioral-level model of the target chip is converted into a low-precision behavioral-level model; If the target chip is one that only needs to verify data flow information, then the behavioral-level model of the target chip is converted into a low-precision behavioral-level model. If the target chip is a chip in the early stage of design, then the behavioral-level model of the target chip is converted into a transaction-level model; If the target chip is a chip in the mid-stage of design, then the behavioral model of the target chip is converted into a periodic approximation model; If the target chip is a chip in the late verification stage, then the behavioral model of the target chip is converted into a periodic accurate model.

3. The automatic calibration method for behavioral-level models of stacked chips according to claim 1, characterized in that: The types of decisions made based on the chip function verification metrics of the target chip to determine whether the current behavioral-level model of the target chip needs to be converted include: If it is necessary to verify the unverified functional modules of the target chip, or to trigger a new state machine state, the behavioral-level model of the target chip is converted into a periodic precise model. If the coverage area of ​​the critical boundary case is not hit for a long time during the simulation, the behavioral model of the target chip will be converted into a periodic accurate model at the corresponding time node in the test sequence.

4. The automatic calibration method for behavioral-level models of stacked chips according to claim 1, characterized in that: Determining whether to change the current behavioral model of the target chip based on its power consumption and temperature parameters includes: If the power consumption of a certain module of the target chip exceeds a preset power consumption threshold, the behavioral-level model of that module and its adjacent modules will be converted into a higher-precision behavioral-level model. If the simulation system predicts that the temperature in a certain area will exceed the preset temperature threshold, then the behavioral-level model of all chips in that area will be converted into a higher-precision behavioral-level model.

5. The automatic calibration method for behavioral-level models of stacked chips according to any one of claims 1 to 4, characterized in that: The simulation system simulates multiple modules containing multiple chips. If it is determined that the type of behavioral model of the target chip needs to be converted, only the behavioral model of the target chip is converted to a behavioral model with matching accuracy.

6. The automatic calibration method for behavioral-level models of stacked chips according to any one of claims 1 to 4, characterized in that: The model performance includes the model's estimated simulation speed and / or power consumption estimation error information.

7. An automatic calibration system for behavioral-level models of stacked chips, characterized in that, include: The behavioral-level model library module is used to build a behavioral-level model library. The behavioral-level model library stores behavioral-level models of various accuracies. The accuracies of the various behavioral-level models, from high to low, include: periodic exact models, periodic approximate models, and transaction-level models. The model identifier library module is used to establish an identifier for each row-level model. The identifier for each row-level model includes the model identifier number, accuracy level, and model performance of the row-level model with that accuracy. The intelligent detection module is used to obtain the conversion index of the target chip in the current simulation, and determine whether it is necessary to convert the type of the current behavioral level model of the target chip based on the conversion index of the target chip. If conversion is required, the intelligent calibration module converts the type of the current behavioral level model of the target chip to a behavioral level model with matching accuracy. The conversion metrics include one of the following: chip performance metrics, chip usage metrics, chip functional verification metrics, and chip power consumption and temperature metrics. When the intelligent detection module determines whether it is necessary to change the type of the current behavioral-level model of the target chip based on the chip performance indicators of the target chip: If the interconnect bandwidth between two target chips exceeds a preset bandwidth threshold, the behavioral-level model of the target chip will be converted into a higher-precision behavioral-level model. If the mutual access time between two target chips exceeds a preset time threshold, the behavioral-level model of the target chip will be converted into a higher-precision behavioral-level model. If the cache hit rate of the target chip is less than the preset cache threshold, the behavioral model of the target chip will be converted into a higher-precision behavioral model.

8. The automatic calibration system for behavioral-level models of stacked chips according to claim 7, characterized in that: The behavioral model library stores behavioral models of computational cores, storage cores, and interconnect intermediary layers.

Images