Wafer defect detection methods, systems and electronic equipment

Abstract

This invention provides a wafer defect detection method, system, and electronic device, relating to the field of machine vision technology. The method fully utilizes the transformation relationship between the imaging unit and the stage to accurately stitch together strip images during wafer defect detection, thereby obtaining high-precision wafer images and improving wafer detection accuracy. Simultaneously, an improved VAE model can be used to accurately obtain the defect area of ​​the wafer under inspection based on brightness, contrast, and structural differences, enabling high-precision identification of minute defects, thus solving the problem of poor detection performance of minute defects in existing technologies.

Description

Technical Field

[0001] This invention relates to the field of machine vision technology, and in particular to a wafer defect detection method, system, and electronic device. Background Technology

[0002] Semiconductor wafers are the substrate components for manufacturing integrated circuits, and even minute defects on their surface (such as scratches, particles, and residues) directly affect chip yield. Therefore, wafer defect detection is a crucial part of semiconductor manufacturing. Traditional detection methods mainly rely on manual sampling under an optical microscope, which is inefficient, subjective, and prone to missing defects.

[0003] Existing automated optical inspection systems have many limitations:

[0004] (1) Most systems rely on supervised deep learning models, which require a large amount of labeled defect data for training. However, there are many types of defects in semiconductor processes, and they are rare. The cost of obtaining labeled data is extremely high.

[0005] (2) Due to the strong specular reflection characteristics and complex patterns on the wafer surface, traditional image processing algorithms have a high false alarm rate;

[0006] (3) In order to cover the entire wafer, it is necessary to acquire and stitch multiple field images. The existing system is not accurate and efficient in terms of autofocus, motion control, image registration and stitching deduplication, which can easily lead to image blurring, misalignment or repeated calculation, affecting the final detection accuracy. Summary of the Invention

[0007] To address the aforementioned issues, existing technologies employ variational autoencoders (VAEs) and rely on reconstruction errors to identify wafer defects. However, the reconstruction results are often overly smooth, resulting in poor detection of minute wafer defects. Therefore, the present invention aims to provide a wafer defect detection method, system, and electronic device. This method fully utilizes the transformation relationship between the imaging unit and the stage to precisely stitch together strip images during wafer defect detection, thereby obtaining high-precision wafer images and improving wafer detection accuracy. Simultaneously, an improved VAE model can be used to accurately obtain the defect region of the wafer under inspection based on brightness, contrast, and structural differences, enabling high-precision identification of minute defects, thus solving the problem of poor detection of minute defects in existing technologies.

[0008] In a first aspect, embodiments of the present invention provide a wafer defect detection method, the method comprising:

[0009] Initialization steps: Obtain the imaging unit and stage corresponding to the wafer to be inspected, and initialize the focusing control module corresponding to the imaging unit based on the image grayscale value of the wafer to be inspected;

[0010] Focusing control steps: Control the wafer to be inspected in the stage to move according to the preset scanning command, and control the imaging unit in real time to acquire the strip image corresponding to the wafer to be inspected according to the preset acquisition frequency through the focusing control module;

[0011] Image processing steps: Determine the transformation relationship between the imaging unit and the stage based on the camera calibration parameters corresponding to the imaging unit and the reference point parameters corresponding to the stage, and obtain the wafer image corresponding to the wafer to be inspected by stitching the strip images based on the transformation relationship.

[0012] Defect analysis steps: Determine the reconstructed image corresponding to the wafer image based on the trained VAE model; obtain the difference region between the reconstructed image and the wafer image based on the brightness, contrast and structural feature values ​​of the reconstructed image, and determine the defect region corresponding to the wafer to be detected through the difference region.

[0013] Optional initialization steps include:

[0014] Acquire the linear scan camera, vacuum chuck, and three-axis motion platform corresponding to the wafer under inspection during the defect inspection process;

[0015] The imaging unit is determined based on a linear scan camera, and the stage is determined based on a vacuum chuck and a three-axis motion platform.

[0016] Determine the digital image of the wafer to be inspected in the imaging unit, obtain the image gray value corresponding to the digital image, and calculate the image gradient value corresponding to the digital image using the Sobel operator;

[0017] The focus evaluation value corresponding to the imaging unit is determined based on the image grayscale value and the image gradient value, and the focus control module is initialized based on the focus evaluation value.

[0018] Optionally, the step of determining the focus evaluation value corresponding to the imaging unit based on the image grayscale value and the image gradient value includes:

[0019] Calculate the focus evaluation value using the following formula. :

[0020] ;

[0021] ;

[0022] ;

[0023] in, and These are the image gradient values ​​in the X and Y directions obtained by convolution using the Sobel operator, respectively. The image grayscale value; and These are the pixel values ​​corresponding to the X and Y directions of the digital image, respectively. This is a mask function based on the local variance of a digital image; This is the gain coefficient; It is a point The variance of the local window centered on the target; This represents the total number of pixels within the local window. This represents the average grayscale value of the pixels within the local window. For pixels within a local window The corresponding pixel value.

[0024] Optional focus control steps include:

[0025] After detecting that the wafer to be inspected is attracted by the vacuum chuck, the three-axis motion platform is controlled to drive the vacuum chuck to move up and down in the vertical direction according to the preset scanning instructions, and the focus evaluation value is acquired in real time.

[0026] The Hill-climbing algorithm is used to obtain the position coordinates of the three-axis motion platform when the focus evaluation value reaches its maximum value, and the position coordinates are determined as the initial focus position.

[0027] Based on the initial focus position control, the focus control module performs real-time focusing on the wafer to be inspected and acquires the corresponding strip image of the wafer to be inspected according to the preset acquisition frequency.

[0028] Optional image processing steps include:

[0029] The camera calibration parameters are determined based on the focal length parameters of the line scan camera, the rotation matrix corresponding to the camera coordinate system and the world coordinate system, and the translation vector. The first transformation relationship between the camera coordinate system and the world coordinate system is then determined using the camera calibration parameters.

[0030] Determine the preset reference mark point in the vacuum suction cup, determine the reference point parameters based on the coordinate values ​​of the reference mark point in the suction cup coordinate system of the vacuum suction cup, and use the reference point parameters to determine the second transformation relationship between the suction cup coordinate system and the world coordinate system;

[0031] The first and second transformation relationships are used to map the pixels in the strip image to the world coordinate system, and the coordinates of the pixels in the world coordinate system are obtained.

[0032] Acquire adjacent strip images corresponding to adjacent acquisition frequencies, determine the corresponding SIFT feature points between adjacent strip images based on coordinate points, and use SIFT feature points to determine the overlapping region corresponding to adjacent strip images.

[0033] After sequentially stitching adjacent strip images based on overlapping regions, the wafer image corresponding to the wafer to be detected is obtained.

[0034] Optionally, the step of sequentially stitching adjacent strip images based on overlapping regions to obtain the wafer image corresponding to the wafer to be inspected includes:

[0035] Obtain the first and second strip images from adjacent strip images; wherein the right side of the first strip image and the left side of the second strip image overlap to form an overlapping region;

[0036] Based on the distances of the target pixels in the overlapping region to the left and right boundaries of the overlapping region, a first weight value and a second weight value are determined for the overlapping region; wherein, the first weight value... Second weight value ; The first distance between the target pixel and the left boundary. This is the second distance between the target pixel and the right boundary;

[0037] The target pixel is updated using the first and second weight values, and the updated target pixel is then used to sequentially stitch together adjacent strip images to obtain the wafer image. The target pixel update process is implemented using the following formula:

[0038] ;

[0039] in, For the updated target pixel; This refers to the first pixel in the first strip image; This refers to the second pixel point in the second strip image.

[0040] Optional defect analysis steps include:

[0041] Obtain the trained VAE model; the loss function used during VAE model training is: ;in, ; To reconstruct the loss function, Input image; To reconstruct the image; The similarity results between the input image and the reconstructed image in terms of brightness, contrast, and structural features; This is the sum of the absolute pixel errors between the input image and the reconstructed image; As a balance factor; This represents the KL divergence value corresponding to the VAE model; These are the decoupling weight values;

[0042] The wafer image is divided into multiple sub-region original images according to the segmentation parameters corresponding to the VAE model, and the sub-region original images are input into the VAE model. The sub-region reconstructed images corresponding to the sub-region original images are obtained through the VAE model.

[0043] Calculate the sum of squared pixel differences between the original image and the reconstructed image of the sub-region, and determine the difference region based on the original image of the sub-region where the sum of squared pixel differences is greater than a preset threshold;

[0044] The defect region corresponding to the wafer to be inspected is determined based on the difference region.

[0045] Optionally, the VAE model training process includes:

[0046] The attention module is used to obtain the global average pooling result, global max pooling result, and local peak pooling result of the VAE model in real time.

[0047] After concatenating the global average pooling result, global max pooling result, and local peak pooling result using the Sigmoid activation function, the channel weight values ​​corresponding to the VAE model are obtained.

[0048] The first feature value output by the attention module is obtained based on the channel weight value, and the scale feature results corresponding to the first feature value are extracted by multiple convolution kernels of different scales respectively.

[0049] The spatial weight values ​​of the VAE model are obtained by weighted fusion calculation of the scale feature results using the Sigmoid activation function.

[0050] The second feature value output by the attention module is obtained using the spatial weight value. The second feature value is updated by multiplying the pixels whose response intensity is less than the preset noise threshold with the preset attenuation coefficient.

[0051] In a second aspect, the present invention provides a wafer defect detection system, the system comprising:

[0052] Initialization module: used to acquire the imaging unit and stage corresponding to the wafer to be inspected, and initialize the focus control module corresponding to the imaging unit based on the image grayscale value of the wafer to be inspected;

[0053] The focusing control module is used to control the movement of the wafer to be inspected in the stage according to the preset scanning instructions, and to control the imaging unit in real time to acquire the strip image corresponding to the wafer to be inspected according to the preset acquisition frequency.

[0054] Image processing module: used to determine the transformation relationship between the imaging unit and the stage based on the camera calibration parameters corresponding to the imaging unit and the reference point parameters corresponding to the stage, and to obtain the wafer image corresponding to the wafer to be inspected by stitching the strip images based on the transformation relationship.

[0055] Defect Analysis Module: Used to determine the reconstructed image corresponding to the wafer image based on the trained VAE model; to obtain the difference region between the reconstructed image and the wafer image based on the brightness, contrast and structural feature values ​​of the reconstructed image, and to determine the defect region corresponding to the wafer to be detected through the difference region.

[0056] Thirdly, embodiments of the present invention also provide an electronic device, which includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, and the processor executing the computer-executable instructions to implement the wafer defect detection method provided in the first aspect.

[0057] This invention provides a wafer defect detection method, system, and electronic device. During the defect detection process of a wafer to be inspected, the method first acquires the imaging unit and stage corresponding to the wafer, and initializes the focusing control module corresponding to the imaging unit based on the image grayscale value of the wafer. Then, it controls the wafer in the stage to move according to a preset scanning command, and uses the focusing control module to control the imaging unit in real time to acquire strip images corresponding to the wafer at a preset acquisition frequency. Subsequently, it determines the transformation relationship between the imaging unit and the stage based on the camera calibration parameters of the imaging unit and the reference point parameters of the stage, and stitches the strip images based on the transformation relationship to obtain the wafer image corresponding to the wafer. Finally, it determines the reconstructed image corresponding to the wafer image based on a trained VAE model; it obtains the difference region between the reconstructed image and the wafer image based on the brightness, contrast, and structural feature values ​​of the reconstructed image, and determines the defect region corresponding to the wafer through the difference region. This method fully utilizes the transformation relationship between the imaging unit and the stage to accurately stitch together strip images during wafer defect detection, thereby obtaining high-precision wafer images and improving wafer detection accuracy. At the same time, an improved VAE model can be used to accurately obtain the defect area of ​​the wafer to be detected from brightness, contrast and structural differences, enabling high-precision identification of minute defects, thus solving the problem of poor detection effect of minute defects in the existing technology.

[0058] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0059] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0060] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0061] Figure 1 A flowchart of a wafer defect detection method provided in an embodiment of the present invention;

[0062] Figure 2 A flowchart of the initialization step S101 of a wafer defect detection method provided in an embodiment of the present invention;

[0063] Figure 3 This is a flowchart of the focusing control step S102 of a wafer defect detection method provided in an embodiment of the present invention;

[0064] Figure 4 A flowchart of image processing step S103 of a wafer defect detection method provided in an embodiment of the present invention;

[0065] Figure 5 A flowchart of step S405 of a wafer defect detection method provided in an embodiment of the present invention;

[0066] Figure 6 A flowchart of defect analysis step S104 of a wafer defect detection method provided in this embodiment of the invention;

[0067] Figure 7 This is a flowchart illustrating the training process of a VAE model in a wafer defect detection method provided by an embodiment of the present invention.

[0068] Figure 8 This is a network architecture diagram of a VAE model in a wafer defect detection method provided in an embodiment of the present invention;

[0069] Figure 9 This is a schematic diagram illustrating the training of the attention module during VAE model training in a wafer defect detection method provided in an embodiment of the present invention.

[0070] Figure 10 This is a schematic diagram of the structure of a wafer defect detection system provided in an embodiment of the present invention;

[0071] Figure 11This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0072] icon:

[0073] 1010 - Initialization module; 1020 - Focus control module; 1030 - Image processing module; 1040 - Defect analysis module;

[0074] 101 - Processor; 102 - Memory; 103 - Bus; 104 - Communication interface. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0076] To facilitate understanding of this embodiment, a wafer defect detection method disclosed in this invention will first be described in detail. For example... Figure 1 As shown, the method includes:

[0077] Initialization step S101: Obtain the imaging unit and stage corresponding to the wafer to be inspected, and initialize the focusing control module corresponding to the imaging unit based on the image grayscale value of the wafer to be inspected.

[0078] The core of this step is to complete the equipment preparation and initial parameter calibration before detection, laying the foundation for the clarity and accuracy of subsequent image acquisition. Specific operations include:

[0079] Equipment and object matching: First, acquire the wafer to be inspected and configure the corresponding imaging unit (usually a high-resolution line scan camera, which needs to meet the resolution requirements of tiny defects in the wafer) and precision stage (with micron-level motion accuracy to support stable wafer movement).

[0080] Focus control module initialization: Based on the initial image grayscale value of the wafer to be inspected, the parameters of the focusing control module of the imaging unit are initialized. Since the uniformity of image grayscale distribution and the richness of detail directly reflect sharpness (e.g., the grayscale levels of circuit patterns on a normal wafer surface are distinct, while the grayscale transition is smooth when blurred), initialization based on grayscale values ​​can quickly determine the initial focus position, avoiding subsequent acquisitions from starting in a severely out-of-focus state and reducing the generation of invalid images.

[0081] Focusing control step S102: Control the wafer to be inspected in the stage to move according to the preset scanning command, and control the imaging unit in real time through the focusing control module to acquire the strip image corresponding to the wafer to be inspected according to the preset acquisition frequency.

[0082] This step ensures full wafer coverage and clear images through coordinated control of stage movement, synchronous acquisition by the imaging unit, and real-time focusing. Specific operations include:

[0083] The stage moves in an orderly manner: according to the preset scanning instructions (usually a regular path, such as horizontal row by row or vertical column by column), the stage is controlled to move the wafer to be inspected. The instruction design must ensure that the motion trajectory does not overlap or omission, and completely covers the effective inspection area of ​​the wafer (avoiding non-circuit areas at the edge of the wafer).

[0084] Image synchronous acquisition and real-time focusing: The imaging unit acquires strip images according to a preset acquisition frequency (a strip refers to a local area of ​​the wafer covered by a single acquisition, which needs to be matched with the movement speed of the stage; too fast a speed can easily cause image ghosting, while too slow a speed will reduce detection efficiency). At the same time, the focusing control module monitors the clarity of the acquired images in real time (e.g., by judging through grayscale gradient values) and dynamically adjusts the focal length or position of the imaging unit to ensure that each strip image maintains high clarity during the movement of the stage, avoiding image blurring caused by movement offset.

[0085] Image processing step S103: Determine the transformation relationship between the imaging unit and the stage based on the camera calibration parameters corresponding to the imaging unit and the reference point parameters corresponding to the stage, and obtain the wafer image corresponding to the wafer to be detected by stitching the strip images based on the transformation relationship.

[0086] This step addresses the pain point of misalignment during multi-view image stitching by establishing spatial correlation through parameter calibration to generate a complete and precisely positioned wafer image. Specific operations include:

[0087] Determine the transformation relationship between the imaging unit and the stage: First, call the camera calibration parameters of the imaging unit (including intrinsic parameters: such as focal length, pixel size, distortion coefficient; extrinsic parameters: such as camera mounting position, attitude angle), and the reference point parameters of the stage (preset fixed reference points on the stage, used to locate the stage motion coordinates); based on these two types of parameters, establish the correspondence between the pixel coordinates of the strip image and the physical motion coordinates of the stage (i.e., the transformation relationship), and clarify the accurate position of each strip image in the overall wafer coordinate system;

[0088] Strip image stitching and deduplication: Based on the above transformation relationship, all acquired strip images are spatially aligned; for overlapping areas of adjacent strips, duplicate parts are removed by judging pixel grayscale consistency to avoid redundant calculations; for edge areas, coordinate calibration is used to ensure no misalignment, and finally, a high-precision wafer image covering the entire wafer, with complete circuit patterns and no positional deviation is formed, which solves the problems of blurry stitching and misalignment in existing systems.

[0089] Defect analysis step S104: Determine the reconstructed image corresponding to the wafer image based on the trained VAE model; obtain the difference region between the reconstructed image and the wafer image according to the brightness, contrast and structural feature values ​​corresponding to the reconstructed image, and determine the defect region corresponding to the wafer to be detected through the difference region.

[0090] This step focuses on the challenge of detecting subtle defects. Through VAE model reconstruction and comparison, and multi-feature analysis, it accurately locates the defect area. Specific operations include:

[0091] Reconstructing the wafer image: The stitched complete wafer image is input into the trained improved VAE (Variational Autoencoder) model. Through prior training on a large number of normal wafer images, the VAE model has learned the brightness distribution, contrast patterns, and circuit structure characteristics of the normal wafer surface. Therefore, it can output a reconstructed image that highly matches the characteristics of a normal wafer (i.e., if the input image is defect-free, the reconstructed image will be almost identical to the original image).

[0092] Multi-dimensional comparison to locate defect areas: Calculate and compare the differences between the original wafer image and the reconstructed image in three core dimensions: brightness difference, such as residue (e.g., photoresist residue) causing abnormal brightness in local areas, creating a difference from the normal brightness of the reconstructed image; contrast difference, such as fine scratches disrupting the grayscale transition in local areas, resulting in a higher contrast between the scratched area and the surrounding area than the normal range; structural feature value difference, such as circuit pattern defects disrupting the normal structural regularity, which can be captured by indicators such as structural similarity (SSIM).

[0093] Finally, the differences in the three dimensions mentioned above are superimposed and verified to eliminate misjudgments caused by noise and accurately determine the defect areas of the wafer to be inspected. It has high recognition accuracy, especially for minute defects (such as micron-level scratches and tiny residues) that are easily missed by traditional methods.

[0094] Optionally, initialization step S101, such as Figure 2 As shown, it includes:

[0095] Step S201: Obtain the linear scan camera, vacuum chuck, and three-axis motion platform corresponding to the wafer under inspection during the defect inspection process.

[0096] The core of this step is to select and match hardware suitable for the wafer inspection scenario, ensuring that the equipment performance meets the requirements for high-precision, non-destructive, and full-coverage inspection. Specific operation and extended instructions are as follows:

[0097] Line scan cameras differ from area scan cameras. Line scan cameras achieve continuous imaging through a single row of pixels plus object movement, and have the characteristics of high resolution and high frame rate. They can quickly capture micron-level circuit patterns and minute defects on the surface of wafers, avoiding the problems of limited single imaging range and too many stitching times of area scan cameras.

[0098] Vacuum chucks are used to fix wafers to be tested without damage. Wafers are brittle and thin (such as silicon-based wafers, which are often hundreds of micrometers thick). Mechanical clamping can easily cause edge damage. Vacuum chucks can achieve stable fixation without contacting the effective circuit area of ​​the wafer by using negative pressure adsorption.

[0099] The three-axis motion platform has micron-level (or even nanometer-level) motion accuracy in the X, Y, and Z directions. The X and Y axes are responsible for driving the wafer to scan along a preset path, while the Z axis can assist in fine-tuning the wafer height to adapt to subsequent focusing requirements, ensuring that the wafer position is stable and without deviation during the motion.

[0100] Step S202: Determine the imaging unit based on the line scan camera, and determine the stage based on the vacuum chuck and the three-axis motion platform.

[0101] This step categorizes hardware functions, clarifies the core modules of the image acquisition end and the wafer carrier motion end in the detection system, and establishes the correspondence between devices. Specifically, the linear scan camera obtained in step S201 is directly defined as the imaging unit, and the combination of the vacuum chuck and the three-axis motion platform is defined as the stage.

[0102] The imaging unit (line scan camera), as the core of visual perception, is only responsible for image acquisition and must be strictly synchronized with the movement rhythm of the stage (such as matching the X-axis movement speed of the stage with the camera frame rate to avoid image stretching or blurring).

[0103] The stage (vacuum chuck + three-axis platform) serves as the core for wafer support and movement. The vacuum chuck solves the fixation problem, while the three-axis platform solves the movement problem. The combination of the two achieves stable wafer fixation and precise, controllable movement, providing the imaging unit with continuous and complete imaging targets.

[0104] Step S203: Determine the digital image corresponding to the wafer to be inspected in the imaging unit, obtain the image grayscale value corresponding to the digital image, and calculate the image gradient value corresponding to the digital image using the Sobel operator.

[0105] This step quantifies the sharpness characteristics of the wafer image through image acquisition and algorithm calculation, providing data for subsequent focusing parameter calibration. Specifically, firstly, the wafer to be inspected is photographed using an imaging unit (linear scan camera) to obtain the corresponding digital image; then, the image grayscale value of the digital image is extracted, and its image gradient value is calculated using the Sobel operator.

[0106] Image grayscale values ​​reflect the brightness of each pixel in a digital image (the value range is usually 0-255, where 0 is pure black and 255 is pure white). The circuit patterns on a normal wafer surface will show a regular grayscale distribution with alternating brightness and darkness (such as metal wiring being a bright area and silicon substrate being a dark area). The difference in grayscale value distribution is the basis for judging whether an image is blurry.

[0107] The Sobel operator is a classic edge detection algorithm that highlights edge details in an image (such as the edges of circuit lines or the outlines of defects) by calculating the rate of change of pixel grayscale values ​​(i.e., gradients) in the horizontal (X-direction) and vertical (Y-direction) directions. A higher gradient value indicates sharper image edges (e.g., sharp circuit lines have high gradient values, while blurry image edges have low gradient values). Introducing gradient values ​​can compensate for the inadequacy of judging sharpness solely based on grayscale values ​​(e.g., in an image with uniform grayscale but no detail, grayscale values ​​cannot distinguish whether it is sharp, while gradient values ​​will be significantly low).

[0108] Step S204: Determine the focus evaluation value corresponding to the imaging unit based on the image grayscale value and image gradient value, and initialize the focus control module based on the focus evaluation value.

[0109] This step determines the focusing benchmark through multi-index fusion, completes the parameter calibration of the focusing module, and lays the foundation for subsequent real-time focusing. Combining the image grayscale values ​​and image gradient values ​​obtained in step S203, the focusing evaluation value corresponding to the imaging unit is calculated; based on this focusing evaluation value, the core parameters of the focusing control module (such as initial focal length and focusing adjustment step size) are initialized.

[0110] The focus rating is a comprehensive sharpness score, which is usually calculated by weighting the uniformity of gray value distribution (such as gray standard deviation, a large standard deviation indicates obvious differences in brightness and rich details) and the overall strength of gradient values ​​(such as the sum or average of gradient values, a high value indicates sharp edges). The higher the rating, the better the focus status of the current imaging unit.

[0111] If the focus control module is adjusted from zero, it is easy to over-adjust or adjust in the wrong direction. By initializing based on the focus evaluation value, the module parameters can be set directly to an initial state close to the optimal focus (such as the evaluation value reaching more than 80% of the optimal value). Subsequent real-time focusing only requires fine-tuning, which greatly improves focusing efficiency and avoids invalid image acquisition caused by initial defocus.

[0112] Optionally, the focus evaluation value corresponding to the imaging unit is determined based on the image grayscale value and the image gradient value. It can be calculated using the following formula:

[0113] ;

[0114] ;

[0115] ;

[0116] in, and These are the image gradient values ​​in the X and Y directions obtained by convolution using the Sobel operator, respectively. The image grayscale value; and These are the pixel values ​​corresponding to the X and Y directions of the digital image, respectively. This is a mask function based on the local variance of a digital image; This is the gain coefficient; It is a point The variance of the local window centered on the target; This represents the total number of pixels within the local window. This represents the average grayscale value of the pixels within the local window. For pixels within a local window The corresponding pixel value.

[0117] The above formula introduces a mask function based on local variance, in addition to the traditional gradient sum of squares. This technique aims to enhance the gradient contribution of textured and detailed areas while suppressing noise interference in flat regions, thereby finding the optimal focal plane more accurately. Masking function As a masking function based on the local variance of an image, it consists of two parts with clearly defined functions:

[0118] Basic Item 1: Ensure that all pixels contribute to the basic gradient, even in solid color areas with zero variance, to guarantee the integrity of the evaluation;

[0119] Incremental Term Extra weights are assigned to regions with rich detail (high variance) to amplify their gradient contribution and focus on what is needed for evaluation. Focusing on sharp images, the gradients in detailed regions are larger, and then... Further enhancement can make the difference in S-values ​​between "clear" and "fuzzy" more significant, thus avoiding misjudgment.

[0120] The essence of image focus evaluation is that when the image is in focus, the grayscale changes of the edges / textures are drastic (large gradient) and the local variance is high (rich details); when the image is out of focus and blurry, the grayscale transition of the edges is gradual (small gradient) and the local variance is low (loss of details).

[0121] Optionally, focus control step S102, such as Figure 3 As shown, it includes:

[0122] Step S301: After detecting that the wafer to be inspected is adsorbed by the vacuum chuck, the three-axis motion platform is controlled to drive the vacuum chuck to move up and down in the vertical direction according to the preset scanning command, and the focus evaluation value is acquired in real time.

[0123] The core of this step is to first ensure the wafer is stably fixed before initiating focusing-related movements and data acquisition, avoiding equipment malfunctions or invalid data due to unstable adsorption. First, it checks whether the wafer to be tested is stably adsorbed by the vacuum chuck; after confirming adsorption, it controls the Z-axis (vertical direction) of the three-axis motion platform to drive the vacuum chuck to move up and down according to the preset scanning instructions, while simultaneously calculating and obtaining the focus evaluation value under the current state in real time.

[0124] Step S302: Use the Hill-climbing algorithm to obtain the position coordinates of the three-axis motion platform when the focus evaluation value reaches its maximum value, and determine the position coordinates as the initial focus position.

[0125] This step is designed to quickly find the optimal focus point in the Z-axis direction. It uses a classic optimization algorithm to accurately locate the focus point, avoiding the inefficiency of manual judgment or blind search. Specifically, the focus evaluation value-Z-axis position data collected in real time in step S301 is input into the Hill-climbing algorithm. Through iterative calculation, the algorithm finds the Z-axis position coordinates corresponding to the maximum value of the focus evaluation value, and defines this coordinate as the initial focus position.

[0126] The Hill-climbing algorithm is a greedy optimization algorithm whose core logic is to move in the direction that increases the evaluation value until it can no longer be improved (i.e., it reaches the maximum value). During the focusing process, the focus evaluation value changes with the Z-axis position in a unimodal curve (the evaluation value is low when the Z-axis distance is too close or too far, and the evaluation value is highest at a certain position in the middle, corresponding to the clearest state), which perfectly matches the unimodal optimization scenario of the algorithm, and can quickly locate the optimal solution without complex calculations.

[0127] The maximum value of the focus evaluation value directly corresponds to the optimal distance between the imaging unit and the wafer. At this point, the acquired image has the richest details (such as sharp edges of circuit lines and distinguishable minor defects). Setting this position as the initial focus position allows subsequent real-time focusing to start from the optimal reference, reducing the adjustment range and time.

[0128] Step S303: Based on the initial focus position, the focus control module performs real-time focusing processing on the wafer to be inspected and acquires the strip image corresponding to the wafer to be inspected according to the preset acquisition frequency.

[0129] This step achieves coordinated horizontal scanning, real-time focusing, and image acquisition, ensuring that each strip image maintains high clarity during the full-area wafer scanning process. Specifically, based on the initial focusing position determined in step S302, the focusing control module monitors the clarity of the acquired images in real time (continuously calculating the focus evaluation value) and dynamically fine-tunes the Z-axis position (if there are tiny bumps on the wafer surface, the evaluation value decreases, and the module immediately drives the Z-axis to move slightly upward to restore the evaluation value to a high level); simultaneously, the X / Y axes of the three-axis motion platform move according to a preset scanning path (such as horizontally row by row), and the imaging unit synchronously acquires the strip images corresponding to the wafer to be inspected at a preset acquisition frequency.

[0130] In practical scenarios, a precision stage can be used, including a vacuum chuck for holding and fixing the wafer and a three-axis motion platform that drives the vacuum chuck to move in the X, Y, and Z axes. The vacuum chuck is used to firmly hold the wafer and prevent displacement during high-speed movement. The three-axis motion platform is driven by a high-precision servo motor. The X and Y axes are responsible for the planar scanning motion of the wafer, driving the wafer to move along a preset path. It works in conjunction with a line scan camera to complete strip image acquisition. An S-shaped acceleration and deceleration curve is used to avoid impact loads during start-up or stopping. The motion controller achieves precise synchronization between the X and Y axis movement speed and the camera's line frequency, ensuring that the acquired strip images are free from stretching or compression deformation. It provides a spatial position reference for image stitching. The repeatability accuracy of the X and Y axes directly determines the alignment accuracy of multi-frame strip images in the world coordinate system. If the positioning deviation is large, it will cause misalignment in the stitched image, thus affecting defect location. The Z axis works with the Autofocus module to adjust the distance between the wafer and the camera lens in real time according to the focus evaluation value, ensuring that the acquired image is always in the best focus state and completing the focus adjustment. Real-time focusing capability along the Z-axis is crucial for ensuring low false negatives and low false negatives in defect detection. If the Z-axis is not focused accurately, the image will be out of focus and blurry, leading to a weakening of the Sobel gradient and misjudgment of VAE model reconstruction errors.

[0131] The specific steps are as follows:

[0132] Initial focusing: When the system starts, the Z-axis moves up and down in preset steps, acquiring an image and calculating the focus evaluation value S after each step;

[0133] Finding the peak: The Z-axis position with the largest S value is found using a hill-climbing algorithm and used as the initial focus position;

[0134] Real-time focus tracking: During the scanning process, if there is a local thickness deviation in the wafer, the focus control module will calculate the S value of each frame in real time; if S decreases, it will trigger a slight adjustment of the Z axis to ensure that S is always kept near the peak value.

[0135] Optionally, image processing step S103, such as Figure 4 As shown, it includes:

[0136] Step S401: Determine the camera calibration parameters based on the focal length parameters of the line scan camera, the rotation matrix corresponding to the camera coordinate system and the world coordinate system, and the translation vector, and use the camera calibration parameters to determine the first transformation relationship between the camera coordinate system and the world coordinate system.

[0137] This step obtains the correlation parameters between image pixels and physical space through camera calibration, providing a basis for the spatial positioning of subsequent pixels and serving as the first step in establishing the coordinate reference for stitching. Specifically, the core parameters of the line scan camera are first extracted, including: focal length parameters (intrinsic parameters, reflecting the imaging capability of the camera's optical system, such as focal length f determining the conversion relationship between pixels and physical size), rotation matrix R, and translation vector t (extrinsic parameters, describing the attitude and position of the camera coordinate system relative to the world coordinate system, which is usually set as the fixed reference coordinate system of the stage, with units in the micrometer range). These three types of parameters are integrated into camera calibration parameters, and based on these parameters, the first transformation relationship between the camera coordinate system and the world coordinate system is established (the mathematical expression is usually: world coordinates = R × camera coordinates + t).

[0138] Step S402: Determine the preset reference mark point in the vacuum suction cup, determine the reference point parameters according to the coordinate values ​​of the reference mark point in the suction cup coordinate system of the vacuum suction cup, and use the reference point parameters to determine the second transformation relationship between the suction cup coordinate system and the world coordinate system.

[0139] This step establishes a coordinate link between the vacuum chuck and the world coordinate system by using a preset reference point, thus forming a coordinate link between the wafer carrier and the physical space. This link, along with the camera-physical space link in step S401, forms a closed loop. Specifically, at least three reference markers (usually high-precision etched circular / cross-shaped marks with fixed and known positions) are first preset on the surface of the vacuum chuck. The precise coordinates of these reference markers in the chuck coordinate system (with the chuck center or a fixed point as the origin, and the X / Y axes aligned with the stage movement direction) are measured. The correspondence between these markers and the chuck coordinates is defined as the reference point parameters. Based on the reference point parameters, a second transformation relationship between the chuck coordinate system and the world coordinate system is calculated using coordinate fitting (e.g., least squares method). This transformation relationship also includes rotation matrices and translation vectors, ensuring that every position of the chuck is mapped to the world coordinate system.

[0140] Step S403: Map the pixels in the strip image to the world coordinate system using the first transformation relationship and the second transformation relationship, and obtain the coordinates of the pixels in the world coordinate system.

[0141] This step is the application of the first two steps. By integrating two transformation relationships, the discrete strip image pixels are transformed into physical coordinates in the world coordinate system, providing a quantitative basis for the alignment of adjacent strips. Specifically, for any pixel in each strip image, the first transformation relationship in step S401 is used to map it from the camera coordinate system (derived from pixel coordinates combined with camera intrinsic parameters) to the initial coordinates in the world coordinate system. Then, combined with the second transformation relationship in step S402 (to compensate for the offset between the suction cup and the world coordinate system), the initial coordinates are fine-tuned, finally obtaining the unique physical coordinates of the pixel in the world coordinate system.

[0142] Step S404: Obtain adjacent strip images corresponding to adjacent acquisition frequencies, determine the corresponding SIFT feature points between adjacent strip images based on coordinate points, and use SIFT feature points to determine the overlapping areas corresponding to adjacent strip images.

[0143] This step addresses how to determine the overlap range of adjacent strips. It uses an anti-interference feature matching algorithm (SIFT) to accurately identify overlapping areas, providing a boundary basis for subsequent stitching and deduplication. Specifically, first, two adjacent strip images from adjacent acquisition frequencies are extracted (e.g., the Nth and N+1th images; due to continuous stage movement, they inevitably overlap partially). The SIFT algorithm is then applied to both images to extract key feature points (such as corners of circuit lines, protrusions at defect edges, etc.). These feature points are scale-invariant and rotation-invariant, ensuring stable matching even with slight angular shifts or scale differences in the strips. Matching feature pairs are selected based on the similarity of the feature points (e.g., Euclidean distance). Based on the physical coordinates of these matching feature pairs (obtained in step S403), the overlap range of the two adjacent strip images in the world coordinate system, i.e., the overlapping area, is determined.

[0144] Step S405: After sequentially stitching adjacent strip images based on the overlapping region, the wafer image corresponding to the wafer to be detected is obtained.

[0145] This step is the final stage of image processing. By fusing the overlapping areas, all adjacent stripes are sequentially stitched together to form a complete image covering the entire wafer without misalignment or repetition. Specifically, based on the overlapping area determined in step S404, adjacent strip images are stitched together. For pixels within the overlapping area, a grayscale consistency weighted fusion is used (e.g., pixels on the left side of the overlapping area are dominated by the left strip, pixels on the right side are dominated by the right strip, and the intermediate transition area is weighted proportionally) to avoid obvious stitching marks (such as light and dark banding). Following a left-to-right order, all adjacent strip images are processed sequentially until all discrete stripes are integrated into a complete image, i.e., the wafer image corresponding to the wafer to be inspected.

[0146] In practical scenarios, the above steps are mainly used to control the movement of the three-axis motion platform and the focus control module, receive camera images, execute image stitching and deduplication algorithms, define the world coordinate system, establish its transformation relationship with the camera coordinate system based on camera calibration, and then establish the association between the suction cup coordinate system and the world coordinate system through reference markers on the suction cup (the wafer is fixed to the suction cup, and the suction cup pose directly maps to the wafer pose). One of its core functions is to establish a unified coordinate system. Camera intrinsic parameters and distortion coefficients are obtained through camera calibration, and then the transformation relationship from the world coordinate system to the camera coordinate system is calibrated through a calibration board. Three reference points with known world coordinates are set on the vacuum suction cup, and the transformation relationship from the suction cup coordinate system to the world coordinate system is calculated by visually identifying these points. Thus, any point on the wafer can be mapped to the camera pixel coordinate system through the above two transformation relationships, laying the foundation for precise motion control and image stitching.

[0147] Optionally, step S405, which involves sequentially stitching adjacent stripe images based on overlapping regions to obtain the wafer image corresponding to the wafer to be detected, is as follows: Figure 5 As shown, it includes:

[0148] Step S501: Obtain the first strip image and the second strip image from the adjacent strip images; wherein the right side of the first strip image and the left side of the second strip image overlap each other to form an overlapping region.

[0149] This step first identifies the two strips to be spliced ​​and defines the spatial range of the overlapping area, thus determining the object boundary for subsequent weighted fusion.

[0150] Specifically, from all the acquired strip images, select a pair of adjacent strips to be stitched together, defining them as the first strip image (usually the strip earlier in the scanning sequence, such as the left strip) and the second strip image (the strip later in the scanning sequence, such as the right strip); based on the overlapping area determined in step S404, clarify the overlapping relationship between the two: the right part of the first strip image and the left part of the second strip image completely overlap, forming a continuous overlapping area.

[0151] Step S502: Based on the distances between the target pixel in the overlapping region and the left and right boundaries of the overlapping region, determine the first weight value and the second weight value corresponding to the overlapping region.

[0152] Specifically, the first weight value Second weight value ; The first distance between the target pixel and the left boundary. This is the second distance between the target pixel and the right boundary.

[0153] Step S503: Update the target pixel using the first weight value and the second weight value, and then stitch the adjacent strip images together using the updated target pixel to obtain the wafer image.

[0154] The update process for the target pixel is achieved through the following formula:

[0155] ;

[0156] in, For the updated target pixel; This refers to the first pixel in the first strip image; This refers to the second pixel point in the second strip image.

[0157] In the image stitching and deduplication process, the line scan camera acquires images at a fixed line frequency during its movement, forming continuous strips. Due to overlapping areas between strips, stitching is necessary. The stitching process involves initial alignment based on an established coordinate system, followed by fine registration using SIFT feature points. For overlapping areas, a fading-in / fading-out (Feathering) algorithm is used to eliminate stitching seams. The characteristics of the line scan camera dictate that a complete image must be obtained through scanning and stitching. This step achieves the unification of multiple frames through path planning, feature matching, and coordinate transformation. In the first step of image stitching, feature point matching uses the SIFT algorithm to extract stable feature points in overlapping areas and find matching pairs between different strip images (e.g., points in strip A and strip B are the same physical point). In the second step, coordinate transformation and unification, a transformation matrix is ​​used to transform the pixel coordinates of each strip image to the world coordinate system. That is, for any pixel (u,v) in the strip image, it is first converted to the camera coordinate system using camera intrinsic parameters, and then converted to the world coordinate system. After all the strip images are unified to the world coordinate system, precise spatial alignment is achieved, and they are initially stitched together into a complete image.

[0158] If overlapping areas are directly superimposed, seams will appear (due to differences in lighting and camera noise causing inconsistent pixel values). The Feathering weighted average method achieves a smooth transition by weighting by distance, as shown in the formula above, and will not be elaborated further.

[0159] Optional, defect analysis step S104, such as Figure 6 As shown, it includes:

[0160] Step S601: Obtain the trained VAE model;

[0161] Step S602: Divide the wafer image into multiple sub-region original images according to the segmentation parameters corresponding to the VAE model, and input the sub-region original images into the VAE model to obtain the sub-region reconstructed image corresponding to the sub-region original image through the VAE model;

[0162] Step S603: Calculate the sum of squared pixel differences between the original image of the sub-region and the reconstructed image of the sub-region, and determine the difference region based on the original image of the sub-region where the sum of squared pixel differences is greater than a preset threshold;

[0163] Step S604: Determine the defect region corresponding to the wafer to be inspected based on the difference region.

[0164] The loss function used during VAE model training is: ;in, ; To reconstruct the loss function, Input image; To reconstruct the image; The similarity results between the input image and the reconstructed image in terms of brightness, contrast, and structural features; This is the sum of the absolute pixel errors between the input image and the reconstructed image; As a balance factor; This represents the KL divergence value corresponding to the VAE model; This is the decoupling weight value.

[0165] MS-SSIM (Multi-Scale Structural Similarity): Measures the structural similarity between an input image x and a reconstructed image, focusing on three dimensions: brightness, contrast, and structure (especially sensitive to structural features such as edges and textures). 1-MS-SSIM represents structural difference: the smaller the value, the more consistent the reconstructed image is with the original image in terms of visual structure (such as circuit textures and edge contours on a wafer surface). Wafer defects often manifest as local structural anomalies (edge ​​breaks, abrupt texture changes), and MS-SSIM can keenly capture such structural damage, more closely matching human visual perception of defects than simple pixel errors.

[0166] The sum of the absolute pixel errors between the input and reconstructed images is used, making it more sensitive to outliers (such as pixels with abrupt grayscale changes due to defects), thus compensating for the shortcomings of MS-SSIM in local pixel accuracy. The balance factor... The emphasis is placed on MS-SSIM because structural integrity is more important than individual pixel errors in wafer inspection. For example, slight pixel grayscale fluctuations may be irrelevant, but texture breaks are definitely defects. This is addressed by setting a high... The value ensures that the model prioritizes learning the structural patterns of normal wafers.

[0167] KL divergence forces decoupling of the latent space, improving representation robustness. KL divergence measures the difference between the latent distribution of the encoder output and the standard normal distribution. KL divergence regularizes the latent space, preventing the model from overlearning from training samples, ensuring that the latent vectors follow a simple distribution, and improving generalization ability. The weights of the KL divergence are enhanced, forcing each dimension of the latent space to be more independent and decoupled. That is, each dimension corresponds to an independent feature of the wafer (such as a certain texture direction or local gray-scale mean), rather than multiple features mixed together. The decoupled latent space can more accurately encode various features of normal wafers. When there are defects in the input, the defects will disrupt the normal distribution of multiple independent features, resulting in a significant increase in reconstruction error, thereby improving the sensitivity of defect identification.

[0168] In summary, this improved loss function can capture structural anomalies (such as circuit edge breaks) and also pay attention to pixel mutations (such as local bright spot defects), taking into account both details and the global picture. At the same time, it enhances the decoupling potential space, improves the representation accuracy of normal patterns, makes the reconstruction error of defect areas more significant, and reduces missed detections.

[0169] Optionally, during the training process of the VAE model, such as Figure 7 As shown, it includes:

[0170] Step S701: Use the attention module to obtain the global average pooling result, global max pooling result, and local peak pooling result corresponding to the VAE model in real time.

[0171] Step S702: After performing feature concatenation on the global average pooling result, the global max pooling result, and the local peak pooling result using the Sigmoid activation function, the channel weight values ​​corresponding to the VAE model are obtained.

[0172] Step S703: Obtain the first feature value output by the attention module based on the channel weight value, and extract the scale feature results corresponding to the first feature value using multiple convolutional kernels of different scales respectively;

[0173] Step S704: After weighted fusion calculation of the scale feature results using the Sigmoid activation function, the spatial weight values ​​corresponding to the VAE model are obtained.

[0174] Step S705: Obtain the second feature value output by the attention module using the spatial weight value, and update the second feature value by multiplying the pixels whose response intensity is less than the preset noise threshold with the preset attenuation coefficient.

[0175] During training, the VAE model incorporates improvements to the decoder. Specifically, an improved CBAM attention module is introduced into the decoder, enabling the model to focus on more important global and channel features during reconstruction, suppressing interference from local noise. This makes defective regions, due to their lack of normal context, difficult to reconstruct well, resulting in significantly higher reconstruction errors. The improved CBAM module is embedded in each decoding block within the decoder, specifically at: convolutional layer - improved CBAM - activation function - upsampling.

[0176] The original CBAM consists of channel attention and spatial attention connected in series. The improved CBAM adds cross-scale feature fusion and noise suppression gating to form a three-level structure of channel attention - cross-scale spatial attention - noise suppression.

[0177] The original CBAM channel attention captures channel importance through global average pooling and global max pooling, but it doesn't pay enough attention to the structured semantic channels of the wafer image (such as channels representing circuit textures and edges). The improved CBAM integrates global statistics and local peak statistics. Global statistics retain the original global average pooling (GAP) and global max pooling (GMP) to capture the overall channel response. Local peak statistics mainly add local peak pooling (LPP), which takes the maximum value within a 3×3 local window for each channel and then performs a global average to capture local significant responses within the channel (such as the local high-intensity response of circuit lines on the wafer within the channel). Finally, the results of GAP, GMP, and LPP are concatenated, and after compressing the dimensions through a 1×1 convolution, the channel weights Mc are output via a Sigmoid function. The formula is as follows: ;in, It is a Sigmoid activation, and [;] indicates feature concatenation.

[0178] The original CBAM spatial attention mechanism captures local spatial relationships using only a single 3×3 convolution, making it difficult to consider the global structural relationships in wafer images (such as circuit layout symmetry and texture continuity). The improved CBAM module, through multi-scale receptive field fusion and the introduction of contextual guidance, allows spatial attention to simultaneously focus on local details, regional structure, and global layout. This ensures that reconstruction follows the overall structural rules of the wafer, assigning low weights to defective regions that do not conform to the global structure, making them difficult to reconstruct accurately. Specifically, the multi-scale receptive field fusion extracts spatial features from the channel attention output using three convolutional kernels of different scales in parallel:

[0179] Small scale: 3×3 convolution (mainly captures local details, such as pixel-level textures);

[0180] Medium scale: 3×3 dilated convolution (dilation rate = 2, receptive field equivalent to 5×5, captures regional-level structures, such as circuit modules);

[0181] Large scale: 3×3 dilated convolution (dilation rate = 4, receptive field equivalent to 9×9, captures the global layout, such as the overall texture orientation of the wafer);

[0182] Finally, the features of the three scales are weighted and fused, and then passed through Sigmoid to output the spatial weight Ms. Another operation is to extract guiding information from the high-level features of the decoder, align the high-level features with the current feature F1 through upsampling, and calculate the cosine similarity between them as the prior weight of spatial attention (strengthening the regions consistent with the global structure). The specific formula is as follows:

[0183] ;

[0184] Where Merge is multi-scale feature fusion, Sim is cosine similarity calculation, and F high is the high-level feature of the decoder.

[0185] There may be sensor noise in the wafer image (such as isolated bright or dark spots), and these noises will be misjudged as significant features by the original CBAM attention module. The response of isolated noise is usually lower than that of structured features. An additional gating mechanism is added to filter through a dynamic threshold, reducing the interference of noise on reconstruction, thus ensuring that the attention only focuses on real structured features. The specific steps are as follows:

[0186] For the feature F2 output by spatial attention, calculate the response intensity s = |F2| for each pixel;

[0187] Dynamically calculate the threshold , where, and are learnable parameters;

[0188] For pixels with response intensity s < T, multiply by the attenuation coefficient to suppress noise; for pixels with response intensity s ≥ T, keep the weight unchanged.

[0189] The formula is as follows: .

[0190] As Figure 8 shown in the improved VAR network architecture diagram, Figure 8 the data corresponding to the decoder in

[0191] Table 1

[0192]

[0193] Figure 8 The data corresponding to the decoder in the table is shown in Table 2 below:

[0194] Table 2

[0195]

[0196] like Figure 9 The training diagram of the attention module during the training of the VAE model shown is not repeated here.

[0197] As can be seen from the wafer defect detection method mentioned in the above embodiments, this method makes full use of the transformation relationship between the imaging unit and the stage to accurately stitch the strip image during the wafer defect detection process, thereby obtaining a high-precision wafer image and improving the wafer detection accuracy. At the same time, this method can use an improved VAE model to accurately obtain the defect area of ​​the wafer to be detected from brightness, contrast and structural differences, and can identify minute defects with high precision, thereby solving the problem of poor detection effect of minute defects in the prior art.

[0198] Corresponding to the wafer defect detection method provided in the foregoing embodiments, this invention provides a wafer defect detection system, such as... Figure 10 As shown, the system includes:

[0199] Initialization module 1010: used to acquire the imaging unit and stage corresponding to the wafer to be inspected, and initialize the focusing control module corresponding to the imaging unit based on the image grayscale value of the wafer to be inspected;

[0200] Focusing control module 1020: Used to control the movement of the wafer to be inspected in the stage according to the preset scanning command, and to control the imaging unit in real time to acquire the strip image corresponding to the wafer to be inspected according to the preset acquisition frequency through the focusing control module;

[0201] Image processing module 1030: used to determine the transformation relationship between the imaging unit and the stage based on the camera calibration parameters corresponding to the imaging unit and the reference point parameters corresponding to the stage, and to obtain the wafer image corresponding to the wafer to be inspected by stitching the strip image based on the transformation relationship.

[0202] Defect Analysis Module 1040: Used to determine the reconstructed image corresponding to the wafer image based on the trained VAE model; to obtain the difference region between the reconstructed image and the wafer image based on the brightness, contrast and structural feature values ​​corresponding to the reconstructed image; and to determine the defect region corresponding to the wafer to be detected through the difference region.

[0203] As can be seen from the wafer defect detection system mentioned in the above embodiments, the system makes full use of the transformation relationship between the imaging unit and the stage to accurately stitch the strip images during the wafer defect detection process, thereby obtaining a high-precision wafer image and improving the wafer detection accuracy. At the same time, the system can use an improved VAE model to accurately obtain the defect area of ​​the wafer to be detected from the brightness, contrast and structural differences, and can identify minute defects with high precision, thereby solving the problem of poor detection effect of minute defects in the prior art.

[0204] The wafer defect detection system provided in this embodiment of the invention has the same implementation principle and technical effect as the aforementioned wafer defect detection method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned wafer defect detection method embodiment.

[0205] This embodiment also provides an electronic device, such as... Figure 11 As shown, it includes a processor 101 and a memory 102; wherein, the memory 102 is used to store one or more computer instructions, which are executed by the processor to implement the steps of the above-described wafer defect detection method.

[0206] Figure 11 The electronic device shown also includes a bus 103 and a communication interface 104, with the processor 101, communication interface 104 and memory 102 connected via the bus 103.

[0207] The memory 102 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. The bus 103 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 11 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0208] The communication interface 104 is used to connect to at least one user terminal and other network units through a network interface, and to send encapsulated IPv4 packets or IPv4 packets to the user terminal through the network interface.

[0209] Processor 101 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 101 or by instructions in software form. The processor 101 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 102. The processor 101 reads the information in memory 102 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0210] This invention also provides a storage medium storing a computer program, which, when run by a processor, executes the steps of the wafer defect detection method described in the foregoing embodiments.

[0211] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, devices, and methods can be implemented in other ways. The system embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0212] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0213] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0214] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0215] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A wafer defect detection method, characterized by, The method comprises: An initialization step: obtaining an imaging unit and a stage corresponding to a wafer to be detected, and initializing a focus control module corresponding to the imaging unit based on image gray values of the wafer to be detected; A focus control step: controlling the wafer to be detected in the stage to move according to a preset scanning instruction, and controlling the imaging unit to obtain strip images corresponding to the wafer to be detected in real time according to a preset acquisition frequency through the focus control module; An image processing step: determining a transformation relationship between the imaging unit and the stage according to camera calibration parameters corresponding to the imaging unit and reference point parameters corresponding to the stage, and obtaining a wafer image corresponding to the wafer to be detected by splicing the strip images based on the transformation relationship; A defect analysis step: determining a reconstructed image corresponding to the wafer image based on a VAE model that has been trained, obtaining a difference area between the reconstructed image and the wafer image according to brightness, contrast and structural feature values corresponding to the reconstructed image, and determining a defect area corresponding to the wafer to be detected through the difference area; The initialization step comprises: Obtaining a linear array camera, a vacuum chuck and a three-axis motion platform corresponding to the wafer to be detected in a defect detection process; Determining the imaging unit based on the linear array camera, and determining the stage based on the vacuum chuck and the three-axis motion platform; Determining a digital image corresponding to the wafer to be detected in the imaging unit, obtaining image gray values corresponding to the digital image, and calculating image gradient values corresponding to the digital image through a Sobel operator; Determining a focus evaluation value corresponding to the imaging unit according to the image gray values and the image gradient values, and initializing the focus control module based on the focus evaluation value; The step of determining the focus evaluation value corresponding to the imaging unit according to the image gray values and the image gradient values comprises: The focus evaluation value is calculated using the following equation : ； ； ； in, and These are the image gradient values ​​in the X and Y directions obtained by convolution using the Sobel operator, respectively. The grayscale value of the image; and These are the coordinate values ​​corresponding to the X and Y directions of the digital image, respectively. This is a mask function based on the local variance of the digital image; This is the gain coefficient; It is a point The variance of the local window centered on the target; The total number of pixels within the local window; The average grayscale value of the pixels within the local window; The pixels within the local window The corresponding grayscale value.

2. The wafer defect detection method of claim 1, wherein The focus control step comprises: After detecting that the wafer to be detected is adsorbed by the vacuum chuck, controlling the three-axis motion platform to drive the vacuum chuck to move up and down along a vertical direction according to a preset scanning instruction, and obtaining the focus evaluation value in real time; Obtaining position coordinates of the three-axis motion platform corresponding to a maximum value of the focus evaluation value by using a Hill-climbing algorithm, and determining the position coordinates as an initial focusing position; Controlling the focus control module to perform real-time focusing processing on the wafer to be detected based on the initial focusing position, and obtaining strip images corresponding to the wafer to be detected according to a preset acquisition frequency.

3. The wafer defect detection method of claim 1, wherein The image processing step comprises: Determining the camera calibration parameters according to focal length parameters of the linear array camera, a rotation matrix and a translation vector corresponding to a camera coordinate system of the linear array camera and a world coordinate system, and determining a first transformation relationship between the camera coordinate system and the world coordinate system by using the camera calibration parameters; determining a preset reference mark point in the vacuum chuck, determining a reference point parameter according to a corresponding coordinate value of the reference mark point in a chuck coordinate system of the vacuum chuck, and determining a second transformation relationship between the chuck coordinate system and a world coordinate system by using the reference point parameter; mapping a pixel point in the strip image to the world coordinate system by using the first transformation relationship and the second transformation relationship, and obtaining a corresponding coordinate point of the pixel point in the world coordinate system; obtaining a corresponding adjacent strip image under an adjacent acquisition frequency, determining a corresponding SIFT feature point between the adjacent strip images based on the coordinate point, and determining an overlapping area corresponding to the adjacent strip images by using the SIFT feature point; after sequentially performing splicing processing on the adjacent strip images based on the overlapping area, obtaining the wafer image corresponding to the wafer to be detected.

4. The wafer defect detection method of claim 3, wherein The step of obtaining the wafer image corresponding to the wafer to be detected after sequentially performing splicing processing on the adjacent strip images based on the overlapping area comprises: obtaining a first strip image and a second strip image in the adjacent strip images; wherein the right side of the first strip image and the left side of the second strip image overlap each other to form the overlapping area; determine a first weight value and a second weight value corresponding to the overlapping region based on distances of a target pixel point in the overlapping region to a left boundary and a right boundary of the overlapping region; wherein the first weight value ; and the second weight value ; a first distance corresponding to the target pixel point and the left boundary, a second distance corresponding to the target pixel point and the right boundary. updating the target pixel point by using the first weight value and the second weight value, and obtaining the wafer image by sequentially performing splicing processing on the adjacent strip images by using the updated target pixel point; the updating process of the target pixel point is realized by the following formula: ； wherein, is the updated target pixel point; is the corresponding first pixel point in the first strip image; is the corresponding second pixel point in the second strip image.

5. The wafer defect detection method of claim 1, wherein The defect analysis step comprises: obtaining a trained VAE model; a loss function used in training of the VAE model is: ; wherein, ; is a reconstruction loss function, is an input image; is a reconstructed image; is a similarity result of the input image and the reconstructed image in terms of brightness, contrast and structural features; is a sum of pixel absolute value errors of the input image and the reconstructed image; is a balance factor; is a KL divergence value corresponding to the VAE model; is a decoupling weight value; dividing the wafer image into a plurality of sub-area original images according to the segmentation parameter corresponding to the VAE model, inputting the sub-area original images into the VAE model, and obtaining a sub-area reconstructed image corresponding to the sub-area original image by the VAE model; calculating the sum of squares of pixel differences between the sub-area original image and the sub-area reconstructed image, and determining the difference area based on the sub-area original image whose sum of squares of pixel differences is greater than a preset threshold; determining a defect area corresponding to the wafer to be detected according to the difference area.

6. The wafer defect detection method of claim 5, wherein In the training process of the VAE model, comprising: real-time obtaining a global average pooling result, a global maximum pooling result and a local peak value pooling result corresponding to the VAE model by using an attention module; after feature splicing of the global average pooling result, the global maximum pooling result and the local peak value pooling result by a Sigmoid activation function, obtaining a channel weight value corresponding to the VAE model; obtaining a first feature value output by the attention module based on the channel weight value, and extracting a scale feature result corresponding to the first feature value by using a plurality of convolution kernels of different scales respectively; after weighted fusion calculation of the scale feature result by a Sigmoid activation function, obtaining a spatial weight value corresponding to the VAE model; The spatial weight value is used to obtain a second feature value output by the attention module, and a product of a pixel with a response strength less than a preset noise threshold and a preset attenuation coefficient is used to update the second feature value.

7. A wafer defect detection system, comprising: The system comprises: An initialization module is configured to acquire an imaging unit and a stage corresponding to a wafer to be detected, and initialize a focus control module corresponding to the imaging unit based on an image gray value of the wafer to be detected; The focus control module is configured to control the wafer to be detected in the stage to move according to a preset scanning instruction, and control the imaging unit to acquire a strip image corresponding to the wafer to be detected at a preset acquisition frequency in real time through the focus control module; An image processing module is configured to determine a transformation relationship between the imaging unit and the stage according to a camera calibration parameter corresponding to the imaging unit and a reference point parameter corresponding to the stage, and acquire a wafer image corresponding to the wafer to be detected by splicing the strip image based on the transformation relationship; A defect analysis module is configured to determine a reconstructed image corresponding to the wafer image based on a VAE model that has been trained, acquire a difference region between the reconstructed image and the wafer image according to a brightness, a contrast and a structural feature value corresponding to the reconstructed image, and determine a defect region corresponding to the wafer to be detected through the difference region; The initialization module is further configured to acquire a line array camera, a vacuum chuck and a three-axis motion platform corresponding to the wafer to be detected in a defect detection process, determine the imaging unit based on the line array camera, determine the stage based on the vacuum chuck and the three-axis motion platform, determine a digital image corresponding to the wafer to be detected in the imaging unit, acquire an image gray value corresponding to the digital image, and calculate an image gradient value corresponding to the digital image through a Sobel operator, determine a focus evaluation value corresponding to the imaging unit according to the image gray value and the image gradient value, and initialize the focus control module based on the focus evaluation value; In the process of determining the focus evaluation value corresponding to the imaging unit according to the image gray value and the image gradient value, the initialization module is further configured to: The focus evaluation value is calculated using the following equation : ； ； ； wherein, and are the image gradient values in X and Y directions respectively obtained by Sobel operator convolution; is the image gray value; and are the coordinate values in X and Y directions respectively corresponding to the digital image; is the mask function based on the local variance of the digital image; is the gain coefficient; is the variance value of the local window with the point as the center; is the total number of pixels in the local window; is the average gray value of the pixels in the local window; is the gray value of the pixel point in the local window.

8. An electronic device, comprising: The electronic device comprises a processor and a memory, the memory stores computer executable instructions capable of being executed by the processor, and the processor executes the computer executable instructions to implement the wafer defect detection method mentioned in any one of claims 1 to 6.

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