Multi-winding motor control system and method based on multi-core chip and interrupt alignment

Abstract

The invention discloses a multi-winding motor control system and method based on a multi-core chip and interrupt alignment, and the system comprises at least two control chips, and each control chip at least comprises a CORE1 core and a CORE2 core. Position synchronous communication is carried out among the control chips through CAN FD ports, each control chip distributes two mutually exclusive GPIO ports for a hardware interrupt line, the GPIO ports are respectively used for triggering and interrupting a high level and receiving external signals, and the GPIO ports are connected in parallel to form an interrupt logic flow; the working mode of the control chip is divided into a master control mode and a slave control mode. The method can be matched with an existing motor inverter product, and is improved based on a mature permanent magnet synchronous motor FOC control technology, so that the development cost is reduced; extension of multiple control chips is supported, and the system is suitable for multi-winding motor scenes with different power requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of multi-winding permanent magnet synchronous motor control, in particular to a multi-winding motor control system and method based on multi-core chips and interrupt alignment. BACKGROUND

[0002] In the field of non-road transportation, the selection of the driving system of the vehicle has a crucial impact on its operating efficiency, cost control and environmental performance. At present, the mainstream driving schemes in the industry are mainly divided into two categories: One type of driving scheme is a high-power diesel engine combined with a gearbox. In actual application, this driving method has high fuel consumption rate of the diesel engine itself, resulting in high daily operating cost of the vehicle. At the same time, the power system composed of the diesel engine and the gearbox has a complex structure, and the components wear out quickly in a high-strength working environment, which not only requires frequent maintenance, but also significantly increases the overall maintenance cost due to the replacement of parts and labor involved in the maintenance process. More importantly, the high-power diesel engine emits a large amount of carbon dioxide, nitrogen oxides and other pollutants during combustion, which has a high carbon emission level and is contrary to the current global low-carbon and environmentally friendly development concept, which is neither economical nor energy-saving.

[0003] Another type of driving scheme is a diesel generator set combined with a voltage-type AC / DC / AC converter and a high-power asynchronous motor. Although this driving method has improved the form of power output, it still has obvious technical shortcomings. The power transmission link is long, from power generation by the diesel generator set to electric energy conversion by the AC / DC / AC converter and then to driving the asynchronous motor, and the energy is lost in the multi-link transmission process, resulting in low power factor and low operating efficiency of the system. In addition, the combination of the diesel generator set, the AC / DC / AC converter and the high-power asynchronous motor occupies a large space of the vehicle, which undoubtedly further limits the loading capacity or operational flexibility of the non-road transportation vehicle which is already tight in space layout.

[0004] In summary, the existing non-road transportation vehicle driving technology has defects in economy, energy saving, efficiency and space utilization, and an optimal driving scheme is needed to solve these problems. SUMMARY

[0005] To solve the above problems, the present application provides a multi-winding motor control system and method based on multi-core chips and interrupt alignment.

[0006] To this end, the technical scheme of the present application is: a multi-winding motor control system based on multi-core chips and interrupt alignment, comprising at least two control chips, and each control chip contains at least two cores CORE1 and CORE2; each control chip has at least two channel CAN ports, and at least one of the CAN ports supports the CAN FD communication protocol; each control chip communicates with each other through the CAN FD port for position synchronization, and each control chip is assigned with 2 mutually exclusive GPIO ports for hardware interrupt line, which are used for triggering interrupt high level and receiving external signals respectively, and the GPIO ports are connected in parallel to form an interrupt logic flow; The working mode of the control chip is divided into master control mode and slave control mode, and the master control mode or the slave control mode is automatically switched through the signal sampling result of CORE1 and the message detection result of the CAN FD port of CORE2; and in each working cycle, only one control chip is in the master control mode, and the remaining control chips are in the slave control mode. The control chip in the master control mode is used to perform speed loop, torque loop and current loop calculation, send control instructions through the CAN FD port and trigger GPIO interrupt, and synchronize PWM carrier frequency duty cycle. The control chip in the slave control mode is used to receive master control instructions, perform torque loop and current loop calculation, feedback state information, and update PWM duty cycle based on GPIO interrupt.

[0007] On the basis of the above scheme and as a preferred scheme of the above scheme: the working mode switching logic of the control chip is that CORE2 obtains valid message information from the CAN FD port, and when CORE1 samples valid resolver signals and temperature signals, the resolver sampling flag bit is set to 1, and the system enters the master control mode. When CORE1 does not sample valid resolver signals, and CORE2 receives resolver sampling flag bit of 1 from the CAN FD port, the system enters the slave control mode. When an abnormal state is detected, a fault report is triggered and the output current is reduced to 0 according to a preset step.

[0008] On the basis of the above scheme and as a preferred scheme of the above scheme: when the control chip is in the master control mode, it is used to receive the speed / torque instruction of the whole vehicle or the upper computer; the motor rotor position and speed are calculated based on the resolver signal; the speed loop, torque loop and current loop calculation are performed to generate d / q axis voltage instructions; the control instructions are sent through the CAN FD port, and the GPIO interrupt is triggered to synchronize the PWM carrier frequency duty cycle of the slave control unit.

[0009] On the basis of the above scheme and as a preferred scheme of the above scheme: when the control chip is in the slave mode, the GPIO synchronization interrupt signal and the master control instruction of the CAN FD port are monitored; the current rotor position information of the motor is acquired based on the received resolver value and angular velocity value; torque loop and current loop calculation are performed to generate voltage control instructions; the speed, torque and current state information are fed back through the CAN FD port.

[0010] On the basis of the above scheme and as a preferred scheme of the above scheme: the two GPIO ports on each control chip satisfy: when one of the GPIO ports is enabled, the other GPIO port is automatically disabled, and all GPIO interfaces are provided with an optocoupler isolation module at the front end of the circuit.

[0011] Another technical scheme of the application is a multi-core chip and interrupt alignment based multi-winding motor control method based on the above control system, comprising the following steps: S1, when the control chip is powered on, the signal sampling result of CORE1 and the message detection result of the CAN FD port of CORE2 are used to automatically judge whether each control chip is in a master control mode or a slave control mode, which are respectively recorded as a master control chip and a slave control chip, and only one control chip is in the master control mode; S2, when the control chip is in the master control mode, the specific processing steps are as follows: S2.1, when the control chip is in the master control mode, steps S2.2 and S2.3 are executed synchronously; S2.2, execute the sampling AD interrupt, in the AD interrupt, the current rotor position information of the motor is acquired through resolver collection, and the current resolver value and current winding angular velocity value obtained by decoding are sent to the slave control chip; at the same time, the current speed of the motor is analyzed, and the carrier frequency is switched according to the current speed of the motor; the next interrupt period is continued to be executed, and it is judged whether the interrupt counter reaches the half carrier period interrupt point, if it reaches the half carrier period interrupt point, the GPIO synchronization interrupt pin is set to high level; S2.3, judge whether the master control chip is in a vehicle control mode or an upper computer control mode, if it is in the vehicle control mode, execute step S2.4, if it is in the upper computer control mode, execute step S2.5; S2.4, judge whether CORE1 receives the control instruction issued by the vehicle, if it receives, execute the speed instruction and torque instruction issued by the vehicle; otherwise, report a communication exception fault; S2.5, judge whether CORE1 receives the control instruction issued by the upper computer, if it receives, execute the speed instruction, torque instruction and current instruction issued by the upper computer; S3, when the control chip is in the slave control mode, the specific processing steps are as follows: S3.1, when the control chip is in the slave mode, synchronously execute step S3.2 and step S3.3; S3.2, judge whether the GPIO synchronous interrupt pin is high level, if yes, execute the highest priority AD interrupt, recalculate the current PWM wave duty cycle and write into the register, initialize the GPIO synchronous interrupt pin, otherwise, directly execute the sampling AD interrupt, then, judge whether the CORE 2 reads the resolver value and angular velocity value sent by the master control chip, if yes, update the resolver value, otherwise, continue to use the resolver value and motor angular velocity value received last time, then, judge whether the current motor rotation direction is forward or reverse, after processing the resolver value in the interval (0, 2π), continue to execute the next interrupt period; S3.3, judge whether the slave control chip is in the whole vehicle control mode or the upper computer control mode, if in the whole vehicle control mode, execute step S3.4, if in the upper computer control mode, execute step S3.5; S3.4, the CORE 1 receives the control instruction sent by the whole vehicle, the CORE 2 obtains the torque instruction and current instruction sent by the master control chip, and executes; S3.5, the CORE 1 receives the control instruction sent by the upper computer, and executes the torque instruction and current instruction sent by the upper computer.

[0012] On the basis of the above scheme and as a preferred scheme of the above scheme: the speed instruction is: The CORE 1 obtains the speed feedback of the motor at the current moment and the torque feedback of the main winding, and the CORE 2 synchronously obtains the torque feedback of the slave winding through CANFD; the CORE 1 calculates the output torque of the motor at the current moment, and obtains the speed regulation torque instruction through the speed loop PI calculation, and evenly distributes the torque instruction to the main winding and the slave winding.

[0013] On the basis of the above scheme and as a preferred scheme of the above scheme: the torque instruction of the master control chip is: through the speed loop / torque loop calculation strategy in the built-in control algorithm, and the id / iq current instruction is parsed by searching the calibration IdIqMap; the torque instruction of the slave control chip is: through the torque loop calculation strategy in the built-in control algorithm, and the id / iq current instruction is parsed by searching the calibration IdIqMap.

[0014] On the basis of the above scheme and as a preferred scheme of the above scheme: the current instruction of the master control chip and the slave control chip is obtained through the current loop calculation in the built-in control algorithm to obtain the Vd / Vq voltage instruction, the voltage instruction is calculated through the SVPWM modulation to obtain the three-phase voltage value to be output, the CORE 1 calculates the double-level IGBT switching tube PWM carrier through sector judgment and vector synthesis by using the three-phase voltage value, and the CORE 1 controls the IGBT to be turned on to output the corresponding voltage value to the motor; Meanwhile, the CORE 2 of the master control chip sends the calculated id / iq current instruction to the slave control chip and acquires the current state of the slave control chip; Meanwhile, the CORE 2 of the master control chip sends the calculated id / iq current instruction to the slave control chip and acquires the current state of the slave control chip;

[0015] On the basis of the above scheme and as a preferred scheme of the above scheme, the specific steps of judging whether each control chip is in the master control mode or the slave control mode in step S1 are as follows: S1.1, the CORE 2 initializes the GPIO for master-slave interruption and sets the resolver sampling flag to 0, and meanwhile, the CORE 1 performs power-on self-test AD sampling; S1.2, it is judged whether the CORE 2 reads the message information from the CAN FD port, if yes, step S1.3 is executed, otherwise, a master-slave communication abnormality fault is reported; S1.3, it is judged whether the CORE 1 samples the resolver cosine and sine signals and the motor temperature resistance signal, if yes, step S1.4 is executed, otherwise, step S1.5 is executed; S1.4, the CORE 2 sets the master control resolver sampling flag to 1 and judges whether the CORE 2 receives the slave control resolver sampling flag to 2, if not, a master-slave communication abnormality fault is reported, if yes, the control chip enters the master control mode; After entering the master control mode, the CORE 2 sends the related message information according to the set period and baud rate, and meanwhile, the CORE 2 interrupt trigger GPIO port outputs high level according to the software set period; If the control chip does not have resolver and temperature sampling abnormality fault and other faults, the next interruption period is continuously executed, otherwise, the related fault information is reported; S1.5, it is judged whether the CORE 2 receives the master control resolver sampling flag to 1, if not, a master-slave communication abnormality fault is reported, if yes, the control chip enters the slave control mode; After entering the slave control mode, the CORE 2 sets the slave control resolver sampling flag to 2, the CORE 2 reads the related message information according to the set period and baud rate and executes; meanwhile, it is judged whether the CORE 2 detects the set interruption trigger GPIO port is triggered, if yes, the CORE 2 executes the hardware interruption and synchronizes with the PWM carrier frequency duty cycle of the master control chip; If the CORE 2 does not receive the master control resolver sampling flag to 0 and does not have other faults, the next interruption period is continuously executed, otherwise, the related fault information is reported.

[0016] Compared with the prior art, the application has the beneficial effects that: The multi-core chip is adopted, CORE1 is responsible for signal sampling and control calculation, CORE2 is responsible for CAN FD communication and interrupt synchronization, multi-task parallel processing is realized, and the control response speed is improved; the high-speed position synchronous communication is realized between control chips through the CAN FD port, and the cooperative operation of the multi-winding motor is ensured; the interrupt logic flow is formed by using the GPIO port, the PWM carrier frequency duty cycle synchronization is triggered through the hardware interrupt, the synchronization error is reduced, and the motor control precision is improved.

[0017] Without the need of developing a new motor controller, the existing motor inverter product can be matched, the mature permanent magnet synchronous motor FOC control technology is improved, the development cost is reduced; the multi-control chip extension is supported, and the multi-winding motor scene with different power requirements is adapted.

[0018] 3. The dependence on diesel engines is eliminated, the emissions of carbon dioxide, nitrogen oxides and other pollutants are reduced, and the daily operating cost is reduced; meanwhile, the power system structure is simplified, the wear of parts is reduced, and the labor cost and part replacement cost of maintenance are reduced. The multi-winding motor and the multi-core chip control system are integrated, the large size of equipment combination in the traditional scheme is avoided, the space occupation of the off-road transport vehicle is saved, the loading capacity and operation flexibility are improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is a low-voltage connection diagram of the dual-winding motor control system of the application; Figure 2 It is a master-slave control mode switching flow chart of the application; Figure 3 It is a master control mode calculation logic diagram of the application; Figure 4 It is a slave control mode calculation logic diagram of the application. DETAILED DESCRIPTION

[0020] The multi-winding motor control system based on the multi-core chip and interrupt alignment described in the embodiment comprises at least two motor controllers, the motor controller comprises a control chip, and each control chip MCU comprises at least two cores CORE1 and CORE2; each control chip has at least two channel CAN ports, and at least one of the CAN ports supports the CAN FD communication protocol.

[0021] As Figure 1As shown, taking the minimum dual-winding motor control unit composed of two motor controllers as an example, the control chip of each motor controller has three CAN FD ports that support the CAN FD communication protocol, namely CAN FD1, CAN FD2 and CAN FD3. In the hardware design, it is specified that the three CAN FD ports are all shielded CAN. It is specified that the GPIO port for hardware interrupt needs to be designed with special optocoupler isolation at the front end of the circuit to reduce high-frequency voltage interference.

[0022] Among them, CAN FD1 is the vehicle CAN bus, used to receive control commands from the vehicle and provide feedback on the status and fault conditions of the electric motor. CAN FD3 is the debugging and programming CAN bus, used to update the electric control program, solidify calibration data, monitor control quantities and related status variables, and provide control commands when the control mode is host computer control. CAN FD2 is the position synchronization CAN bus, where the master control chip sends the relevant signals in Table 1 to the slave control chip via this CAN bus. The default communication baud rate for this CAN bus is agreed to be 5Mbps, and the communication period is 500us.

[0023] Table 1. Communication protocol from master controller to slave controller in CAN FD2 Because different chips have different GPIO ports, this control method does not specify the specific pin definitions for the hardware interrupt GPIO. Each control unit will allocate two GPIO ports to the hardware interrupt line, one for triggering an interrupt high level and the other for receiving external high and low level signals; these two GPIO ports will be mutually exclusive, meaning that if one is enabled, the other will be disabled. Each multi-winding motor control unit will connect these IO ports in parallel to a set of hard lines to form the interrupt logic flow.

[0024] The specific control mode and logic are as follows: S1. Master-Slave Control Mode Switching Logic: When the control chip powers on, since the program does not manually define whether it is a master or slave control unit, the control chip needs to determine whether it is currently in master or slave control mode. The specific steps are as follows: S1.1, CORE 2 initializes the master-slave interrupt GPIO and sets the resolver sampling flag to 0. At the same time, CORE 1 performs a power-on self-test on the AD sampling status. S1.2 Determine whether CORE 2 has read the message information from the CAN FD2 bus. If yes, proceed to step S1.3. Otherwise, report the master-slave communication abnormality and perform loop detection until CORE 2 reads the message information. S1.3 Determine whether CORE 1 has sampled the resolver sine and cosine signals and the motor temperature and resistance signals. If it has, proceed to step S1.4; otherwise, proceed to step S1.5.

[0025] S1.4, CORE 2 sets the master resolver sampling (Res_Init) flag to 1, and determines whether CORE 2 receives the slave resolver sampling (Res_Init) flag to 2 from the CAN FD2 bus. If not, it reports a master-slave communication abnormality and loops the detection until it receives the flag. If it receives the flag, the control chip enters master control mode. S1.4.1 After entering the main control mode, CORE 2 sends relevant message information on the CAN FD 2 bus according to the set period and baud rate. At the same time, the CORE 2 interrupt triggers the GPIO port to output a high level according to the software set period. S1.4.2 Determine if the control chip has any abnormal faults in resolver and temperature sampling. If a fault exists, report the main control sampling abnormality fault through CAN FD1 and CAN FD3, reduce the output current to 0 according to the set step size, set the main control resolver sampling (Res_Init) flag to 0, and then wait for the driver to intervene. S1.4.3 If there are no abnormal faults in the resolver and temperature sampling, then determine whether there are other faults in the control chip. If there are other faults, report the relevant fault information through CAN FD1 and CAN FD3. If there are no other faults, continue to execute the next interrupt cycle and end.

[0026] S1.5 determines whether CORE 2 has received the master resolver sampling (Res_Init) flag set to 1 from the CAN FD 2 bus. If not, it reports a master-slave communication abnormality and performs loop detection until it receives the flag. If it receives the flag, the control chip enters slave mode. S1.5.1 After entering slave mode, CORE 2 will set the slave resolver sampling flag to position 2; S1.5.2, CORE 2 reads and executes relevant message information on the CAN FD 2 bus according to the set period and baud rate; At the same time, it checks whether the interrupt trigger GPIO port set by CORE 2 has been triggered. If it has not been triggered, it checks in a loop until it is triggered. If it is triggered, CORE 2 executes a hardware interrupt and synchronizes with the PWM carrier frequency duty cycle of the main control chip. S1.5.3 Determine whether CORE 2 receives the master control resolver sampling (Res_Init) flag set to 0 from the CAN FD 2 bus. If it receives Res_Init set to 0, report the master control sampling abnormality fault through CAN FD1 and CAN FD 3, reduce the output current to 0 according to the set step size, set the slave control resolver sampling (Res_Init) flag set to 0, and then wait for the driver to intervene. S1.5.4 If Res_Init is not received as 0, then determine whether there are other faults in the control chip. If there are other faults, report the relevant fault information through CAN FD1 and CAN FD3. If there are no other faults, continue to execute the next interrupt cycle and end.

[0027] S2. When the controller determines that it is currently in master control mode, it executes the calculation logic for master control mode. The host computer control mode and the vehicle control mode are mutually exclusive. To switch between them, the _Debug flag needs to be toggled in the software. The calculation steps for the master control mode are as follows: S2.1 When the control chip enters the master control mode, steps S2.2 and S2.3 are executed simultaneously. S2.2 Execute the sampling AD interrupt, increment the interrupt counter by 1. In the AD interrupt, the current rotor position information of the motor is acquired through the resolver, and the current resolver value and the current winding angular velocity value obtained by acquisition and decoding are sent to the slave control chip through the CAN FD2 bus. At the same time, the current motor speed is parsed and the carrier frequency is switched according to the current motor speed. Continue to execute the next interrupt cycle. At the same time, it is determined whether the interrupt counter has reached the half-carrier cycle interrupt point. If it has reached the half-carrier cycle interrupt point, the GPIO synchronous interrupt pin is set to high level. If it has not reached the half-carrier cycle interrupt point, continue to execute the next interrupt cycle, and finally end.

[0028] S2.3 Execute a 1ms scheduling cycle, and then determine whether the main control chip is in the vehicle control mode or the host computer control mode. If it is in the vehicle control mode, execute step S2.4; if it is in the host computer control mode, execute step S2.5. S2.4 Determine whether CORE 1 has received control commands from the vehicle from the CAN FD 1 bus. If it has, execute the speed and torque commands from the vehicle. Otherwise, report a communication error or fault and perform a loop check until it receives the commands. S2.5 Determine whether CORE 1 has received control commands from the host computer on the CAN FD 3 bus. If it has, execute the speed command, torque command, and current command sent by the host computer; otherwise, continue to wait and check cyclically until it receives them.

[0029] The speed command in master control mode is as follows: Enter the speed loop logic, CORE 1 obtains the current speed feedback of the motor and the torque feedback of the main winding, and CORE 2 simultaneously obtains the current torque feedback of the slave winding through the CAN FD2 bus; CORE 1 calculates the current output torque of the motor, and after speed loop PI calculation, obtains the speed regulation torque command, and evenly distributes the torque command to the main winding and the slave winding.

[0030] The torque command in master control mode is as follows: enter the torque loop logic, the torque command is calculated by the speed loop / torque loop in the built-in control algorithm, and parsed into id / iq current command by checking the calibration IdIqMap.

[0031] The current command in master control mode is: enter the current loop logic and perform two steps simultaneously: Step 1: CORE 2 sends the calculated id / iq current command to the slave chip via the CAN FD 2 bus; CORE 2 obtains the current status of the slave controller (slave chip) via the CAN FD 2 bus; Another step: The current command is calculated by the current loop in the built-in control algorithm to obtain the Vd / Vq voltage command; the voltage command is modulated by SVPWM to calculate the three-phase voltage value to be output; CORE 1 calculates the PWM carrier of the dual-level IGBT switching transistor by sector judgment and vector synthesis of the three-phase voltage value; CORE 1 controls the IGBT to conduct and output the corresponding voltage value to the motor. Next, it is determined whether there are other faults in the control chip. If a fault exists, the relevant fault information is reported through CAN FD1 and CAN FD3; if no fault exists, the next 1ms scheduling cycle is executed, and then the process ends.

[0032] S3. When the controller determines that it is currently in slave mode, it executes the slave control mode calculation logic. The host computer control mode and the vehicle control mode are mutually exclusive. If you want to switch, you need to switch the _Debug flag in the software.

[0033] The slave controller cannot execute speed loop related commands; it can only execute torque loop / current loop related commands.

[0034] The calculation logic for the slave control mode is as follows: S3.1 After the control chip enters slave mode, steps S3.2 and S3.3 are executed synchronously. S3.2 Determine if the GPIO synchronous interrupt pin is at a high level. S3.2.1 If it is high, execute the highest priority AD interrupt, recalculate the current PWM wave duty cycle and write it into the register, and initialize the GPIO synchronous interrupt pin; S3.2.2 If it is not a high level, then the sampling AD interrupt will be executed directly; S3.2.3 Determine whether CORE 2 has read the resolver value and angular velocity value sent by the main control chip on the CAN FD 2 bus. If it has, update the resolver value; otherwise, continue to use the previously received resolver value and motor angular velocity value. S3.2.4 Determine whether the motor is currently rotating forward or backward. After processing the resolver value in the range of (0, 2π), continue to execute the next interrupt cycle and finally end.

[0035] S3.3 Execute a 1ms scheduling cycle to determine whether the slave control chip is in vehicle control mode or host computer control mode. If it is in vehicle control mode, execute step S3.4. If it is in host computer control mode, execute step S3.5. S3.4 Determine whether CORE 1 has received the control command issued by the vehicle from the CAN FD 1 bus. If it has not received it, report a communication abnormality fault and check it in a loop until it receives it. If it has received it, CORE 2 obtains the torque / current control command issued by the main control chip through the CAN FD2 bus and executes the torque and current commands issued by the main control chip. S3.5 Determine whether CORE 1 has received control commands from the host computer on the CAN FD 3 bus. If not, wait and check repeatedly until received. If received, execute the torque and current commands sent by the host computer.

[0036] In slave mode, the torque command is as follows: enter the torque loop logic, the torque command is processed by the torque loop calculation strategy in the built-in control algorithm, and parsed into id / iq current command by checking the calibration IdIqMap.

[0037] The current command in slave mode is: enter the current loop logic and perform two steps simultaneously: Step 1: CORE 1 obtains the current feedback from the winding at the current moment, and CORE 1 queries the output torque of the winding at the current moment according to IdIqMap; CORE 2 sends the current torque / current feedback from the winding to the main control chip through the CAN FD 2 bus; CORE 2 obtains the current status of the main controller through the CAN FD 2 bus. Another step: The current command is calculated by the current loop in the built-in control algorithm to obtain the Vd / Vq voltage command; the voltage command is modulated by SVPWM to calculate the three-phase voltage value to be output; CORE 1 calculates the PWM carrier of the dual-level IGBT switching transistor by sector judgment and vector synthesis of the three-phase voltage value; CORE 1 controls the IGBT to conduct and output the corresponding voltage value to the motor. Next, it is determined whether there are other faults in the control chip. If a fault exists, the relevant fault information is reported through CAN FD1 and CAN FD3; if no fault exists, the next 1ms scheduling cycle is executed, and then the process ends.

[0038] This invention uses a multi-winding motor and its control system to replace the power system on off-road transport vehicles. The multi-winding motor involved is a new product and is an actuator, which will not be described in detail in this invention. The motor controller involved is an existing product. Except for the few points involved in the minimum dual-winding motor control unit mentioned above, the other components are no different from the existing motor controller products on the market.

[0039] The control method involved in this paper is not an update of existing product hardware, but rather an innovation in control strategy and method based on existing technology and products, using mature products with lower cost and lower failure rate.

[0040] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A multi-winding motor control system based on multi-core chips and interrupt alignment, characterized in that: It includes at least two control chips, and each control chip contains at least two cores, CORE1 and CORE2; each control chip has at least two CAN ports, and at least one of the CAN ports supports the CAN FD communication protocol; the control chips communicate with each other for position synchronization through the CAN FD ports, and each control chip allocates two mutually exclusive GPIO ports for hardware interrupt lines, which are used to trigger an interrupt high level and receive external signals, respectively, and the GPIO ports are connected in parallel to form an interrupt logic flow; The control chip operates in two modes: master control mode and slave control mode. It automatically switches to master control mode or slave control mode based on the signal sampling results of CORE1 and the message detection results of the CAN FD port on CORE2. In each working cycle, only one control chip is in master control mode, and the rest of the control chips are in slave control mode. In master control mode, the control chip is used to perform speed loop, torque loop and current loop calculations, send control commands through the CAN FD port and trigger GPIO interrupts, and synchronize the PWM carrier frequency duty cycle. In slave mode, the control chip receives master control commands, performs torque loop and current loop calculations, provides status information, and updates the PWM duty cycle synchronously based on GPIO interrupts.

2. The multi-winding motor control system based on multi-core chip and interrupt alignment as described in claim 1, characterized in that: The working mode switching logic of the control chip is as follows: CORE 2 obtains valid message information from the CAN FD port. When CORE 1 samples a valid resolver signal and temperature signal, it sets the resolver sampling flag to 1, and the system enters the main control mode. When CORE 1 fails to sample a valid resolver signal, and CORE 2 receives a resolver sampling flag of 1 from the CAN FD port, the system enters slave mode. When an abnormal state is detected, a fault report is triggered and the output current is reduced to 0 in a preset step size.

3. The multi-winding motor control system based on multi-core chip and interrupt alignment as described in claim 1, characterized in that: When the control chip is in master control mode, it is used to receive speed / torque commands from the vehicle or host computer. The motor rotor position and speed are calculated based on the resolver signal; speed loop, torque loop and current loop calculations are performed to generate d / q axis voltage commands; control commands are sent through the CANFD port and GPIO interrupts are triggered to synchronize the PWM carrier frequency duty cycle of the slave control unit.

4. The multi-winding motor control system based on multi-core chip and interrupt alignment as described in claim 1, characterized in that: When the control chip is in slave mode, it monitors the GPIO synchronous interrupt signal and the master control command of the CAN FD port; updates the current resolver information of the motor based on the received resolver value and angular velocity value; performs torque loop and current loop calculations to generate voltage control commands; and feeds back the status information of speed, torque and current through the CAN FD port.

5. The multi-winding motor control system based on multi-core chip and interrupt alignment as described in claim 1, characterized in that: Each control chip has two GPIO ports that satisfy the following condition: when one GPIO port is enabled, the other GPIO port is automatically disabled, and all GPIO interfaces are equipped with optocoupler isolation modules at the front end of the circuit.

6. A multi-winding motor control method based on multi-core chips and interrupt alignment, using the control system described in any one of claims 1 to 5, characterized in that: Includes the following steps: S1. When the control chip is powered on, it automatically determines whether each control chip is in master control mode or slave control mode based on the signal sampling result of CORE1 and the message detection result of the CAN FD port on CORE2. These are recorded as master control chip and slave control chip, respectively. At the same time, there is only one control chip in master control mode. S2. When the control chip is in master control mode, the specific processing steps are as follows: S2.1 When the control chip enters the master control mode, steps S2.2 and S2.3 are executed simultaneously. S2.2 Execute the sampling AD interrupt. In the AD interrupt, the current rotor position information of the motor is collected through the resolver, and the current resolver value and the current winding angular velocity value obtained by the acquisition and decoding are sent to the slave control chip. At the same time, the current speed of the motor is analyzed, and the carrier frequency is switched according to the current speed of the motor. Continue to execute the next interrupt cycle. At the same time, it is determined whether the interrupt counter has reached the half-carrier cycle interrupt point. If it has reached the half-carrier cycle interrupt point, the GPIO synchronous interrupt pin is set to high level. S2.3 Determine whether the main control chip is in vehicle control mode or host computer control mode. If it is in vehicle control mode, execute step S2.

4. If it is in host computer control mode, execute step S2.

5. S2.4 Determine whether CORE 1 has received the control command issued by the vehicle. If it has, execute the speed and torque commands issued by the vehicle; otherwise, report a communication abnormality or fault. S2.5 Determine whether CORE 1 has received the control command sent by the host computer. If it has, execute the speed command, torque command and current command sent by the host computer. S3. When the control chip is in slave mode, the specific processing steps are as follows: S3.1 After the control chip enters slave mode, steps S3.2 and S3.3 are executed synchronously. S3.

2. Determine if the GPIO synchronous interrupt pin is high. If yes, execute the highest priority AD interrupt, recalculate the current PWM waveform duty cycle and write it to the register, and initialize the GPIO synchronous interrupt pin. Otherwise, directly execute the sampling AD interrupt. Next, determine if CORE 2 has read the resolver value and angular velocity value sent by the main control chip. If it has, update the resolver value. Otherwise, continue to use the previously received resolver value and motor angular velocity value. Then, determine whether the motor is currently rotating forward or backward. After processing the resolver value in the (0, 2π) range, continue to execute the next interrupt cycle. S3.3 Determine whether the slave control chip is in vehicle control mode or host computer control mode. If it is in vehicle control mode, execute step S3.

4. If it is in host computer control mode, execute step S3.

5. S3.4 and CORE 1 receive control commands from the vehicle, while CORE 2 obtains and executes torque and current commands from the main control chip. S3.5 and CORE 1 receive control commands from the host computer and execute the torque and current commands sent by the host computer.

7. The multi-winding motor control method based on multi-core chip and interrupt alignment as described in claim 6, characterized in that: The rotation speed command is: CORE 1 obtains the current motor speed feedback and main winding torque feedback, while CORE 2 synchronously obtains the current torque feedback of the slave winding via CAN FD. CORE 1 calculates the current motor output torque, and after speed loop PI calculation, obtains the speed regulation torque command, which is then evenly distributed to the main winding and slave winding.

8. The multi-winding motor control method based on multi-core chip and interrupt alignment as described in claim 6, characterized in that: The torque command of the master control chip is calculated by the speed loop / torque loop in the built-in control algorithm and parsed into an id / iq current command by checking the calibration IdIqMap; the torque command of the slave control chip is calculated by the torque loop in the built-in control algorithm and parsed into an id / iq current command by checking the calibration IdIqMap.

9. The multi-winding motor control method based on multi-core chip and interrupt alignment as described in claim 6, characterized in that: The current commands from the master control chip and slave control chip are used to calculate the Vd / Vq voltage commands through the current loop in the built-in control algorithm. The voltage commands are then modulated by SVPWM to calculate the required three-phase voltage values. CORE 1 calculates the PWM carrier of the dual-level IGBT switching transistor by using sector judgment and vector synthesis of the three-phase voltage values. CORE 1 controls the IGBT to turn on and output the corresponding voltage values ​​to the motor. At the same time, the master control chip's CORE 2 sends the calculated id / iq current command to the slave control chip and obtains the current status of the slave control chip; The slave controller chip's CORE 1 obtains the current feedback from the slave winding at the current moment and queries the output torque of the slave winding at the current moment according to IdIqMap; the slave controller chip's CORE 2 sends the current torque / current feedback from the slave winding to the master controller chip and obtains the current status of the master controller chip.

10. The multi-winding motor control method based on multi-core chip and interrupt alignment as described in claim 6, characterized in that: The specific steps for determining whether each control chip is in master control mode or slave control mode in step S1 are as follows: S1.1, CORE 2 initializes the master-slave interrupt GPIO and sets the resolver sampling flag to 0. At the same time, CORE 1 performs a power-on self-test on the AD sampling status. S1.2 Determine whether CORE 2 has read message information from the CAN FD port. If yes, proceed to step S1.3; otherwise, report a master-slave communication failure. S1.3 Determine whether CORE 1 has sampled the resolver sine and cosine signals and the motor temperature and resistance signals. If it has, proceed to step S1.4; otherwise, proceed to step S1.

5. S1.4, CORE 2 sets the master control resolver sampling flag to 1 and determines whether CORE 2 receives the slave control resolver sampling flag at 2. If not, it reports a master-slave communication abnormality; if it receives the flag, the control chip enters master control mode. After entering master control mode, CORE 2 sends out relevant message information according to the set period and baud rate. At the same time, the CORE 2 interrupt triggers the GPIO port to output a high level according to the software set period. If the control chip does not have any abnormal faults in the resolver or temperature sampling, or other faults, it will continue to execute the next interrupt cycle; otherwise, it will report the relevant fault information. S1.5 Determine whether CORE 2 has received the master control resolver sampling flag at position 1. If not, report a master-slave communication abnormality; if received, the control chip enters slave control mode. After entering slave mode, CORE 2 sets the slave resolver sampling flag to 2. CORE 2 reads and executes relevant message information according to the set period and baud rate. At the same time, it determines whether the interrupt trigger GPIO port set by CORE 2 is triggered. If it is triggered, CORE 2 executes a hardware interrupt and synchronizes the PWM carrier frequency duty cycle with the master control chip. If CORE 2 does not receive the main control resolver sampling flag at position 0 and there are no other faults, it will continue to execute the next interrupt cycle; otherwise, it will report the relevant fault information.

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