A tapped inductor, a resonant cavity structure, an oscillator structure, a chip and a device

Abstract

This invention discloses a tapped inductor, a resonant cavity structure, an oscillator structure, a chip, and a device, belonging to the field of electronic communication technology. The tapped inductor includes an inductor Ld and an inductor Lg; wherein, there are two coupling mechanisms between inductors Ld and Lg: electrical coupling and magnetic coupling. Electrical coupling corresponds to voltage-enhanced coupling along the current direction between inductors Ld and Lg, while magnetic coupling is the mutual inductance coupling between inductors Ld and Lg. The resonant cavity structure includes: a drain-end resonant branch, composed of inductors Ld and Cd connected in parallel; and a gate-end resonant branch, composed of inductors Lg and Cg connected in parallel. The two branches are symmetrically distributed in a differential manner, respectively connected to the drain and gate of the active part of the oscillator. The tapped inductor transformer network proposed in this invention achieves greater passive gain from the drain to the gate in the oscillator; the resonant cavity based on the electro-magnetically coupled tapped inductor solves the problem that traditional structures cannot achieve higher gains.

Description

Technical Field

[0001] This invention relates to the field of radio frequency source circuits in electronic communication technology, and particularly to an electro-magnetically coupled tapped inductor, resonant cavity structure, oscillator structure, chip, and device. Background Technology

[0002] With the rapid development of emerging electronic systems such as 5G, software-defined radio (SDR), millimeter-wave radar, and high-speed interconnect chips, higher comprehensive performance requirements are being placed on RF front-end modules, especially voltage-controlled oscillators (VCOs) in frequency synthesizers. In millimeter-wave bands such as 25GHz, an ideal VCO not only requires extremely low phase noise (PN) to improve system signal integrity and communication sensitivity, but also good stability and power efficiency to support the needs of short-range high-speed communication and highly integrated designs.

[0003] However, in advanced CMOS processes, VCOs face numerous challenges in achieving low phase noise (PN) performance due to deteriorated device noise characteristics, reduced power supply voltage, and enhanced parasitic effects. Particularly in the millimeter-wave band, the up-conversion effect of flicker noise (1 / f³) significantly worsens PN at low-frequency offsets, leading to performance bottlenecks such as signal distortion and increased bit error rate. While existing technologies have made progress in reducing phase noise and suppressing 1 / f³ noise, no single structure can comprehensively address these performance indicators within chip area constraints, making this a key challenge in current VCO design. Summary of the Invention

[0004] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide an electro-magnetically coupled tapped inductor, a resonant cavity structure, an oscillator structure, a chip, and a device.

[0005] The first technical solution adopted in this invention is:

[0006] An electro-magnetically coupled tapped inductor includes an inductor Ld and an inductor Lg, wherein one end of the inductor Ld is connected to one end of the inductor Lg;

[0007] There are two coupling mechanisms between the inductor Ld and the inductor Lg: electric coupling and magnetic coupling. Electric coupling corresponds to the voltage enhancement coupling between inductor Ld and inductor Lg along the current direction, while magnetic coupling is the mutual inductance coupling between inductor Ld and inductor Lg.

[0008] The second technical solution adopted in this invention is:

[0009] A resonant cavity structure based on the above-described electro-magnetically coupled tapped inductor includes:

[0010] The drain-end resonant branch consists of an inductor Ld and a capacitor Cd connected in parallel.

[0011] The gate-end resonant branch consists of an inductor Lg and a capacitor Cg connected in parallel.

[0012] The two branches are symmetrically distributed in a differential manner and are connected to the drain and gate of the active part of the oscillator, respectively.

[0013] The third technical solution adopted in this invention is:

[0014] An oscillator includes a first NMOS transistor, a second NMOS transistor, and a resonant cavity. The resonant cavity is implemented using the resonant cavity structure described above. The drain resonant branch includes an inductor Ld1, an inductor Ld2, and a capacitor Cd. The gate resonant branch includes an inductor Lg1, an inductor Lg2, and a capacitor Cg.

[0015] One end of the inductor Ld1 is connected to the drain of the first NMOS transistor (node ​​D1), and the other end is connected to the power supply voltage; one end of the inductor Ld2 is connected to the drain of the second NMOS transistor (node ​​D2), and the other end is connected to the power supply voltage; the two ends of the capacitor Cd are connected to nodes D1 and D2 respectively.

[0016] One end of the inductor Lg1 is connected to node D1, and the other end is connected to the gate of the second NMOS transistor (node ​​G2); one end of the inductor Lg2 is connected to node D2, and the other end is connected to the gate of the first NMOS transistor (node ​​G1); the two ends of the capacitor Cg are connected to nodes G1 and G2 respectively.

[0017] The source of the first NMOS transistor and the source of the second NMOS transistor are both grounded;

[0018] Among them, there is a magnetic coupling path (KM) between inductor Ld1 and inductor Lg1, and between inductor Ld2 and Lg2, to achieve mutual inductance; there is an electric coupling path (KE) between node D1 and node G2, and between node D2 and node G1, to form electric coupling.

[0019] The fourth technical solution adopted in this invention is:

[0020] A dual-core oscillator structure includes two symmetrical oscillation cores, wherein the oscillation cores are implemented using the oscillator described in the third technical solution;

[0021] Both oscillating cores have independent electro-magnetically coupled resonant cavities, consisting of inductors Ld and Lg and parallel capacitors Cd and Cg. The two oscillating cores are coupled together through magnetic coupling between the leakage inductance of one core and the gate inductance of the other. For example, Ld1 of the first oscillating core is coupled to Lg2 of the second oscillating core through mutual inductance.

[0022] The fifth technical solution adopted in this invention is:

[0023] A quad-core oscillator structure includes four oscillation cores, wherein the oscillation cores are implemented using the oscillator described above.

[0024] Four oscillation cores are arranged symmetrically in a ring; each core integrates an independent electro-magnetically coupled resonant cavity, including dual-drain inductors and dual-gate inductors;

[0025] The four cores are connected through fixed multi-coupling paths. The specific coupling methods are as follows: the horizontal cores connect to the leakage inductance of core1 and core3 with the gate terminals of adjacent cores through electromagnetic coupling; the vertical cores connect to core2 and core4 through cross-core mutual inductance paths in the same way as the horizontal coupling paths; all coupling paths together form a closed-loop electro-magnetic coupling network to realize a dual-path synchronization mechanism.

[0026] The sixth technical solution adopted in this invention is:

[0027] An oscillator includes a PMOS transistor, an NMOS transistor, and a resonant cavity. The resonant cavity is implemented using the resonant cavity structure described above. The drain resonant branch includes an inductor Ld1, an inductor Ld2, and a capacitor Cd. The gate resonant branch includes an inductor Lg1, an inductor Lg2, and a capacitor Cg.

[0028] The source of the PMOS transistor is connected to the power supply voltage, and the drain is connected to one end of the inductor Ld1; the other end of the inductor Ld1 is connected to one end of the inductor Ld2; the other end of the inductor Ld2 is connected to the drain of the NMOS transistor; the source of the NMOS transistor is grounded.

[0029] One end of the inductor Lg1 is connected to the drain of the PMOS transistor, and the other end is connected to the gate of the NMOS transistor; one end of the inductor Lg2 is connected to the gate of the PMOS transistor, and the other end is connected to the drain of the NMOS transistor.

[0030] The two ends of the capacitor Cd are connected to the drain of the PMOS transistor and the drain of the NMOS transistor, respectively; the two ends of the capacitor Cg are connected to the gate of the PMOS transistor and the gate of the NMOS transistor, respectively.

[0031] The seventh technical solution adopted in this invention is:

[0032] A dual-core oscillator structure includes two symmetrical oscillation cores, wherein the oscillation cores are implemented using the oscillator described above;

[0033] Both oscillating cores have independent electro-magnetically coupled resonant cavities. In each oscillating core, inductors Ld and Lg are connected in series to form a resonant branch. The two resonant branches are cross-connected to achieve a differential structure.

[0034] The eighth technical solution adopted in this invention is:

[0035] A quad-core oscillator structure is provided, consisting of two sets of independent symmetrical differential oscillator units, and multi-mode operation configuration is achieved through cross-core coupling paths. The differential oscillator units are implemented using the dual-core oscillator structure described above.

[0036] The ninth technical solution adopted in this invention is:

[0037] A dual-core oscillator structure includes two oscillating cores. The oscillating cores are implemented using the oscillator described above. The two oscillating cores are arranged symmetrically with PMOS and NMOS transistors in an alternating manner. The PMOS and NMOS transistors form a differential structure and cooperate with an electro-magnetically coupled resonant cavity to construct a differential feedback path.

[0038] The tenth technical solution adopted in this invention is:

[0039] A quad-core oscillator structure is provided, consisting of two sets of independent symmetrical differential oscillator units, and multi-mode operation configuration is achieved through cross-core coupling paths. The differential oscillator units are implemented using the dual-core oscillator structure described above.

[0040] The eleventh technical solution adopted in this invention is:

[0041] A chip comprising the circuit structures described above (tap inductor, resonant cavity structure, oscillator, dual-core oscillator structure, and quad-core oscillator structure).

[0042] The twelfth technical solution adopted in this invention is:

[0043] An electronic device comprising the chip described above.

[0044] The beneficial effects of this invention are as follows: This invention provides a tapped inductor-transformer network based on electro-magnetic coupling technology, achieving greater passive gain from the drain to the gate in the oscillator. This invention provides a resonant cavity based on an electro-magnetically coupled tapped inductor structure, solving the problem that traditional structures cannot achieve higher gains. This invention provides a dual-core extended oscillator structure based on the above resonant cavity, optimizing the inductor Q and achieving low phase noise within a compact chip area. This invention provides a quad-core extended structure based on the above dual-core oscillator structure, increasing the oscillation frequency and achieving low flicker noise across the entire bandwidth within a compact area. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the resonant cavity of the electro-magnetically coupled inductor in Embodiment 1 of the present invention;

[0047] Figure 2 This is a circuit diagram of an NMOS-only oscillator based on an electro-magnetically coupled inductor resonant cavity in Embodiment 1 of the present invention;

[0048] Figure 3 This is a dual-core extended circuit diagram of the NMOS-only oscillator based on an electro-magnetically coupled inductor resonant cavity in Embodiment 1 of the present invention;

[0049] Figure 4 This is a quad-core extended circuit diagram of the NMOS-only oscillator based on an electro-magnetically coupled inductor resonant cavity in Embodiment 1 of the present invention;

[0050] Figure 5 This is the quad-core extended inductor layout of the NMOS-only oscillator based on an electro-magnetically coupled inductor resonant cavity in Embodiment 1 of the present invention;

[0051] Figure 6 This is a circuit diagram of a traditional tapped inductor oscillator;

[0052] Figure 7 This is a diagram showing the Q value and inductance value of the inductor in Embodiment 1 of the present invention;

[0053] Figure 8 This is a simulation diagram of phase noise in Embodiment 1 of the present invention;

[0054] Figure 9 This is the FoM simulation diagram in Embodiment 1 of the present invention;

[0055] Figure 10 This is the phase noise test diagram in Embodiment 1 of the present invention;

[0056] Figure 11 This is a schematic diagram of the tuning range test results in Embodiment 1 of the present invention;

[0057] Figure 12 This is a schematic diagram of the simulation results of the transfer frequency within the tuning range in Embodiment 1 of the present invention;

[0058] Figure 13This is a physical image of the chip in Embodiment 1 of the present invention;

[0059] Figure 14 This is a schematic diagram of the differential oscillator structure in Embodiment 2 of the present invention;

[0060] Figure 15 This is a schematic diagram of the dual-core quad-mode oscillator structure in Embodiment 3 of the present invention;

[0061] Figure 16 This is a schematic diagram of the cross-coupled differential oscillator in Embodiment 4 of the present invention;

[0062] Figure 17 This is a schematic diagram of the dual-core quad-mode oscillator structure in Embodiment 5 of the present invention. Detailed Implementation

[0063] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0064] The terminology used in the embodiments of this application is for the purpose of describing specific embodiments only and is not intended to limit the embodiments of this application. The singular forms "a," "described," and "the" used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, unless otherwise expressly limited, terms such as "set," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0065] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0066] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0067] In the description of this application, "and / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship.

[0068] To address existing technical issues, researchers have attempted to optimize the VCO architecture from multiple dimensions, including: 1) Harmonic shaping techniques: By adjusting the position of harmonic impedances (such as third harmonic shaping, second harmonic filtering, etc.), harmonic currents in noise-sensitive frequency bands are suppressed, thereby improving phase noise performance. 2) Electromagnetic coupling structure: The mutual inductance effect of inductors is used to achieve energy coupling and synchronous oscillation between cores, improving the equivalent inductance quality factor (Q) and oscillation stability. 3) Noise sensitivity function (ISF) optimization: Modulation design is performed on the device's time response characteristics to noise to reduce phase jitter caused by noise injection.

[0069] Despite some progress in existing research, most solutions still suffer from the following shortcomings in 25GHz millimeter-wave applications: 1) Large area overhead: Some solutions employ multiple tail inductors for harmonic control, occupying a large chip area and hindering system integration. 2) Limited suppression range: Complex inductor matching networks struggle to achieve effective wide-band suppression of 1 / f³ noise in the millimeter-wave band. 3) High circuit complexity: Additional switching networks and bias circuits are required to support multi-mode or harmonic control, increasing design and verification burdens. 4) Limited system FoMA: There is still room for improvement in the overall trade-off between power consumption and noise performance.

[0070] To address the problem of broadband flicker noise suppression, existing technologies propose a harmonic shaping-based strategy. This involves introducing a tail-end filtering network (such as a harmonic tail inductor) and switching it on and off in different modes to suppress low-frequency (1 / f) noise. 3This paper addresses the issues of phase noise (PN) and thermal noise (1 / f²). For example, the first technical document proposes reducing the phase noise (PN) of a millimeter-wave voltage-controlled oscillator (VCO) by coupling multiple oscillating cores. Theoretically, an N-core oscillator can achieve a PN improvement of 10log(N) compared to a single core. However, in practice, frequency mismatch between cores introduces phase noise penalties, affecting overall performance. This document further proposes a dual-path synchronous quad-core oscillator structure, utilizing a toroidal transformer to construct dual coupling paths, synchronizing adjacent and non-adjacent cores respectively. This effectively suppresses PN degradation caused by frequency mismatch while maintaining high Q characteristics. The oscillator is implemented using a 65nm CMOS process, covering the 22.4–26.8GHz frequency band (tuning range 18.2%). At the 25.8GHz output frequency, the PN at a 10MHz offset is -138dBc / Hz, the power consumption is 19.7mW, and the FoM reaches 193.3dBc / Hz. However, this structure requires additional bias resistors and a complex tail inductor network, significantly increasing circuit design complexity and chip area.

[0071] The second technical document proposes a millimeter-wave quad-core VCO structure based on a toroidal twisted-wire transformer for broadband Class-F operation without manual tuning. In this structure, each coil of the toroidal transformer achieves a low inductance value while maintaining a high quality factor (Q). The twisted-wire wiring structure extends the differential-mode impedance peak, achieving Class-F harmonic shaping over a wide frequency range without the need for additional manual tuning of the second or third harmonics. Furthermore, this design introduces a passive voltage gain path from drain to gate in the oscillator resonant cavity, which helps reduce phase noise (PN). Regarding common-mode resonance, to suppress the up-conversion effect of flicker noise (1 / f³) and reduce its corner frequency, the structure employs an "8"-shaped stacked inductor to extend the peak common-mode impedance near the second harmonic. This prototype VCO achieved a 24.3% tuning range in the 18.5–23.6 GHz range, with flicker noise corner frequencies maintained between 140–250 kHz. At a 100 kHz frequency offset, the phase noise (PN) was -93.4 dBc / Hz, and the FoM peak reached 193 dBc / Hz (based on 23 GHz). While this architecture exhibits excellent performance in phase noise and low flicker noise corner frequencies, its reliance on complex active / passive circuitry (including a special transformer and common-mode inductor structure) significantly increases design complexity and chip area, resulting in insufficient system usability and portability. Furthermore, it fails to effectively address the frequency mismatch issue between cores in multi-core VCOs.

[0072] The third technical paper constructs a high-impedance resonant point using a multi-tap inductor, effectively achieving second-harmonic filtering. This results in a phase noise of -134 dBc / Hz at a 10 MHz offset point at a 12.74 GHz output frequency, while maintaining the 1 / f³ corner frequency between 190 and 300 kHz. However, this structure has limitations in achieving a wide tuning range and struggles to maintain frequency flexibility. Although this paper achieves excellent performance in a very small area, its special inductor shape prevents multi-mode broadband tuning, and its voltage gain is also lower than the former.

[0073] Based on this, the present invention provides a new technical solution to solve the following problems: 1) realize an enhanced electro-magnetic coupled inductor structure; 2) solve the noise suppression problem of harmonic shaping; 3) solve the problem of large area of ​​additional circuit chips; 4) solve the problems of small area, low phase noise and low corner frequency; 5) realize full-band noise suppression based on harmonic shaping.

[0074] Example 1:

[0075] This embodiment provides an innovative circuit structure for a broadband low-noise oscillator, with the overall architecture modularly extended around a resonant cavity constructed from an electro-magnetically coupled inductor. This circuit structure mainly includes the following four levels: 1) a resonant cavity structure based on an electro-magnetically coupled inductor, such as... Figure 1 As shown; 2) The NMOS-only single-core oscillator structure using the above resonant cavity, as shown. Figure 2 As shown; 3) An NMOS-only dual-core coupled oscillator structure extended from a single-core structure, such as... Figure 3 As shown; 4) Further extend to a quad-core oscillator structure to achieve wideband coverage and multi-mode collaborative operation, such as Figure 4 As shown; 5) Layout implementation based on the above-mentioned quad-core structure of the resonant cavity, as shown. Figure 5 As shown.

[0076] The various structures are built progressively from simple to complex, maintaining the core topology of the resonant cavity unchanged. Tuning capability, output power, and noise performance are further improved through multi-core expansion and mode multiplexing, exhibiting good scalability, reconfigurability, and area efficiency. The circuit structure and working principle of each structure are described in detail below.

[0077] (1) Circuit structure description

[0078] (1.1) Resonant cavity

[0079] Figure 1The image shows the resonant cavity structure based on an electro-magnetically coupled inductor proposed in this embodiment. As the core resonant network of the oscillator, this structure has a high Q value, high voltage gain, and harmonic suppression capability, providing excellent noise and frequency performance support for the subsequent oscillation unit.

[0080] The resonant cavity network mainly includes: Ld: an inductor connected to the drain of the active circuit; Lg: an inductor connected to the gate of the active circuit; Cd and Cg: connected in parallel with Ld and Lg respectively, forming two LC resonant circuits; parasitic resistances rd and rg: connected in series with Ld and Lg respectively, representing the parasitic resistances of the actual inductors; nodes Vd and Vg: the drain and gate voltage ports output to the active unit respectively.

[0081] More importantly, this structure introduces two coupling mechanisms simultaneously between Ld and Lg: the blue path ke represents the electrical coupling channel from Ld to Lg, forming capacitive coupling between the gate and drain; the red path km represents the magnetic coupling path between Ld and Lg, achieving coordinated resonant response through mutual inductance.

[0082] The two coupling mechanisms mentioned above work together to form a novel electro-magnetic hybrid coupling (E-M mixed Coupled) structure, which essentially enhances the voltage gain between the drain and the gate, helping to reduce the noise figure of the oscillator.

[0083] (1.2) Single-core oscillator

[0084] Figure 2 The following is based on Figure 1 The proposed electro-magnetically coupled resonant cavity structure is used to construct an NMOS-only single-core differential oscillator circuit. This structure, while maintaining the core of the resonant cavity, combines active cross-coupled transistors to form a complete oscillation unit, possessing advantages such as low phase noise, high gain, and process friendliness.

[0085] See Figure 2The NMOS-only single-core differential oscillator includes: two sets of drain inductors Ld1 and Ld2, one end of which is connected to the power supply voltage terminal VDD, and the other end is connected to the drain nodes D1 and D2 of transistors M1 and M2, respectively; a drain parallel capacitor Cd connected between nodes D1 and D2; two sets of gate inductors Lg1 and Lg2, one end of inductor Lg1 connected to node D1 and the other end connected to the gate node G2 of M2, and one end of inductor Lg2 connected to node D2 and the other end connected to the gate node G1 of M1; and a gate capacitor Cg connected between G1 and G2. Transistors M1 and M2 are N-type MOS transistors, with their drains connected to nodes D1 and D2 respectively, and their sources connected to a common node. They are connected to ground (VSS) via a series tail inductor Ltail, where Ltail represents the parasitic inductance of the tail trace in the actual circuit layout. The gate of transistor M1 is connected to node G1, and the gate of transistor M2 is connected to node G2, forming a cross-coupled structure. There are magnetic coupling paths (KM) between inductors Ld1 and Lg2, and between Ld2 and Lg1, to achieve mutual inductance. There are electrical coupling paths (KE) between nodes D1 and G2, and between D2 and G1, to form electrical coupling.

[0086] (1.3) Dual-core oscillator

[0087] Figure 3 This embodiment provides a dual-core oscillator circuit structure based on an electro-magnetically coupled resonant cavity. The circuit includes two sets of symmetrical, cross-coupled NMOS-only oscillating units, labeled as the left core and the right core, respectively. The device connections of each core are as follows:

[0088] The core oscillation section on the left: cross-coupled NMOS transistors M1 and M1', with their sources connected to a set of tail inductors and then grounded; the gate of M1 is connected to node G1, and the gate of M1' is connected to G1'; the drains D1 and D1' are connected to the upper drain inductor Ld1 and the lower drain inductor Ld1', respectively; the upper end of Ld1 is connected to the power supply VDD, and the lower end of Ld1' is connected to ground; node G1 is connected to the upper end of the gate inductor Lg1, and the other end is connected to D1; node G1' is connected to the lower side of the gate inductor Lg1', and the other end is connected to D1'.

[0089] The right-side oscillation core consists of cross-coupled NMOS transistors M2 and M2', with their sources connected to the tail inductor and then grounded. The gate of M2 is connected to G2', and the gate of M2' is connected to G2. The drains D2 and D2' are connected to the drain inductors Ld2 and Ld2', respectively, and are connected to the power supply VDD and ground. The gates G2 and G2' are connected to the drains D2 and D2' through the gate inductors Lg2 and Lg2', respectively.

[0090] Inter-core coupling relationships: There are magnetic coupling paths marked with red arrows between the left and right cores, between Ld1 and Lg2, and between Ld2 and Lg1, labeled KM; there are also corresponding magnetic coupling paths KM between the two cores in the lower half; in addition, the gray path KM′ marked in the figure represents the coupling enhancement path introduced by the drain inductance of another core, that is, the Ld of the first core forms enhanced mutual inductance to the Lg of the second core.

[0091] (1.4) Quad-core oscillator

[0092] Figure 4 This is a schematic diagram of a quad-core oscillator based on an electro-magnetic coupling structure provided in this embodiment. The oscillator consists of four cross-coupled oscillating cores (core#1 to core#4), which are arranged symmetrically in a circular ring to form a closed ring quad-core coupled system.

[0093] The specific structure and connection relationships are as follows:

[0094] Oscillating Core: Each core consists of a pair of cross-coupled transistors, with its source grounded and its drain connected to the power supply VDD via a pair of series inductors (LD1, LD2). The gate of each core is coupled to the drain path of the adjacent core via dual gate inductors (LG1_1, LG1_2 and LG2_1, LG2_2).

[0095] Inductor Network and Magnetic Coupling Path: The peripheral inductor network arranged in a ring around the oscillator simultaneously carries the functions of differential mode oscillation and magnetic coupling. Adjacent cores achieve cross magnetic coupling through the drain-gate coupling path (as shown in KDG1, KDG2, KGG), thereby forming a multi-path feedback enhancement path, improving synchronization and suppressing phase noise degradation caused by frequency mismatch.

[0096] Dual-path synchronization mechanism: Figure 4 The coupling paths indicated by the middle arrow include direct coupling between adjacent cores and cross coupling between diagonally opposite cores. This dual-path coupling method helps improve the overall synchronization performance of a quad-core system and reduces frequency mismatch effects.

[0097] Power supply structure: Each core is independently connected to VDD, and power is supplied in a symmetrical manner from top to bottom and left to right to form a stable power distribution network; the ground (VSS) terminal is uniformly connected to the common ground structure at the bottom of the chip.

[0098] This structure makes full use of the quad-core layout and magnetic coupling enhancement mechanism to achieve low phase noise while maintaining a high quality factor (Q), and has good scalability and structural symmetry, making it suitable for high-performance millimeter-wave oscillator applications.

[0099] Figure 5This diagram illustrates the physical layout of a quad-core inductor based on an electro-magnetic coupling structure. The diagram shows the device layout-level wiring view, including the physical distribution of gate and drain inductors, power supply paths, and the coupling network between the four cross-coupled oscillating cores. The drain of each oscillating core is connected to the power supply VDD via two series-connected drain inductors LD1 and LD2. The gate of each oscillating core is connected to the drain path of the adjacent core via two sets of series-connected gate inductors LG1_1→LG1_2 and LG2_1→LG2_2, forming an electro-magnetic cross-coupling. These inductors are arranged in a ring interconnection between the core cells, forming a closed coupling network between the four cores. The central region consists of four cross-coupled NMOS cores, surrounded by four sets of inductors. All connections are directly implemented through metal wiring, eliminating the need for additional switching components. This connection structure ensures a fixed mutual inductance coupling path between the four cores, achieving frequency synchronization and low phase noise characteristics.

[0100] (2) Explanation of circuit working principle

[0101] The oscillator resonant cavity used in this embodiment is as follows: Figure 1 As shown, it mainly consists of two inductors (Ld and Lg) and their respective parasitic resistances and parallel capacitances (Cd and Cg). Ld and Cd form the drain-end resonant branch, while Lg and Cg form the gate-end resonant branch. The two branches are symmetrically distributed in a differential manner and are connected to the drain and gate of the active section of the oscillator, respectively. This resonant cavity is the core of the entire oscillator for frequency selection and energy storage.

[0102] In this structure, there are two coupling mechanisms between Ld and Lg: electrical coupling ke (represented by the blue path), which corresponds to the voltage enhancement coupling between Ld and Lg along the current direction, providing direct voltage coupling from the drain signal to the gate; and magnetic coupling km (represented by the red path), which is the mutual inductive coupling between Ld and Lg, using shared magnetic flux to achieve inductive energy transfer.

[0103] These two coupling paths work together to form an electro-magnetic hybrid coupling structure.

[0104] In an oscillator, the resonant cavity plays a crucial role in setting the oscillation frequency, storing energy to maintain oscillation, suppressing noise, and enhancing positive feedback. The electro-magnetically coupled resonant cavity used in this embodiment not only improves the voltage gain and oscillation start-up capability, but also reduces active noise through the coupling mechanism, achieving effective 1 / f³ noise suppression. This is the core foundation for realizing a low-noise, high-performance oscillator.

[0105] Figure 6The diagram shows a traditional tapped inductor oscillator, which achieves electrical coupling by introducing a capacitive voltage divider structure between Ld and Lg, thereby obtaining a voltage boost at the gate relative to the drain, which in turn drives the cross-coupled NMOS pair to maintain oscillation. In this structure, the voltage gain Av mainly depends on the capacitive coupling path from Ld to Lg, and Av > 1 can typically be achieved.

[0106] The embodiment proposed Figure 2 In the architecture, based on Figure 1 The electro-magnetically coupled resonant cavity structure in this design introduces a magnetic coupling path while maintaining electrical coupling, achieving energy transfer through the mutual inductance between Ld and Lg. This dual electro-magnetic coupling significantly improves the equivalent voltage gain Av, resulting in a larger gate voltage swing.

[0107] A higher Av not only improves the oscillator's start-up margin and amplitude stability, but also directly results in better noise performance. According to the noise theory of two-port networks, the oscillator's noise figure can be expressed as:

[0108] NF=1+γ / Av

[0109] Where γ is the transistor noise figure. It can be seen that the larger Av is, the less noise the system introduces into the transistor itself, thus effectively reducing the output phase noise.

[0110] Therefore, compared with traditional electrically coupled oscillators, this embodiment significantly improves the gain through electro-magnetic hybrid coupling under the NMOS-only architecture, thereby obtaining a lower noise figure and better phase noise performance, which constitutes the key foundation for realizing a broadband low-noise oscillator.

[0111] Figure 3 The diagram shows a dual-core NMOS-only oscillator structure based on an electro-magnetically coupled resonant cavity. This structure consists of two... Figure 2 It is composed of single-core structures, each core having an independent electro-magnetic coupled resonant cavity, consisting of inductors Ld and Lg and parallel capacitors Cd and Cg.

[0112] In this structure, the two cores are coupled together via magnetic coupling between the leakage inductance of one core and the gate inductance of the other. Specifically, Ld1 of the first oscillating core is coupled to Lg2 of the second oscillating core through mutual inductance, and vice versa. This coupling path not only maintains the signal transmission and phase relationship between the cores, but also forms a cross-core feedback path.

[0113] The coupling structure enables the two sets of resonant cavities to achieve frequency coupling resonance, allowing the oscillation signal to share energy between the two cores. The cross-coupled NMOS transistors form positive feedback paths within their respective cores, maintaining the oscillation conditions. Due to the existence of the gate-drain coupling path across the cores, the gate voltage of each core, in addition to the feedback from its own resonant cavity, is also superimposed with the induced signal from the other core, thus jointly driving the cross-coupled unit.

[0114] Figure 7 Simulation results of the inductor equivalent quality factor (Q value) under this structure are presented, showing that the frequency response of the resonant cavity is more concentrated after the introduction of the coupling path, reflecting the effective resonance synergy formed among multiple oscillating cores.

[0115] This structure maintains an NMOS-only form, with all active devices still being N-type MOSFETs. The resonant frequency is determined by the LC network of each core, and the coupling coefficient is set by the inductor layout and mutual inductance parameters, making it suitable for subsequent multi-core expansion and mode configuration.

[0116] Figure 4 The figure shown is a quad-core high-performance NMOS-only oscillator structure proposed in this embodiment. Figure 3 Based on the dual-core oscillator shown, a closed-loop electro-magnetic coupling system was constructed through extension and optimization, aiming to achieve lower phase noise and stronger frequency synchronization performance.

[0117] The structure consists of four cross-coupled NMOS oscillator cores (Core#1 to Core#4), arranged symmetrically in a ring. Each core unit integrates an independent electro-magnetically coupled resonant cavity, including dual drain inductors (LD1, LD2) and dual gate inductors (LG1_1, LG1_2, LG2_1, LG2_2), forming a high QLC network with both differential-mode and common-mode coupling paths.

[0118] The four cores are connected via fixed multi-path coupling, without relying on any programmable switches or polarity adjustment devices, resulting in stable and symmetrical coupling. The specific coupling methods are as follows: Horizontal core pairs (Core#1 and Core#2, Core#3 and Core#4) establish lateral magnetic coupling through the mutual inductance path between their leakage inductance and the gate inductance of adjacent cores; vertical core pairs (Core#1 and Core#4, Core#2 and Core#3) establish vertical coupling using a similar cross-core mutual inductance path; all coupling paths together form a closed-loop electro-magnetic coupling network, achieving a dual-path synchronization mechanism and simultaneously improving the cooperative oscillation performance between adjacent and non-adjacent cores.

[0119] This quad-core structure excels in improving oscillator output amplitude, reducing phase noise (PN) penalty caused by frequency mismatch, and enhancing synchronization stability, making it particularly suitable for high-performance frequency synthesis scenarios in the millimeter-wave band.

[0120] (3) Advantages and beneficial effects

[0121] Compared with the prior art, the structure provided in this embodiment has at least the following advantages:

[0122] 1) This embodiment proposes a tapped inductor-transformer network based on electro-magnetic coupling technology, which realizes a larger passive gain from the drain to the gate in the oscillator.

[0123] 2) This embodiment proposes a device noise suppression technique without harmonic shaping, which can achieve low corner frequency without introducing additional circuitry into the oscillator.

[0124] 3) The quad-core oscillator proposed in this embodiment solves the problem of simultaneously achieving small area, low phase noise and low rotation frequency.

[0125] The VCO proposed in this embodiment is implemented using a 65nm bulk CMOS process, and its power consumption is 14.8-15.3mW at a power supply voltage (VDD) of 0.45V. The actual chip is shown below. Figure 13 As shown, the core area is 0.044 mm². Figure 11 The measured tuning range (FTR) of the oscillator is given. Figure 10 Phase noise (PN) curves are presented, with an FTR of 22 GHz to 26.8 GHz and a total coverage of 19.7%. At a 100 kHz offset frequency, the phase noise at the GHz frequency point is as follows. Figure 8 The simulation results for phase noise across the entire tuning range are shown at the following frequency offsets: 100kHz: lowest frequency -96.21dBc / Hz, highest frequency -86.28dBc / Hz; 1MHz: lowest frequency -118.1dBc / Hz, highest frequency -114.5dBc / Hz; and 10MHz: lowest frequency -138.4dBc / Hz, highest frequency -137.9dBc / Hz. (Participants...) Figure 9 The simulation results for FoM at 100kHz, 1MHz, and 10MHz are 191.8dBc / Hz, 193.6, and 195.5, respectively. See [link / reference]. Figure 12 The 1 / f³ phase noise corner frequency of the device appears in the range of 80-1200kHz.

[0126] Example 2:

[0127] See Figure 14Based on the resonant cavity in Embodiment 1, this embodiment provides a schematic diagram of a differential oscillator structure including PMOS and NMOS devices, which has an electro-magnetically coupled resonant cavity and symmetrical power supply paths at the top and bottom.

[0128] The circuit includes the following structural connections: two sets of PMOS transistors PM1 and PM2, with their sources connected to the power supply VDD and their drains connected to nodes d1′ and d2′ respectively; two sets of NMOS transistors NM1 and NM2, with their drains connected to nodes d1 and d2 respectively and their sources connected to ground VSS; a differential resonant cavity is connected between each set of PMOS and NMOS transistors, specifically including: the left branch includes inductors Ld1, Lg1 and Ld2, Lg2, connected to nodes d1 and d2 respectively; the right branch includes inductors Ld1′, Lg1′ and Ld2′, Lg2′, connected to nodes d1′ and d2′ respectively;

[0129] Each set of Ld and Lg inductors is connected in series to form a resonant branch; the left and right branches are cross-connected to achieve a differential structure: the output terminals of Lg1 and Lg2′ are connected respectively; the output terminals of Lg2 and Lg1′ are connected respectively; there is a magnetic coupling path between inductors Ld2 and Lg2′, and between Ld1 and Lg1′, marked as KM, to indicate the electro-magnetic coupling mechanism.

[0130] Example 3:

[0131] like Figure 15 As shown, this embodiment provides a dual-core quad-mode oscillator structure, which in... Figure 14 Based on this, it is expanded to consist of two sets of independent symmetrical differential oscillator units, and achieves multi-mode operation configuration through cross-core coupling path.

[0132] The circuit includes:

[0133] The first group (left side) of the differential oscillator unit contains two sets of cross-structure transistors: PMOS transistors PM 1-1 With PM 2-1 Its source is connected to VDD, and its drain is connected to nodes d1′_1 and d2′_1 respectively; NMOS transistor NM 1-1 With NM 2-1 Its drain is connected to nodes d1_1 and d2_1 respectively, and its source is connected to ground VSS;

[0134] Resonant cavity structure: Node d1_1 is connected to inductor Ld1_1 in series with gate inductor Lg1_1; Node d2_1 is connected to inductor Ld2_1 in series with gate inductor Lg2_1; Symmetrical paths Ld1′_1-Lg1′_1 and Ld2′_1-Lg2′_1 form a differential structure with it; Inductive coupling path KM exists between Ld2_1 and Lg2′_1, and between Ld1_1 and Lg1′_1.

[0135] Second group (right side) differential oscillator unit (structure completely symmetrical to the left side): PMOS: PM 1-2 With PM 2-2 NMOS: NM 1-2 With NM 2-2 ;

[0136] Inductor paths: Ld1_2-Lg1_2, Ld2_2-Lg2_2, Ld1′_2-Lg1′_2, Ld2′_2-Lg2′_2; Inductive coupling path KMK_MKM is located within the second group, such as... Figure 15 As shown.

[0137] Dual-mode coupling path: In the diagram, Kmode, indicated by the blue arrow, represents a cross-group coupling path, connecting the inductors of the left group with the corresponding inductors of the right group (e.g., Lg to Lg or Ld to Ld). Kmode can be used for mode switching or to activate multi-mode cooperative operation. The path is defined by the design, and the connection relationship is as follows: Figure 15 As shown.

[0138] Example 4:

[0139] See Figure 16 This embodiment provides a cross-coupled differential oscillator with a symmetrical power supply structure. The circuit shown uses PMOS and NMOS arranged symmetrically and alternately. The PMOS and NMOS form a differential structure and are used in conjunction with an electro-magnetic coupled resonant cavity to construct a differential feedback path.

[0140] The circuit connections are as follows: Active device section: Left side includes: PMOS transistor PM1, whose source is connected to VDD above, and whose drain is connected to the drain of NMOS transistor NM1; the source of NMOS transistor NM1 is connected to ground VSS; Right side includes: PMOS transistor PM2, whose source is connected to VDD above, and whose drain is connected to the drain of NMOS transistor NM2; the source of NMOS transistor NM2 is connected to ground VSS.

[0141] Resonant cavity structure: The left branch consists of two series resonant paths: the upper branch is Ld1-Lg1, connected to the common node of PM1 / NM1 respectively; the lower branch is Ld2-Lg2, connected to the lower part of the symmetrical structure of PM1 / NM1; the right branch structure is completely symmetrical with the left: the upper branch is Ld1'-Lg1'; the lower branch is Ld2'-Lg2'; each group of inductors forms a series LC resonant path for signal feedback and frequency selection. Coupling path: The red arrow marks the magnetic coupling path K_M, which acts on: Ld1 and Lg1'; Ld2 and Lg2' respectively; all coupling paths are connected in a cross-arm manner, providing energy coupling between differential paths.

[0142] Example 5:

[0143] Figure 17 This diagram shows a circuit connection diagram of a dual-core quad-mode oscillator structure according to this embodiment. Figure 16 Based on this, it is expanded to consist of two sets of independent symmetrical differential oscillator units, and achieves multi-mode operation configuration through cross-core coupling path.

[0144] The circuit includes: the first group (left side) of differential oscillator units: containing two sets of cross-structure transistors: PMOS transistors PM 1-1 With PM 2-1 Its source is connected to VDD, and its drain is connected to nodes d1′_1 and d2′_1 respectively; NMOS transistor NM 1-1 With NM 2-1 Its drain is connected to nodes d1_1 and d2_1 respectively, and its source is connected to ground VSS;

[0145] Resonant cavity structure: Node d1_1 is connected to inductor Ld1_1 in series with gate inductor Lg1_1; Node d2_1 is connected to inductor Ld2_1 in series with gate inductor Lg2_1; symmetrical paths Ld1′_1-Lg1′_1 and Ld2′_1-Lg2′_1 form a differential structure with it; inductive coupling path K_M exists between Ld2_1 and Lg2′_1, and between Ld1_1 and Lg1′_1. Second group (right side) differential oscillator unit: PMOS: PM 1-2 With PM 2-2 NMOS: NM 1-2 With NM 2-2 Inductor paths: Ld1_2-Lg1_2, Ld2_2-Lg2_2, Ld1′_2-Lg1′_2, Ld2′_2-Lg2′_2; Inductor coupling path K_M is located inside the second group.

[0146] Dual-mode coupling path: K_mode, marked with a blue arrow in the figure, represents a cross-group coupling path, connecting the inductor of the left group with the corresponding inductor of the right group (such as Lg to Lg or Ld to Ld).

[0147] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0148] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made based on the essence of the content of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A dual-core oscillator structure, characterized in that, It consists of two symmetrical oscillating cores, each with an independent electro-magnetically coupled resonant cavity, composed of inductors Ld and Lg and parallel capacitors Cd and Cg. The two oscillating cores are coupled together through magnetic coupling between the leakage inductance of one core and the gate inductance of the other core. There are two coupling mechanisms between inductors Ld and Lg: electrical coupling and magnetic coupling. Electrical coupling corresponds to voltage-enhanced coupling along the current direction between inductors Ld and Lg, while magnetic coupling is the mutual inductance coupling between inductors Ld and Lg. The oscillation core includes a first NMOS transistor, a second NMOS transistor, and a resonant cavity; The resonant cavity includes a drain resonant branch and a gate resonant branch; The drain resonant branch includes inductor Ld1, inductor Ld2 and capacitor Cd, and the gate resonant branch includes inductor Lg1, inductor Lg2 and capacitor Cg. One end of the inductor Ld1 is connected to the drain of the first NMOS transistor, which is denoted as node D1, and the other end is connected to the power supply voltage; one end of the inductor Ld2 is connected to the drain of the second NMOS transistor, which is denoted as node D2, and the other end is connected to the power supply voltage; the two ends of the capacitor Cd are connected to nodes D1 and D2 respectively. One end of the inductor Lg1 is connected to node D1, and the other end is connected to the gate of the second NMOS transistor, which is denoted as node G2; one end of the inductor Lg2 is connected to node D2, and the other end is connected to the gate of the first NMOS transistor, which is denoted as node G1; the two ends of the capacitor Cg are connected to nodes G1 and G2 respectively. The source of the first NMOS transistor and the source of the second NMOS transistor are both grounded; Among them, there are magnetic coupling paths between inductors Ld1 and Lg1, and between inductors Ld2 and Lg2, to achieve mutual inductance; there are electrical coupling paths between nodes D1 and G2, and between nodes D2 and G1, to form electrical coupling.

2. A quad-core oscillator structure, characterized in that, It includes four oscillation cores; Four oscillation cores are arranged symmetrically in a ring; each core integrates an independent electro-magnetically coupled resonant cavity, including dual-drain inductors and dual-gate inductors; The four cores are connected through fixed multi-path coupling, and the specific coupling method is as follows: the horizontal cores connect to the leakage inductance of core1 and core3 through electromagnetic coupling to the gate of the adjacent cores to form electromagnetic coupling; the vertical cores connect to core2 and core4 through cross-core mutual inductance paths in the same way as the horizontal coupling path to form vertical coupling; all coupling paths together form a closed-loop electro-magnetic coupling network to realize the dual-path synchronization mechanism. The oscillation core includes a first NMOS transistor, a second NMOS transistor, and a resonant cavity; The resonant cavity includes a drain resonant branch and a gate resonant branch; The drain-end resonant branch includes inductors Ld1 and Ld2 and capacitor Cd, and the gate-end resonant branch includes inductors Lg1, Lg2 and capacitor Cg. There are two coupling mechanisms between inductors Ld and Lg: electrical coupling and magnetic coupling. Electrical coupling corresponds to voltage enhancement coupling along the current direction between inductors Ld and Lg, while magnetic coupling is mutual inductance coupling between inductors Ld and Lg. One end of the inductor Ld1 is connected to the drain of the first NMOS transistor, which is denoted as node D1, and the other end is connected to the power supply voltage; one end of the inductor Ld2 is connected to the drain of the second NMOS transistor, which is denoted as node D2, and the other end is connected to the power supply voltage; the two ends of the capacitor Cd are connected to nodes D1 and D2 respectively. One end of the inductor Lg1 is connected to node D1, and the other end is connected to the gate of the second NMOS transistor, which is denoted as node G2; one end of the inductor Lg2 is connected to node D2, and the other end is connected to the gate of the first NMOS transistor, which is denoted as node G1; the two ends of the capacitor Cg are connected to nodes G1 and G2 respectively. The source of the first NMOS transistor and the source of the second NMOS transistor are both grounded; Among them, there are magnetic coupling paths between inductors Ld1 and Lg1, and between inductors Ld2 and Lg2, to achieve mutual inductance; there are electrical coupling paths between nodes D1 and G2, and between nodes D2 and G1, to form electrical coupling.

3. A dual-core oscillator structure, characterized in that, It includes two symmetrical oscillating cores; Both oscillating cores have independent electro-magnetically coupled resonant cavities. In each oscillating core, inductors Ld and Lg are connected in series to form a resonant branch. The two resonant branches achieve a differential structure through cross-connection. There are two coupling mechanisms between inductors Ld and Lg: electrical coupling and magnetic coupling. Electrical coupling corresponds to voltage enhancement coupling along the current direction between inductors Ld and Lg, while magnetic coupling is the mutual inductance coupling between inductors Ld and Lg. The oscillation core includes a PMOS transistor, an NMOS transistor, and a resonant cavity; The resonant cavity includes a drain resonant branch and a gate resonant branch; The drain resonant branch includes inductor Ld1, inductor Ld2 and capacitor Cd, and the gate resonant branch includes inductor Lg1, inductor Lg2 and capacitor Cg. The source of the PMOS transistor is connected to the power supply voltage, and the drain is connected to one end of the inductor Ld1; the other end of the inductor Ld1 is connected to one end of the inductor Ld2; the other end of the inductor Ld2 is connected to the drain of the NMOS transistor; the source of the NMOS transistor is grounded. One end of the inductor Lg1 is connected to the drain of the PMOS transistor, and the other end is connected to the gate of the NMOS transistor; one end of the inductor Lg2 is connected to the gate of the PMOS transistor, and the other end is connected to the drain of the NMOS transistor. The two ends of the capacitor Cd are connected to the drain of the PMOS transistor and the drain of the NMOS transistor, respectively; the two ends of the capacitor Cg are connected to the gate of the PMOS transistor and the gate of the NMOS transistor, respectively.

4. A quad-core oscillator structure, characterized in that, It consists of two sets of independent symmetrical differential oscillator units and achieves multi-mode operation configuration through cross-core coupling path. The differential oscillator unit adopts the dual-core oscillator structure described in claim 3.

5. A dual-core oscillator structure, characterized in that, It includes two oscillation cores, in which PMOS and NMOS transistors are arranged alternately and symmetrically. The PMOS and NMOS transistors form a differential structure and are used in conjunction with an electro-magnetic coupling resonant cavity to construct a differential feedback path. The oscillation core includes a PMOS transistor, an NMOS transistor, and a resonant cavity; The resonant cavity includes a drain resonant branch and a gate resonant branch; The drain-end resonant branch includes inductors Ld1 and Ld2 and capacitor Cd, and the gate-end resonant branch includes inductors Lg1, Lg2 and capacitor Cg. There are two coupling mechanisms between inductors Ld and Lg: electrical coupling and magnetic coupling. Electrical coupling corresponds to voltage enhancement coupling along the current direction between inductors Ld and Lg, while magnetic coupling is mutual inductance coupling between inductors Ld and Lg. The source of the PMOS transistor is connected to the power supply voltage, and the drain is connected to one end of the inductor Ld1; the other end of the inductor Ld1 is connected to one end of the inductor Ld2; the other end of the inductor Ld2 is connected to the drain of the NMOS transistor; the source of the NMOS transistor is grounded. One end of the inductor Lg1 is connected to the drain of the PMOS transistor, and the other end is connected to the gate of the NMOS transistor; one end of the inductor Lg2 is connected to the gate of the PMOS transistor, and the other end is connected to the drain of the NMOS transistor. The two ends of the capacitor Cd are connected to the drain of the PMOS transistor and the drain of the NMOS transistor, respectively; the two ends of the capacitor Cg are connected to the gate of the PMOS transistor and the gate of the NMOS transistor, respectively.

6. A quad-core oscillator structure, characterized in that, It consists of two sets of independent symmetrical differential oscillator units and achieves multi-mode operation configuration through cross-core coupling path. The differential oscillator unit adopts the dual-core oscillator structure described in claim 5.

7. A chip, characterized in that, This includes the dual-core oscillator structure of claim 1, the quad-core oscillator structure of claim 2, the dual-core oscillator structure of claim 3, the quad-core oscillator structure of claim 4, the dual-core oscillator structure of claim 5, or the quad-core oscillator structure of claim 6.

8. An electronic device, characterized in that, Includes the chip described in claim 7.

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