Quickly-started high-precision relaxation oscillator

Abstract

The invention discloses a quick-start high-precision relaxation oscillator, and the relaxation oscillator comprises a reference voltage generation module which is used for generating a first reference voltage and a second reference voltage; the capacitor charging and discharging module is used for generating first and second real-time voltages which change periodically; the bypass reference voltage generation module is electrically connected with the reference voltage generation module and is used for generating bypass reference voltage based on the second reference voltage; the charging and discharging control module is electrically connected with the reference voltage generation module and the capacitor charging and discharging module and is used for controlling the capacitor charging and discharging module to alternately charge and discharge based on the first reference voltage and the first and second real-time voltages; the bypass control module is electrically connected with the reference voltage generation module and the bypass reference voltage generation module, and is used for controlling the charging current multiple of the capacitor charging and discharging module based on the first reference voltage and the bypass reference voltage. According to the invention, high-precision frequency output of the oscillator in a wide voltage and wide temperature range can be realized, and a stable and quick starting effect can be achieved in a second period.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of oscillators, and more particularly relates to a high-precision relaxation oscillator with fast start-up. BACKGROUND

[0002] Oscillator circuits, as the core clock supply units of chips, provide basic clock signals for the timing synchronization and logic operation of various electronic systems, and their performance directly determines the running accuracy and stability of the chips. Currently, the mainstream oscillator circuits are mainly divided into relaxation oscillators, ring oscillators, crystal oscillators, etc., among which the relaxation oscillators are widely used in many medium and high-end chip application scenarios due to their relatively simple structure and controllable cost.

[0003] In high-precision chip products (such as precision measuring instruments, high-end industrial control chips, medical electronic devices, etc.), strict requirements are put forward for the accuracy and stability of the clock signal. Specifically, the chip often needs to run in a complex working environment, and the fluctuation of the power supply voltage (such as the voltage fluctuation caused by the load change of the power supply system) and the drastic change of the working temperature (such as the wide temperature range of -40℃ to 125℃ in industrial sites) are common working conditions, which requires the oscillator to always output a frequency-stable clock signal when the above variables change, so as to avoid problems such as data processing errors and measurement accuracy reduction caused by clock drift.

[0004] At the same time, in real-time response application scenarios (such as fast-starting sensor nodes, emergency processing circuits, high-frequency data acquisition modules, etc.), the start-up speed of the oscillator becomes a key performance indicator. Traditional oscillators mostly adopt a feedback structure, and the clock signal needs to go through multiple oscillation periods before reaching a stable output state. This delay characteristic is difficult to meet the application requirements of explicit start-up speed, which may lead to risks such as system response lag, data loss or start-up failure.

[0005] In the prior art, there are mainly two typical solutions to the stability and start-up speed of the oscillator, but both have obvious defects: One is a simplified structure relaxation oscillator, as shown in Figure 4 , which realizes oscillation by means of a simple RC charging and discharging circuit and a comparator. Although it can start up quickly (the first period can output a stable frequency), the period formula T=kRC+T_dly contains the comparator delay term T_dly. Since the comparator delay is significantly affected by temperature and power voltage, the environmental adaptability of the output frequency of this type of oscillator is poor, and it cannot meet the stability requirements of high-precision scenarios.

[0006] The other is an improved oscillator based on an op-amp voltage regulator, as shown in Figure 5As shown, the reference voltage Vref_int is stabilized by the operational amplifier, the influence of the comparator delay on the period is eliminated, the period formula is simplified to T=kRC, and the frequency stability is improved. However, in this structure, the ratio of the integral capacitor Cint to the charge-discharge capacitor Cx is large, and the operational amplifier is in the loop and needs to have high open-loop gain to suppress the reference voltage mismatch error, resulting in a long circuit stable time of 10-20 periods, and the starting speed is seriously insufficient.

[0007] Therefore, it is a key to solve the current technical bottleneck and meet the application requirements of high-precision fast response chips to develop an oscillator circuit that can maintain stable output frequency under different power supply voltages and different temperature conditions, and has the characteristics of fast starting. SUMMARY

[0008] The purpose of the present application is to provide a fast-starting high-precision relaxation oscillator, which solves the technical problem that the existing oscillator cannot balance the output frequency stability and fast-starting performance under different power supply voltages and temperatures, and the stability and starting speed of the oscillator are difficult to coexist in high-precision scenarios, realizes high-precision frequency output of the oscillator in a wide voltage and temperature range, and achieves fast starting effect in the second cycle.

[0009] To achieve the above-mentioned purpose, the present application provides a fast-starting high-precision relaxation oscillator, comprising: a reference voltage generation module for generating a first reference voltage and a second reference voltage; a capacitor charging and discharging module for generating a periodically changing first real-time voltage and a second real-time voltage by alternating charging and discharging, and then forming a periodic oscillation signal; a bypass reference voltage generation module electrically connected with the reference voltage generation module, for generating a bypass reference voltage based on the second reference voltage; a charging and discharging control module electrically connected with the reference voltage generation module and the capacitor charging and discharging module, respectively, the charging and discharging control module being used for controlling the capacitor charging and discharging module to alternately charge and discharge based on the first reference voltage, the first real-time voltage and the second real-time voltage; a bypass control module electrically connected with the reference voltage generation module and the bypass reference voltage generation module, respectively, for controlling the charging current multiple of the capacitor charging and discharging module based on the first reference voltage and the bypass reference voltage.

[0010] Optionally, the reference voltage generation module comprises: a first current source, a first resistor, a second resistor and a third resistor connected in series; the first current source is connected to a current reference bus; the output end of the first reference voltage is arranged between the first resistor and the second resistor; The output end of the second reference voltage is arranged between the second resistor and the third resistor. The output end of the third resistor is electrically connected with the ground end.

[0011] Optionally, the capacitor charging and discharging module comprises: a second current source, a third current source, a first control switch, a second control switch, a third control switch, a fourth control switch, a first bypass switch, a second bypass switch, a first capacitor and a second capacitor; The second current source and the third current source are connected to the current reference bus; The first control switch and the second control switch are connected in parallel to the second current source, and the first bypass switch and the second bypass switch are connected in parallel to the third current source; The first control switch is connected in series with the first capacitor, and the second control switch is connected in series with the second capacitor; The third control switch is connected in parallel to the first control switch with the first capacitor, and the fourth control switch is connected in parallel to the second control switch with the second capacitor; The output end of the first real-time voltage is arranged between the first control switch and the first capacitor; The output end of the second real-time voltage is arranged between the second control switch and the second capacitor; The other end of the first bypass switch is connected to the output end of the first real-time voltage, and the other end of the second bypass switch is connected to the output end of the second real-time voltage; The output ends of the first capacitor, the second capacitor, the third control switch and the fourth control switch are electrically connected with the ground end; The first capacitor and the second capacitor are the same.

[0012] Optionally, the bypass reference voltage generating module comprises: a fourth current source, a fifth control switch, a sixth control switch, a unit gain negative feedback operational amplifier, a first bypass capacitor and a second bypass capacitor; The fourth current source is connected to the current reference bus; The input end of the fifth control switch is connected to the output end of the fourth current source; The output end and the inverting end of the unit gain negative feedback operational amplifier are connected to the output end of the fifth control switch, and the non-inverting end is connected to the output end of the second reference voltage; The input end of the first bypass capacitor is connected to the output end of the fourth current source, and the output end is electrically connected with the ground end; An input terminal of the second bypass capacitor is connected to an output terminal of the fifth control switch, and an output terminal thereof is electrically connected to the ground terminal; An output terminal of the bypass reference voltage is arranged between the fourth current source and the first bypass capacitor; The sixth control switch is connected in parallel with the first bypass capacitor.

[0013] Optionally, the charge-discharge control module comprises: The first comparator, the second comparator, the latch composed of the first NAND gate and the second NAND gate, the first inverter and the second inverter; A non-inverting terminal of the first comparator is electrically connected to the output terminal of the first reference voltage, and an inverting terminal thereof is electrically connected to the output terminal of the first real-time voltage; A non-inverting terminal of the second comparator is electrically connected to the output terminal of the first reference voltage, and an inverting terminal thereof is electrically connected to the output terminal of the second real-time voltage; A first input terminal of the first NAND gate is electrically connected to the output terminal of the first comparator, a second input terminal thereof is electrically connected to the output terminal of the second NAND gate, and an output terminal thereof is electrically connected to the control terminal of the fourth control switch; A first input terminal of the second NAND gate is electrically connected to the output terminal of the second comparator, a second input terminal thereof is electrically connected to the output terminal of the first NAND gate, and an output terminal thereof is electrically connected to the control terminal of the third control switch; An input terminal of the first inverter is electrically connected to the output terminal of the first NAND gate, and an output terminal thereof is electrically connected to the control terminal of the second control switch; An input terminal of the second inverter is electrically connected to the output terminal of the second NAND gate, and an output terminal thereof is electrically connected to the control terminal of the first control switch.

[0014] Optionally, the bypass control module comprises: The third comparator, the first AND gate, the second AND gate and the third inverter; A non-inverting terminal of the third comparator is electrically connected to the output terminal of the first reference voltage, and an inverting terminal thereof is electrically connected to the output terminal of the bypass reference voltage; A first input terminal of the first AND gate is electrically connected to the output terminal of the third comparator, a second input terminal thereof is electrically connected to the control terminal of the first control switch, and an output terminal thereof is electrically connected to the control terminal of the first bypass switch; A first input terminal of the second AND gate is electrically connected to the output terminal of the third comparator, a second input terminal thereof is electrically connected to the control terminal of the second control switch, and an output terminal thereof is electrically connected to the control terminal of the second bypass switch; An input terminal of the third inverter is electrically connected with an output terminal of the third comparator, and an output terminal of the third inverter is electrically connected with a control terminal of the fifth control switch.

[0015] Optionally, the working mechanism of the high-precision relaxation oscillator comprises: a four-phase cycle.

[0016] Optionally, the high-precision relaxation oscillator enables before comprising: controlling the third control switch, the fourth control switch and the sixth control switch to be closed, and controlling the first control switch, the second control switch, the fifth control switch, the first bypass switch and the second bypass switch to be opened, so that the voltages of the first capacitor, the second capacitor and the first bypass capacitor are zero; after the voltages are zero, controlling the third control switch, the fourth control switch and the sixth control switch to be opened.

[0017] Optionally, the four-phase cycle comprises: first phase: the fifth control switch is closed, and the bypass reference voltage is clamped to the second reference voltage by the unit-gain negative feedback operational amplifier; the first control switch is opened, the first bypass switch and the third control switch are closed, and the first capacitor is short-circuited; the second control switch is closed, the second bypass switch and the fourth control switch are opened, and the second current source charges the second capacitor until the second real-time voltage reaches the first reference voltage, the output of the second comparator flips, and enters the second phase; second phase: the second control switch and the second bypass switch are opened, the fourth control switch is closed, the second capacitor is short-circuited and stops charging; the first control switch and the first bypass switch are closed, the third control switch is opened, and the second current source and the third current source simultaneously charge the first capacitor; the fifth control switch is opened, and the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage, the output of the third comparator flips, and enters the third phase; third phase: the fifth control switch is closed, and the bypass reference voltage is clamped to the second reference voltage by the unit-gain negative feedback operational amplifier; the second control switch is opened, the fourth control switch and the second bypass switch are closed, and the second capacitor is short-circuited; the first control switch is closed, the third control switch and the first bypass switch are open, the second current source charges the first capacitor until the first real-time voltage reaches the first reference voltage, the output of the first comparator flips, entering the fourth phase; Fourth phase: the first control switch and the first bypass switch are open, the third control switch is closed, the first capacitor is shorted, stopping charging; the second control switch and the second bypass switch are closed, the fourth control switch is open, the second current source and the third current source simultaneously charge the second capacitor; the fifth control switch is open, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage, the output of the third comparator flips, entering the first phase.

[0018] Optionally, the four-phase cycle includes: First phase: the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage by the unity-gain negative feedback operational amplifier; the second control switch is open, the fourth control switch and the second bypass switch are closed, the second capacitor is shorted; the first control switch is closed, the third control switch and the first bypass switch are open, the second current source charges the first capacitor until the first real-time voltage reaches the first reference voltage, the output of the first comparator flips, entering the second phase; Second phase: the first control switch and the first bypass switch are open, the third control switch is closed, the first capacitor is shorted, stopping charging; the second control switch and the second bypass switch are closed, the fourth control switch is open, the second current source and the third current source simultaneously charge the second capacitor; the fifth control switch is open, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage, the output of the third comparator flips, entering the third phase; Third phase: the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage by the unity-gain negative feedback operational amplifier; the first control switch is open, the first bypass switch and the third control switch are closed, the first capacitor is shorted; The second control switch is closed, the second bypass switch and the fourth control switch are opened, the second capacitor is charged by the second current source until the second real-time voltage reaches the first reference voltage, the output of the second comparator flips, entering the fourth phase; Fourth phase: The second control switch and the second bypass switch are opened, the fourth control switch is closed, the second capacitor is short-circuited and stops charging; The first control switch and the first bypass switch are closed, the third control switch is opened, and the first capacitor is charged by the second current source and the third current source at the same time; The fifth control switch is opened, and the first bypass capacitor is charged by the fourth current source until the bypass reference voltage increases from the second reference voltage to the first reference voltage, and the output of the third comparator flips, entering the first phase.

[0019] The present application has the beneficial effects that: the first reference voltage and the second reference voltage are provided by the reference voltage generation module, which lays a precise voltage reference for the entire oscillation system; the bypass reference voltage generation module generates a bypass reference voltage based on the second reference voltage, and the bypass control module adjusts the charging current multiple based on the bypass reference voltage and the first reference voltage, which can effectively eliminate the influence of comparator delay, power voltage fluctuation and temperature change on the oscillation period in traditional oscillators, so that the oscillation period is determined only by the RC parameter, and the oscillator can output a high-precision stable oscillation signal under different power voltages and different temperature conditions.

[0020] The charge-discharge control module can quickly respond to voltage changes and control the alternating charging and discharging of the capacitors based on the first reference voltage and the first and second real-time voltages generated by the capacitor charge-discharge module, avoiding the delay of multi-cycle adjustment in traditional feedback structures; at the same time, the precise control of the charging current multiple by the bypass control module can speed up the charging and discharging process of the capacitors, so that the oscillation signal can reach a stable output state in the second cycle, significantly improving the start-up speed of the oscillator.

[0021] The synergistic effect of the bypass reference voltage generation module and the bypass control module can naturally eliminate voltage mismatch errors through the system loop, which not only simplifies the circuit design and reduces the hardware implementation cost, but also further improves the precision and reliability of the oscillation signal.

[0022] The present application takes into account both frequency stability and fast start-up dual-core performance, and its output of high-precision stable oscillation signal and fast start-up capability can fully meet the stringent requirements of precision measurement, industrial control, medical electronics and other high-precision scenarios for clock signals, and has wide application value and practicality.

[0023] The system of the present application has other features and advantages which will be apparent from or which will be elaborated upon in the accompanying drawings and the detailed description which follows, and which, together with the claims, are intended to explain the principles of the application. BRIEF DESCRIPTION OF DRAWINGS

[0024] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout the figures.

[0025] Figure 1 A diagram of a fast-starting high-precision relaxation oscillator according to one embodiment of the present application is shown.

[0026] Figure 2 A, Figure 2 B, Figure 2 C and Figure 2 D respectively show a diagram of a first four-phase cycle of a fast-starting high-precision relaxation oscillator according to one embodiment of the present application.

[0027] Figure 3 A, Figure 3 B, Figure 3 C and Figure 3 D respectively show a diagram of a second four-phase cycle of a fast-starting high-precision relaxation oscillator according to one embodiment of the present application.

[0028] Figure 4 A diagram of a relaxation oscillator according to the background art of the present application is shown.

[0029] Figure 5 A diagram of an improved op-amp-based oscillator according to the background art of the present application is shown. DETAILED DESCRIPTION

[0030] The present application will now be described in more detail with reference to the drawings. Although the preferred embodiment of the present application is shown in the drawings, it is understood that the present application can be carried out in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and fully convey the scope of the present application to those skilled in the art. EMBODIMENT

[0031] As Figure 1 shown, the present embodiment provides a fast-starting high-precision relaxation oscillator, comprising: The reference voltage generation module is configured to generate a first reference voltage VREF1 and a second reference voltage VREF2. The capacitor charging and discharging module is configured to generate a periodically changing first real-time voltage VC1 and a second real-time voltage VC2 through alternating charging and discharging, and further form a periodic oscillation signal. The bypass reference voltage generation module is electrically connected with the reference voltage generation module, and is configured to generate a bypass reference voltage VBYP based on the second reference voltage VREF2. The charging and discharging control module is electrically connected with the reference voltage generation module and the capacitor charging and discharging module, respectively, and is configured to control the capacitor charging and discharging module to alternately charge and discharge based on the first reference voltage VREF1, the first real-time voltage VC1 and the second real-time voltage VC2. The bypass control module is electrically connected with the reference voltage generation module and the bypass reference voltage generation module, respectively, and is configured to control the charging current multiple of the capacitor charging and discharging module based on the first reference voltage VREF1 and the bypass reference voltage VBYP.

[0032] Specifically, in the circuit system, the reference voltage generation module undertakes the basic and key voltage generation task, and can accurately generate the first reference voltage VREF1 and the second reference voltage VREF2 to provide a stable voltage reference for the subsequent module work.

[0033] The capacitor charging and discharging module generates the periodically changing first real-time voltage VC1 signal and the second real-time voltage VC2 signal through alternating charging and discharging operations, and these signals further combine to form a periodic oscillation signal, which is the core part of the circuit to realize the oscillation function.

[0034] The bypass reference voltage generation module is electrically connected with the reference voltage generation module, and generates the bypass reference voltage VBYP based on the second reference voltage VREF2 to provide the required voltage signal for the circuit control related to the bypass.

[0035] The charging and discharging control module is electrically connected with the reference voltage generation module and the capacitor charging and discharging module, respectively, and is configured to accurately control the alternating charging and discharging process of the capacitor charging and discharging module according to the first reference voltage VREF1, the first real-time voltage VC1 signal and the second real-time voltage VC2 signal, to ensure that the capacitor charging and discharging is performed according to the expected rhythm and rule.

[0036] The bypass control module is also electrically connected with the reference voltage generation module and the bypass reference voltage generation module, respectively, and controls the charging current multiple of the capacitor charging and discharging module according to the first reference voltage VREF1 and the bypass reference voltage VBYP, to adjust the size of the charging current and meet the current demand in different working scenarios.

[0037] The synergy of the bypass reference voltage generating module and the bypass control module can naturally eliminate the voltage mismatch error through a system loop, which simplifies the circuit design, reduces the hardware implementation cost, and further improves the precision and reliability of the oscillation signal.

[0038] The high-precision relaxation oscillator provided in the embodiment has multiple significant beneficial effects brought by the introduction of the innovative bypass loop and four-phase operation timing, and successfully solves the core contradiction between precision, stability and speed in the traditional structure.

[0039] Firstly, high precision and high stability are achieved. The most core beneficial effect of the embodiment is that the oscillation period is ultimately determined by the stable resistance, capacitance value and reference current (T=kRC), which completely eliminates the comparator delay (T_dly) which is greatly affected by the power voltage and temperature change. This is achieved by the bypass loop, which actively "measures" and "stores" the delay error in each cycle and dynamically compensates in the subsequent phase, so that the output frequency can remain highly stable under different working voltages and temperature environments.

[0040] Secondly, fast startup is achieved. Unlike the traditional high-precision oscillator which needs 10-20 cycles to stabilize the output, the embodiment quickly establishes the bypass voltage reference through the unit gain operational amplifier, and the optimized switching timing makes the oscillator output a stable target frequency in the second cycle. This feature greatly meets the needs of low-power applications and systems that require fast response.

[0041] Thirdly, the structure is simple and reliable, reducing the implementation difficulty and cost. The embodiment avoids using complex high-gain and high-bandwidth operational amplifiers, and only uses a simple unit-gain buffer, whose offset voltage can be averaged out by the system loop. At the same time, the entire design is based on matched current mirrors and capacitors, which is very conducive to the implementation of integrated circuits, improving the consistency and reliability of mass production.

[0042] In summary, the embodiment ingeniously uses analog circuit timing control to achieve high precision, high stability and fast startup, which are traditionally mutually restrictive goals, and provides an easy-to-integrate and robust solution with high practical value and market competitiveness.

[0043] In the embodiment, the reference voltage generating module includes: a first current source Is1, a first resistor R1, a second resistor R2 and a third resistor R3 connected in series; The first current source Is1 is connected to the current reference bus L; The output end OUT1 of the first reference voltage VREF1 is arranged between the first resistor R1 and the second resistor R2; The output end OUT2 of the second reference voltage VREF2 is arranged between the second resistor R2 and the third resistor R3. The output end of the third resistor R3 is electrically connected with the ground end GND.

[0044] Specifically, the reference voltage generating module is a circuit based on a precise resistance voltage dividing network, and a core function of the circuit is to convert a stable input reference current into two reference voltages with a precise proportional relationship. An input of the module is a precise current source Is1 which is not sensitive to power voltage and temperature variation, and the current source is connected to a current reference bus L to provide a stable current reference I_REF (1x current). The first resistor R1, the second resistor R2 and the third resistor R3 are connected in series in sequence and are the same in resistance value, and constitute a high-precision voltage divider.

[0045] After the current I_REF flows out from the Is1, the current flows through the first resistor R1, the second resistor R2 and the third resistor R3 in sequence. According to Ohm's law, a voltage drop generated on each resistor is V_R=I_REF R (where R is the resistance value of a single resistor). Therefore, the output end OUT1 between the first resistor R1 and the second resistor R2 outputs the first reference voltage VREF1, and a voltage value of the first reference voltage VREF1 is VREF1=I_REF (R2+R3)=2 I_REF R. The output end OUT2 between the second resistor R2 and the third resistor R3 outputs the second reference voltage VREF2, and a voltage value of the second reference voltage VREF2 is VREF2=I_REF R3=I_REF R. The other end of the third resistor R3 is grounded to provide a loop for the current.

[0046] Since the first reference voltage VREF1 and the second reference voltage VREF2 are derived from the same reference current and the same series of matched resistors, any absolute resistance value change or current fluctuation caused by process deviation or temperature variation will synchronously and proportionally affect the two output voltages. This means that the voltage ratio between them always remains constant, and the period formula T=k R C in the oscillator is proportional to VREF / I_REF, and therefore the proportional stability is crucial to ensure the stability of the oscillation frequency. The structure is simple and reliable, and does not need an operational amplifier, and high-precision voltage ratio generation can be achieved by using carefully laid matched resistors in an integrated circuit.

[0047] In the embodiment, the capacitor charging and discharging module comprises: The second current source Is2, the third current source Is3, the first control switch S1, the second control switch S2, the third control switch S3, the fourth control switch S4, the first bypass switch S1_byp, the second bypass switch S2_byp, the first capacitor C1 and the second capacitor C2; The second current source Is2 and the third current source Is3 are connected to the current reference bus L. The first control switch S1 and the second control switch S2 are connected in parallel to the second current source Is2, and the first bypass switch S1_byp and the second bypass switch S2_byp are connected in parallel to the third current source Is3. The first control switch S1 is connected in series with the first capacitor C1, and the second control switch S2 is connected in series with the second capacitor C2. The third control switch S3 is connected in parallel to the first control switch S1 and the first capacitor C1, and the fourth control switch S4 is connected in parallel to the second control switch S2 and the second capacitor C2. The output end OUT3 of the first real-time voltage VC1 is arranged between the first control switch S1 and the first capacitor C1. The output point of the second real-time voltage VC2 is arranged between the second control switch S2 and the second capacitor C2. The other end of the first bypass switch S1_byp is connected to the output end OUT3 of the first real-time voltage VC1, and the other end of the second bypass switch S2_byp is connected to the output point of the second real-time voltage VC2. The output ends of the first capacitor C1, the second capacitor C2, the third control switch S3 and the fourth control switch S4 are electrically connected to the ground end GND. The first capacitor C1 and the second capacitor C2 are the same.

[0048] Specifically, the capacitor charging and discharging module is the core executive mechanism of the oscillator, and its function is to generate the required periodic voltage ramp signal by alternately charging and discharging two matched capacitors through precisely controlled current. The core of the module is two completely identical first capacitors C1 and second capacitors C2 and a set of parallel charging paths composed of the second current source Is2 and the third current source Is3, and the charging and discharging process is managed by the coordinated action of the first control switch S1, the second control switch S2, the third control switch S3, the fourth control switch S4, the first bypass switch S1_byp and the second bypass switch S2_byp.

[0049] The charging path is composed of two independent 1x second current sources Is2 and third current sources Is3, which obtain bias from the current reference bus L to ensure stable and matched output current. The charging operation is precisely controlled by two pairs of switch combinations: Normal charging path (1x current): dominated by the first control switch S1 and the second control switch S2. When the first control switch S1 is closed, the current of the second current source Is2 charges the first capacitor C1, generating the first real-time voltage VC1; when the second control switch S2 is closed, the current of the second current source Is2 charges the second capacitor C2, generating the second real-time voltage VC2.

[0050] Fast charging path (superimposed as 2x current): dominated by the first bypass switch S1_byp and the second bypass switch S2_byp. When the first control switch S1 and the first bypass switch S1_byp are closed at the same time, the second current source Is2 and the third current source Is3 are in parallel, and together charge the first capacitor C1, with a total charging current of 2 times (2x); similarly, the second control switch S2 and the second bypass switch S2_byp can be closed at the same time to achieve fast charging of the second capacitor C2. This design is the key to achieving fast start.

[0051] The discharge path is responsible for the third control switch S3 and the fourth control switch S4. When the third control switch S3 is closed, it short-circuits the two ends of the first capacitor C1 to the ground end GND, causing it to discharge and reset quickly; similarly, the fourth control switch S4 is closed to discharge the second capacitor C2. These two switches are enabled when the oscillator is initialized or the capacitor state needs to be reset, ensuring that each oscillation period starts from a known zero voltage state.

[0052] In summary, the module flexibly combines the above paths by receiving switch signals from the charge-discharge control module, and realizes the switching of the three states of reset (discharge), normal charging (1x current), and fast charging (2x current) of the first capacitor C1 and the second capacitor C2. Thus, two paths of alternating and linearly changing voltage slopes (the first real-time voltage VC1 and the second real-time voltage VC2) are generated at the output end OUT3 and the output end OUT4, providing a basis for generating stable oscillation signals for subsequent comparator circuits.

[0053] In this embodiment, the bypass reference voltage generation module comprises: a fourth current source Is4, a fifth control switch S5, a sixth control switch S6, a unit gain negative feedback operational amplifier A_BYP, a first bypass capacitor Cbyp, and a second bypass capacitor CL; The fourth current source Is4 is connected to the current reference bus L. The input end of the fifth control switch S5 is connected to the output end of the fourth current source Is4. The output end and the inverting end of the unit gain negative feedback operational amplifier A_BYP are both connected to the output end of the fifth control switch S5, and the non-inverting end is connected to the output end OUT2 of the second reference voltage VREF2. The input terminal of the first bypass capacitor Cbyp is connected to the output terminal of the fourth current source Is4, and the output terminal is electrically connected to the ground terminal GND; The input terminal of the second bypass capacitor CL is connected to the output terminal of the fifth control switch S5, and the output terminal is electrically connected to the ground terminal GND; The output terminal OUT5 of the bypass reference voltage VBYP is arranged between the fourth current source Is4 and the first bypass capacitor Cbyp; The sixth control switch S6 is connected in parallel with the first bypass capacitor Cbyp.

[0054] Specifically, the bypass reference voltage generation module is a core innovative module for realizing high-precision frequency control. Its core task is to quickly establish, maintain and copy an accurate reference voltage, and measure and compare the delay of the comparator to realize compensation. The module receives the second reference voltage VREF2 from the reference voltage generation module, and generates the key bypass reference voltage VBYP through a clever circuit composed of a unit gain operational amplifier and a switched capacitor. The working mode of the module is determined by the fifth control switch S5 (wherein the sixth control switch S6 is only closed before the oscillator is enabled, and remains disconnected after the oscillator is enabled), and mainly divided into two modes: 1. Sampling / clamping mode (the fifth control switch S5 is closed): in this mode, the unit gain negative feedback operational amplifier A_BYP plays a core role. Its non-inverting input terminal is connected to the stable second reference voltage VREF2, and since its output terminal is directly connected to the inverting input terminal through the fifth control switch S5, it constitutes a standard unit gain buffer (voltage follower) configuration. At this time, the unit gain negative feedback operational amplifier A_BYP accurately clamps the voltage of the output terminal OUT5 and the second bypass capacitor CL to the second reference voltage VREF2 with its low output impedance characteristic. The second bypass capacitor CL acts as a compensation and filtering capacitor in this mode, stabilizing the operational amplifier output and preventing oscillation. This mode is used to establish a pure and accurate voltage reference point for subsequent measurement at the system initialization or cycle start. This mode is used to quickly and accurately clamp the bypass reference voltage VBYP to the second reference voltage VREF2 at the oscillator start or cycle initial stage.

[0055] 2. Hold / measure mode (fifth control switch S5 is off): When the fifth control switch S5 is off, the unit gain negative feedback operational amplifier A_BYP is isolated from the main circuit, and the output end OUT5 enters a holding state. At this time, the first bypass capacitor Cbyp becomes the core element. The fourth current source Is4 (providing a stable 1x current) starts to charge the first bypass capacitor Cbyp. Since the other end of the first bypass capacitor Cbyp is grounded, the voltage at the input end will linearly rise from the second reference voltage VREF2 clamped before, and the change rate of the voltage is determined by the current I and the value of the first bypass capacitor Cbyp (dV / dt=I / Cbyp). This linearly rising ramp voltage is used for comparison with the first reference voltage VREF1, and the charging time contains the delay information of the comparator, which is the key to realize error measurement.

[0056] When the oscillator is working normally, since the fifth control switch S5 is connected to VREF2 through the unit gain negative feedback operational amplifier A_BYP, the first bypass capacitor Cbyp will be discharged to VREF2, providing an initial state for the next cycle and ensuring that the measurement accuracy is not affected by the residual charge of the previous period.

[0057] In summary, the module realizes accurate and rapid establishment of voltage through the rapid clamping function of the operational amplifier, and then converts time information into voltage information through the charging of the capacitor by the constant current source, thereby skillfully realizing the "sampling" and "measurement" of the circuit delay, and providing vital support for the realization of high precision and rapid stability of the entire system.

[0058] In the embodiment, the charge and discharge control module comprises: a first comparator CMPa, a second comparator CMPb, a latch composed of a first NAND gate N1 and a second NAND gate N2, a first inverter F1, and a second inverter F2; a same-phase end of the first comparator CMPa is electrically connected to an output end OUT1 of a first reference voltage VREF1, and an opposite-phase end thereof is electrically connected to an output end of a first real-time voltage VC1; a same-phase end of the second comparator CMPb is electrically connected to the output end OUT1 of the first reference voltage VREF1, and an opposite-phase end thereof is electrically connected to an output end of a second real-time voltage VC2; a first input end of the first NAND gate N1 is electrically connected to an output end of the first comparator CMPa, a second input end thereof is electrically connected to an output end of the second NAND gate N2, and an output end thereof is electrically connected to a control end of a fourth control switch S4; a first input end of the second NAND gate N2 is electrically connected to an output end of the second comparator CMPb, a second input end thereof is electrically connected to an output end of the first NAND gate N1, and an output end thereof is electrically connected to a control end of a third control switch S3; The input end of the first inverter F1 is electrically connected with the output end of the first NAND gate N1, and the output end is electrically connected with the control end of the second control switch S2. The input end of the second inverter F2 is electrically connected with the output end of the second NAND gate N2, and the output end is electrically connected with the control end of the first control switch S1.

[0059] Specifically, the charge-discharge control module is the core decision unit of the oscillator logic function, responsible for monitoring the capacitor voltage state and generating the corresponding switch control signal to accurately manage the alternating process of capacitor charging and discharging. The core of the module is the first comparator CMPa and the second comparator CMPb, which act as the "judge organ" of the system, continuously comparing the first real-time voltage VC1 and the second real-time voltage VC2 with the stable first reference voltage VREF1.

[0060] The working principle is as follows: when the first real-time voltage VC1 or the second real-time voltage VC2 linearly rises during charging and reaches VREF1, the output of the first comparator CMPa or the second comparator CMPb will flip. This flip signal is sent to an SR latch composed of a first NAND gate N1 and a second NAND gate N2 cross-coupled. The latch latches the transient jump signal generated by the comparator into a stable logic state (i.e. "first capacitor C1 charging, second capacitor C2 discharging" or "second capacitor C2 charging, first capacitor C1 discharging"), thereby eliminating the risk of output jitter that may exist in the comparator, ensuring the stability and certainty of the control signal.

[0061] The output of the latch directly drives the discharge control path: the output end of the first NAND gate N1 directly controls the fourth control switch S4 (parallel to the second capacitor C2), and the output end of the second NAND gate N2 directly controls the third control switch S3 (parallel to the first capacitor C1). This design means that the state of the latch directly determines which capacitor is discharged.

[0062] At the same time, in order to generate complementary charging control signals, the outputs of the latch are respectively passed through the first inverter F1 and the second inverter F2. The first inverter F1 inverts the output of the first NAND gate N1, and the result is used to control the second control switch S2 (controlling the charging of the second capacitor C2); the second inverter F2 inverts the output of the second NAND gate N2, and the result is used to control the first control switch S1 (controlling the charging of the first capacitor C1). Through the inverters, it is ensured that the logic states of the charging switches (first control switch S1 / second control switch S2) and the discharging switches (third control switch S3 / fourth control switch S4) are always opposite, thereby strictly preventing the short-circuit operation of charging and discharging on the same capacitor at the same time.

[0063] In summary, the module converts the analog signal changes of the capacitor voltage into a set of stable, complementary, and conflict-free digital switch control signals through the cooperative work of the comparator, latch, and inverter, thereby reliably coordinating the alternating work of the entire capacitor charging and discharging module, and is the key to the sustained and stable operation of the oscillator.

[0064] In the embodiment, the bypass control module comprises: a third comparator CMPc, a first AND gate Y1, a second AND gate Y2, and a third inverter F3; The non-inverting terminal of the third comparator CMPc is electrically connected to the output terminal OUT1 of the first reference voltage VREF1, and the inverting terminal thereof is electrically connected to the output terminal of the bypass reference voltage VBYP; The first input terminal of the first AND gate Y1 is electrically connected to the output terminal of the third comparator CMPc, the second input terminal thereof is electrically connected to the control terminal of the first control switch S1, and the output terminal thereof is electrically connected to the control terminal of the first bypass switch S1_byp; The first input terminal of the second AND gate Y2 is electrically connected to the output terminal of the third comparator CMPc, the second input terminal thereof is electrically connected to the control terminal of the second control switch S2, and the output terminal thereof is electrically connected to the control terminal of the second bypass switch S2_byp; The input terminal of the third inverter F3 is electrically connected to the output terminal of the third comparator CMPc, and the output terminal thereof is electrically connected to the control terminal of the fifth control switch S5.

[0065] Specifically, the bypass control module is an intelligent management unit for realizing the functions of fast charging and delay compensation of the oscillator. Its core responsibility is to monitor the state of the bypass reference voltage VBYP, and only in the correct timing window, to intelligently enable the fast charging path (control the first bypass switch S1_byp and the second bypass switch S2_byp) and manage the sampling and measurement mode of the bypass voltage (control the fifth control switch S5).

[0066] The core of the module is the third comparator CMPc, which continuously compares the stable first reference voltage VREF1 with the linearly changing bypass reference voltage VBYP. When the bypass reference voltage VBYP is lower than the first reference voltage VREF1 during the charging process, the third comparator CMPc outputs a high level; when the bypass reference voltage VBYP rises to exceed the first reference voltage VREF1, the third comparator CMPc outputs a flip to a low level. This flip action is the key to triggering phase switching and realizing delay compensation.

[0067] The first AND gate Y1 and the second AND gate Y2 together constitute the enable logic of the fast charging. Their first input terminals are connected to the output terminal of the third comparator CMPc, and their second input terminals are connected to the control terminals of the first control switch S1 and the second control switch S2 respectively. This connection means that to turn on the fast charging (i.e. to activate the first bypass switch S1_byp or the second bypass switch S2_byp), two conditions must be met simultaneously: one, the third comparator CMPc outputs high (indicating that VBYP < VREF1, the system is in the measurement phase); two, the corresponding main charging switch (the first control switch S1 or the second control switch S2) has been turned on (indicating that the first capacitor C1 or the second capacitor C2 is being charged). This "AND" logic ensures that the fast charging function is only activated at specific time periods within the main charging period, thus achieving precise timing control.

[0068] The third inverter F3 directly inverts the output of the third comparator CMPc, and its output is used to control the fifth control switch S5. When the third comparator CMPc outputs high (VBYP < VREF1), the third inverter F3 outputs low, which will close the fifth control switch S5, allowing the unit-gain negative feedback operational amplifier A_BYP to access the circuit and clamp the bypass reference voltage VBYP to VREF2. When the third comparator CMPc output flips to low (VBYP ≥ VREF1), the third inverter F3 outputs high, thereby opening the fifth control switch S5, disconnecting the output terminal OUT5 of the bypass reference voltage VBYP from the unit-gain negative feedback operational amplifier A_BYP, and entering the constant-current charging phase dominated by the fourth current source Is4.

[0069] In summary, the bypass control module, through the combination of comparators, logic gates and inverters, converts the voltage state information of the bypass reference voltage VBYP into precise control signals for the fast charging switches (the first bypass switch S1_byp and the second bypass switch S2_byp) and the mode switching switch (the fifth control switch S5), which is the core logic circuit that coordinates the seamless connection of the three processes of normal charging, fast charging and delayed measurement.

[0070] In this embodiment, the working mechanism of the high-precision relaxation oscillator includes: Four-phase cycle.

[0071] In this embodiment, before the high-precision relaxation oscillator is enabled, it includes: The third control switch S3, the fourth control switch S4 and the sixth control switch S6 are controlled to be closed, and the first control switch S1, the second control switch S2, the fifth control switch S5, the first bypass switch S1_byp and the second bypass switch S2_byp are controlled to be open, so that the voltages of the first capacitor C1, the second capacitor C2 and the first bypass capacitor Cbyp are zero. After the voltage of the first capacitor C1, the second capacitor C2 and the first bypass capacitor Cbyp is zero, the third control switch S3, the fourth control switch S4 and the sixth control switch S6 are controlled to be turned off.

[0072] In this embodiment, the SR latch composed of two NAND gates (the first NAND gate N1 and the second NAND gate N2) has two stable output states: State A (Q=0, QA=1): Q=0 (the first NAND gate N1 output) → the first control switch S1 is turned off (through the second inverter F2) → the charging of the first capacitor C1 is stopped. QA=1 (the second NAND gate N2 output) → the second control switch S2 is turned on (through the inverter F1) → the charging of the second capacitor C2 is started. Meanwhile, QA=1 → the fourth control switch S4 is turned on (directly connected) → the first capacitor C1 is short-circuited to discharge.

[0073] State B (Q=1, QA=0): Q=1 (the first NAND gate N1 output) → the first control switch S1 is turned on → the charging of the first capacitor C1 is started. QA=0 (the second NAND gate N2 output) → the second control switch S2 is turned off → the charging of the second capacitor C2 is stopped. Meanwhile, Q=1 → the third control switch S3 is turned on (directly connected) → the second capacitor C2 is short-circuited to discharge.

[0074] Therefore, as shown in Figure 2 and Figure 3 (the sixth control switch S6 is kept turned off in the high-precision relaxation oscillator, so Figure 2 and Figure 3 are not shown), there are two four-phase cycles; The first one, as shown in Figure 2 , the four-phase cycle includes: First phase: The fifth control switch S5 is turned on, and the bypass reference voltage VBYP is clamped to the second reference voltage VREF2 through the unit-gain negative feedback operational amplifier A_BYP; The first control switch S1 is turned off, the first bypass switch S1_byp and the third control switch S3 are turned on, and the first capacitor C1 is short-circuited; The second control switch S2 is turned on, the second bypass switch S2_byp and the fourth control switch S4 are turned off, and the second current source Is2 charges the second capacitor C2 until the second real-time voltage VC2 reaches the first reference voltage VREF1, the output of the second comparator CMPb flips, and enters the second phase; Second phase: The second control switch S2 and the second bypass switch S2_byp are turned off, the fourth control switch S4 is turned on, the second capacitor C2 is short-circuited, and the charging is stopped; The first control switch S1 and the first bypass switch S1_byp are closed, the third control switch S3 is open, and the second current source Is2 and the third current source Is3 simultaneously charge the first capacitor C1; The fifth control switch S5 is open, and the fourth current source Is4 charges the first bypass capacitor Cbyp until the bypass reference voltage VBYP increases from the second reference voltage VREF2 to the first reference voltage VREF1, and the output of the third comparator CMPc flips, entering the third phase; The third phase: The fifth control switch S5 is closed, and the bypass reference voltage VBYP is clamped to the second reference voltage VREF2 by the unit-gain negative feedback operational amplifier A_BYP; The second control switch S2 is open, and the fourth control switch S4 and the second bypass switch S2_byp are closed, and the second capacitor C2 is shorted; The first control switch S1 is closed, the third control switch S3 and the first bypass switch S1_byp are open, and the second current source Is2 charges the first capacitor C1 until the first real-time voltage VC1 reaches the first reference voltage VREF1, and the output of the first comparator CMPa flips, entering the fourth phase; The fourth phase: The first control switch S1 and the first bypass switch S1_byp are open, the third control switch S3 is closed, and the first capacitor C1 is shorted and stops charging; The second control switch S2 and the second bypass switch S2_byp are closed, and the fourth control switch S4 is open, and the second current source Is2 and the third current source Is3 simultaneously charge the second capacitor C2; The fifth control switch S5 is open, and the fourth current source Is4 charges the first bypass capacitor Cbyp until the bypass reference voltage VBYP increases from the second reference voltage VREF2 to the first reference voltage VREF1, and the output of the third comparator CMPc flips, entering the first phase.

[0075] Specifically, the high-precision relaxation oscillator works through a precisely defined four-phase cycle, and each phase is switched by a comparator trigger, ensuring the stability of the output frequency and the fast start-up characteristics.

[0076] As Figure 2As shown in Figure A, Phase ① (Initialization and C2 Charging): At the start of this phase, the fifth control switch S5 closes, connecting the unity-gain negative feedback operational amplifier A_BYP to the circuit. This allows the bypass reference voltage VBYP node to be precisely clamped to the second reference voltage VREF2, establishing a clean reference. Simultaneously, the first capacitor C1 is short-circuited and reset through the closed third control switch S3 and the first bypass switch S1_byp, ensuring its voltage is zero. The second control switch S2 closes, allowing the second current source Is2 to charge the second capacitor C2, causing its second real-time voltage VC2 to rise linearly from zero. The end of this phase is determined by the second comparator CMPb. When the second real-time voltage VC2 rises to reach the first reference voltage VREF1, the output of the second comparator CMPb flips, triggering the system to enter the second phase.

[0077] like Figure 2 As shown in Figure B, Phase ② (Fast charging and delayed sampling of the first capacitor C1): Upon entering the second phase, the second control switch S2 opens, stopping the charging of the second capacitor C2, and immediately closes the fourth control switch S4 to short-circuit and reset the second capacitor C2. The first control switch S1 and the first bypass switch S1_byp close simultaneously, causing the second current source Is2 and the third current source Is3 to connect in parallel, jointly charging the first capacitor C1 with twice the current (2x). At the same time, the fifth control switch S5 opens, connecting the output terminal OUT5 of the bypass reference voltage VBYP to the unity-gain negative feedback operational amplifier A_BYP. The fourth current source Is4 begins charging the first bypass capacitor Cbyp. Since its initial voltage is the second reference voltage VREF2, the bypass reference voltage VBYP rises linearly from this value. The end of this phase is determined by the third comparator CMPc. When the bypass reference voltage VBYP rises to the first reference voltage VREF1, the output of the third comparator CMPc flips, indicating that a charging time including its own delay has been measured and the system enters the third phase.

[0078] like Figure 2As shown in Figure C, Phase ③ (normal charging of the first capacitor C1 and reset of the second capacitor C2): In the third phase, the fifth control switch S5 closes again, and the unity-gain negative feedback operational amplifier A_BYP clamps the bypass reference voltage VBYP back to the second reference voltage VREF2, preparing for the next measurement. The second capacitor C2 remains short-circuited through the closed fourth control switch S4 and the second bypass switch S2_byp. The first control switch S1 remains closed, but the first bypass switch S1_byp is open, so the charging current for the first capacitor C1 returns to one current (1x), which continues to complete the charging. The end of this phase is determined by the first comparator CMPa. When the first real-time voltage VC1 rises to the first reference voltage VREF1, the output of the first comparator CMPa flips, and the system enters the fourth phase.

[0079] like Figure 2 As described in D, Phase ④ (Fast charging and delay compensation of the second capacitor C2): The last phase is symmetrically complementary to the second phase. The first control switch S1 and the first bypass switch S1_byp are open, and the first capacitor C1 is short-circuited and reset through the closed third control switch S3. The second control switch S2 and the second bypass switch S2_byp are simultaneously closed, causing the second current source Is2 and the third current source Is3 to be connected in parallel again, rapidly charging the second capacitor C2 with twice the current (2x). The fifth control switch S5 is open, and the fourth current source Is4 charges the first bypass capacitor Cbyp again, with the initial conditions being exactly the same as in the second phase. When the bypass reference voltage VBYP charges again from the second reference voltage VREF2 to the first reference voltage VREF1, the output of the third comparator CMPc flips, and the time taken is exactly the same as in the second phase, thus accurately compensating for the comparator delay. This flip signal triggers the system to return to the first phase, starting the next complete oscillation cycle, thereby continuously generating a stable clock output.

[0080] The second type, such as Figure 3 As shown, the four-phase cycle includes: First phase: When the fifth control switch S5 is closed, the bypass reference voltage VBYP is clamped to the second reference voltage VREF2 through the unity-gain negative feedback operational amplifier A_BYP. The second control switch S2 is open, the fourth control switch S4 and the second bypass switch S2_byp are closed, and the second capacitor C2 is short-circuited. The first control switch S1 is closed, the third control switch S3 and the first bypass switch S1_byp are open, the second current source Is2 charges the first capacitor C1 until the first real-time voltage VC1 reaches the first reference voltage VREF1, the output of the first comparator CMPa flips and enters the second phase. Second phase: The first control switch S1 and the first bypass switch S1_byp are open, the third control switch S3 is closed, the first capacitor C1 is shorted, and the charging is stopped; The second control switch S2 and the second bypass switch S2_byp are closed, the fourth control switch S4 is open, the second current source Is2 and the third current source Is3 simultaneously charge the second capacitor C2; The fifth control switch S5 is open, the fourth current source Is4 charges the first bypass capacitor Cbyp until the bypass reference voltage VBYP increases from the second reference voltage VREF2 to the first reference voltage VREF1, the output of the third comparator CMPc flips, and enters the third phase; The third phase: The fifth control switch S5 is closed, and the bypass reference voltage VBYP is clamped to the second reference voltage VREF2 by the unit-gain negative feedback operational amplifier A_BYP; The first control switch S1 is open, the first bypass switch S1_byp and the third control switch S3 are closed, and the first capacitor C1 is shorted; The second control switch S2 is closed, the second bypass switch S2_byp and the fourth control switch S4 are open, the second current source Is2 charges the second capacitor C2 until the second real-time voltage VC2 reaches the first reference voltage VREF1, the output of the second comparator CMPb flips, and enters the fourth phase; The fourth phase: The second control switch S2 and the second bypass switch S2_byp are open, the fourth control switch S4 is closed, the second capacitor C2 is shorted, and the charging is stopped; The first control switch S1 and the first bypass switch S1_byp are closed, the third control switch S3 is open, the second current source Is2 and the third current source Is3 simultaneously charge the first capacitor C1; The fifth control switch S5 is open, the fourth current source Is4 charges the first bypass capacitor Cbyp until the bypass reference voltage VBYP increases from the second reference voltage VREF2 to the first reference voltage VREF1, the output of the third comparator CMPc flips, and enters the first phase.

[0081] Specifically, as Figure 3As described above with respect to FIGS. 3A, 3B, 3C, 3D, the second four-phase cycle operates in the same manner as the first four-phase cycle, except that the order of charging the capacitors is different. The first four-phase cycle performs the first sampling and compensation of the comparator delay by first quickly charging the first capacitor CI and then quickly charging the second capacitor C2, which directs the circuit from an unordered initial state into a stable oscillation cycle. The second four-phase cycle performs the first sampling and compensation of the comparator delay by first quickly charging the second capacitor C2 and then quickly charging the first capacitor CI, which directs the circuit from an unordered initial state into a stable oscillation cycle. That is, the fast charging phases of the first capacitor CI and the second capacitor C2 are arranged in different phases (the second capacitor C2 is in the second phase and the first capacitor CI is in the fourth phase), so that in each complete oscillation cycle, both capacitors are fast charged and compensated for delay. This maintains the frequency stable and consistent.

[0082] The foregoing description of the various embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the various embodiments to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the various embodiments be limited not with this detailed description, but rather by the claims appended hereto.

Claims

1. A high-precision relaxation oscillator with fast start-up, characterized in that, include: A reference voltage generation module is used to generate a first reference voltage and a second reference voltage. The capacitor charging and discharging module is used to generate a periodically changing first real-time voltage and a second real-time voltage through alternating charging and discharging, thereby forming a periodic oscillation signal; A bypass reference voltage generating module, electrically connected to the reference voltage generating module, is used to generate a bypass reference voltage based on the second reference voltage; The charge-discharge control module is electrically connected to the reference voltage generation module and the capacitor charge-discharge module respectively. The charge-discharge control module is used to control the capacitor charge-discharge module to charge and discharge alternately based on the first reference voltage, the first real-time voltage and the second real-time voltage. The bypass control module is electrically connected to the reference voltage generation module and the bypass reference voltage generation module, respectively, and is used to control the charging current multiple of the capacitor charging and discharging module based on the first reference voltage and the bypass reference voltage.

2. The high-precision relaxation oscillator with rapid start-up according to claim 1, characterized in that, The reference voltage generating module includes: A first current source, a first resistor, a second resistor, and a third resistor are connected in series. The first current source is connected to the current reference bus; The output terminal of the first reference voltage is located between the first resistor and the second resistor; The output terminal of the second reference voltage is located between the second resistor and the third resistor; The output terminal of the third resistor is electrically connected to the ground terminal.

3. The high-precision relaxation oscillator with rapid start-up according to claim 2, characterized in that, The capacitor charging and discharging module includes: Second current source, third current source, first control switch, second control switch, third control switch, fourth control switch, first bypass switch, second bypass switch, first capacitor and second capacitor; The second current source and the third current source are both connected to the current reference bus. The first control switch and the second control switch are connected in parallel to the second current source, and the first bypass switch and the second bypass switch are connected in parallel to the third current source; The first control switch is connected in series with the first capacitor, and the second control switch is connected in series with the second capacitor; The third control switch is connected in parallel with the first capacitor and the fourth control switch is connected in parallel with the second capacitor and the second control switch. The output terminal of the first real-time voltage is located between the first control switch and the first capacitor; The output terminal of the second real-time voltage is located between the second control switch and the second capacitor; The other end of the first bypass switch is connected to the output terminal of the first real-time voltage, and the other end of the second bypass switch is connected to the output terminal of the second real-time voltage. The output terminals of the first capacitor, the second capacitor, the third control switch, and the fourth control switch are all electrically connected to the ground terminal. The first capacitor and the second capacitor are the same.

4. The high-precision relaxation oscillator with rapid start-up according to claim 3, characterized in that, The bypass reference voltage generating module includes: Fourth current source, fifth control switch, sixth control switch, unity-gain negative feedback operational amplifier, first bypass capacitor and second bypass capacitor; The fourth current source is connected to the current reference bus; The input terminal of the fifth control switch is connected to the output terminal of the fourth current source; The output terminal and the inverting terminal of the unity-gain negative feedback operational amplifier are both connected to the output terminal of the fifth control switch, and its non-inverting terminal is connected to the output terminal of the second reference voltage. The input terminal of the first bypass capacitor is connected to the output terminal of the fourth current source, and its output terminal is electrically connected to the ground terminal. The input terminal of the second bypass capacitor is connected to the output terminal of the fifth control switch, and its output terminal is electrically connected to the ground terminal. The output terminal of the bypass reference voltage is located between the fourth current source and the first bypass capacitor; The sixth control switch is connected in parallel with the first bypass capacitor.

5. The high-precision relaxation oscillator with rapid start-up according to claim 4, characterized in that, The charge / discharge control module includes: The system consists of a first comparator, a second comparator, a latch composed of a first NAND gate and a second NAND gate, a first inverter, and a second inverter. The non-inverting input of the first comparator is electrically connected to the output of the first reference voltage, and its inverting input is electrically connected to the output of the first real-time voltage. The non-inverting input of the second comparator is electrically connected to the output of the first reference voltage, and its inverting input is electrically connected to the output of the second real-time voltage. The first input terminal of the first NAND gate is electrically connected to the output terminal of the first comparator, its second input terminal is electrically connected to the output terminal of the second NAND gate, and its output terminal is electrically connected to the control terminal of the fourth control switch. The first input terminal of the second NAND gate is electrically connected to the output terminal of the second comparator, its second input terminal is electrically connected to the output terminal of the first NAND gate, and its output terminal is electrically connected to the control terminal of the third control switch. The input terminal of the first inverter is electrically connected to the output terminal of the first NAND gate, and its output terminal is electrically connected to the control terminal of the second control switch. The input terminal of the second inverter is electrically connected to the output terminal of the second NAND gate, and its output terminal is electrically connected to the control terminal of the first control switch.

6. The high-precision relaxation oscillator with rapid start-up according to claim 5, characterized in that, The bypass control module includes: The third comparator, the first AND gate, the second AND gate, and the third inverter; The non-inverting input of the third comparator is electrically connected to the output of the first reference voltage, and its inverting input is electrically connected to the output of the bypass reference voltage. The first input terminal of the first AND gate is electrically connected to the output terminal of the third comparator, its second input terminal is electrically connected to the control terminal of the first control switch, and its output terminal is electrically connected to the control terminal of the first bypass switch. The first input terminal of the second AND gate is electrically connected to the output terminal of the third comparator, its second input terminal is electrically connected to the control terminal of the second control switch, and its output terminal is electrically connected to the control terminal of the second bypass switch. The input terminal of the third inverter is electrically connected to the output terminal of the third comparator, and its output terminal is electrically connected to the control terminal of the fifth control switch.

7. The high-precision relaxation oscillator with rapid start-up according to claim 6, characterized in that, The working mechanism of the high-precision relaxation oscillator includes: Four-phase cycle.

8. The high-precision relaxation oscillator with rapid start-up according to claim 7, characterized in that, The high-precision relaxation oscillator is enabled before the following: The third, fourth, and sixth control switches are closed, and the first, second, fifth, first bypass, and second bypass switches are opened, so that the voltage of the first capacitor, the second capacitor, and the first bypass capacitor is zero. When the voltage is zero, the third, fourth, and sixth control switches are disconnected.

9. The high-precision relaxation oscillator with rapid start-up according to claim 8, characterized in that, The four-phase cycle includes: First phase: When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier. The first control switch is open, the first bypass switch and the third control switch are closed, and the first capacitor is short-circuited. When the second control switch is closed, the second bypass switch and the fourth control switch are open, the second current source charges the second capacitor until the second real-time voltage reaches the first reference voltage, and the output of the second comparator flips and enters the second phase. Second phase: When the second control switch and the second bypass switch are open, the fourth control switch is closed, the second capacitor is short-circuited, and charging stops. When the first control switch and the first bypass switch are closed, the third control switch is open, and the second current source and the third current source simultaneously charge the first capacitor. When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then the output of the third comparator flips and enters the third phase. Third phase: When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier. The second control switch is open, the fourth control switch and the second bypass switch are closed, and the second capacitor is short-circuited; When the first control switch is closed, the third control switch and the first bypass switch are open, the second current source charges the first capacitor until the first real-time voltage reaches the first reference voltage, and the output of the first comparator flips and enters the fourth phase. Fourth phase: When the first control switch and the first bypass switch are disconnected, and the third control switch is closed, the first capacitor is short-circuited and charging stops. When the second control switch and the second bypass switch are closed, the fourth control switch is open, and the second current source and the third current source simultaneously charge the second capacitor. When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then, the output of the third comparator flips and enters the first phase.

10. The high-precision relaxation oscillator with rapid start-up according to claim 8, characterized in that, The four-phase cycle includes: First phase: When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier. The second control switch is open, the fourth control switch and the second bypass switch are closed, and the second capacitor is short-circuited; When the first control switch is closed, the third control switch and the first bypass switch are open, the second current source charges the first capacitor until the first real-time voltage reaches the first reference voltage, and the output of the first comparator flips and enters the second phase. Second phase: When the first control switch and the first bypass switch are disconnected, and the third control switch is closed, the first capacitor is short-circuited and charging stops. When the second control switch and the second bypass switch are closed, the fourth control switch is open, and the second current source and the third current source simultaneously charge the second capacitor. When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then the output of the third comparator flips and enters the third phase. Third phase: When the fifth control switch is closed, the bypass reference voltage is clamped to the second reference voltage through the unity-gain negative feedback operational amplifier. The first control switch is open, the first bypass switch and the third control switch are closed, and the first capacitor is short-circuited. When the second control switch is closed, the second bypass switch and the fourth control switch are open, the second current source charges the second capacitor until the second real-time voltage reaches the first reference voltage, and the output of the second comparator flips and enters the fourth phase. Fourth phase: When the second control switch and the second bypass switch are open, the fourth control switch is closed, the second capacitor is short-circuited, and charging stops. When the first control switch and the first bypass switch are closed, the third control switch is open, and the second current source and the third current source simultaneously charge the first capacitor. When the fifth control switch is turned off, the fourth current source charges the first bypass capacitor until the bypass reference voltage increases from the second reference voltage to the first reference voltage. Then, the output of the third comparator flips and enters the first phase.

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