Driving circuit, driving chip, control method and laser radar

Abstract

The invention relates to a driving circuit, a driving chip, a control method and a laser radar. The driving circuit comprises a first high-side switch transistor, a first bootstrap driving module used for driving the first high-side switch transistor, and a charging module. Wherein the first high-side switching transistor is provided with a parasitic gate capacitor; the first end of the first high-side switching transistor is used for inputting a high-voltage side power supply signal, and the second end of the first high-side switching transistor is used for being connected with a load; and the charging module is used for charging the gate capacitor for a first time length within an associated time period in which the first bootstrap driving module conducts the first high-side switching transistor based on the control of a first control signal, so as to compensate at least part of charges charged by the first bootstrap driving module for the gate capacitor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, in particular to a driving circuit, a driving chip, a control method and a laser radar. BACKGROUND

[0002] In a laser radar system, the laser driver circuit is one of the core components, and its performance directly affects the detection distance, accuracy and reliability of the entire system. In laser radar applications, high-side switch transistor driving circuits usually use bootstrap driving technology to achieve high-efficiency and low-power laser driving. In a high-side switch driving circuit, the bootstrap capacitor is a key element for driving the gate of the high-side switch transistor. The bootstrap capacitor charges and provides a driving voltage for the gate of the high-side switch transistor when the high-side switch transistor is turned on.

[0003] In laser radar high-side driving applications, Laterally-Diffused Metal-Oxide Semiconductor (LDMOS) transistors are widely used as high-side switch transistors due to their high voltage resistance and low on-resistance. However, LDMOS transistors usually have a large gate capacitance, and a large amount of charge is needed to raise the gate voltage to the required level. In laser radar high-side driving switch applications, due to the large gate capacitance of LDMOS, the existing bootstrap driving scheme cannot provide enough charge to the gate capacitance in a short time.

[0004] Therefore, how to solve the problem of insufficient charging under large gate capacitance load and improve the peak current of the high-side switch transistor is a problem to be solved. SUMMARY

[0005] Therefore, the embodiments of the present application provide a driving circuit, a driving chip, a control method and a laser radar to solve the problems in the background art.

[0006] According to a first aspect of the embodiments of the present disclosure, a driving circuit is provided, which comprises: a first high-side switch transistor, a first bootstrap driving module for driving the first high-side switch transistor, and a charging module; wherein, The first high-side switch transistor has a parasitic gate capacitance; a first end of the first high-side switch transistor is used for inputting a high-voltage side power supply signal, and a second end of the first high-side switch transistor is used for connecting a load; The charging module is used for charging the gate capacitance for a first time duration within a time period when the first bootstrap driving module turns on the first high-side switch transistor based on the control of the first control signal, to compensate for at least part of the charge of the gate capacitance charged by the first bootstrap driving module.

[0007] In some embodiments, the charging module is configured to perform one of the following: charging the gate capacitor before the start time at which the first bootstrap drive module controls the first high-side switch transistor to turn on, and stopping charging the gate capacitor during the turn-on duration; charging the gate capacitor for a first duration from the start time; charging the gate capacitor for a first duration after the start time, wherein an end time of the first duration is before an end time of the turn-on duration; charging the gate capacitor for a first duration before the start time.

[0008] In some embodiments, the first bootstrap drive module comprises a first bootstrap capacitor, a first buffer module, and a first diode, wherein: an anode of the first diode is configured to input a first low-voltage side power supply signal; an upper plate of the first bootstrap capacitor is connected to a cathode of the first diode; the upper plate of the first bootstrap capacitor is connected to a first power supply terminal of the first buffer module; a lower plate of the first bootstrap capacitor is connected to a second power supply terminal of the first buffer module; an input terminal of the first buffer module is configured to input the first control signal; an output terminal of the first buffer module is connected to a gate of the first high-side switch transistor; the second power supply terminal of the first buffer module is connected to a second terminal of the first high-side switch transistor.

[0009] In some embodiments, the charging module comprises a second bootstrap drive module and a second high-side switch transistor, wherein: a first terminal of the second high-side switch transistor is configured to input a high-voltage side power supply signal, and a second terminal of the second high-side switch transistor is configured to be connected to the gate of the first high-side switch transistor; the second bootstrap drive module is configured to drive the second high-side switch transistor to turn on for the first duration to charge the gate capacitor.

[0010] In some embodiments, the second bootstrap drive module comprises a second buffer module, a second diode, and a second bootstrap capacitor. an anode of the second diode is configured to input a second low-voltage side power supply signal; an upper plate of the second bootstrap capacitor is connected to a cathode of the second diode; the upper plate of the second bootstrap capacitor is connected to a first power supply terminal of the second buffer module; The lower plate of the second bootstrap capacitor is connected to a second power terminal of the second buffer module; An input terminal of the second buffer module is configured to receive a second control signal, An output terminal of the second buffer module is connected to a control terminal of the second high-side switch transistor; A second power terminal of the second buffer module is connected to a second terminal of the second high-side switch transistor.

[0011] In some embodiments, the first control signal and the second control signal are the same control signal, and the second buffer module is configured to drive the second high-side switch transistor to be turned on for the first time duration based on the first control signal; or The first control signal and the second control signal are different control signals, and the second control signal is configured to control the second buffer module to drive the second high-side switch transistor to be turned on for the first time duration.

[0012] In some embodiments, the second buffer module includes a digital buffer module configured to perform a time delay based on the first control signal to adjust a starting time of the first time duration, wherein the time delay is associated with a first register value of the digital buffer module; and / or The first time duration is associated with a second register value of the digital buffer module.

[0013] In some embodiments, a conduction current between the first terminal of the first high-side switch transistor and the second terminal of the first high-side switch transistor is positively correlated with the first time duration.

[0014] In some embodiments, the first bootstrap drive module further includes a clamping component configured to clamp a voltage difference between the gate of the first high-side switch transistor and the second terminal of the first high-side switch transistor.

[0015] In some embodiments, the clamping component includes a Zener diode, wherein a cathode of the Zener diode is connected to the gate of the first high-side switch transistor, and an anode of the Zener diode is connected to the second terminal of the first high-side switch transistor.

[0016] According to a second aspect of the embodiments of the present disclosure, a driving chip is provided, and the driving chip includes at least one driving channel, and each driving channel includes the driving circuit according to the first aspect.

[0017] According to a third aspect of the embodiments of the present disclosure, a laser radar is provided, and the laser radar includes the driving circuit according to the first aspect or the driving chip according to the second aspect, The laser radar further includes at least one laser. The driving circuit is used to drive at least one laser; or each driving channel of the driving chip is used to drive at least one laser.

[0018] According to a fourth aspect of the present disclosure, a driving circuit control method is provided, applied to the driving circuit as described in the first aspect; the driving circuit control method includes: The control charging module charges the gate capacitor for a first duration during the associated time period when the first bootstrap driving module controls the first high-side switching transistor to turn on based on the first control signal.

[0019] This application provides a driving circuit, a driving chip, a control method, and a lidar. The driving circuit includes: a first high-side switching transistor, a first bootstrap driving module for driving the first high-side switching transistor, and a charging module; wherein, the first high-side switching transistor has a parasitic gate capacitance; a first terminal of the first high-side switching transistor is used to input a high-voltage side power supply signal, and a second terminal of the first high-side switching transistor is used to connect a load; the charging module is used to charge the gate capacitance for a first duration during the associated time period when the first bootstrap driving module controls the first high-side switching transistor to turn on based on a first control signal, to compensate for at least a portion of the charge charged by the first bootstrap driving module to the gate capacitance. Thus, during the associated time period when the first bootstrap driving module controls the first high-side switching transistor to turn on based on the first control signal, the charging module can charge the gate capacitance to reduce the amount of charge required for the first bootstrap driving module to turn on the first high-side switching transistor, thereby reducing the charge loss of the bootstrap capacitor of the first bootstrap driving module, increasing the gate-source voltage of the first high-side switching transistor, and further increasing the peak current of the high-side switching transistor to meet the driving requirements. Because bootstrap capacitors have less charge loss, they can be made with smaller capacitance values, thus avoiding the need to increase their capacitance or number. This reduces issues such as increased chip area, parasitic effects, and complex wiring caused by adding too many capacitors, thereby improving the performance of the driver chip.

[0020] Additional aspects and advantages of the embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments of this application. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, are provided. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of those features. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1One of the circuit block diagrams of the driving circuit provided in the embodiments of this application; Figure 2 This is a schematic diagram of the charging pulse timing provided in an embodiment of this application; Figure 3 A second schematic diagram of the driving circuit provided in the embodiments of this application; Figure 4 The third schematic diagram of the circuit block diagram of the driving circuit provided in the embodiments of this application; Figure 5 The fourth schematic diagram of the circuit block diagram of the driving circuit provided in the embodiments of this application; Figure 6 The fifth schematic diagram of the circuit block diagram of the driving circuit provided in the embodiments of this application; Figure 7 A schematic circuit block diagram of the driver chip provided in the embodiments of this application; Figure 8 This is one of the structural schematic diagrams of a lidar provided in the embodiments of this application; Figure 9 This is a second schematic diagram of the structure of the lidar provided in the embodiments of this application; Figure 10 This is a flowchart illustrating the control method provided in an embodiment of this application. Detailed Implementation

[0022] To make the technical solution and beneficial effects of the present invention more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0023] The embodiments described in this application are not exhaustive, but merely illustrative of some embodiments, and are not intended to limit the scope of protection of this application. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined with each other. For example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0024] In each embodiment of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0025] The terminology used in the embodiments of this application is for the purpose of describing specific embodiments only and is not intended to limit the scope of this application.

[0026] In the embodiments of this application, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the aforementioned," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular expression or a plural expression.

[0027] In the embodiments of this application, "multiple" refers to two or more.

[0028] In some embodiments, the terms “at least one of”, “one or more”, “a plurality of”, “multiple”, etc., may be used interchangeably.

[0029] The prefixes "first," "second," etc., used in the embodiments of this application are merely for distinguishing different descriptive objects and do not impose restrictions on the position, order, priority, value, or content of the descriptive objects. The description of the descriptive objects is based on the claims or the context of the embodiments, and the use of prefixes should not constitute unnecessary restrictions. For example, the numerical value of the descriptive object is not limited by ordinal numbers and can be one or more. Taking "first device" as an example, the numerical value of "device" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the descriptive object is "device," then "first device" and "second device" can be the same device or different devices, and their types can be the same or different.

[0030] In some embodiments, the term "connection" can refer to the transmission of electrical signals or data between the connected end and the connected end, and can be understood as "electrical connection," "communication connection," etc. A "connection" can be a direct connection between two components, an indirect connection established through other components, a connection within two components, or any other possible form of connection.

[0031] In some embodiments, the terms “greater than”, “greater than or equal to”, “not less than”, “more than”, “more than or equal to”, “not less than”, “higher than”, “higher than or equal to”, “not lower than”, “above”, “exceeding”, etc. can be used interchangeably, and the terms “less than”, “less than or equal to”, “not greater than”, “less than”, “less than or equal to”, “not more than”, “lower than”, “lower than or equal to”, “not higher than”, “below”, etc. can be used interchangeably.

[0032] Furthermore, each element, each row, or each column in the table of this disclosure can be implemented as an independent embodiment, and any combination of any element, any row, or any column can also be implemented as an independent embodiment.

[0033] It should be noted that the switching transistors (including the first high-side switching transistor, the second high-side switching transistor, and / or the third high-side switching transistor) in the embodiments of this application can be N-type transistors (MOS) unless contradictory. For N-type transistors, the on-state level is high and the off-state level is low. That is, when the gate of an N-type transistor is high, its input and output terminals are connected; when the gate of an N-type transistor is low, its input and output terminals are off. In specific implementations, the gate of each of the above-mentioned switching transistors is used as its control terminal. In the embodiments of this application, the drain and source are determined according to the transistor type: for N-type transistors, the drain can be used as the first terminal and the source as the second terminal. In addition, the on-state level and off-state level in the embodiments of this invention are general terms. The on-state level refers to any level that can make the transistor conduct, and the off-state level refers to any level that can make the transistor turn off / turn off. It is understood that the conduction of a transistor can include the conduction of the source and drain of the transistor. The turn-off of a transistor can include the turn-off of the source and drain of the transistor.

[0034] In multi-channel high-side laser driver applications, the high-side drive switch (i.e., high-side drive switch transistor) of each drive channel is a switching circuit used to connect the positive terminal of the power supply (such as VDD) to the positive terminal of the load. It is often used in applications that require precise control of the positive switching of the power supply, and is particularly suitable for systems where the load is grounded and the control signal is low-voltage logic.

[0035] Its key application is in laser drivers for lidar. High-side drive switching transistors are the performance levers of lidar. Ranging, resolution, and eye safety limits all depend on the peak optical power you can extract from the laser pulse. With the laser cathode grounded, high-side drive switching transistors allow the laser anode to swing cleanly, simplifying optical / mechanical integration. Each drive channel must output a 20A pulse of 2–10 nanoseconds from a 30V–40V power supply.

[0036] For high-side drive switching transistors, LDNMOS can be selected. LDNMOS can withstand a voltage of 40V and is cheaper than GaN. The disadvantage of LDNMOS is its very large gate capacitance. When driving the gate of LDNMOS, it is required to keep Vgs about 5V higher than the rising source node voltage (which rises to about 15–20V) throughout the entire pulse.

[0037] To achieve clean overdrive, each drive channel requires a bootstrap capacitor of at least 1–3 nF. Since the gate-source capacitance Cgs of LDNMOS is 200–500 pF, this means that 1–2.5 nC of charge is needed to raise the gate voltage to +5V, which is approximately 10 times that required for GaN devices.

[0038] To accommodate the 1~3nF on-chip bootstrap capacitor, a metal-to-metal capacitor area of ​​>20mm² will be required. The long top-layer metal connection will introduce inductance and resistance, slowing down the rise time of the 5V gate voltage and causing pulse flattening.

[0039] If capacitors are added externally to the chip, on the one hand, multiple large-size MLCC capacitors and their pins will crowd the circuit board; on the other hand, the approximately 2–3 nH inductance of each capacitor circuit will dissipate voltage during the fast edge, resulting in pulse flattening.

[0040] If a smaller bootstrap capacitor is used, the less charge on the bootstrap capacitor will result in insufficient gate charge. This causes the gate voltage Vgs to drop, which in turn increases the on-resistance Rds(on), reduces the peak current, and shortens the detection range of the lidar. The slower rise / fall times of the gate voltage Vgs will prolong the optical pulse and reduce depth accuracy.

[0041] Therefore, how to solve the problem of insufficient charging under large gate capacitance load and improve the peak current of high-side switching transistors is an urgent problem to be solved.

[0042] This disclosure provides a driving circuit 100, such as... Figure 1 As shown, the driving circuit 100 includes: a first high-side switching transistor Q1, a first bootstrap driving module 110 for driving the first high-side switching transistor Q1, and a charging module 120; wherein, The first high-side switching transistor Q1 has a parasitic gate capacitance Cgs; the first terminal of the first high-side switching transistor Q1 is used to input the high-voltage side power supply signal VDDH, and the second terminal of the first high-side switching transistor Q1 is used to connect to the load. The charging module 120 is used to charge the gate capacitor Cgs for a first duration during the associated time period when the first bootstrap driving module 110 turns on the first high-side switching transistor Q1 based on the first control signal (Fire1), so as to compensate for at least part of the charge charged by the first bootstrap driving module 110 on the gate capacitor Cgs.

[0043] In one possible implementation, the drive circuit 100 may include circuitry within a drive chip. A drive chip may include one or more drive channels, and each drive channel may include one drive circuit 100. Each drive channel can be used to drive a different load.

[0044] In one possible implementation, the drive circuit 100 may include a circuit composed of multiple electronic devices (including active electronic devices and / or passive electronic devices).

[0045] In one possible implementation, the load may include at least one of the following: laser D0, LED light, or motor.

[0046] For example, the driving circuit 100 may be a circuit in a multi-channel high-side laser driver used to drive a semiconductor laser diode. Multiple driving channels are integrated on the same integrated circuit chip, and each driving channel has a driving circuit 100. The load of the driving circuit 100 is a laser D0 (such as a semiconductor laser diode). One driving channel on a multi-channel high-side laser driver can drive one or more common-cathode semiconductor laser diodes.

[0047] The first high-side switching transistor Q1 can be implemented using a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0048] In one possible implementation, the first high-side switching transistor Q1 can be a laterally diffused metal-oxide-semiconductor (LDMOS) transistor to accommodate larger load currents and withstand excessive drain-source stress. LDMOS has a smaller drain-source on-resistance Rds(on) when turned on. For example, the first high-side switching transistor Q1 can be implemented using an N-channel LDMOS.

[0049] like Figure 1As shown, the first high-side switching transistor Q1 is powered by a high-voltage power supply. For example, the drain of an N-channel LDMOS receives the high-voltage power supply signal VDDH, the source of the N-channel LDMOS is connected to the load, and the gate voltage of the drain of the N-channel LDMOS is used to control the turn-on and turn-off of the drain and source. The voltage value of the high-voltage power supply signal is higher than the operating voltage value of the first bootstrap driving module 110. Therefore, when the first bootstrap driving module 110 drives the first high-side switching transistor Q1, a bootstrap capacitor is needed to maintain the voltage of the gate of the first high-side switching transistor Q1 (such as the gate of an N-channel LDMOS). Figure 1 In this circuit, capacitor C0 is used to filter the high-voltage side power supply signal VDDH. The drive circuit 100 may or may not include capacitor C0.

[0050] In one possible implementation, the first terminal of the first high-side switching transistor Q1 is the drain, and the second terminal of the first high-side switching transistor Q1 is the source.

[0051] When the first bootstrap driving module 110 drives the first high-side switching transistor Q1 to turn on, the first bootstrap capacitor C1 of the first bootstrap driving module 110 charges the gate capacitance Cgs of the gate of the first high-side switching transistor Q1 to increase the gate voltage Vg, thereby turning on the first high-side switching transistor Q1. The charge of the first bootstrap capacitor C1 charges the gate capacitance Cgs. If the first bootstrap capacitor C1 is small and the gate capacitance Cgs is large, the gate voltage may not reach the predetermined voltage value, resulting in an increase in the on-resistance Rdson of the first high-side switching transistor Q1 and a decrease in the peak current. The gate capacitance Cgs may include the parasitic capacitance between the gate and source of the first high-side switching transistor Q1.

[0052] Here, the charging module 120 can be used to charge the gate capacitor Cgs to compensate for the charge generated by the first bootstrap capacitor C1 charging the gate capacitor Cgs, thereby reducing the charge loss generated by the bootstrap capacitor of the first bootstrap driving module 110 charging the gate capacitor Cgs. This can reduce the influence of the large gate capacitor Cgs on the gate voltage Vg when the first bootstrap driving module 110 drives the first high-side switching transistor Q1, and improve the gate voltage value.

[0053] In one possible implementation, the associated time period for the first bootstrap driving module 110 to control the conduction of the first high-side switching transistor Q1 based on the first control signal may include at least one of the following: the time period before the first bootstrap capacitor C1 charges the gate capacitor Cgs to conduct the first high-side switching transistor Q1; or the time period during which the first bootstrap capacitor C1 charges the gate capacitor Cgs; or the time period after the first bootstrap capacitor C1 charges the gate capacitor Cgs to conduct the first high-side switching transistor Q1.

[0054] The first duration refers to the time during which the charging module 120 charges the gate capacitance Cgs of the first high-side switching transistor Q1. The first duration can be adjusted according to specific application requirements, for example, it can be from 0 nanoseconds to 3 nanoseconds. The choice of the first duration will affect the magnitude of the current after the first high-side switching transistor Q1 is turned on. The longer the first duration, the more fully the gate capacitance Cgs is charged, and the larger the conduction current.

[0055] In one possible implementation, the charging module 120 can charge the gate capacitor Cgs for a first duration after the first control signal enable moment. The enable moment of the first control signal can be the moment when the first control signal instructs the first bootstrap driving module 110 to drive the first high-side switching transistor Q1 to turn on via a level shift. Here, there can be a drive delay between the first control signal enable moment and the moment when the first bootstrap driving module 110 drives the first high-side switching transistor Q1 to turn on. The drive delay can include the response time of the first bootstrap driving module 110, and / or the response time of the first high-side switching transistor Q1, etc.

[0056] The charging module 120 can charge the gate capacitance Cgs of the first high-side switching transistor Q1 using a charging pulse. The first duration can be the duration of the charging pulse, i.e., the pulse width.

[0057] In one possible implementation, the charging module 120 can draw current from the high-voltage side power supply to charge the gate capacitor Cgs.

[0058] Thus, during the associated time period when the first bootstrap driving module 110 controls the conduction of the first high-side switching transistor Q1 based on the first control signal, the charging module 120 can charge the gate capacitor Cgs to reduce the amount of charge required for the first bootstrap driving module 110 to conduct the first high-side switching transistor Q1. This reduces the charge loss of the bootstrap capacitor in the first bootstrap driving module 110, increases the gate-source voltage of the first high-side switching transistor Q1, and further increases the peak current of the high-side switching transistor to meet the driving requirements. Since the charge loss of the bootstrap capacitor is relatively small, a smaller capacitance value can be used, thus avoiding the need to increase the capacitance or number of bootstrap capacitors. This reduces the chip area occupation, parasitic effects, and wiring complexity caused by adding too many capacitors, thereby improving the performance of the driving chip.

[0059] In some embodiments, the charging module 120 is used for one of the following: The gate capacitor Cgs is charged before the start time when the first bootstrap driving module 110 controls the first high-side switching transistor Q1 to turn on, and the charging of the gate capacitor Cgs is stopped during the turn-on time. The gate capacitor Cgs is charged for a first duration starting from the stated start time; The gate capacitor Cgs is charged for a first duration after the start time, wherein the end time of the first duration is before the end time of the conduction duration; The gate capacitor Cgs is charged for a first duration prior to the start time.

[0060] In one possible implementation, the first duration is less than the on-time of the first high-side switching transistor Q1. Specifically, Figure 2 This is a timing diagram showing the on-time of the first high-side switching transistor Q1 and the charging pulses of the charging module 120. (See diagram below.) Figure 2 As shown, the high level in timing P indicates the conduction state of the first high-side switching transistor Q1. The high level in timing S1~S2 indicates a charging pulse, and the duration of the high level is the first duration. The start time ts of the conduction of the first high-side switching transistor Q1 is approximately the start time of the first bootstrap driving module 110 charging the gate capacitor Cgs.

[0061] like Figure 2As shown, the charging pulse S1 starts before the start time ts of the first high-side switching transistor Q1 being turned on, and ends after the start time ts of the first high-side switching transistor Q1 being turned on, but before the end time te of the first high-side switching transistor Q1 being turned on. That is, the charging module 120 charges the gate capacitor Cgs before the first bootstrap driving module 110 turns on the first high-side switching transistor Q1, and continues to charge the gate capacitor Cgs for a period of time after the first bootstrap driving module 110 is turned on. This reduces the charge loss of the first bootstrap driving module 110 in charging the gate capacitor Cgs, increases the gate-source voltage of the first high-side switching transistor Q1, and thus increases the peak current of the high-side switching transistor, meeting the driving requirements.

[0062] like Figure 2 As shown, the start time of the charging pulse S2 is the same as the start time ts of the first high-side switching transistor Q1 being turned on, and the end time of the charging pulse is after the start time ts of the first high-side switching transistor Q1 being turned on, and before the end time te of the first high-side switching transistor Q1 being turned on. That is, the charging module 120 and the first bootstrap driving module 110 simultaneously charge the gate capacitor Cgs, and the first bootstrap driving module 110 continues to charge the gate capacitor Cgs for a period of time after it is turned on. This reduces the charge loss of the first bootstrap driving module 110 in charging the gate capacitor Cgs, increases the gate-source voltage of the first high-side switching transistor Q1, and thus increases the peak current of the high-side switching transistor to meet the driving requirements.

[0063] like Figure 2 As shown, the charging pulse S3 is located after the start time ts of the first high-side switching transistor Q1 being turned on, and before the end time te of the first high-side switching transistor Q1 being turned on. That is, the charging module 120 charges the gate capacitor Cgs after the first bootstrap driving module 110, and continues to charge the gate capacitor Cgs for a period of time after the first bootstrap driving module 110 is turned on. In this way, the charge of the gate capacitor Cgs can be increased, thereby increasing the gate-source voltage of the first high-side switching transistor Q1, and further increasing the peak current of the high-side switching transistor to meet the driving requirements.

[0064] like Figure 2As shown, the charging pulse S4 is located before the start time ts when the first high-side switching transistor Q1 is turned on. That is, the charging module 120 completes the charging of the gate capacitor Cgs before the first bootstrap driving module 110 charges the gate capacitor Cgs, and continues to charge the gate capacitor Cgs for a period of time after the first bootstrap driving module 110 is turned on. In this way, the amount of charge charged by the first bootstrap driving module 110 to the gate capacitor Cgs can be reduced, thereby increasing the gate-source voltage of the first high-side switching transistor Q1, and thus increasing the peak current of the high-side switching transistor to meet the driving requirements.

[0065] In some embodiments, such as Figure 1 As shown, the first bootstrap driving module 110 includes: a first bootstrap capacitor C1, a first buffer module U1, and a first diode D1; wherein, The anode of the first diode D1 is used to input the first low-voltage side power supply signal VDD1; The upper plate of the first bootstrap capacitor C1 is connected to the cathode of the first diode D1; The upper plate of the first bootstrap capacitor C1 is connected to the first power supply terminal of the first buffer module U1; The lower plate of the first bootstrap capacitor C1 is connected to the second power supply terminal of the first buffer module U1; The input terminal of the first buffer module U1 is used to input the first control signal; The output terminal of the first buffer module U1 is connected to the gate of the first high-side switching transistor Q1; The second power supply terminal of the first buffer module U1 is connected to the second terminal of the first high-side switching transistor Q1.

[0066] Here, the voltage value of the first low-voltage side power supply signal VDD1 is lower than the voltage value of the high-voltage side power supply signal VDDH. For example, if the voltage value of the first low-voltage side power supply signal VDD1 is 5V, the voltage value of the high-voltage side power supply signal VDDH can be greater than 20V, such as 30V. In this way, the drive channel can operate at a lower voltage, reducing operating losses.

[0067] The gate voltage Vg of the first high-side switching transistor Q1 is determined by the voltage between the two plates of the first bootstrap capacitor C1. Before the first control signal enables the first bootstrap drive module 110, the first low-side power supply signal VDD1 charges the first bootstrap capacitor C1 through the first diode D1. The voltage across the first bootstrap capacitor C1 can be higher than the threshold voltage (Vth) at which the first high-side switching transistor Q1 is turned on.

[0068] When the first control signal enables the first bootstrap driving module 110, the first high-side switching transistor Q1 is turned on. The voltage on the upper plate of the first bootstrap capacitor C1 is the sum of the voltage value of the first low-voltage side power supply signal VDD1 and the voltage value of the output voltage Vout of the source of the first high-side switching transistor Q1, thereby maintaining the first high-side switching transistor Q1 in the on state. Here, when the first high-side switching transistor Q1 is turned on, the output voltage Vout of the source of the first high-side switching transistor Q1 is the difference between the voltage value of the high-side power supply signal VDDH and the on-state voltage value of the first high-side switching transistor Q1.

[0069] In one possible implementation, the first buffer module U1 can be used for at least one of the following: During the on-time of the first high-side switching transistor Q1, the gate of the first high-side switching transistor Q1 and the upper plate of the first bootstrap capacitor C1 are turned on (e.g., through a MOS). Thus, the voltage between the two plates of the first bootstrap capacitor C1 enables the first high-side switching transistor Q1 to turn on. During the off-time of the first high-side switching transistor Q1, the gate of the first high-side switching transistor Q1 is disconnected from the upper plate of the first bootstrap capacitor C1, and the gate and source of the first high-side switching transistor Q1 are turned on (e.g., through a MOS transistor). This releases the gate charge and improves the turn-off speed of the first high-side switching transistor Q1.

[0070] In one possible implementation, the first buffer module U1 can be used to delay the first control signal. The first buffer module U1 can adjust the buffer duration between the arrival time of the first control signal at the first buffer module U1 and the output time of the first buffer module U1 to turn on or off the first high-side switching transistor Q1 by means of internal delay or other methods.

[0071] In some embodiments, such as Figure 3 As shown, the charging module 120 includes a second bootstrap driving module 121 and a second high-side switching transistor Q2; wherein, The first terminal of the second high-side switching transistor Q2 is used to input the high-voltage side power supply signal VDDH, and the second terminal of the second high-side switching transistor Q2 is used to connect to the gate of the first high-side switching transistor Q1. The second bootstrap driving module 121 is used to drive the second high-side switching transistor Q2 to conduct for the first duration in order to charge the gate capacitor Cgs.

[0072] Here, the second high-side switching transistor Q2 can be used to draw current from the high-voltage side power supply to charge the gate capacitor Cgs. The second bootstrap driving module 121 can control the turn-on and turn-off of the second high-side switching transistor Q2 through its gate. The second bootstrap driving module 121 can control the second high-side switching transistor Q2 to be turned on for a first duration, so as to charge the gate capacitor Cgs with the high-voltage side power supply for a first duration.

[0073] In one possible implementation, the first terminal of the second high-side switching transistor Q2 is the drain, and the second terminal of the second high-side switching transistor Q2 is the source.

[0074] like Figure 3 As shown, when the first high-side switching transistor Q1 is turned on, the voltage at the lower plate of the first bootstrap capacitor C1 rises to the output voltage Vout of the source of the first high-side switching transistor Q1. When the first high-side switching transistor Q1 is turned on, the first buffer module U1 conducts the upper plate of the first bootstrap capacitor C1 and the gate of the first high-side switching transistor Q1. The voltage at the upper plate of the first bootstrap capacitor C1 is the sum of the voltage of the first low-side power supply signal VDD1 and the output voltage Vout of the source of the first high-side switching transistor Q1. Therefore, the gate voltage Vg of the first high-side switching transistor Q1 is the sum of the voltage of the first low-side power supply signal VDD1 and the output voltage Vout of the source of the first high-side switching transistor Q1. The gate of the first high-side switching transistor Q1 is connected to the source of the second high-side switching transistor Q2. Therefore, the source voltage of the second high-side switching transistor Q2 is the sum of the voltage of the first low-voltage side power supply signal VDD1 and the output voltage Vout of the source of the first high-side switching transistor Q1. Thus, a higher voltage value is required to control the turn-on and turn-off of the second high-side switching transistor Q2. Therefore, when the second bootstrap driving module 121 drives the second high-side switching transistor Q2, a bootstrap capacitor is needed to maintain the gate voltage of the second high-side switching transistor Q2.

[0075] Since the second high-side switching transistor Q2 can charge the gate capacitance Cgs of the first high-side switching transistor Q1 using a smaller current, the power of the second high-side switching transistor Q2 can be set to be less than the power of the first high-side switching transistor Q1. For example, the power of the second high-side switching transistor Q2 can be 1 / 5 to 1 / 10 of the power of the first high-side switching transistor Q1.

[0076] In some embodiments, such as Figure 4 As shown, the second bootstrap driving module 121 includes: a second buffer module U2, a second diode D2, and a second bootstrap capacitor C2; The anode of the second diode D2 is used to input the second low-voltage side power supply signal VDD2; The upper plate of the second bootstrap capacitor C2 is connected to the cathode of the second diode D2; The upper plate of the second bootstrap capacitor C2 is connected to the first power supply terminal of the second buffer module U2; The lower plate of the second bootstrap capacitor C2 is connected to the second power supply terminal of the second buffer module U2; The input terminal of the second buffer module U2 is used for the second control signal (Fire2). The output terminal of the second buffer module U2 is connected to the control terminal of the second high-side switching transistor Q2; The second power supply terminal of the second buffer module U2 is connected to the second terminal of the second high-side switching transistor Q2.

[0077] Here, the voltage value of the second low-voltage side power supply signal VDD2 is lower than the voltage value of the high-voltage side power supply signal VDDH. The second bootstrap driver module 121 can operate at a lower voltage, reducing operating losses.

[0078] In one possible implementation, the first low-voltage side power supply signal VDD1 and the second low-voltage side power supply signal VDD2 can be the same low-voltage side power supply signal.

[0079] The gate voltage of the second high-side switching transistor Q2 is determined by the voltage between the two plates of the second bootstrap capacitor C2. Before the second control signal enables the second bootstrap drive module 121, the second low-side power supply signal VDD2 charges the second bootstrap capacitor C2 through the second diode D2. The voltage across the second bootstrap capacitor C2 is higher than the threshold voltage (Vth) at which the second high-side switching transistor Q2 is turned on.

[0080] When the second high-side switching transistor Q2 is turned on, the lower plate of the second bootstrap capacitor C2 is connected to the gate of the first high-side switching transistor Q1. The voltage between the two plates of the second bootstrap capacitor C2 is the sum of the voltage value of the second low-voltage side power supply signal VDD2 and the voltage value of the gate voltage Vg of the first high-side switching transistor Q1.

[0081] In one possible implementation, the second buffer module U2 is used for at least one of the following: during the on-time of the second high-side switching transistor Q2, turning on (e.g., through a MOS) the gate of the second high-side switching transistor Q2 and the upper plate of the second bootstrap capacitor C2. Thus, the voltage between the two plates of the second bootstrap capacitor C2 enables the second high-side switching transistor Q2 to turn on; during the off-time of the second high-side switching transistor Q2, disconnecting the gate of the second high-side switching transistor Q2 from the upper plate of the second bootstrap capacitor C2, and turning on (e.g., through a MOS) the gate of the second high-side switching transistor Q2 and the source of the second high-side switching transistor Q2. This releases the gate charge and improves the turn-off speed of the second high-side switching transistor Q2.

[0082] In one possible implementation, the second buffer module U2 can be used to delay the second control signal. The second buffer module U2 can adjust the buffer duration between the arrival time of the second control signal at the second buffer module U2 and the output time of the second buffer module U2 to turn on or off the second high-side switching transistor Q2 by means of internal delay or other methods.

[0083] In one possible implementation, the second buffer module U2 can control the time domain position of the second high-side switching transistor Q2 during its conduction period, that is, control the positional relationship between the charging pulse and the first high-side switching transistor Q1 during its conduction period.

[0084] In this way, the second high-side switching transistor Q2 completes the charging of the gate capacitance Cgs of the first high-side switching transistor Q1, thereby reducing the amount of charge in the first high-side switching transistor Q1, which in turn reduces the charge loss of the bootstrap capacitor of the first bootstrap driving module 110, increases the gate-source voltage of the first high-side switching transistor Q1, and further increases the peak current of the high-side switching transistor to meet the driving requirements.

[0085] In some embodiments, the first control signal and the second control signal are the same control signal, and the second buffer module U2 is used to drive the second high-side switching transistor Q2 to conduct for the first duration based on the first control signal; or; The first control signal and the second control signal are different control signals. The second control signal is used to control the second buffer module U2 to drive the second high-side switching transistor Q2 to conduct for the first duration.

[0086] Here, the first control signal used to control the first buffer module U1 and the second control signal used to control the second buffer module U2 can be the same control signal. After being triggered by the first control signal (or the second control signal), the second buffer module U2 can adjust its own response duration to adjust the temporal positional relationship between the charging pulse and the conduction period of the first high-side switching transistor Q1.

[0087] The first control signal used to control the first buffer module U1 and the second control signal used to control the second buffer module U2 can be different control signals. The time-domain positional relationship between the charging pulse of the charging module 120 and the conduction period of the first high-side switching transistor Q1 can be adjusted by adjusting the time-domain positional relationship between the first control signal and the second control signal. For example, the second buffer module U2 can use a fixed response duration. Thus, the time-domain position of the charging pulse of the charging module 120 can be adjusted by adjusting the triggering time of the second control signal.

[0088] Thus, the timing position of the charging pulse can be adjusted through the second buffer module U2 or through the second control signal to meet different charging needs and improve charging flexibility.

[0089] In some embodiments, the second buffer module U2 includes a digital buffer module for delaying based on the first control signal to adjust the start time of the first duration, wherein the delay is associated with a first register value of the digital buffer module; and / or The first duration is associated with the second register value of the digital buffer module.

[0090] The digital buffer module can adjust its own response time to delay the first control signal, thereby adjusting the start time of the first duration.

[0091] The second buffer module U2 can be configured with a first register to set its value. Different first register values ​​correspond to different delays.

[0092] The second buffer module U2 can also be equipped with a second register for setting its value. Different second register values ​​correspond to different first durations.

[0093] For example, the second register can occupy two bits to indicate four different first durations, such as indicating: 0 nanoseconds, 1 nanosecond, 2 nanoseconds, or 3 nanoseconds.

[0094] In this way, the digital buffer module enables the adjustment of the charging pulse time domain position and / or pulse width, thereby achieving flexible adjustment of the charging of the gate capacitor Cgs to meet different needs.

[0095] In some embodiments, the conduction current between the first terminal of the first high-side switching transistor Q1 and the second terminal of the first high-side switching transistor Q1 is positively correlated with the first duration.

[0096] Here, the longer the first duration, the longer the charging module 120 charges the gate capacitor Cgs, resulting in a higher gate-source voltage of the first high-side switching transistor Q1, thus increasing the on-state current of the high-side switching transistor. Conversely, the shorter the first duration, the shorter the charging time of the charging module 120 on the gate capacitor Cgs, resulting in a lower charge used by the first bootstrap capacitor C1 to charge the gate capacitor Cgs, and thus a lower voltage across the first bootstrap capacitor C1. Consequently, the gate-source voltage of the first high-side switching transistor Q1 is lower, and therefore the on-state current of the first high-side switching transistor Q1 is lower.

[0097] In some embodiments, such as Figure 5 As shown, the first bootstrap driving module 110 further includes a clamping component 111 for clamping the voltage difference between the gate of the first high-side switching transistor Q1 and the second terminal of the first high-side switching transistor Q1.

[0098] When the second high-side switching transistor Q2 is turned on, the gate of the first high-side switching transistor Q1 is connected to the high-voltage side power supply signal VDDH. On the one hand, when the first high-side switching transistor Q1 is not turned on, a high gate-source voltage difference will be generated, which may damage the first high-side switching transistor Q1. On the other hand, when the first buffer module U1 is turned on, the high-voltage side power supply signal VDDH is directly injected into the upper plate of the first bootstrap capacitor C1, which may cause the first bootstrap drive module 110 to fail. Therefore, a clamping component 111 can be provided between the gate of the first high-side switching transistor Q1 and the second terminal (source) of the first high-side switching transistor Q1 to clamp the voltage difference between the gate of the first high-side switching transistor Q1 and the second terminal (source) of the first high-side switching transistor Q1.

[0099] The clamping component 111 can be implemented using diodes, transistors, clamping chips, etc.

[0100] The clamping component 111 can keep the voltage between the gate of the first high-side switching transistor Q1 and the second terminal of the first high-side switching transistor Q1 within a safe range, thereby improving the reliability of the first high-side switching transistor Q1 and reducing the risk of failure of the first bootstrap driving module 110.

[0101] In some embodiments, such as Figure 6As shown, the clamping component 111 includes a Zener diode ZD1, wherein the cathode of the Zener diode ZD1 is connected to the gate of the first high-side switching transistor Q1, and the anode of the Zener diode ZD1 is connected to the second terminal (source) of the first high-side switching transistor Q1.

[0102] In one possible implementation, the Zener diode ZD1 can maintain the voltage between the gate of the first high-side switching transistor Q1 and the second terminal (source) of the first high-side switching transistor Q1 within the range of 5.7V.

[0103] In one possible implementation, the aforementioned first control signal and / or second control signal can be sent by the controller to control the drive circuit to drive the load.

[0104] A specific example is provided in conjunction with the above embodiments to illustrate this application in detail.

[0105] like Figure 6 As shown, the driving circuit includes a charging module.

[0106] The ground reference of the charging module is the gate of the first high-side switching transistor (the gate voltage varies with the source voltage).

[0107] The second bootstrap capacitor within the charging module uses a 50–100pF capacitor to store a fixed +5V voltage. That is, the second low-voltage side power supply signal is 5V.

[0108] The drain of the second high-side switching transistor is connected to the high-voltage side power supply signal, and the source of the second high-side switching transistor is connected to the gate of the first high-side switching transistor.

[0109] The size of the second high-side switching transistor is approximately 1 / 5 to 1 / 10 of that of the first high-side switching transistor, corresponding to Rds(on)≈1–2Ω.

[0110] The second control signal of the second buffer module is converted into a 5V or 0V voltage to control the second high-side switching transistor to turn on or off.

[0111] First high-side switching transistor gate clamping: A 5.7V Zener diode is placed between the gate and source of the first high-side switching transistor to prevent overshoot.

[0112] The five stages of drive circuit control are shown in Table 1: Table 1

[0113] The charging module can regulate the gate and source voltage Vgs of the first high-side switching transistor.

[0114] When the second high-side switching transistor is turned on, its gate charges the gate of the first high-side switching transistor at a rate of Ig = (Vhv / Rds(on,SC)). Here, Ig represents the charging current, Vhv represents the voltage value of the high-voltage side power supply signal, and Rds(on,SC) represents the on-resistance between the drain and source of the second high-side switching transistor.

[0115] The longer the pulse width (i.e. the first duration) of the charging pulse of the charging module, the higher the gate voltage of the first high-side switching transistor, until it is clamped by 5.7V Zener.

[0116] The gate voltage of the first high-side switching transistor after the charging pulse is approximately: Vsrc + ΔQ / Cgs, where ΔQ = Ig × tsc. Here, Vsrc represents the initial gate voltage of the first high-side switching transistor, ΔQ represents the amount of charging charge, and tsc represents the first duration (pulse width of the charging pulse).

[0117] Therefore, Vgs ∝ tsc; for example, for a 300pF gate capacitor, a pulse width change of 2ns can adjust Vgs by approximately 0.5V.

[0118] By programming the tsc in steps of 0.5–1 ns, the peak laser current can be corrected according to process deviations, or multi-level optical power modulation can be achieved.

[0119] The TSC code for each channel is stored in an on-chip register; factory testing can scan the pulse width, measure the light output, and lock the code—no external correction components are required.

[0120] It can perform dynamic power control, and the firmware can adjust the TSC online in real time according to temperature compensation or eye safety dimming requirements, with a delay of microseconds.

[0121] Its advantage lies in achieving ±5% laser current precision control while retaining the ultra-fast response (<2ns) advantage of the supercharger architecture, adapting to PVT changes.

[0122] Using the solution of this application, the gate rise time of the first high-side switching transistor is reduced from 8–15ns to ≤2ns. Since there is no need to increase the capacitance of the first bootstrap capacitor, the silicon area of ​​the driver chip can be saved: from an additional >20mm² of capacitance to a tiny FET + tiny capacitor of <0.3–0.5mm². No external capacitors are required. External device requirements: 8 MLCCs → 0. Reduced loop inductance: multiple nH → <500pH (on-chip). Peak laser current loss: eliminated; a full 20A current can be maintained at high repetition rate (PRF). Charge is injected directly from the high-voltage power rail via the charging module, effectively reducing parasitic parameters, protecting the gate of the first high-side switching transistor, and easily supporting high-channel-count LiDAR SoC expansion.

[0123] Since the Vgs of the first high-side switching transistor is only about 5V, even a change of 0.5V in Vgs (by fine-tuning the charging pulse width by 1–2ns) can result in a change in current of several amperes.

[0124] The actual data of the peak current of the first high-side switching transistor were adjusted by adjusting the first duration, as shown in Table 2: Table 2

[0125] Regarding the driver chip structure: Each drive channel is equipped with a charging module. The local reference node of the charging module is the gate of the first high-side switching transistor; it rises along with the source voltage during laser emission.

[0126] The second bootstrap capacitor in the charging module is approximately 1 / 10 of the gate capacitance (Cgs) of the first high-side switching transistor; it provides the energy required by the control circuit, while the gate of the first high-side switching transistor...

[0127] The drain of the second high-side switching transistor is connected to a 30–40V power rail, and the source of the second high-side switching transistor is connected to the gate of the first high-side switching transistor. The size of the second high-side switching transistor is approximately 10–20% of that of the first high-side switching transistor, enabling the delivery of large current pulses in a very small silicon area.

[0128] The second buffer module in the second bootstrap drive module converts the second control signal pulse into a 0 / 5V drive signal relative to the gate node of the second high-side switching transistor.

[0129] An integrated gate-source clamp for the first high-side switching transistor (≈5.7V Zener or equivalent) limits the Vgs voltage of the first high-side switching transistor under all process / voltage / temperature (PVT) deviations and pulse width errors, ensuring its safety.

[0130] The charging module provides a time-limited sequence of charging pulses. Within a narrow window (approximately 1–3 ns), the second high-side switching transistor is turned on to inject charge from the high-voltage side power supply into the gate of the first high-side switching transistor, and then completely turned off.

[0131] Robust structural size ratio: – The second bootstrap capacitance is ≤ 10–20% of the gate capacitance of the first high-side switching transistor.

[0132] – The Rds(on) of the second high-side switching transistor is approximately 1 / 5 to 1 / 10 of that of the first high-side switching transistor.

[0133] Automatic charging path of the second bootstrap capacitor: It supports pulse repetition frequencies of ≥10MHz without the need for external components or additional pins.

[0134] Digital fine-tuning of the charging pulse width (achieved by setting a second buffer module): Each channel has a programmable register that compensates for process, voltage, temperature, and aging variations. It offers scalability without requiring external bootstrap capacitors. This architecture adds only <0.3–0.5 mm² of silicon area per channel and requires no additional package pins, enabling the integration of eight or more high-side laser drive channels on a single chip.

[0135] Charging pulse width modulation (PWMSC) is achieved through a charging module.

[0136] A multi-channel high-side laser driver, wherein the peak laser diode current (peak current of the first high-side switching transistor) is set by digitally adjusting the duration of the charging pulse.

[0137] The charging pulse drives the second high-side switching transistor, thereby establishing an adjustable gate-source voltage on the first high-side switching transistor.

[0138] Key features: A time-limited pulse (0–10 ns) is issued synchronously with the laser trigger command.

[0139] The gate charge of the first high-side switching transistor is proportional to the pulse width of the charging pulse. The first high-side switching transistor Vgs and the first high-side switching transistor on-state current Ilaser exhibit predictable proportional changes.

[0140] An integrated first high-side switching transistor gate clamp ensures that the Vgs of the first high-side switching transistor does not exceed the safety limit, even at maximum pulse width.

[0141] Performance range: For example: tsc=0ns⇒~1A; tsc=3ns⇒≥20A (clamping takes effect); It can maintain an electrical rise time of <2ns at any programming level.

[0142] Innovations of Pulse Width Modulation Charging (PWMSC)

[0143] Digital fine-tuning register: Each channel is encoded (e.g., 3–5 bits) and stored in non-volatile or OTP memory to eliminate the effects of process differences or mismatches.

[0144] Dynamic power regulation application scenarios: Firmware control TSC updates to support: 1. Temperature compensation; 2. Eye-safe "low beam" vs. "high beam"; 3. Multi-echo / return LiDAR pulse mode.

[0145] Calibration and testing methods: The factory process iteratively scans the TSC, measures the optical output, and locks the value—no external DAC required.

[0146] Closed-loop adaptive: Monitors photodiode current or power rail voltage drop feedback to automatically adjust TSC in real time.

[0147] Pulse width timing range limitation: The TSC programmable range starts from 0ns and continues until the gate clamp is turned on (approximately Vgs≈5.7V) to ensure safe operation.

[0148] Channel scalability: The architecture supports ≥8 channels without adding package pins, and each channel can reuse the same on-chip timing for one charging module.

[0149] This disclosure provides a driver chip, such as... Figure 7 As shown, the driver chip 200 includes at least one driver channel 210; the driver channel 210 includes the driver circuit 100. The driver circuit 100 is implemented as described in any of the above embodiments, and will not be repeated here.

[0150] This disclosure provides a lidar, such as... Figure 8 The lidar 10 shown includes a driving circuit 100, or, as... Figure 9 The lidar 10 shown includes a driver chip 200.

[0151] The lidar also includes at least one laser.

[0152] In one possible implementation, the driver chip 200 includes at least one driver channel 210; the driver channel 210 includes the driver circuit 100.

[0153] The driving circuit 100 is used to drive at least one laser; or a driving channel 210 of the driving chip 200 is used to drive at least one laser.

[0154] The specific implementation of the driving circuit 100 or the driving chip 200 is as described in any of the above embodiments, and will not be repeated here.

[0155] The driver circuit 100 or driver chip 200 can be applied to the following scenarios: 1. Power supply control for vertical-cavity surface-emitting laser (VCSEL).

[0156] The high-side switching transistor (first high-side switching transistor) is used to controllably connect the positive terminal of the power supply (e.g., 5V / 12V) to the anode of the VCSEL laser for laser pulse emission control.

[0157] It supports fast switching, enabling precise control of short pulses (typically 1ns~10ns) for high-precision ranging.

[0158] 2. Optical power modulation.

[0159] By cooperating with PWM or pulse modulation signals, the optical output power or pulse width can be precisely adjusted by controlling the conduction time of the high-side switching transistor (the first high-side switching transistor), thereby realizing functions such as near-field / far-field power control.

[0160] 3. Multi-channel laser scanning system.

[0161] In multi-beam or MEMS scanning lidar, high-side switching transistors (first high-side switching transistors) control lasers in multiple drive channels respectively, supporting time-division multiplexing (TDM) or space-division multiplexing (SDM) strategies.

[0162] 4. Laser safety protection and control.

[0163] When an abnormal signal is received (such as overheating, overcurrent, or system malfunction), the high-side switching transistor (the first high-side switching transistor) can quickly disconnect the laser power supply path to achieve emergency shutdown.

[0164] This disclosure provides a driving circuit control method, applied to a driving circuit; such as... Figure 10 As shown, the control method of the drive circuit 100 includes: Step 1001: The control charging module charges the gate capacitor for a first duration during the associated time period when the first bootstrap driving module turns on the first high-side switching transistor based on the first control signal.

[0165] In one possible implementation, the driver chip includes a driver circuit. The implementation of the driver circuit and / or driver chip is as described in any of the above embodiments, and will not be repeated here.

[0166] In one possible implementation, the drive circuit control method can be executed by the controller.

[0167] In one possible implementation, the drive circuit includes a controller.

[0168] In one possible implementation, the controller is independent of the drive circuitry.

[0169] The implementation method of the drive circuit driving the load under the control of the controller is as described in any of the above embodiments, and will not be repeated here.

[0170] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0171] In the description of this specification, references to "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0172] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A driving circuit, characterized in that, The driving circuit includes: a first high-side switching transistor, a first bootstrap driving module for driving the first high-side switching transistor, and a charging module; wherein... The first high-side switching transistor has a parasitic gate capacitance; the first terminal of the first high-side switching transistor is used to input a high-voltage side power supply signal, and the second terminal of the first high-side switching transistor is used to connect a load; The charging module is used to charge the gate capacitor for a first duration during the associated time period when the first bootstrap driving module turns on the first high-side switching transistor based on the first control signal, so as to compensate for at least part of the charge charged by the first bootstrap driving module to the gate capacitor.

2. The driving circuit according to claim 1, characterized in that, The charging module is used for one of the following: The gate capacitor is charged before the start time when the first bootstrap driving module controls the first high-side switching transistor to turn on, and the charging of the gate capacitor is stopped during the turn-on duration; The gate capacitor is charged for a first duration starting from the stated start time; The gate capacitor is charged for a first duration after the start time, wherein the end time of the first duration is before the end time of the conduction duration; The gate capacitor is charged for a first duration before the start time.

3. The driving circuit according to claim 1, characterized in that, The first bootstrap driving module includes: a first bootstrap capacitor, a first buffer module, and a first diode; wherein... The anode of the first diode is used to input a first low-voltage side power supply signal; The upper plate of the first bootstrap capacitor is connected to the cathode of the first diode; The upper plate of the first bootstrap capacitor is connected to the first power supply terminal of the first buffer module; The lower plate of the first bootstrap capacitor is connected to the second power supply terminal of the first buffer module; The input terminal of the first buffer module is used to input the first control signal; The output terminal of the first buffer module is connected to the gate of the first high-side switching transistor; The second power supply terminal of the first buffer module is connected to the second terminal of the first high-side switching transistor.

4. The driving circuit according to claim 1, characterized in that, The charging module includes a second bootstrap driving module and a second high-side switching transistor; wherein... The first terminal of the second high-side switching transistor is used to input a high-voltage side power supply signal, and the second terminal of the second high-side switching transistor is used to connect to the gate of the first high-side switching transistor. The second bootstrap driving module is used to drive the second high-side switching transistor to conduct for the first duration in order to charge the gate capacitor.

5. The driving circuit according to claim 4, characterized in that, The second bootstrap driving module includes: a second buffer module, a second diode, and a second bootstrap capacitor; The anode of the second diode is used to input the second low-voltage side power supply signal; The upper plate of the second bootstrap capacitor is connected to the cathode of the second diode; The upper plate of the second bootstrap capacitor is connected to the first power supply terminal of the second buffer module; The lower plate of the second bootstrap capacitor is connected to the second power supply terminal of the second buffer module; The input terminal of the second buffer module is used for the second control signal. The output terminal of the second buffer module is connected to the control terminal of the second high-side switching transistor; The second power supply terminal of the second buffer module is connected to the second terminal of the second high-side switching transistor.

6. The driving circuit according to claim 5, characterized in that, The first control signal and the second control signal are the same control signal, and the second buffer module is used to drive the second high-side switching transistor to conduct for the first duration based on the first control signal; or; The first control signal and the second control signal are different control signals. The second control signal is used to control the second buffer module to drive the second high-side switching transistor to conduct for the first duration.

7. The driving circuit according to claim 6, characterized in that, The second buffer module includes a digital buffer module for adjusting the start time of the first duration based on the first control signal by performing a time delay, wherein the time delay is associated with a first register value of the digital buffer module; and / or The first duration is associated with the second register value of the digital buffer module.

8. The driving circuit according to claim 1, characterized in that, The conduction current between the first terminal of the first high-side switching transistor and the second terminal of the first high-side switching transistor is positively correlated with the first duration.

9. The driving circuit according to any one of claims 1 to 8, characterized in that, The first bootstrap driving module further includes a clamping component for clamping the voltage difference between the gate of the first high-side switching transistor and the second terminal of the first high-side switching transistor.

10. The driving circuit according to claim 9, characterized in that, The clamping component includes a Zener diode, wherein the cathode of the Zener diode is connected to the gate of the first high-side switching transistor, and the anode of the Zener diode is connected to the second terminal of the first high-side switching transistor.

11. A driver chip, characterized in that, The driver chip includes at least one driver channel, and each driver channel includes a driver circuit as described in any one of claims 1 to 9.

12. A lidar, characterized in that, Includes the driving circuit as described in any one of claims 1 to 9 or the driving chip as described in claim 11. The lidar also includes at least one laser; The driving circuit is used to drive at least one laser; or each driving channel of the driving chip is used to drive at least one laser.

13. A method for controlling a drive circuit, characterized in that, Applied to the driving circuit as described in any one of claims 1 to 9; The drive circuit control method includes: The control charging module charges the gate capacitor for a first duration during the associated time period when the first bootstrap driving module controls the first high-side switching transistor to turn on based on the first control signal.

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