Successive approximation register analog-to-digital converter device based on composite dielectric gate and working method

Abstract

The application discloses a successive approximation type analog-digital conversion device based on a composite dielectric grid and a working method, and belongs to the technical field of semiconductor devices, analog-digital conversion and storage-computation integration. The device is divided into coupling units with different areas according to binary values, and then the control of each weight coupling unit is realized through binary weights. The device does not need large MIM capacitors and complex metal switch trees, thereby reducing area consumption. The on-off characteristics of a semiconductor are utilized, and whether the readout transistor is turned on or not is taken as a comparison result to realize the step-by-step comparison between a two-part interval and an input quantity, thereby avoiding the comparison circuit logic of a circuit stage, so that the power consumption of a quantization unit is significantly reduced. In addition, the device provided by the application has a simple structure, can be extended in a row or column direction in parallel according to actual conditions, and mismatch can be eliminated through code table compensation. The device can be used as an on-chip ADC front end and can also be embedded in a pixel / storage-computation unit as a local quantizer, and has strong versatility.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, analog-to-digital conversion and storage-computation integration, and in particular to a successive approximation type analog-to-digital conversion device based on a composite dielectric gate and a working method thereof. BACKGROUND

[0002] With the popularity of edge terminals, micro sensors and low-power artificial intelligence devices, there is an increasing demand for chips to integrate non-volatile storage and high-energy-efficiency analog interface / ADC. The traditional on-chip architecture scheme usually integrates a separate analog front end and ADC outside the storage array. The analog front end realizes signal acquisition and preprocessing, the ADC completes the conversion of analog signals to digital signals, and the storage array is responsible for data storage and transmission. The three work together to realize data processing. However, in this scheme, the storage array, the analog front end and the ADC have redundant module layout, and in order to reduce signal attenuation, additional driving buffers and shielding layers need to be added, which will further increase the area consumption. In addition, in operation, data needs to be transported back and forth between the storage unit and the computing / conversion unit, which cannot meet the demand of real-time, high-speed storage of data in application scenarios, and consumes a large amount of energy with low energy efficiency.

[0003] At present, the mainstream ADC readout architecture mainly includes the following schemes:

[0004] (1) Capacitor array type successive approximation (SAR) ADC: its principle is based on successive approximation method, through binary search algorithm to approximate input voltage value, to realize DAC with binary weight capacitor or split capacitor, and then to search code word with comparator. The advantages of this scheme are low power consumption, digital friendly, simple structure and easy integration; but hundreds of high matching degree capacitors and switches are needed; when the resolution is improved, the total value of the capacitor increases, the input equivalent capacitor rises significantly, which leads to driving difficulty; at the same time, capacitor mismatch, kT / C thermal noise and switch injection will directly limit the effective number of bits (ENOB), and force to use larger area unit to exchange matching.

[0005] (2) Resistor string / resistor ladder ADC: its principle is to form a voltage division network by connecting multiple resistors in series, and each resistor node is controlled by a switch to connect to the reference voltage or ground, and the output voltage corresponding to different digital code values is realized by controlling the switch state. This scheme has good stability due to its inherent monotony, and has low power consumption and low differential linearity; but because the entire resistor array is always connected between the reference voltage and ground, continuous current consumption leads to high static power consumption, area increases exponentially with resolution, and a large number of analog switches are needed.

[0006] (3) Pipeline / oversampling (Sigma-Delta) ADC: the principle of pipeline ADC is to decompose the analog-digital conversion process into multiple cascaded sub-stages, each stage completes low-resolution conversion and extracts the residual signal into the next stage for further processing; the principle of oversampling ADC is to realize high-resolution analog-digital conversion through oversampling and noise shaping technology; this scheme has low power consumption and low cost, and also has high resolution and accuracy, suitable for medium-speed or high-precision application scenarios, but the analog amplifier and reference refresh circuit are complex, and the power consumption and area are difficult to meet the constraints of micro-power and ultra-small SoC / sensor nodes.

[0007] In addition, the existing scheme also has the following key pain points:

[0008] (1) The traditional ADC scheme is composed of sampling, voltage comparison, clock control and other circuit modules, which occupies a large area of silicon chip, limiting the integration and miniaturization development of the chip;

[0009] (2) A large number of sense amplifiers or high-speed peripheral ADCs are needed for high-parallel array output, and due to the size of the traditional scheme, the array readout of small-size devices cannot be realized by single-column configuration of a traditional ADC, which needs to be multiplexed, introducing non-ideal factors and complex control timing.

[0010] (3) The circuit-level ADC needs multi-stage amplification, clock and calibration logic, and the dynamic power consumption and static leakage are significant during operation, which is difficult to meet the low-power application requirements. SUMMARY

[0011] In order to solve the problems existing in the prior art, the present application provides a successive approximation type analog-digital converter based on composite dielectric gate, which can realize sampling and holding, binary weighting and successive approximation comparison structure at the device level, and can realize row synchronization and column readout with a small number of control lines, significantly reducing the area and energy consumption of analog-digital conversion, and also having good weight linearity and calibrability.

[0012] The device provided by the present application comprises a P-substrate, a floating gate, a readout control gate and a write control gate; the floating gate is arranged above the P-substrate, and the readout control gate and the write control gate are arranged above the floating gate.

[0013] The P-substrate is provided with an input well, a shallow trench isolation, a successive approximation weight coupling unit group and a readout transistor, one end of the P-substrate is provided with the readout transistor, the other side of the readout transistor is provided with the successive approximation weight coupling unit group, and the other side of the successive approximation weight coupling unit group is provided with the input well; the input well, the successive approximation weight coupling unit group and the readout transistor are separated by the shallow trench isolation.

[0014] The successive approximation weight coupling unit group comprises a plurality of weight coupling units with different effective coupling areas, and the plurality of weight coupling units are separated by shallow trench isolation.

[0015] The floating gate above the input well far from the shallow trench isolation is disconnected, which is a left-right structure. Control gates are arranged above the left and right floating gates. The control gate far from the input well and the weight coupling unit is a write control gate, and the control gate above the input well and the weight coupling unit is a read control gate.

[0016] The floating gate is arranged above the P-substrate, and the floating gate above the input well far from the shallow trench isolation is disconnected, which is a left-right structure. Control gates are arranged above the left and right floating gates. The control gate far from the input well and the weight coupling unit is a write control gate, and the control gate above the input well and the weight coupling unit is a read control gate.

[0017] The device further comprises a high reference potential, a low reference potential and a pull-up resistor, wherein the high reference potential and the low reference potential are located on both sides of the P-substrate d, and the plurality of weight coupling units are connected to the high reference potential and the low reference potential at the same time.

[0018] The drain region of the read transistor is connected to the high reference point through the pull-up resistor, and the source region of the read transistor is connected to the low reference point.

[0019] Further, the read control gate and the floating gate are capacitively coupled, which is used to apply a fixed bias in the read stage.

[0020] Further, the plurality of weight coupling units are separated by shallow trench isolation, and the effective coupling areas of each weight coupling unit are configured according to a binary ratio and are capacitively coupled to the floating gate.

[0021] Further, one end of each weight coupling unit is provided with an upper gate, and the other end is provided with a lower gate. Each weight coupling unit is connected to the high reference potential through the upper gate and connected to the low reference potential through the lower gate.

[0022] Further, the upper gate and the lower gate each comprise a source end and a drain end, the drain end is located on the outer side, and the source end is located on the inner side.

[0023] Further, the upper gate and the lower gate are mutually exclusive in the open state, that is, the upper gate is open and the lower gate is closed, and the upper gate is closed and the lower gate is open.

[0024] Further, the write control gate is turned on in the sampling stage to store the input potential to the input well, and is turned off in the holding stage.

[0025] Further, the channel of the read transistor is located in the gate-down region formed by the floating gate and the read control gate.

[0026] Furthermore, the composite dielectric layer of the floating gate is a silicon oxide / silicon nitride / silicon oxide stack, with an equivalent oxide layer thickness of 3-15 nm.

[0027] The second objective of this invention is to provide a working method for a successive approximation analog-to-digital converter based on a composite dielectric gate; this method quantizes the input quantity by using a bisection method, that is, by successively bisecting the input quantity to approximate the input quantity, and finally obtaining the quantized value;

[0028] Determine the bit width to be quantized, and then divide the binary values ​​from the most significant bit to the least significant bit into coupling wells of different areas. Divide each coupling well into weighted coupling units, and connect each weighted coupling unit to the high / low reference potential through the upper and lower selectors.

[0029] When enabling several weighted coupling units sequentially, by comparison The equivalent threshold voltage is used to determine the state of the readout transistor based on the potential at the lower end of the pull-up resistor. The conduction of the weighted coupling unit is converted into the on or off state of the readout transistor. By detecting the state of the readout transistor, the result of successive binary approximation of several weighted coupling units is obtained, thus obtaining an n-bit digital quantization code. Finally, the digital quantization code is inverted bit by bit to obtain the ADC quantization result of the input quantity.

[0030] The complete process involves enabling each coupling unit sequentially in the order of MSB→LSB (most significant bit to least significant bit). Simultaneously, it detects whether the readout transistor is on or off, and obtains the successive binary approximation result; thus, it obtains an n-bit digital quantization code, and inverts each bit of the digital quantization code to obtain the ADC quantization result of the input quantity.

[0031] Furthermore, the entire device workflow includes: sampling phase, holding phase, successive approximation phase, and readout phase;

[0032] Sampling phase: Open the write control gate and couple the input quantity to the floating gate through the input well;

[0033] Hold phase: Close the write control gate;

[0034] Successive approximation stage: A fixed bias is applied to the readout control gate, and several weighted coupling units are enabled sequentially in order from the most significant bit to the least significant bit. If the readout transistor is turned on, the enable of the weighted coupling unit is retained and the code value 1 is output; otherwise, the lower selector of the weighted coupling unit is turned on, the weighted coupling unit is cleared, and the code value 0 is output.

[0035] Output stage: The obtained n-bit result is formed into a digital code in the order from the most significant bit to the least significant bit, and then the digital code is inverted bit by bit and the quantization result is output.

[0036] Further, the effective coupling area of the several weight coupling units satisfies the expression:

[0037]

[0038] wherein, represents the effective coupling area of the nth weight coupling unit.

[0039] Further, the high reference potential _k and the low reference potential _k satisfy any fixed value in the interval of 0-Vdd, and can also be positive and negative symmetrical potentials;

[0040] Further, the floating gate and the readout control gate are capacitively coupled, and the readout control gate provides a fixed potential in the successive approximation stage:

[0041]

[0042] wherein, represents the threshold of the readout transistor, represents the quantized full amplitude voltage;

[0043] Further, the write control gate is used to sample the input well potential. When the write control gate is enabled, the electron write tube is turned on, realizing the storage of the input quantity into the input well. When the write control gate is disabled, the electron write tube is turned off.

[0044] Further, the device enables the weight coupling units in the order of MSB→LSB (most significant bit to least significant bit) in sequence, and simultaneously detects whether the readout transistor is turned on or not, to obtain the result of successive bisection approximation.

[0045] The specific steps are as follows: first, a fixed voltage is applied to the readout control gate so that the device readout transistor is in the on state,

[0046] The bias setting of the readout control gate is:

[0047]

[0048]

[0049] wherein, represents the threshold of the readout transistor, represents the quantized full amplitude voltage, represents the nth quantized code value, is the input quantity, is the input quantity of the weight coupling unit, is the input well capacitance, is the nth quantized code value, is the input quantity, Bit quantization capacitor

[0050] Opening the write control gate, writing the input quantity to the input well, at this time if the read transistor continues to be opened, quantization can be carried out, otherwise it is determined that the over-range is exceeded, and the FS voltage needs to be replaced.

[0051] According to the MSB→LSB (most significant bit to least significant bit) order, a plurality of weight coupling units are enabled in sequence, that is, a plurality of upper gates of the weight coupling units are opened in sequence, and lower gates of the weight coupling units are closed; the write voltage value is:

[0052]

[0053] If the read transistor is turned on at this time, the state of the upper and lower gates of the weight coupling unit at this time is maintained, and the judgment of the next coupling unit is carried out;

[0054] If the read transistor is turned off at this time, the state of the upper and lower gates of the weight coupling unit at this time is reversed, that is, the upper gate is closed and the lower gate is turned on, and the judgment of the next coupling unit is carried out;

[0055] Finally, the comparison of all the weight coupling units is completed, thereby obtaining an n-bit digital quantization code, and the digital code is inverted bit by bit to obtain the input ADC quantization result.

[0056] A third object of the present application is to provide a preparation method of a successive approximation type analog-to-digital converter device based on a composite medium grid, the method comprising:

[0057] Step one: forming a P-type substrate on a silicon wafer through photolithography, doping, oxidation and mask control;

[0058] Step two: forming a shallow trench isolation strip through etching along the column direction of the P-type substrate obtained in step one and backfilling a medium;

[0059] Step three: performing photolithography on the device treated in step two, defining input wells and each weight coupling unit according to binary area, then performing ion implantation and high-temperature annealing back expansion / activation;

[0060] Step four: removing the sacrificial oxide layer through etching, and growing a tunneling oxide layer through a thermal oxidation method, a wet chemical method or a plasma-assisted oxidation method;

[0061] Step five: depositing a first layer of polysilicon and doping, and then performing patterning to form a floating gate;

[0062] Step six: depositing a medium (silicon oxide / silicon nitride / silicon oxide stack) between the floating gate and the read control gate;

[0063] Step seven: depositing a second layer of polysilicon or metal gate and patterning, forming control gate / row word line along the row direction, and simultaneously forming write control gate;

[0064] Step eight: completing light doping source-drain of the upper and lower pass-gate tubes, forming side wall, heavy doping source-drain, and annealing activation;

[0065] Step nine: performing chemical mechanical polishing on the interlayer dielectric layer, and opening contact holes to: input well, contact area / selection tube of each level of weight coupling unit, and lead-out position of read control gate / write control gate;

[0066] Step ten: connecting the upper pass-gate tube of each level of weight coupling unit to a high reference potential, connecting the lower pass-gate tube to a low reference potential, and laying power supply / ground / position line;

[0067] Step eleven: realizing passivation by chemical vapor deposition, atomic layer deposition, or thermal oxidation, and then performing dicing and packaging, to complete the preparation of the device / array.

[0068] A fourth object of the present application is to provide a successive approximation type analog-to-digital converter device array based on a composite medium gate, which is composed of a plurality of successive approximation quantization devices based on a composite medium gate structure stacked in the row or column direction, and read control gates, write control gates, high and low reference potentials connected to corresponding positions of other devices in the same direction.

[0069] In order to offset process and temperature drift mismatch, power-on self-calibration is provided, and the steps include inputting a set of high-precision DAC signals, using successive approximation devices for quantization, making a code table of output quantization values and input quantization values, or calculating a mapping function relationship, storing calibration parameters on the chip, and adjusting the output according to the calibration parameters.

[0070] Compared with the prior art, the present application has the following beneficial effects:

[0071] The application provides a successive approximation type analog-digital conversion device based on a composite dielectric gate and a working method. BRIEF DESCRIPTION OF DRAWINGS

[0072] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0073] Figure 1 A top view structural schematic diagram of a successive approximation type analog-digital conversion device based on a composite dielectric gate provided by the first embodiment of the present application is shown in FIG. 1.

[0074] Figure 2 A cross-sectional schematic diagram of the successive approximation type analog-digital conversion device based on the composite dielectric gate provided by the first embodiment of the present application along the column direction is shown in FIG. 2.

[0075] Figure 3 An equivalent circuit schematic diagram of the successive approximation type analog-digital conversion device based on the composite dielectric gate provided by the first embodiment of the present application is shown in FIG. 3.

[0076] Figure 4 A working timing diagram of the successive approximation type analog-digital conversion device based on the composite dielectric gate provided by the second embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0077] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail in combination with the drawings.

[0078] Embodiment one

[0079] The present embodiment provides a successive approximation type analog-digital conversion device based on a composite dielectric gate, and the structure of the device is as shown in FIG. 1.Figure 1 and Figure 2 As shown in the figure, it comprises: a P-substrate, a floating gate, a read control gate and a write control gate; the floating gate is arranged above the P-substrate, and the read control gate and the write control gate are arranged above the floating gate;

[0080] The P-substrate is provided with an input well, shallow trench isolation, a successive approximation weight coupling unit group and a read transistor. One end of the P-substrate is provided with the read transistor, the other side of the read transistor is provided with the successive approximation weight coupling unit group, and the other side of the successive approximation weight coupling unit group is provided with the input well. The input well, the successive approximation weight coupling unit group and the read transistor are separated by the shallow trench isolation.

[0081] The successive approximation weight coupling unit group comprises a plurality of weight coupling units with different effective coupling areas, and the plurality of weight coupling units are also separated by the shallow trench isolation.

[0082] The floating gate above the end away from the shallow trench isolation of the input well is disconnected, i.e., the structure of the left and right ends. The control gates are correspondingly arranged above the left and right end floating gates. The control gate away from the input well and the weight coupling unit is the write control gate, and the control gate above the input well and the weight coupling unit is the read control gate.

[0083] The floating gate is arranged above the P-substrate, and the floating gate above the end away from the shallow trench isolation of the input well is disconnected, i.e., the structure of the left and right ends. The control gates are correspondingly arranged above the left and right end floating gates. The control gate away from the input well and the weight coupling unit is the write control gate, and the control gate above the input well and the weight coupling unit is the read control gate.

[0084] The device further comprises a high reference potential, a low reference potential and a pull-up resistor. The high reference potential and the low reference potential are respectively located on both sides of the P-substrate, and the plurality of weight coupling units are simultaneously connected to the high reference potential and the low reference potential.

[0085] The drain region of the read transistor is connected to the high reference potential through the pull-up resistor, and the source region of the read transistor is connected to the low reference potential.

[0086] The read control gate and the floating gate are capacitively coupled, and used for applying a fixed bias in the read stage.

[0087] The plurality of weight coupling units are separated by the shallow trench isolation, and the effective coupling areas of each weight coupling unit are configured according to a binary ratio and capacitively coupled with the floating gate.

[0088] One end of each weight coupling unit is provided with an upper gate, and the other end is provided with a lower gate; and each weight coupling unit is connected with a high reference potential through the upper gate and connected with a low reference potential through the lower gate; the upper gate and the lower gate both include a source end and a drain end, the drain end is located at the outer side, and the source end is located at the inner side; the upper gate and the lower gate are in an open state and are mutually exclusive, that is, the upper gate is open and the lower gate is closed, and the upper gate is closed and the lower gate is open;

[0089] The write control gate is turned on in the sampling stage for storing the input potential to the input well and turned off in the holding stage; the channel of the read transistor is located in the gate-down region formed by the floating gate and the read control gate; the composite dielectric layer of the floating gate is a silicon oxide / silicon nitride / silicon oxide stack, and the equivalent oxide layer thickness is 3-15 nm.

[0090] The equivalent circuit of the device is as shown in Figure 3

[0091] The write part includes an electronic write tube, the corresponding control gate is a write control gate, and the connected external signal is a write drain voltage, which is the input to be quantized;

[0092] The weight coupling unit part includes an input well equivalent capacitor and eight equivalent capacitors, the upper plate of each equivalent capacitor is connected to a high potential , and the lower plate is connected to a substrate potential; the upper plate of each equivalent capacitor is a floating gate equivalent capacitor, and the upper plate of the floating gate equivalent capacitor is connected to a read control gate;

[0093] The read part includes an electronic read tube, the read control gate is connected together with the read control gate above the weight coupling unit, the read drain voltage is connected to a high potential through a pull-up resistor , and the read source voltage is connected to a substrate;

[0094] The read drain outputs a quantized signal.

[0095] Embodiment two

[0096] The embodiment provides a working method of a successive approximation type analog-to-digital conversion device based on a composite dielectric gate, which is based on the device described in embodiment one, and in the embodiment, the use method is introduced by taking the 1.22V voltage quantized by an 8-bit quantized unit device as an example; the working time sequence of each weight coupling unit in the method is as shown in Figure 4 .

[0097] The method comprises the following steps:

[0098] Step S1: sequentially operating the weight coupling units according to the working time sequence as shown in Figure 4 , , , , ​​, , and The voltage applied to each weight coupling unit is 1.28V, 0.64V,..., 0.01V in turn;

[0099] Step S2: A fixed voltage is applied to the readout control gate so that

[0100] = 0.64V + 2.56V

[0101] At this time, the device readout transistor is in an open state (i.e., the drain region outputs a high level), and the readout transistor compares the size of the equivalent threshold voltage of the device through comparison , and the high and low of the comparison result is represented by the opening and closing of the transistor; the opening or closing state of the readout transistor is determined by detecting the size of the potential at the lower end of the pull-up resistor, and a high potential represents off and a low potential represents on;

[0102] Step S3: The write control gate is opened, so that the channel writes an input voltage to the input well, and the input amount is denoted as At this time, the state of the readout transistor is used to determine the next operation:

[0103] If the readout transistor is open, output , and jump to step S4;

[0104] If the readout transistor is closed, output , which exceeds the comparison range, and the range is reset;

[0105] The range setting method is as follows: multiply 2.56V in = + 2.56V and the voltage 1.28V, 0.64V,..., 0.01V corresponding to each weight coupling unit by a coefficient K (K>1) to obtain a new equivalent voltage, and then repeat step S3;

[0106] Step S4: The upper tube (upper gate) of the weight coupling unit is opened, and the on voltage 1.28V is turned on and written, and the signal amount is denoted as At this time, the size of and is compared;

[0107] If the readout transistor is open, output , and jump to step S5;

[0108] If the readout transistor is closed, output , and the lower tube (lower gate) of the weight coupling unit is opened so that the weight coupling well Cleared, redirected to S5;

[0109] Step S5: Open the weighted coupling unit The upper selector transistor is turned on and written with a voltage of 0.64V, and its signal quantity is denoted as... Comparison at this time and Size;

[0110] If the read transistor is turned on, then the output will be... Proceed to step S6;

[0111] If the read transistor is off, the output will be... Open the weighted coupling unit The lower selection tube enables weighted coupling wells Cleared, redirected to S6;

[0112] Step S6: Follow the above process sequentially to obtain the results. , , , as well as The value;

[0113] Step S7: Open the weighted coupling unit The upper selector transistor is turned on and a voltage of 0.01V is written to it; its signal quantity is denoted as... ,Compare and Size;

[0114] If the read transistor is turned on, then the output will be... Proceed to step S8;

[0115] If the read transistor is off, the output will be... Open the weighted coupling unit The lower selection tube enables weighted coupling wells Cleared, redirected to S8;

[0116] Step S8: Organize the results obtained in the above steps to obtain... At this point, the following equation holds true:

[0117]

[0118] Will The output quantization result of the ADC is obtained by taking the bit-by-bit inverse code.

[0119] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0120] The above merely describes preferred embodiments of the present application, and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A successive approximation type analog-digital conversion device based on a composite dielectric gate, characterized by, The device comprises a P-substrate, a floating gate, a read control gate and a write control gate; The floating gate is arranged above the P-substrate, and the read control gate and the write control gate are arranged above the floating gate; The P-substrate is provided with an input well, shallow trench isolation, a group of successive approximation weight coupling units and a read transistor; one end of the P-substrate is provided with the read transistor, the other side of the read transistor is provided with the group of successive approximation weight coupling units, and the other side of the group of successive approximation weight coupling units is provided with the input well; the input well, the group of successive approximation weight coupling units and the read transistor are separated by the shallow trench isolation, and the weight coupling units in the group of successive approximation weight coupling units are also separated by the shallow trench isolation; The group of successive approximation weight coupling units comprises a plurality of weight coupling units with different effective coupling areas, and the weight coupling units are separated by the shallow trench isolation; the effective coupling areas of the plurality of weight coupling units are configured according to binary ratios; the group of successive approximation weight coupling units is capacitively coupled with the floating gate, and is used for applying a fixed bias in a read stage; The read control gate is used for providing a fixed potential in a successive approximation stage; wherein, representing a threshold value of the read transistor, representing a full-scale voltage of quantization; The effective coupling areas of the plurality of weight coupling units satisfy the expression: wherein, represents the effective coupling area of the nth weight coupling unit.

2. The device of claim 1, wherein, The floating gate has a structure of two segments, and is disconnected above the end of the input well away from the shallow trench isolation; the write control gate is arranged above one segment of the floating gate, and the read control gate is arranged above the other segment of the floating gate.

3. The device of claim 2, wherein, The device further comprises a pull-up resistor, a high reference potential and a low reference potential; The high reference potential and the low reference potential are located at two sides of the P-substrate, respectively; The high reference potential and the low reference potential satisfy any fixed value in the interval of 0-Vdd; The drain region of the read transistor is connected with the high reference potential through the pull-up resistor, and the source region is connected with the low reference potential.

4. The device of claim 3, wherein, One end of each weight coupling unit in the group of successive approximation weight coupling units is provided with an upper gate, and the other end is provided with a lower gate; the weight coupling unit is connected with the high reference potential through the upper gate, and is connected with the low reference potential through the lower gate; The upper gate and the lower gate each comprise a source end and a drain end, and the drain end of the upper gate and the lower gate is located at the outer side, and the source end is located at the inner side; The upper gate and the lower gate are mutually exclusive in the open state, that is, the upper gate is open and the lower gate is closed, or the upper gate is closed and the lower gate is open.

5. The device of claim 4, wherein, The write control gate is turned on in a sampling stage to store an input potential to the input well, and is turned off in a holding stage.

6. The device of claim 5, wherein, The composite dielectric layer in the floating gate is a silicon oxide / silicon nitride / silicon oxide stack, and the equivalent oxide layer thickness is 3-15 nm.

7. A method of operating a successive approximation analog-to-digital conversion device based on a composite dielectric gate, characterized by, The working method is based on the device according to any one of claims 1-6; The working method sequentially enables a plurality of weight coupling units in order from the most significant bit to the least significant bit, and simultaneously compares the bias of the readout control gate when sequentially enabled and the equivalent threshold voltage, and then judges the state of the readout transistor according to the potential of the pull-up resistor; whether the weight coupling unit is turned on or not is converted into whether the readout transistor is turned on or off, the result of the successive bisection approximation of the plurality of weight coupling units is obtained by detecting whether the readout transistor is turned on or not, thereby obtaining an n-bit digital quantization code, and finally the digital quantization code is inverted bit by bit to obtain the ADC quantization result of the input quantity.

8. The method of working according to claim 7, characterized in that, The working method comprises: Step S1: a fixed voltage is applied to the read control gate to make the read transistor in a conductive state, The bias of the read control gate is set as: wherein, represents the first quantized code value, represents the input quantity, represents the signal quantity input to the weight coupling unit, is the input well capacitance, is the first bit quantization capacitance; Step S2: open the write control gate, write the input quantity to the input well, at this time if the read transistor continues to be on, quantization is performed, otherwise it is determined that the range is exceeded, and the quantization full-scale voltage is replaced ; Step S3: a plurality of weight coupling units are sequentially enabled in the order of the most significant bit to the least significant bit, that is, the upper gate of the weight coupling unit is sequentially opened, and the lower gate of the weight coupling unit is sequentially closed; the conductive write voltage value is: If the read transistor is on at this time, the state of the upper and lower pass-gates of the weight coupling unit at this time is maintained, and the judgment of the next coupling unit is performed; If the read transistor is off at this time, the state of the upper and lower pass-gates of the weight coupling unit at this time is reversed, i.e. the upper pass-gate is off and the lower pass-gate is on, and the judgment of the next weight coupling unit is performed; Step S4: the comparison of all weight coupling units is completed according to the operation in step S3, thereby obtaining an n-bit digital quantization code, and the digital quantization code is inverted bit by bit to obtain the input ADC quantization result.

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