Silicon capacitor structure and manufacturing method thereof

Abstract

The invention discloses a silicon capacitor structure and a manufacturing method thereof, and the method comprises the steps: bonding a first substrate with a second substrate, the first substrate comprises a first surface and a second surface which are opposite to each other, and the second surface is bonded with the second substrate; forming a deep trench in the first substrate; a first insulating layer and a polycrystalline silicon layer are formed in the deep groove, the polycrystalline silicon layer and the first substrate are separated by the first insulating layer, the first substrate serves as one electrode plate of the silicon capacitor structure, and the polycrystalline silicon layer serves as the other electrode plate of the silicon capacitor structure; and releasing the bonding between the first substrate and the second substrate. According to the silicon capacitor structure and the manufacturing method thereof provided by the invention, the first substrate and the second substrate are bonded, so that the probability of warping of the first substrate is reduced when the deep groove is etched in the first substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon capacitor structure and its manufacturing method. Background Technology

[0002] Silicon capacitors typically consist of a bottom electrode (polycrystalline silicon or metal), a dielectric layer (SiO2, Si3N4, etc.), and a top electrode (polycrystalline silicon or metal). Existing silicon capacitor structures are divided into planar and trench types. Planar structures are simpler and have smaller capacitance; compared to planar structures, trench structures are more complex but have larger capacitance.

[0003] In the field of semiconductor devices, trench silicon capacitors, with their advantages of high capacitance density and small footprint, have become core components in integrated circuit power management, signal filtering, and other modules. A key step in their manufacturing process is the etching process to form a regularly arranged trench structure on the surface of a silicon substrate. However, the etching process is highly susceptible to silicon wafer warping, severely impacting the yield of subsequent processes and device performance.

[0004] Stress accumulation during the etching process is the main cause of warpage. For example, after dense etching on one side, the etched area will bend towards the non-etched surface due to stress concentration, forming an arc-shaped warpage. Therefore, the trench depth of trench-type silicon capacitors is limited, making it difficult to increase the surface area of ​​the electrode and dielectric contact to improve capacitance.

[0005] Silicon wafer warping can lead to alignment deviations in subsequent photolithography processes, uneven film deposition thickness, and in severe cases, even wafer breakage, significantly reducing production efficiency and product reliability. Summary of the Invention

[0006] In view of the above problems, the purpose of the present invention is to provide a silicon capacitor structure and a method for manufacturing the same, which reduces the probability of warping of the first substrate when etching deep trenches in the first substrate by bonding the first substrate to the second substrate.

[0007] According to one aspect of the present invention, a method for manufacturing a silicon capacitor structure is provided, comprising: bonding a first substrate to a second substrate, the first substrate including opposing first and second surfaces, the second surface being bonded to the second substrate; forming a deep trench in the first substrate; forming a first insulating layer and a polysilicon layer in the deep trench, the first insulating layer separating the polysilicon layer and the first substrate, wherein the first substrate serves as one electrode plate of the silicon capacitor structure, and the polysilicon layer serves as the other electrode plate of the silicon capacitor structure; and releasing the bonding between the first substrate and the second substrate.

[0008] Optionally, the step of forming a deep trench in the first substrate includes: forming a patterned mask layer on a first surface of the first substrate; and forming a deep trench in the first substrate via the mask layer.

[0009] Optionally, the deep trench extends along the first surface of the first substrate to the vicinity of the second surface.

[0010] Optionally, the deep trenches extend in alternating bends on a first surface of the first substrate.

[0011] Optionally, the step of forming a first insulating layer and a polysilicon layer in the deep trench includes: depositing an insulating material in a first surface of the first substrate and in the deep trench to form a first insulating layer, the first insulating layer covering the sidewalls and bottom of the deep trench and forming a trench along the deep trench; depositing a polysilicon layer in the trench and etching back the polysilicon layer so that the upper surface of the polysilicon layer is flush with the first surface of the first substrate.

[0012] Optionally, between the steps of forming the first insulating layer and the polysilicon layer in the deep trench and debonding the first substrate and the second substrate, the method further includes: forming a second insulating layer on the first insulating layer and the polysilicon layer; forming a conductive channel that penetrates the second insulating layer and extends into the polysilicon layer; and forming a first metal layer and a passivation layer on the second insulating layer.

[0013] Optionally, the passivation layer includes vias that penetrate the passivation layer and expose a portion of the upper surface of the first metal layer.

[0014] Optionally, after the step of unbonding the first substrate and the second substrate, the method further includes: forming a second metal layer on a second surface of the first substrate.

[0015] According to another aspect of the present invention, a silicon capacitor structure is provided, which is formed using the manufacturing method described above.

[0016] The silicon capacitor structure and manufacturing method provided by the present invention bond a first substrate to a second substrate, so that when a deep trench is etched in the first substrate, the second substrate can provide support for the first substrate, thereby reducing the probability of the first substrate warping.

[0017] Furthermore, since the second substrate provides support for the first substrate, the aspect ratio of the deep trenches can be further increased when etching deep trenches in the first substrate, thereby increasing the surface area of ​​the electrode and dielectric contact to improve the capacitance. Attached Figure Description

[0018] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0019] Figure 1A flowchart illustrating a method for manufacturing a silicon capacitor structure according to an embodiment of the present invention is shown;

[0020] Figures 2a to 2l Cross-sectional views of each stage of a method for manufacturing a silicon capacitor structure according to an embodiment of the present invention are shown;

[0021] Figure 3 A method for manufacturing a silicon capacitor structure according to an embodiment of the present invention is shown. Figure 2c The corresponding top view. Detailed Implementation

[0022] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0023] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0024] Figure 1 A flowchart illustrating a method for manufacturing a silicon capacitor structure according to an embodiment of the present invention is shown; Figures 2a to 2l Cross-sectional views of each stage of a method for manufacturing a silicon capacitor structure according to an embodiment of the present invention are shown. Figure 3 A method for manufacturing a silicon capacitor structure according to an embodiment of the present invention is shown. Figure 2c The corresponding top view.

[0025] refer to Figure 2l The silicon capacitor structure of this application includes a substrate 120, a first insulating layer 131, a polysilicon layer 132, a second insulating layer 133, a conductive channel 134, a first metal layer 135, a passivation layer 136, and a second metal layer 137.

[0026] Specifically, the substrate 120 includes opposing first and second surfaces, and includes at least one deep trench extending from the first surface of the substrate 120 toward the second surface, extending to the vicinity of the second surface but not penetrating the substrate 120, i.e., the bottom of the deep trench is spaced a predetermined distance D1 from the second surface of the substrate 120. Wherein, as... Figure 2l The multiple deep trenches shown are actually connected, but the connection area is not shown in the cross-sectional view. However, it can be understood that the deep trenches meander along one direction on the surface of the substrate 120, for example, in a bow-like shape.

[0027] A first insulating layer 131 is located on the first surface of the substrate 120, as well as the sidewalls and bottom of the deep trench. The first insulating layer 131 forms a second trench around the sidewalls and bottom of the deep trench. A polysilicon layer 132 fills the second trench. The first insulating layer 131 serves to separate the polysilicon layer 132 and the substrate 120. The upper surface of the polysilicon layer 132 is flush with the first surface of the substrate 120, but lower than the upper surface of the first insulating layer 131 located on the first surface of the substrate 120.

[0028] The second insulating layer 133 is located on the polysilicon layer 132 and the first insulating layer 131. The second insulating layer 133 and the first insulating layer 131 together surround the polysilicon layer 132, thereby separating the polysilicon layer 132 from other material layers.

[0029] The conductive channel 134 penetrates the second insulating layer 133 and extends into the polysilicon layer 132 beneath the second insulating layer 133. Specifically, the conductive channel 134 is located, for example, within the range of a deep trench, such that after penetrating the second insulating layer 133, the conductive channel 134 can extend into the corresponding polysilicon layer 132, rather than into the first insulating layer 131 and / or the substrate 120.

[0030] The first metal layer 135 is located on the second insulating layer 133, but the first metal layer 135 is electrically connected to the polysilicon layer 132 via the conductive channel 134.

[0031] A passivation layer 136 is located on the first metal layer 135 and serves to protect the first metal layer 136. The passivation layer 136 also includes a via 104, which penetrates the passivation layer 136 and exposes the surface of the first metal layer 135. The via 104 serves as an electrical connection window to the package frame during subsequent packaging of the silicon capacitor structure.

[0032] The second metal layer 137 is located on the second surface of the substrate 120.

[0033] exist Figure 2l In the silicon capacitor structure shown, the polysilicon layer 132 serves as one of the first and second electrode plates of the capacitor, and the substrate 120 serves as the other of the first and second electrode plates of the capacitor; the first insulating layer 131 serves as the dielectric layer of the first and second electrode plates in the isolation capacitor; the first metal layer 135 and the second metal layer 137 are respectively connected to the polysilicon layer 132 and the substrate 120, serving as the lead-out layers of the two electrode plates of the capacitor.

[0034] Further, refer to Figure 1 and Figures 2a to 2l The method for manufacturing this silicon capacitor structure includes:

[0035] Step S10: Bond the first substrate to the second substrate.

[0036] In this step, the second surface of the first substrate 110 and the first surface of the second substrate 110 are first pretreated to remove impurities from the bonding surface and optimize the surface condition; then, the first surface of the second substrate 110 and the second surface of the first substrate 120 are aligned and bonded together, as follows. Figure 2a As shown.

[0037] In this process, the first substrate 120 serves as the substrate in the silicon capacitor structure, and the second substrate 110 serves as the bonding substrate, which is used to support the first substrate 120 in subsequent processes to reduce the probability of the first substrate 122 warping.

[0038] In this application, the purpose of bonding the first substrate 120 and the second substrate 110 is to support the first substrate 120. The bonding of the first substrate 120 and the second substrate 110 will also be touched in subsequent steps. That is, the second substrate 110 is not part of the final silicon capacitor structure. Therefore, this bonding method needs to consider the support strength and whether the final debonding process will affect the silicon capacitor structure.

[0039] The first substrate 120 serves as an electrode plate in the final silicon capacitor structure. The first substrate 120 can be a doped single-crystal silicon substrate or a silicon substrate.

[0040] Step S20: A mask layer is formed on the first surface of the first substrate, and a deep trench is formed in the first substrate through the mask layer.

[0041] In this step, a mask layer 101 is formed on the first surface of the first substrate 120 using processes such as chemical vapor deposition, physical vapor deposition, and liquid phase deposition. The mask layer 101 is then patterned to define the etching region of the deep trench on the first surface of the first substrate 120. Figure 2b As shown.

[0042] In this embodiment, the mask layer 101 is, for example, photoresist. The photoresist is first coated on the first surface of the first substrate 120 using a spin coating process, and then patterned by exposure and development.

[0043] Furthermore, wet etching, dry etching, ion beam etching, and other processes are used to etch the first substrate 120 through a mask layer to form deep trenches 102 in the first substrate 120, such as... Figure 2c As shown.

[0044] The deep trench 102 extends from the first surface of the first substrate 120 to the second surface, but the deep trench 102 does not penetrate the first substrate 120. Compared with trenches that are not etched by bonding with the second substrate 110, the deep trench 102 in this application, due to the support of the second substrate 110, can increase the etching depth of the trench during the etching process, achieve a higher aspect ratio, and at the same time reduce the degree of warpage of the first substrate 120, which facilitates subsequent processes.

[0045] In this embodiment, the deep trench 102 extends in alternating bends on the first surface of the first substrate 120. Specifically, refer to... Figure 3 , Figure 2c For example, along Figure 3 The cross-sectional view obtained in the direction shown by the dashed line in the figure, the alternating bending extension refers to the deep trench 102 being alternately bent and extended in the directions such as y, x, y, (-x), y, x, y, (-x), y, where x is a first direction along the first surface of the first substrate 120, y is a second direction along the first surface of the first substrate 120, the first direction is perpendicular to the second direction; and (-x) represents the direction opposite to the first direction.

[0046] Step S30: Form a first insulating layer in the first surface and deep trench of the first substrate.

[0047] In this step, insulating materials are deposited on the first surface of the first substrate 120 and in the deep trench 102 using processes such as chemical vapor deposition, physical vapor deposition, and liquid phase deposition to form a first insulating layer 131, such as... Figure 2d As shown.

[0048] The first insulating layer 131 covers the first surface of the first substrate 120, the sidewalls and bottom of the deep trench 102, and the first insulating layer 131 forms a trench inside the deep trench 102 with a size smaller than that of the deep trench 102 around the sidewalls of the deep trench.

[0049] The first insulating layer 131 serves as the dielectric layer between the two electrode plates in the silicon capacitor structure. At this time, the dimensions such as the depth and width of the trench affect the capacitance of the silicon capacitor structure. Therefore, the capacitance of the silicon capacitor can be controlled by controlling the dimensions such as the depth and width of the deep trench 131 and the thickness of the first insulating layer 131.

[0050] The first insulating layer 131 needs to have multiple characteristics such as high dielectric constant, low dielectric loss, good insulation, high breakdown field strength, strong adhesion to the silicon substrate, and stable chemical and thermal properties. Specifically, the material of the second insulating layer 131 includes one or more combinations of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, etc., and silicon oxide is used as an example in this application.

[0051] Step S40: Deposit a polysilicon layer in a deep trench and etch back the polysilicon layer.

[0052] In this step, a polysilicon layer 132 is deposited in the deep trench using processes such as chemical vapor deposition, physical vapor deposition, and liquid phase deposition. Then, the polysilicon layer 132 is etched back so that the upper surface of the portion of the polysilicon layer 132 located in the deep trench 102 is flush with the upper surface of the first substrate 120. Figure 2e and 2f As shown.

[0053] In this step, since the polysilicon layer 132 will eventually be etched back to be flush with the first surface of the first substrate 120, the deposited polysilicon layer 132 can be used to fill the deep trench 102, thus avoiding material waste.

[0054] Furthermore, since the upper surface of the polysilicon layer 132 after back etching is flush with the first surface of the first substrate 120, a groove is formed between the upper surface of the polysilicon layer 132 and the upper surface of the first insulating layer 131.

[0055] In this embodiment, the polysilicon layer 132 serves as another electrode plate in the silicon capacitor structure. Separated by the first insulating layer 131, the polysilicon layer 132 and the first substrate 120 form a capacitor structure.

[0056] In other embodiments, the polysilicon layer 132 may also be other materials such as gold, aluminum, copper, tantalum nitride, or titanium nitride that can form a capacitor with the first substrate 120.

[0057] Step S50: Form a second insulating layer on the first insulating layer and on the surface of the polysilicon layer.

[0058] In this embodiment, a second insulating layer 133 is formed on the surface of the first insulating layer 131 and the surface of the polysilicon layer 132 using processes such as chemical vapor deposition, physical vapor deposition, and liquid phase deposition. Figure 2g As shown.

[0059] The second insulating layer 133 and the first insulating layer 131 surround the polysilicon layer 132 and separate the polysilicon layer 132 from other material layers.

[0060] The material of the second insulating layer 133 includes, for example, oxides, nitrides, etc.

[0061] Step S60: Form a conductive channel that penetrates the second insulating layer and extends into the polysilicon layer.

[0062] In this step, a patterned mask layer is first formed on the second insulating layer 133, and the second insulating layer 133 is etched through the mask layer to form vias penetrating the second insulating layer 133 and extending into the polysilicon layer 132; then, conductive material is deposited in the vias to form conductive channels 134, such as... Figure 2h As shown.

[0063] The patterned mask layer exposes a portion of the polysilicon layer 132 on the upper surface of the second insulating layer 133 above it, such that the formed via extends through the second insulating layer 133 and into the polysilicon layer 132, rather than into the second substrate 120.

[0064] The conductive channel 134 is electrically connected to the polycrystalline silicon layer 132. The material of the conductive channel 134 includes, for example, tungsten, aluminum, copper, doped polycrystalline silicon, etc.

[0065] Furthermore, it also includes removing the mask layer after forming the conductive channel and planarizing the surface of the conductive channel so that its upper surface is flush with the upper surface of the second insulating layer 133.

[0066] Step S70: Form a first metal layer and a passivation layer on the second insulating layer.

[0067] In this step, chemical vapor deposition, physical vapor deposition, and liquid phase deposition are used to sequentially deposit a first metal layer 135 and a passivation layer 136 on the second insulating layer 133, such as... Figure 2i and 2h As shown.

[0068] The first metal layer 135 is electrically connected to the polysilicon layer 132 via a conductive channel 134. The passivation layer 136 is used to protect the first metal layer 135.

[0069] Furthermore, it also includes forming a via 104 in the passivation layer 136, the via 104 penetrating the passivation layer 136 and exposing a portion of the surface of the first metal layer 135. In this embodiment, the via 104 serves as an electrical connection window between the silicon capacitor structure and the package frame during subsequent packaging.

[0070] Step S80: Debond the first substrate and the second substrate.

[0071] In this step, the bonding between the first substrate 120 and the second substrate 110 is released, such as... Figure 2k As shown.

[0072] Specifically, the debonding methods include pyrolysis, laser debonding, mechanical peeling, solvent dissolution, and other methods. A suitable debonding method can be selected according to the bonding method between the first substrate 120 and the second substrate 110 to avoid damage to the second surface of the second substrate 120 or to avoid damage to the structure formed on the first surface of the second substrate 120.

[0073] Step S90: Form a second metal layer on the second surface of the first substrate.

[0074] In this step, a second metal layer 137 is deposited on the second surface of the first substrate 120 using processes such as chemical vapor deposition, physical vapor deposition, and liquid phase deposition. Figure 2l As shown.

[0075] exist Figure 2l In the silicon capacitor structure shown, the polysilicon layer 132 serves as one electrode plate of the capacitor, and the first substrate 120 serves as the other electrode plate of the capacitor; the first metal layer 135 is electrically connected to the polysilicon layer 132 via a conductive channel 134, the second metal layer 137 is electrically connected to the second substrate, and the first insulating layer 131 separates the polysilicon layer 132 and the second substrate 120.

[0076] The silicon capacitor structure and manufacturing method provided by the present invention bond a first substrate to a second substrate, so that when a deep trench is etched in the first substrate, the second substrate can provide support for the first substrate, thereby reducing the probability of the first substrate warping.

[0077] Furthermore, since the second substrate provides support for the first substrate, the aspect ratio of the deep trenches can be further increased when etching deep trenches in the first substrate, thereby increasing the surface area of ​​the electrode and dielectric contact to improve the capacitance.

[0078] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a silicon capacitor structure, wherein, include: A first substrate is bonded to a second substrate, wherein the first substrate includes a first surface and a second surface facing each other, and the second surface faces the second substrate; Deep trenches are formed in the first substrate; A first insulating layer and a polysilicon layer are formed in the deep trench. The first insulating layer separates the polysilicon layer and the first substrate. The first substrate serves as one electrode plate of the silicon capacitor structure, and the polysilicon layer serves as the other electrode plate of the silicon capacitor structure. Debond the first substrate and the second substrate.

2. The manufacturing method according to claim 1, wherein, The step of forming a deep trench in the first substrate includes: A patterned mask layer is formed on the first surface of the first substrate; A deep trench is formed in the first substrate via the mask layer.

3. The manufacturing method according to claim 2, wherein, The deep trench extends from the first surface of the first substrate to the vicinity of the second surface.

4. The manufacturing method according to claim 2, wherein, On the first surface of the first substrate, the deep trenches extend in alternating bends.

5. The manufacturing method according to claim 2, wherein, The steps of forming the first insulating layer and the polysilicon layer in the deep trench include: An insulating material is deposited on the first surface of the first substrate and in the deep trench to form a first insulating layer, the first insulating layer covering the sidewalls and bottom of the deep trench and forming a trench along the deep trench; A polysilicon layer is deposited in the trench, and the polysilicon layer is etched back to make the upper surface of the polysilicon layer flush with the first surface of the first substrate.

6. The manufacturing method according to claim 5, wherein, Between the steps of forming the first insulating layer and the polysilicon layer in the deep trench and debonding the first substrate and the second substrate, the method further includes: A second insulating layer is formed on the first insulating layer and on the polysilicon layer; A conductive channel is formed that penetrates the second insulating layer and extends into the polycrystalline silicon layer; A first metal layer and a passivation layer are formed on the second insulating layer.

7. The manufacturing method according to claim 6, wherein, The passivation layer includes vias that penetrate the passivation layer and expose a portion of the upper surface of the first metal layer.

8. The manufacturing method according to claim 1, wherein, After the step of unbonding the first substrate and the second substrate, the method further includes: A second metal layer is formed on the second surface of the first substrate.

9. A silicon capacitor structure, formed using the manufacturing method described in any one of claims 1-8.

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