Mim capacitor and method of making the same

Abstract

The application provides a MIM capacitor and a manufacturing method thereof, and the method comprises the following steps: providing a substrate comprising a device area and a dummy area, forming a first shallow trench in the substrate, filling the first shallow trench with first polysilicon, etching the first polysilicon to form a second shallow trench in the first shallow trench, filling the second shallow trench with a dielectric layer, etching the dielectric layer to form a third shallow trench in the second shallow trench, filling the third shallow trench with second polysilicon, and performing ion implantation on the first polysilicon and the second polysilicon in the dummy area to form a lower plate and an upper plate. The MIM capacitor is manufactured in the previous process, and an additional mask plate is not needed, so that one mask plate is saved, and the production cost is reduced compared with the prior art. Meanwhile, the MIM capacitor does not occupy the area of the metal layer, the use area of the chip main body is increased, and the integration of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a MIM capacitor and its manufacturing method. Background Technology

[0002] Lateral double diffused metal oxide semiconductor (LDMOS) is a high-voltage, high-power semiconductor device widely used in information communication, computer, and automotive industries. Meanwhile, MIM capacitors, due to their high voltage tolerance and precision, are often used in integrated circuit chips for charge storage and voltage control.

[0003] Existing MIM capacitors are fabricated and integrated in the back-end metal interconnect process. They are usually composed of an Mn metal layer and an M(n-1) metal layer, with a conductive layer added between the upper and lower metal layers to utilize the capacitance between the upper and lower metal layers. Figure 1 Please refer to the structural diagram of an existing MIM capacitor. Figure 1 As shown, a conductive layer 3 is added between the M(n-1) metal layer 1 and the Mn metal layer 2 as the upper electrode (CTM), the M(n-1) metal layer 1 as the lower electrode, and the dielectric layer 4 between the two metal layers as the dielectric layer of the MIM capacitor. The M(n-1) metal layer 1, the dielectric layer 4 and the conductive layer 3 constitute the MIM capacitor. Figure 1 The plug 5 is used to connect the M(n-1) layer metal layer 1 or conductive layer 3 to the Mn layer metal layer 2.

[0004] However, the fabrication of the aforementioned MIM capacitors requires additional masks and manufacturing processes. Furthermore, capacitors typically occupy a considerable area, which hinders the improvement of semiconductor device integration density. Summary of the Invention

[0005] The purpose of this invention is to provide a MIM capacitor and its manufacturing method, which can save on photomasks, reduce production costs, and improve device integration without occupying metal layer area.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a MIM capacitor, comprising the following steps:

[0007] A substrate is provided, the substrate including a device region and a virtual region, and a first shallow trench is formed in the substrate within the device region and the virtual region;

[0008] The first shallow trench is filled with a first polysilicon, and the first polysilicon completely fills the first shallow trench.

[0009] The first polysilicon is etched to retain a portion of the thickness of the first polysilicon on the sidewall of the first shallow trench, and a second shallow trench is formed in the first shallow trench.

[0010] A dielectric layer is filled into the second shallow trench, and the dielectric layer completely fills the second shallow trench;

[0011] The dielectric layer is etched to retain a portion of the thickness of the dielectric layer on the sidewall of the second shallow trench, thereby forming a third shallow trench within the second shallow trench;

[0012] The third shallow trench is filled with a second polysilicon, which completely fills the third shallow trench; and

[0013] Ion implantation is performed on the first polysilicon and the second polysilicon in the virtual region to form the lower electrode plate and the upper electrode plate.

[0014] Optionally, within the device region, the first polysilicon, the dielectric layer, and the second polysilicon form a shallow trench isolation structure.

[0015] Optionally, the method for ion implantation of the first polysilicon and the second polysilicon within the virtual region includes:

[0016] A patterned mask layer is formed, which exposes the first polysilicon and the second polysilicon of the virtual region;

[0017] Ion implantation is performed using the patterned mask layer as a mask; and

[0018] Remove the patterned mask layer.

[0019] Optionally, a source / drain region is also formed within the device region. While ion implantation is performed to form the source / drain region within the device region, ion implantation is also performed on the first polysilicon and the second polysilicon within the virtual region.

[0020] Optionally, an anisotropic dry etching process can be used to etch the first polysilicon and the dielectric layer.

[0021] Optionally, the material of the dielectric layer includes silicon nitride.

[0022] Optionally, the longitudinal section of the first polysilicon is annular, surrounding the dielectric layer; the longitudinal section of the dielectric layer is also annular, surrounding the second polysilicon.

[0023] Optionally, after forming the first shallow trench and before filling the first polysilicon, the fabrication method further includes: forming an isolation layer that covers the sidewalls and bottom of the first shallow trench.

[0024] Accordingly, the present invention also provides a MIM capacitor, manufactured using the MIM capacitor manufacturing method described above, wherein the MIM capacitor comprises:

[0025] The substrate includes a device region and a virtual region;

[0026] A first shallow trench is located within the substrate of the virtual region;

[0027] The lower electrode plate is located on the sidewall of the first shallow trench, forming a second shallow trench within the first shallow trench;

[0028] A dielectric layer, located on the sidewall of the second shallow trench, forms a third shallow trench within the second shallow trench; and

[0029] The upper electrode plate is located within the third shallow trench.

[0030] Optionally, the lower electrode is a first polycrystalline silicon that has undergone ion implantation, and the upper electrode is a second polycrystalline silicon that has undergone ion implantation.

[0031] In summary, the MIM capacitor and its fabrication method provided by the present invention include a substrate comprising a device region and a virtual region. A first shallow trench is formed within the substrate in the device region and the virtual region. A first polysilicon layer is then filled into the first shallow trench, completely filling it. The first polysilicon layer is then etched to retain a portion of its thickness on the sidewalls of the first shallow trench, forming a second shallow trench. A dielectric layer is then filled into the second shallow trench, completely filling it. The dielectric layer is then etched to retain a portion of its thickness on the sidewalls of the second shallow trench, forming a third shallow trench. A second polysilicon layer is then filled into the third shallow trench, completely filling it. Finally, ion implantation is performed on the first and second polysilicon layers in the virtual region to form a lower electrode and an upper electrode. The unexpected effect of this invention is that it fabricates MIM capacitors in the front-end process without the need for an additional mask, saving the use of one mask and reducing production costs compared to existing technologies. At the same time, the MIM capacitors fabricated using the method described in this invention do not occupy the area of ​​the metal layer, increasing the usable area of ​​the chip body and improving the integration of the device.

[0032] Furthermore, an unexpected effect of this invention is that while fabricating a MIM capacitor in the first shallow trench of the virtual region (without ion implantation), a shallow trench isolation structure is fabricated in the first shallow trench of the device region. While performing ion implantation on the first and second polysilicon in the virtual region, ion implantation is also performed in the device region to form source and drain regions. That is, while fabricating the shallow trench isolation structure and source and drain regions in the device region, a MIM capacitor is formed in the virtual region. The fabrication of the MIM capacitor does not add any additional steps, thereby simplifying the process steps and saving manufacturing costs. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of an existing MIM capacitor.

[0034] Figure 2 This is a flowchart of a method for manufacturing a MIM capacitor according to an embodiment of the present invention.

[0035] Figure 3 This is a schematic diagram of the structure after the formation of the first shallow trench according to an embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram of the structure after the isolation layer is formed, according to an embodiment of the present invention.

[0037] Figure 5 This is a schematic diagram of the structure after filling the first shallow trench with first polysilicon, according to an embodiment of the present invention.

[0038] Figure 6 This is a schematic diagram of the structure after the formation of the second shallow trench according to an embodiment of the present invention.

[0039] Figure 7 This is a schematic diagram of the structure after the medium layer is filled in the second shallow trench, according to an embodiment of the present invention.

[0040] Figure 8 This is a schematic diagram of the structure after the formation of the third shallow trench according to an embodiment of the present invention.

[0041] Figure 9 This is a schematic diagram of the structure after filling the third shallow trench with second polysilicon, according to an embodiment of the present invention.

[0042] Figure 10 This is a schematic diagram of the structure during ion implantation provided in an embodiment of the present invention.

[0043] Figure 11 This is a schematic diagram of the structure of a MIM capacitor after it has been formed, according to an embodiment of the present invention.

[0044] Figure 12This is a top view of the first shallow trench after filling with second polysilicon, provided in an embodiment of the present invention.

[0045] Explanation of reference numerals in the attached figures:

[0046] Figure 1 In the diagram, 1- M(n-1) metal layer, 2- Mn metal layer, 3- conductive layer, 4- dielectric layer, and 5- plug.

[0047] Figures 3 to 12 In the diagram, 10-substrate; 11-P-type substrate; 12-P-type well region; 13-isolation layer; 21-first shallow trench; 22-second shallow trench; 23-third shallow trench; 30-first polysilicon; 31-lower electrode; 40-dielectric layer; 50-second polysilicon; 51-upper electrode; 60-patterned mask layer. Detailed Implementation

[0048] The core idea of ​​this invention is to fabricate MIM capacitors in the front-end process without the need for additional photomasks, thus saving photomasks and reducing production costs. At the same time, MIM capacitors do not occupy the area of ​​the metal layer, increasing the usable area of ​​the chip body and improving the integration of the device.

[0049] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0050] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0051] Figure 2This is a flowchart illustrating a method for manufacturing a MIM capacitor according to an embodiment of the present invention. Please refer to it. Figure 2 As shown, the method for manufacturing a MIM capacitor provided in this embodiment of the invention includes the following steps:

[0052] S1: Provide a substrate, the substrate including a device region and a virtual region, and form a first shallow trench in the substrate including the device region and the virtual region;

[0053] S2: Fill the first shallow trench with first polysilicon, and the first polysilicon fills the first shallow trench;

[0054] S3: Etch the first polysilicon to retain a portion of the thickness of the first polysilicon on the sidewall of the first shallow trench, and form a second shallow trench in the first shallow trench.

[0055] S4: Fill the second shallow trench with a dielectric layer, the dielectric layer filling the second shallow trench;

[0056] S5: Etch the dielectric layer to retain a portion of the thickness of the dielectric layer on the sidewall of the second shallow trench, and form a third shallow trench in the second shallow trench;

[0057] S6: Fill the third shallow trench with a second polysilicon, the second polysilicon completely filling the third shallow trench; and

[0058] S7: Ion implantation is performed on the first polysilicon and the second polysilicon in the virtual region to form the lower electrode plate and the upper electrode plate.

[0059] Figures 2 to 11 This is a schematic diagram illustrating the structural steps of a method for manufacturing a MIM capacitor according to an embodiment of the present invention. Next, we will combine... Figure 1 and Figures 2 to 11 The method for manufacturing the MIM capacitor provided in the embodiments of the present invention will be described in detail.

[0060] In step S1, please refer to Figure 3 As shown, a substrate 10 is provided, the substrate 10 including a device region I and a virtual region II, and a first shallow trench 21 is formed in the substrate 10 within the device region I and the virtual region II.

[0061] The substrate 10 can be made of silicon, germanium, germanium-silicon, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 10 is made of silicon.

[0062] In one embodiment of the present invention, the substrate 10 includes a P-type substrate 11 and a P-type well region 12 located on the P-type substrate 11. The P-type substrate 11 is a raw silicon wafer doped with P-type impurities (such as boron, indium, gallium, etc.), making the material exhibit P-type conductivity overall. The P-type well region 12 can be obtained by ion implantation into the P-type substrate 11, and the P-type well region 12 can have a higher doping concentration than the P-type substrate 11.

[0063] The substrate 10 includes a device region I and a virtual region II. The virtual region II is located at the edge of the device region I. The virtual region I can be located on both sides of the device region I or around the device region II, depending on the size of the device region I and actual needs.

[0064] A first shallow trench 21 is formed within the substrate 10 of the device region I and the virtual region II. Specifically, the first shallow trench 21 is formed within the P-type well region 12. Multiple first shallow trenches 21 can be formed in both the device region I and the virtual region II. The first shallow trenches 21 in the device region I are used to form shallow trench isolation structures, and the first shallow trenches 21 in the virtual region II are used to form MIM capacitors. The number of first shallow trenches 21 in both the device region I and the virtual region II can be determined according to actual requirements (the required number of shallow trench isolation structures and the required number of MIM capacitors).

[0065] For example, a photoresist layer is formed on the substrate 10 (specifically the P-type well region 12), the photoresist layer is exposed and developed to form a patterned photoresist layer, the substrate 10 is etched using the patterned photoresist layer as a mask to form a first shallow trench 21 in the substrate 10, and then the patterned photoresist layer is removed.

[0066] Please refer to Figure 4 As shown, after forming the first shallow trench 21, an isolation layer 13 is further formed, which covers the sidewalls and bottom of the first shallow trench 21. Exemplarily, the isolation layer 13 is made of silicon dioxide and can be formed using a thermal oxidation process, or by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or a combination thereof. The function of the isolation layer 13 is to isolate the subsequently formed MIM capacitor from the substrate 10.

[0067] In step S2, please refer to Figure 5 As shown, the first shallow trench 21 is filled with a first polysilicon 30, and the first polysilicon 30 completely fills the first shallow trench 21.

[0068] In this embodiment, the first polycrystalline silicon 30 can be formed using any suitable method known to those skilled in the art, such as pyrolysis, chemical vapor deposition, or silicon decomposition compound method. For example, the pyrolysis method utilizes the chemical reaction of silicon gas and hydrogen gas to generate polycrystalline silicon, offering advantages such as simple preparation process and low cost; the chemical vapor deposition method utilizes silicon source gas, dopant gas, and dilution gas to generate polycrystalline silicon through a chemical reaction, offering advantages such as high purity, good uniformity, and porous film; the silicon decomposition compound method generates polycrystalline silicon through a solid-phase reaction in the presence of easily decomposable silicon compounds (such as silicon trichloride, silane, etc.), offering advantages such as simple preparation process and high purity; the specific manufacturing method can be determined according to the specific requirements for the first polycrystalline silicon 30.

[0069] The first polysilicon 30 fills the first shallow trench 21 and covers the upper surface of the substrate 10. Then, the first polysilicon 30 is planarized (e.g., chemical mechanical polishing) until the upper surface of the substrate 10 is exposed. The first polysilicon 30 is formed in the first shallow trench 21, and the upper surface of the first polysilicon 30 is flush with the upper surface of the substrate 10.

[0070] In step S3, please refer to Figure 6 As shown, the first polysilicon 30 is etched to retain a portion of the thickness of the first polysilicon 30 on the sidewall of the first shallow trench 21, forming a second shallow trench 22 within the first shallow trench 21.

[0071] In one embodiment of the present invention, the first polysilicon 30 can be etched using the same etching process as the sidewall etching process, without the need for a mask. For example, an anisotropic dry etching process is used to etch back the first polysilicon 30 until a portion of the surface of the substrate 10 is exposed (specifically, a portion of the surface of the isolation layer 13 is exposed). A portion of the thickness of the first polysilicon 30 is retained on the sidewall of the first shallow trench 21, and a second shallow trench 22 is formed within the first shallow trench 21. The first polysilicon 30 has a certain thickness; therefore, the first polysilicon 30 actually covers not only the sidewall of the first shallow trench 21 but also the bottom portion of the first shallow trench 21 near the sidewall. The cross-sectional width of the second shallow trench 22 (… Figure 6 The width in the horizontal direction is less than the cross-sectional width of the first shallow trench 21.

[0072] Please refer to Figure 12 As shown, the first polysilicon 30 covers the sidewall of the first shallow trench 21, and its longitudinal section is annular (e.g., a rectangular annular shape). The outer surface of the first polysilicon 30 is in contact with the sidewall of the first shallow trench 21, and the inner surface of the first polysilicon 30 forms the sidewall of the second shallow trench 22. Please continue to refer to... Figure 6 As shown, the first polysilicon 30 in contact with the left sidewall of the first shallow trench 21 and the first polysilicon 30 in contact with the right sidewall of the first shallow trench 21 are actually connected, and their thickness ( Figure 6 The thickness in the horizontal direction is equal.

[0073] The cross-sectional width of the second shallow trench 22 ( Figure 6 The width in the horizontal direction is less than the cross-sectional width of the first shallow trench 21, and the cross-sectional width of the first shallow trench 21 is equal to the cross-sectional width of the second shallow trench 22 plus twice the thickness of the first polysilicon 30. Figure 6 The sum of the thicknesses in the horizontal direction. The cross-sectional length of the second shallow trench 22 ( Figure 6 The length in the vertical direction is equal to the cross-sectional length of the first shallow trench 21.

[0074] In step S4, please refer to Figure 7 As shown, a dielectric layer 40 is filled in the second shallow trench 22, and the dielectric layer 40 completely fills the second shallow trench 22.

[0075] In this embodiment, the dielectric layer 40 can be formed using any suitable process known to those skilled in the art, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. For example, the dielectric layer 40 is made of silicon nitride.

[0076] The dielectric layer 40 fills the second shallow trench 22 and covers the upper surface of the substrate 10. Then, the dielectric layer 40 is planarized (e.g., chemical mechanical polishing) until the upper surface of the substrate 10 is exposed. The dielectric layer 40 is formed in the second shallow trench 22, and the upper surface of the dielectric layer 40 is flush with the upper surface of the substrate 10.

[0077] The dielectric layer 40 fills the second shallow trench 22 and is in contact with the surrounding first polysilicon 30, which surrounds the dielectric layer 40 from its sidewalls.

[0078] In step S5, please refer to Figure 8 As shown, the dielectric layer 40 is etched to retain a portion of the thickness of the dielectric layer 40 on the sidewall of the second shallow trench 22, forming a third shallow trench 23 within the second shallow trench 22.

[0079] In one embodiment of the present invention, the dielectric layer 40 can be etched using the same etching process as the sidewall etching process, without the need for a mask. For example, an anisotropic dry etching process is used to etch back the dielectric layer 40 until a portion of the surface of the substrate 10 (specifically, a portion of the surface of the isolation layer 13) is exposed. A portion of the dielectric layer 40 is retained on the sidewall of the second shallow trench 22, and a third shallow trench 23 is formed within the second shallow trench 22. The dielectric layer 40 has a certain thickness; therefore, the dielectric layer 40 actually covers not only the sidewall of the second shallow trench 22 but also the bottom portion of the second shallow trench 22 near the sidewall. The cross-sectional width of the third shallow trench 23 (… Figure 8 The width in the horizontal direction is less than the cross-sectional width of the second shallow trench 22.

[0080] Please refer to Figure 12 As shown, the dielectric layer 40 covers the sidewalls of the second shallow trench 22, and its longitudinal section is annular (e.g., a rectangular annular shape). The outer surface of the dielectric layer 40 is in contact with the sidewalls of the second shallow trench 22, and the inner surface of the dielectric layer 40 forms the sidewalls of the third shallow trench 23. Please continue to refer to... Figure 8 As shown, the dielectric layer 40 in contact with the left sidewall of the second shallow trench 22 and the dielectric layer 40 in contact with the right sidewall of the second shallow trench 22 are actually connected, and their thickness ( Figure 8 The thickness in the horizontal direction is equal.

[0081] The cross-sectional width of the third shallow trench 23 ( Figure 8 The width in the horizontal direction is less than the cross-sectional width of the second shallow trench 22, and the cross-sectional width of the second shallow trench 22 is equal to the cross-sectional width of the third shallow trench 23 plus twice the thickness of the dielectric layer 40. Figure 8 The sum of the thicknesses in the horizontal direction. The cross-sectional length of the third shallow trench 23 ( Figure 8 The length in the vertical direction is equal to the cross-sectional length of the second shallow trench 22.

[0082] From the first shallow trench 21, the second shallow trench 22 to the third shallow trench 23, the cross-sectional width decreases sequentially, while the cross-sectional length remains unchanged.

[0083] In step S6, please refer to Figure 9 As shown, the third shallow trench 23 is filled with a second polysilicon 50, and the second polysilicon 50 completely fills the third shallow trench 23.

[0084] In this embodiment, the second polysilicon 50 can be formed using any suitable method known to those skilled in the art, such as pyrolysis, chemical vapor deposition, or silicon decomposition compounding. The second polysilicon 50 fills the third shallow trench 23 and covers the upper surface of the substrate 10. Then, the second polysilicon 50 is planarized (e.g., chemical mechanical polishing) until the upper surface of the substrate 10 is exposed. The second polysilicon 50 is formed within the third shallow trench 23, and the upper surface of the second polysilicon 50 is flush with the upper surface of the substrate 10.

[0085] Please refer to Figure 9 and Figure 12 As shown, a partial thickness of the first polysilicon 30 is formed on the sidewall of the first shallow trench 21. The first polysilicon 30 annularly covers the sidewall of the first shallow trench 21, thereby forming a second shallow trench 22 located within the first shallow trench 21. A partial thickness of the dielectric layer 40 is formed on the sidewall of the second shallow trench 22. The dielectric layer 40 annularly covers the sidewall of the second shallow trench 22, thereby forming a third shallow trench 23 located within the second shallow trench 22. The second polysilicon 50 fills the third shallow trench 23. That is, the first polysilicon 30, the dielectric layer 40, and the second polysilicon 50 fill the first shallow trench 21, and the first polysilicon 30, the dielectric layer 40, and the second polysilicon 50 sequentially fill the first shallow trench 21 in a direction perpendicular to the substrate 10. The longitudinal section of the first polysilicon 30 is annular, surrounding the dielectric layer 40, and the longitudinal section of the dielectric layer 40 is also annular, surrounding the second polysilicon 50.

[0086] In step S7, please refer to Figure 10 As shown, the first polysilicon 30 and the second polysilicon 50 in the virtual region II are ion implanted to form the lower electrode plate 31 and the upper electrode plate 51.

[0087] In one embodiment of the present invention, a patterned mask layer 60 is first formed, which covers the upper surface of the substrate 10, exposing the first polysilicon 30 and the second polysilicon 50 of the virtual region II. The material of the patterned mask layer 60 comprises silicon nitride. Exemplarily, firstly, a mask layer is formed on the substrate 10, covering the entire surface of the substrate 10, and then the mask layer is patterned to expose the first polysilicon 30 and the second polysilicon 50 of the virtual region II, forming the patterned mask layer 60. The patterning process, for example, involves forming photoresist on the mask layer, exposing and developing the photoresist using a mask to form a patterned photoresist layer, etching the mask layer using the patterned photoresist layer as a mask to form the patterned mask layer 60, and then removing the patterned photoresist layer. Next, ion implantation is performed using the patterned mask layer 60 as a mask, implanting ions into the first polysilicon 30 and the second polysilicon 50. Afterwards, the patterned mask layer 60 is removed, forming a structure as shown below. Figure 11 The structure shown is as follows. After ion implantation, the first polysilicon 30 serves as the lower electrode 31 of the MIM capacitor, and after ion implantation, the second polysilicon 50 serves as the upper electrode 51 of the MIM capacitor. The upper electrode 51, the dielectric layer 40, and the lower electrode 31 together constitute the MIM capacitor.

[0088] The first polysilicon 30 and the second polysilicon 50 in the virtual region II are ion-implanted to form the capacitor plates. Of course, heat treatment can be performed after ion implantation to activate the implanted ions. The first polysilicon 30 and the second polysilicon 50 in the device region I are not ion-implanted. The first polysilicon 30, the dielectric layer 40, and the second polysilicon 50 together form an isolation structure within the first shallow trench 21, i.e., a shallow trench isolation structure. In other words, during the formation of the un-ion-implanted MIM capacitor in the virtual region II, a shallow trench isolation structure is formed in the device region I.

[0089] The shallow trench isolation structure includes a first polysilicon 30, a dielectric layer 40, and a second polysilicon 50 arranged in a direction perpendicular to the substrate 10. The first polysilicon 30 has a ring-shaped longitudinal section surrounding the dielectric layer 40, and the dielectric layer 40 also has a ring-shaped longitudinal section surrounding the second polysilicon 50. The shallow trench isolation structure is similar to a field plate structure and can disperse the electric field.

[0090] This invention fabricates MIM capacitors in the front-end process, eliminating the need for additional photomasks (as in existing technologies, such as...). Figure 1As shown, an additional mask is required when forming conductive layer 3. Compared with the prior art, this saves the use of one mask and reduces production costs. At the same time, the MIM capacitor made by the method described in this invention does not occupy the area of ​​the metal layer (it is formed in the shallow trench), which increases the usable area of ​​the chip body and improves the integration of the device.

[0091] In one embodiment of the present invention, a source / drain region (not shown) is further formed within the device region I. When source / drain ion implantation is performed within the device region I to form the source / drain region, a patterned mask layer is formed on the substrate 10. The patterned mask layer exposes the area to be implanted by source / drain ion implantation, and source / drain ion implantation is performed using the patterned mask layer as a mask. The patterning process, for example, involves forming photoresist on the mask layer, exposing and developing the photoresist using a mask to form a patterned photoresist layer, etching the mask layer using the patterned photoresist layer as a mask to form a patterned mask layer, and then removing the patterned photoresist layer. In this embodiment, while fabricating the patterned mask layer and exposing the area to be implanted by source / drain ion implantation, the first polysilicon 30 and the second polysilicon 50 within the virtual region II can also be exposed simultaneously, meaning that only an improvement to the mask used in the prior art is required. Therefore, while ion implantation is performed in device region I to form the source / drain regions, ion implantation can also be performed on the first polysilicon 30 and the second polysilicon 50 in virtual region II. That is, the process of ion implantation of the first polysilicon 30 and the second polysilicon 50 in virtual region II to form the lower electrode 31 and the upper electrode 51 does not require an additional mask. The ions implanted during source / drain ion implantation in device region I are the same as the ions implanted into the polysilicon in virtual region II.

[0092] In another embodiment of the present invention, the ions implanted during source / drain ion implantation in device region I may be different from the ions implanted into the polysilicon in virtual region II. For example, after forming a patterned mask layer on the substrate 10 that exposes the region in device region I requiring source / drain ion implantation and the first polysilicon 30 and the second polysilicon 50 in virtual region II, source / drain ion implantation in device region I can be performed first, followed by ion implantation into the polysilicon in virtual region II.

[0093] In this invention, while fabricating a MIM capacitor in the first shallow trench 21 of virtual region II (without ion implantation), a shallow trench isolation structure is fabricated in the first shallow trench 21 of device region I. While performing ion implantation on the first polysilicon 30 and the second polysilicon 50 of virtual region II, ion implantation is also performed in device region I to form source and drain regions. That is, while fabricating the shallow trench isolation structure and source and drain regions in device region I, a MIM capacitor is formed in virtual region II. The fabrication of the MIM capacitor does not add any additional steps, thereby simplifying the process steps and saving manufacturing costs.

[0094] In the method for fabricating a MIM capacitor provided by the present invention, a substrate 10 is provided, the substrate 10 including a device region I and a virtual region II. A first shallow trench 21 is formed in the substrate 10 within the device region I and the virtual region II. Then, a first polysilicon 30 is filled into the first shallow trench 21, the first polysilicon 30 completely filling the first shallow trench 21. Subsequently, the first polysilicon 30 is etched, retaining a portion of the thickness of the first polysilicon 30 on the sidewalls of the first shallow trench 21. A second shallow trench 22 is formed within the first shallow trench 21. Then, the... A dielectric layer 40 is filled into the second shallow trench 22, completely filling the trench. Then, the dielectric layer 40 is etched, retaining a portion of its thickness on the sidewalls of the second shallow trench 22, forming a third shallow trench 23 within the trench. Next, a second polysilicon 50 is filled into the third shallow trench 23, completely filling it. Then, ion implantation is performed on the first polysilicon 30 and the second polysilicon 50 within the virtual region II to form a lower electrode 31 and an upper electrode 51. An unexpected effect of this invention is that it fabricates MIM capacitors in the front-end process without requiring an additional mask, saving the use of one mask and reducing production costs compared to existing technologies. Simultaneously, the MIM capacitors fabricated using the method described in this invention do not occupy the area of ​​the metal layer, increasing the usable area of ​​the chip body and improving device integration.

[0095] Accordingly, the present invention also provides a MIM capacitor, which is manufactured using the MIM capacitor manufacturing method described above.

[0096] Please refer to Figure 11 As shown, the MIM capacitor includes:

[0097] Substrate 10, the substrate 10 including device region I and virtual region II;

[0098] The first shallow trench 21 is located within the base 10 of the virtual region II;

[0099] The lower electrode plate 31 is located on the side wall of the first shallow trench 21, and forms a second shallow trench 22 in the first shallow trench 21;

[0100] A dielectric layer 40 is located on the sidewall of the second shallow trench 22, forming a third shallow trench 23 within the second shallow trench 22;

[0101] The upper electrode plate 51 is located within the third shallow trench 23.

[0102] Please refer to Figure 10 and Figure 11 As shown, the lower electrode 31 is a first polycrystalline silicon 30 that has undergone ion implantation, and the upper electrode 51 is a second polycrystalline silicon 50 that has undergone ion implantation.

[0103] A first shallow trench 21 is also formed within the substrate 10 of the device region I. A first polysilicon 30 is located on the sidewall of the first shallow trench 21, and a second shallow trench 22 is formed within the first shallow trench 21. A dielectric layer 40 is located on the sidewall of the second shallow trench 22, and a third shallow trench 23 is formed within the second shallow trench 22. A second polysilicon 50 is located within the third shallow trench 23. The first polysilicon 30, the dielectric layer 40, and the second polysilicon 50 constitute a shallow trench isolation structure within the device region I.

[0104] In one embodiment of the present invention, please refer to Figure 11 As shown, an isolation layer 13 is also formed on the sidewall and bottom of the first trench 21. The material of the isolation layer 13 includes silicon dioxide. The isolation layer 13 is used to isolate the substrate 10 from the MIM capacitor formed in the substrate 10.

[0105] In this invention, the MIM capacitor does not occupy the area of ​​the metal layer, thereby increasing the usable area of ​​the chip body and improving the integration of the device.

[0106] In summary, the MIM capacitor and its fabrication method provided by the present invention include a substrate comprising a device region and a virtual region. First shallow trenches are formed in the substrate within the device region and the virtual region, respectively. First polysilicon is then filled into the first shallow trenches, completely filling them. Next, the first polysilicon is etched to retain a portion of its thickness on the sidewalls of the first shallow trenches, forming a second shallow trench. A dielectric layer is then filled into the second shallow trench, completely filling it. Next, the dielectric layer is etched to retain a portion of its thickness on the sidewalls of the second shallow trench, forming a third shallow trench. A second polysilicon is then filled into the third shallow trench, completely filling it. Finally, ion implantation is performed on the first and second polysilicon in the virtual region to form a lower electrode and an upper electrode. The unexpected effect of this invention is that it fabricates MIM capacitors in the front-end process without the need for an additional mask, saving the use of one mask and reducing production costs compared to existing technologies. At the same time, the MIM capacitors fabricated using the method described in this invention do not occupy the area of ​​the metal layer, increasing the usable area of ​​the chip body and improving the integration of the device.

[0107] Furthermore, an unexpected effect of this invention is that while fabricating a MIM capacitor in the first shallow trench of the virtual region (without ion implantation), a shallow trench isolation structure is fabricated in the first shallow trench of the device region. While performing ion implantation on the first and second polysilicon in the virtual region, ion implantation is also performed in the device region to form source and drain regions. That is, while fabricating the shallow trench isolation structure and source and drain regions in the device region, a MIM capacitor is formed in the virtual region. The fabrication of the MIM capacitor does not add any additional steps, thereby simplifying the process steps and saving manufacturing costs.

[0108] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that, Includes the following steps: A substrate is provided, the substrate including a device region and a virtual region, and a first shallow trench is formed in the substrate within the device region and the virtual region; The first shallow trench is filled with a first polysilicon, and the first polysilicon completely fills the first shallow trench. The first polysilicon is etched to retain a portion of the thickness of the first polysilicon on the sidewall of the first shallow trench, and a second shallow trench is formed in the first shallow trench. A dielectric layer is filled into the second shallow trench, and the dielectric layer completely fills the second shallow trench; The dielectric layer is etched to retain a portion of the thickness of the dielectric layer on the sidewall of the second shallow trench, thereby forming a third shallow trench within the second shallow trench; The third shallow trench is filled with a second polysilicon, which completely fills the third shallow trench; and Ion implantation is performed on the first polysilicon and the second polysilicon in the virtual region to form the lower electrode plate and the upper electrode plate.

2. The method for manufacturing a MIM capacitor according to claim 1, characterized in that, Within the device region, the first polysilicon, the dielectric layer, and the second polysilicon form a shallow trench isolation structure.

3. The method for manufacturing a MIM capacitor according to claim 1, characterized in that, The method for ion implantation of the first polysilicon and the second polysilicon within the virtual region includes: A patterned mask layer is formed, which exposes the first polysilicon and the second polysilicon of the virtual region; Ion implantation is performed using the patterned mask layer as a mask; and Remove the patterned mask layer.

4. The method for manufacturing a MIM capacitor according to claim 1, characterized in that, A source / drain region is also formed within the device region. While ion implantation is performed to form the source / drain region within the device region, ion implantation is also performed on the first polysilicon and the second polysilicon within the virtual region.

5. The method for manufacturing a MIM capacitor according to claim 1, characterized in that, The first polysilicon and the dielectric layer are etched using an anisotropic dry etching process.

6. The method for manufacturing a MIM capacitor according to claim 1, characterized in that, The material of the dielectric layer includes silicon nitride.

7. The method for manufacturing a MIM capacitor according to claim 1, characterized in that, The first polysilicon has a ring-shaped longitudinal section that surrounds the dielectric layer; the dielectric layer also has a ring-shaped longitudinal section that surrounds the second polysilicon.

8. The method for manufacturing a MIM capacitor according to any one of claims 1 to 7, characterized in that, After forming the first shallow trench and before filling the first polysilicon, the fabrication method further includes: forming an isolation layer that covers the sidewalls and bottom of the first shallow trench.

9. A MIM capacitor, characterized in that, The MIM capacitor is manufactured using the manufacturing method of any one of claims 1 to 8, wherein the MIM capacitor comprises: The substrate includes a device region and a virtual region; A first shallow trench is located within the substrate of the virtual region; The lower electrode plate is located on the sidewall of the first shallow trench, forming a second shallow trench within the first shallow trench; A dielectric layer, located on the sidewall of the second shallow trench, forms a third shallow trench within the second shallow trench; and The upper electrode plate is located within the third shallow trench.

10. The MIM capacitor according to claim 9, characterized in that, The lower electrode plate is a first polycrystalline silicon that has undergone ion implantation, and the upper electrode plate is a second polycrystalline silicon that has undergone ion implantation.

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