Semiconductor device and electronic apparatus

Abstract

The present disclosure provides a semiconductor device and an electronic device, relates to the technical field of semiconductor, and is used for improving the conduction performance of the semiconductor device and reducing the specific on-resistance of the semiconductor device. The semiconductor device comprises a substrate, a drift layer located on one side of the substrate and provided with a P-type channel part; a first semiconductor structure comprising an N-type channel part extending along a first direction and a first P-type connecting part located on the side surface of the N-type channel part along a second direction; the first direction is the thickness direction of the substrate, and the second direction is perpendicular to the first direction; a second semiconductor structure and the P-type channel part overlap in the first direction and comprise a second P-type connecting part located on one side of the P-type channel part along the second direction; a first electrode is arranged on at least one side of the first semiconductor structure and the second semiconductor structure away from the substrate; a second electrode is arranged on the other side of the P-type channel part along the second direction; and a third electrode is arranged on the side of the substrate away from the drift layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor device and an electronic device. BACKGROUND

[0002] A junction field-effect transistor (JFET) has the advantages of simple structure and reliable performance, and is widely used as an electrically controlled switch structure in electronic devices of traditional silicon (Si) and wide-bandgap semiconductors (such as silicon carbide (SiC), gallium nitride (GaN), etc.).

[0003] A JFET is a semiconductor device that uses the electric field effect to control current. The JFET can control the width of the conduction channel through the depletion layer width generated by a reverse-biased PN junction, thereby achieving precise control of the current between the source and the drain. SUMMARY

[0004] Some embodiments of the present disclosure aim to provide a semiconductor device and an electronic device for improving the conduction performance of the semiconductor device and reducing the specific on-resistance of the semiconductor device.

[0005] In some embodiments, a semiconductor device is provided, including a substrate, a drift layer, a first semiconductor structure, a second semiconductor structure, a first electrode, a second electrode, and a third electrode; the drift layer is arranged on one side of the substrate along a first direction, and the drift layer is provided with a P-type channel portion; the first direction is the thickness direction of the substrate; the first semiconductor structure is arranged on the side of the drift layer away from the substrate; the first semiconductor structure includes an N-type channel portion and a first P-type connection portion extending along the first direction, and the first P-type connection portion is located on the side surface of the N-type channel portion along a second direction; the second direction is perpendicular to the first direction; the second semiconductor structure is arranged on the side of the drift layer away from the substrate, and the second semiconductor structure and the P-type channel portion overlap in the first direction; the second semiconductor structure includes a second P-type connection portion, and the second P-type connection portion is located on the side of the P-type channel portion along the second direction; the first electrode is arranged on at least the side of the first semiconductor structure and the second semiconductor structure away from the substrate; the second electrode is arranged on at least the other side of the P-type channel portion along the second direction; and the third electrode is arranged on the side of the substrate away from the drift layer.

[0006] The N-type channel portion of the semiconductor device is a vertical channel, which can greatly improve the electron mobility of the semiconductor device, improve the conduction capacity of the N-type channel portion of the first conduction region, optimize the conduction performance of the semiconductor device, and reduce the specific on-resistance of the semiconductor device. At the same time, the size of the N-type channel portion in the second direction (horizontal direction) can be reduced, the space ratio of the N-type channel portion can be compressed, the density of the N-type channel portion can be increased, and the specific on-resistance of the semiconductor device can be further reduced.

[0007] In some embodiments, the drift layer further comprises a first well region and a second well region located on two sides of the first semiconductor structure along the second direction respectively; one end of the N-type channel portion is connected to the first electrode, and the other end of the N-type channel portion is connected to the first well region; one end of the first P-type connection portion is connected to the first electrode, and the other end of the first P-type connection portion is connected to the second well region.

[0008] In some embodiments, the semiconductor device comprises a first device unit comprising two first semiconductor structures arranged adjacent along the second direction; in the two first semiconductor structures of the first device unit, the two first P-type connection portions are located between the two N-type channel portions, and the two first P-type connection portions are connected to the same second well region.

[0009] In some embodiments, the second semiconductor structure further comprises a support portion extending along the first direction, and the second P-type connection portion is located on a side surface of the support portion along the second direction; the drift layer further comprises a third well region and a fourth well region located on two sides of the second semiconductor structure along the second direction respectively; one end of the second P-type connection portion is connected to the first electrode, and the other end of the second P-type connection portion is connected to the third well region; one end of the support portion is connected to the first electrode, and the other end of the support portion is connected to the fourth well region; and the second electrode is arranged at least on a side of the fourth well region away from the substrate.

[0010] In some embodiments, the semiconductor device comprises a second device unit comprising two second semiconductor structures arranged adjacent along the second direction; in the two second semiconductor structures of the second device unit, the two support portions are located between the two second P-type connection portions, and the two support portions are connected to the same fourth well region.

[0011] In some embodiments, the first device unit and the second device unit are arranged alternately along a third direction, and the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0012] In some embodiments, in the first device unit and the second device unit arranged adjacent along the third direction, the N-type channel portion and the support portion are connected; the first well region and the third well region are connected; and the second well region and the fourth well region are connected.

[0013] In some embodiments, the second electrode extends along the third direction, and alternately passes through the second well region between the two first P-type connection portions in the first device unit, and the fourth well region between the two support portions in the second device unit.

[0014] In some embodiments, the first electrode comprises a first portion and a second portion, each of the first portion and the second portion extending along the third direction; the first portion is disposed on a side of the first semiconductor structure and the second semiconductor structure away from the substrate, and the first portion alternately passes through the first semiconductor structure and the second semiconductor structure adjacent along the third direction; the second portion is disposed on a side of the first well region and the third well region away from the substrate, and alternately passes through the first well region in the first device unit and the third well region in the second device unit.

[0015] In some embodiments, the plurality of first device units are arranged along a second direction, and the plurality of second device units are arranged along the second direction.

[0016] In some embodiments, among two first device units adjacent along the second direction, two N-type channel portions are connected to a same first well region; among two second device units adjacent along the second direction, two second P-type connection portions are connected to a same third well region.

[0017] In some embodiments, the semiconductor device comprises a second device unit, the second device unit comprising two second semiconductor structures arranged adjacent along a second direction; among the two second semiconductor structures of the second device unit, two second P-type connection portions are located between two support portions, and the two second P-type connection portions are connected to a same third well region.

[0018] In some embodiments, the first device unit and the second device unit are alternately arranged along the second direction.

[0019] In some embodiments, among the first device unit and the second device unit adjacent along the second direction, a first well region connected by the N-type channel portion and a fourth well region connected by the support portion are a same well region; at least a portion of the second electrode is located on the same well region.

[0020] In some embodiments, the first electrode comprises a third portion, a fourth portion, a fifth portion and a sixth portion; the third portion is disposed on a side of the first semiconductor structure away from the substrate, and the fourth portion is disposed on a side of the second semiconductor structure away from the substrate; the fifth portion is disposed on a side of the second well region corresponding to the first device unit away from the substrate, and the sixth portion is disposed on a side of the third well region corresponding to the second device unit away from the substrate.

[0021] In some embodiments, the semiconductor device further comprises a cathode pad disposed on a side of a region occupied by the first device unit and the second device unit along a third direction; the third direction is perpendicular to the first direction and perpendicular to the second direction; one end of the second electrode is connected to the cathode pad.

[0022] In some embodiments, the semiconductor device further comprises an N-type source contact portion and a P-type source contact portion; the N-type source contact portion is disposed between the first semiconductor structure and the first electrode; and the P-type source contact portion is disposed between the second semiconductor structure and the first electrode.

[0023] In some embodiments, an electronic device is provided, comprising a semiconductor device as described in some embodiments above. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0025] Figure 1 is a partial top view of a semiconductor device according to some embodiments;

[0026] Figure 2 is a partial top view of a semiconductor device according to some embodiments; Figure 1 is a cross-sectional view along the section line AA in

[0027] Figure 3 is a partial top view of a semiconductor device according to some embodiments; Figure 1 is a cross-sectional view along the section line BB in

[0028] Figure 4 is a partial top view of a semiconductor device according to some embodiments; Figure 1 is a cross-sectional view along the section line CC in

[0029] Figure 5 is a partial top view of a semiconductor device according to some embodiments;

[0030] Figure 6 is a partial top view of a semiconductor device according to some embodiments;

[0031] Figure 7 is a partial top view of a semiconductor device according to some embodiments; Figure 6 is a cross-sectional view along the section line DD in

[0032] Figure 8 is a flow chart of a manufacturing process of a semiconductor device according to some embodiments;

[0033] Figure 9 is a partial cross-sectional view of a semiconductor device according to some embodiments;

[0034] Figure 10 is a partial top view of a semiconductor device according to some embodiments;

[0035] Figure 11 is a partial cross-sectional view of a semiconductor device according to some embodiments;

[0036] Figure 12 partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0037] Figure 13 partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0038] Figure 14 partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0039] Figure 15 partial top view of yet another semiconductor device according to some embodiments;

[0040] Figure 16 partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0041] Figure 17 partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0042] Figure 18 partial top view of yet another semiconductor device according to some embodiments;

[0043] Figure 19 partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0044] Figure 20 partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0045] Figure 21 partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0046] Figure 22 partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0047] Figure 23 partial cross-sectional view of yet another semiconductor device according to some embodiments;

[0048] Figure 24 partial cross-sectional view of yet another semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art should fall within the scope of the present disclosure.

[0050] Unless the context clearly requires otherwise, throughout the description and the claims, the word "comprise," and variations such as "comprises" or "comprising," will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps. In describing some embodiments, the use of "connection" and / or "coupling" and / or variations thereof can be used. For example, the term "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited in terms of the terminology used.

[0051] The terms "first", "second", etc. are used herein only to describe different instances, and cannot be construed to refer to a relative importance or an implicit indication of the number of technical features indicated. Thus, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0052] In describing some embodiments, the use of "connected" and / or variations thereof can be used. For example, the term "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited in terms of the terminology used.

[0053] As used herein, "parallel", "perpendicular", "equal" include the stated condition and conditions similar to the stated condition within an acceptable deviation range, wherein the acceptable deviation range is determined by those of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, wherein the acceptable deviation range of approximately parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and approximately perpendicular, wherein the acceptable deviation range of approximately perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, a difference between the two of less than or equal to 5% of either.

[0054] It should be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0055] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0056] A semiconductor device refers to a component that utilizes the special electrical properties of a semiconductor material (mainly silicon, followed by germanium, gallium arsenide, etc.) to achieve a specific electronic function.

[0057] Semiconductor devices are diverse in types, and can include, for example, a solid-state circuit breaker. The solid-state circuit breaker can be applied to new energy vehicles, photovoltaic energy storage, etc., and can be applied to a direct current circuit breaker in a new energy vehicle direct current power distribution system, energy storage, medium voltage direct connection, flexible direct current transmission, etc. The solid-state circuit breaker can trigger self-turn-off of a device when the absolute value of current in a direct current bus is greater than a driving current, thereby playing a protective role for a direct current power grid.

[0058] For example, the solid-state circuit breaker can be normally open under normal working conditions, and current passes through the solid-state circuit breaker to reach a power switch and a power load. When a short circuit occurs in the power load, the solid-state circuit breaker can detect an excessively high current signal in the direct current bus and actively turn off the current in the direct current bus according to the excessively high current signal. Some embodiments of the present disclosure take the semiconductor device as an example for description of the solid-state circuit breaker.

[0059] In some embodiments, as shown in FIGS. 1A and 1B, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b. Figure 1 、 Figure 2 、 Figure 3 As shown in FIG. 1A, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b. Figure 2 As shown in FIG. 1B, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b. Figure 1 As shown in FIG. 1A, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b. Figure 3 As shown in FIG. 1B, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b. Figure 1 As shown in FIG. 1A, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b.

[0060] As shown in FIG. 1A, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b. Figure 1 As shown in FIG. 1A, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b. Figure 2 As shown in FIG. 1A, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b. Figure 3 As shown in FIG. 1A, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b.

[0061] As shown in FIG. 1A, the semiconductor device 1000 can include a substrate 10, a first conductive region a, and a second conductive region b.Figure 1 , Figure 2 , Figure 3 As shown, a drift layer 20 may be disposed on one side of the substrate 10 along the first direction Z, where the first direction Z is the thickness direction of the substrate 10. The drift layer 20 may be, for example, an n-type drift layer 20.

[0062] In some embodiments, such as Figure 1 , Figure 2 As shown, a first semiconductor structure 30 may be disposed on the side of the drift layer 20 away from the substrate 10. The first semiconductor structure 30 may be located, for example, in the first conductive region a. The drift layer 20 may contain a first well region 22 and a second well region 23, both of which may be P-wells. The first well region 22 and the second well region 23 are both located in the first conductive region a, and may be located on both sides of the first semiconductor structure 30 along the second direction X.

[0063] like Figure 1 , Figure 2 As shown, the drift layer 20 may also include a current diffusion layer 26, which is located in the first conductive region a and between the first well region 22 and the second well region 23; the orthogonal projection of the first semiconductor structure 30 on the substrate 10 may overlap with the orthogonal projection of the current diffusion layer 26 on the substrate 10.

[0064] like Figure 1 , Figure 2 As shown, the first semiconductor structure 30 may include an N-type channel portion 31 extending along a first direction Z and a first P-type connection portion 32, i.e., the N-type channel portion 31 is a vertical N-type channel portion 31; and the first P-type connection portion 32 may be located on the side of the N-type channel portion 31 along a second direction X; the second direction X is perpendicular to the first direction Z. A pn ​​junction may be formed between the N-type channel portion 31 and the first P-type connection portion 32, and the formed pn junction may be used to clamp the N-type channel portion 31.

[0065] The N-channel portion 31 can be, for example, a silicon carbide N-channel portion 31.

[0066] In some embodiments, such as Figure 1 , Figure 2 As shown, the first electrode 50 may be disposed on the side of the first semiconductor structure 30 away from the substrate 10. The semiconductor device 1000 may also include an N-type source contact 80, which is disposed between the first semiconductor structure 30 and the first electrode 50.

[0067] like Figure 1 , Figure 2As shown, one end of the N-type channel portion 31 can be connected with the first electrode 50 through the N-type source contact portion 80, and the other end of the N-type channel portion 31 can be connected with the first well region 22; one end of the first P-type connection portion 32 can be connected with the first electrode 50 through the N-type source contact portion 80, and the other end of the first P-type connection portion 32 can be connected with the second well region 23.

[0068] In some embodiments, as shown in Figure 1 , Figure 3 As shown, the drift layer 20 can further include a P-type channel portion 21, a third well region 24, and a fourth well region 25, the third well region 24 and the fourth well region 25 can both be P-wells, and the P-type channel portion 21 can be located between the third well region 24 and the fourth well region 25; for example, the P-type channel portion 21, the third well region 24, and the fourth well region 25 are all located in the second conductive region b.

[0069] As shown in Figure 1 , Figure 3 The drift layer 20 can further include a second semiconductor structure 40 located away from the substrate 10, for example, the second semiconductor structure 40 can be located in the second conductive region b. The second semiconductor structure 40 can overlap the P-type channel portion 21 in the first direction Z; that is, the orthographic projection of the second semiconductor structure 40 on the substrate 10 can overlap the orthographic projection of the P-type channel portion 21 on the substrate 10. The third well region 24 and the fourth well region 25 can be located on both sides of the second semiconductor structure 40 along the second direction X, respectively.

[0070] As shown in Figure 1 , Figure 3 Referring to Figure 2 , the second semiconductor structure 40 can include a support portion 42 and a second P-type connection portion 41, the support portion 42 can extend along the first direction Z, and the support portion 42 and the N-type channel portion 31 can be formed in the same step, for example. The second P-type connection portion 41 can be located on the side surface of the support portion 42 on one side along the second direction X, and the second P-type connection portion 41 is located on one side of the P-type channel portion 21 along the second direction X.

[0071] In some embodiments, as shown in Figure 1 , Figure 3 The first electrode 50 can be located on the side of the second semiconductor structure 40 away from the substrate 10. The semiconductor device 1000 can further include a P-type source contact portion 90 located between the second semiconductor structure 40 and the first electrode 50.

[0072] As shown in Figure 1 , Figure 3As shown, one end of the second P-type connection portion 41 can be connected to the first electrode 50 through the P-type source contact portion 90, and the other end of the second P-type connection portion 41 can be connected to the third well region 24, thereby realizing the connection between the third well region 24 and the first electrode 50; one end of the support portion 42 can be connected to the first electrode 50 through the P-type source contact portion 90, and the other end of the support portion 42 can be connected to the fourth well region 25.

[0073] like Figure 1 , Figure 2 , Figure 3 As shown, the first electrode 50 is at least disposed on the side of the first semiconductor structure 30 and the second semiconductor structure 40 away from the substrate 10. For example, the first electrode 50 may include a first portion 51 and a second portion 52. A portion of the first portion 51 may be located on the side of the first semiconductor structure 30 away from the substrate 10, and another portion of the first portion 51 may be located on the side of the second semiconductor structure 40 away from the substrate 10. The portion of the first portion 51 located on the first semiconductor structure 30 may be connected to the portion located on the second semiconductor structure 40. For example, the first portion 51 may be a single integral structure.

[0074] like Figure 1 , Figure 2 , Figure 3 As shown, a portion of the second part 52 may be located on the side where the N-type channel portion 31 of the first semiconductor structure 30 is located, that is, a portion of the second part 52 may be disposed on the side of the first well region 22 away from the substrate 10. Another portion of the second part 52 may be located on the side where the second P-type connection portion 41 of the second semiconductor structure 40 is located, that is, another portion of the second part 52 may be disposed on the side of the third well region 24 away from the substrate 10. The portion of the second part 52 disposed on the side of the first well region 22 away from the substrate 10 may be connected to the portion disposed on the side of the third well region 24 away from the substrate 10. For example, the second part 52 may be a single, integral structure.

[0075] The first electrode 50 can be, for example, a floating electrode of the semiconductor device 1000, that is, the first electrode 50 is an electrode connected to an electrical node in the circuit that does not form a stable, low-impedance DC path. The voltage of the first electrode 50 is not directly determined by the power supply or ground, but by complex parasitic effects and dynamic environment.

[0076] like Figure 1 , Figure 2 , Figure 3 As shown, the second electrode 60 is at least located on the other side of the P-type channel portion 21 along the second direction X; that is, a portion of the second electrode 60 and the second P-type connection portion 41 can be located on both sides of the P-type channel portion 21 in the drift layer 20 along the second direction X. A portion of the second electrode 60 can be located on the side of the fourth well region 25 away from the substrate 10.

[0077] As shown in Figure 1 , Figure 2 , Figure 3 , another part of the second electrode 60 can be located on the side where the first P-type connection part 32 of the first semiconductor structure 30 is located, i.e. the other part of the second electrode 60 can be arranged on the side of the second well region 23 away from the substrate 10.

[0078] In some embodiments, as shown in Figure 1 , Figure 4 , wherein, Figure 4 is Figure 1 , a cross-sectional view along the CC cross-sectional line. The semiconductor device 1000 can further comprise a cathode pad 100; the second electrode 60 can be, for example, a cathode electrode of the semiconductor device 1000, and one end of the second electrode 60 is connected to the cathode pad 100.

[0079] As shown in Figure 1 , Figure 4 , the cathode pad 100 can be arranged, for example, on the side of the drift layer 20 away from the substrate 10. The second electrode 60 can extend to the side of the cathode pad 100 close to the substrate 10 and be connected to the cathode pad 100.

[0080] As shown in Figure 1 , Figure 2 , Figure 3 , the third electrode 70 can be arranged on the side of the substrate 10 away from the drift layer 20. The third electrode 70 can be, for example, an anode electrode of the semiconductor device 1000.

[0081] The part of the semiconductor device 1000 located in the first conductive region a forms an N-type device. For example, the third electrode 70 (anode electrode) can serve as the drain of the N-type device, the first part 51 of the first electrode 50 can serve as the source of the N-type device, and the second electrode 60 (cathode electrode) arranged on the side of the second well region 23 away from the substrate 10 can serve as the gate of the N-type device.

[0082] The part of the semiconductor device 1000 located in the second conductive region b forms a P-type device. For example, the third electrode 70 (anode electrode) can serve as the gate of the P-type device, the first part 51 of the first electrode 50 can serve as the source of the P-type device, and the second electrode 60 (cathode electrode) arranged on the side of the fourth well region 25 away from the substrate 10 can serve as the drain of the P-type device.

[0083] Under normal working conditions, the semiconductor device 1000 is normally open, the voltage between the gate and the source of the N-type device is zero, the pn junction between the N-type channel part 31 and the first P-type connection part 32 is in a natural state, the depletion region is very thin, the N-type channel part 31 is the widest and has the smallest resistance, and the current can pass smoothly.

[0084] For example, the current inputted into the third electrode 70 (anode electrode) of the semiconductor device 1000 is transmitted through the substrate 10, the drift layer 20, the N-type channel portion 31, the first portion 51 of the first electrode 50 of the P-type device, the first portion 51 of the first electrode 50 of the N-type device, the second P-type connection portion 41, the third well region 24, the P-type channel portion 21, the second electrode 60 (cathode electrode) of the semiconductor device 1000, and thus flows out of the semiconductor device 1000.

[0085] When a short circuit occurs in the electric load, as the voltage of the third electrode 70 (anode electrode) increases, the pn junction between the N-type channel portion 31 and the first P-type connection portion 32 is in a reverse bias state, the depletion region gradually widens, and the N-type channel portion 31 gradually narrows. When the voltage between the gate and the source of the N-type device is the pinch-off voltage, the depletion region completely pinches off the N-type channel portion 31, and the current is blocked.

[0086] The N-type channel portion 31 of the semiconductor device 1000 is a vertical channel, which can greatly improve the electron mobility of the semiconductor device 1000, improve the conduction capability of the N-type channel portion 31 of the first conductive region a, optimize the conduction performance of the semiconductor device 1000, and reduce the specific on-resistance of the semiconductor device 1000. Meanwhile, the size of the N-type channel portion 31 in the second direction X (horizontal direction) can be reduced, the space proportion of the N-type channel portion 31 can be compressed, the density of the N-type channel portion 31 can be increased, and the specific on-resistance of the semiconductor device 1000 can be further reduced.

[0087] In some embodiments, as shown in Figure 1 , Figure 2 the semiconductor device 1000 can include a first device unit 1, and the first device unit 1 can include two first semiconductor structures 30 arranged adjacent to each other in the second direction X.

[0088] As shown in Figure 1 , Figure 2 of the two first semiconductor structures 30 of the first device unit 1, the two first P-type connection portions 32 are located between the two N-type channel portions 31, and the two first P-type connection portions 32 can be connected to the same second well region 23.

[0089] In some embodiments, as shown in Figure 1 , Figure 3 the semiconductor device 1000 can further include a second device unit 2, and the second device unit 2 can include two second semiconductor structures 40 arranged adjacent to each other in the second direction X.

[0090] As shown in Figure 1 , Figure 3As shown, in the two second semiconductor structures 40 of the second device unit 2, the two support portions 42 are located between the two second P-type connection portions 41, and the two support portions 42 can be connected to the same fourth well region 25.

[0091] In some embodiments, as shown in FIG. 1, and referring to FIG. 2, Figure 5 Figure 1 Figure 2 Figure 3 As shown, the first conductive regions a and the second conductive regions b can be arranged alternately along a third direction Y, the third direction Y being perpendicular to the first direction Z and perpendicular to the second direction X. That is, the first device units 1 in the first conductive regions a and the second device units 2 in the second conductive regions b can be arranged alternately along the third direction Y.

[0092] The present disclosure does not limit the number of the first conductive regions a and the second conductive regions b.

[0093] As shown, and referring to Figure 5 Figure 1 Figure 2 Figure 3 As shown, the cathode pad 100 can be arranged at one side of the region occupied by the first device units 1 and the second device units 2 along the third direction Y.

[0094] In the monolithic integrated semiconductor device 1000, the proportion of the parallel connection number of the cells of the first device units 1 and the second device units 2 can be freely allocated, so as to better reduce the specific on-resistance of the semiconductor device 1000.

[0095] In some embodiments, as shown in FIG. 1, and referring to FIG. 2, Figure 1 Figure 2 Figure 3 In the first device units 1 and the second device units 2 arranged along the third direction Y and adjacent to each other, the N-type channel portion 31 and the support portion 42 can be connected; the first well region 22 and the third well region 24 can be connected; and the second well region 23 and the fourth well region 25 can be connected.

[0096] In some embodiments, as shown in FIG. 1, and referring to FIG. 2, Figure 1 Figure 2 Figure 3 The second electrode 60 can extend along the third direction Y and alternately pass through the second well region 23 between the two first P-type connection portions 32 in the first device unit 1 and the fourth well region 25 between the two support portions 42 in the second device unit 2, and finally be connected to the cathode pad 100 arranged at one side of the region occupied by the first device units 1 and the second device units 2 along the third direction Y.

[0097] In some embodiments, as shown in FIG. 1, and referring to FIG. 2, Figure 1 Figure 2 Figure 3 ​​​​​​​​​​​​As shown, the first portion 51 and the second portion 52 of the first electrode 50 can each extend along the third direction Y; the first portion 51 can alternately pass through the first semiconductor structure 30 and the second semiconductor structure 40 adjacent along the third direction Y.

[0098] As shown, the second portion 52 can alternately pass through the first well region 22 in the first device unit 1 and the third well region 24 in the second device unit 2. Figure 1 、 Figure 2 、 Figure 3 As shown, the second portion 52 can alternately pass through the first well region 22 in the first device unit 1 and the third well region 24 in the second device unit 2.

[0099] In some embodiments, as shown in Figure 1 , the plurality of first device units 1 are arranged along the second direction X, and the plurality of second device units 2 are arranged along the second direction X. That is, the first conductive region a can include the plurality of first device units 1 arranged along the second direction X; the second conductive region b can include the plurality of second device units 2 arranged along the second direction X; and one first device unit 1 corresponds to one second device unit 2.

[0100] In some embodiments, as shown in Figure 1 、 Figure 2 、 Figure 3 As shown, in the two first device units 1 adjacent along the second direction X, the two N-type channel portions 31 can be connected to the same first well region 22; in the two second device units 2 adjacent along the second direction X, the two second P-type connection portions 41 can be connected to the same third well region 24.

[0101] In some embodiments, as shown in Figure 6 、 Figure 7 As shown, the first conductive region a and the second conductive region b can be alternately arranged along the second direction X, that is, the first device units 1 in the first conductive region a and the second device units 2 in the second conductive region b can be alternately arranged along the second direction X. Figure 7 , Figure 6 is a cross-sectional view along the DD section line in

[0102] In some embodiments, as shown in Figure 6 、 Figure 7 As shown, the first conductive region a and the second conductive region b can be alternately arranged along the second direction X, that is, the first device units 1 in the first conductive region a and the second device units 2 in the second conductive region b can be alternately arranged along the second direction X.

[0103] In some embodiments, as shown in Figure 6 、 Figure 7As shown, among the first device unit 1 and the second device unit 2 adjacent along the second direction X, the first well region 22 connected with the N-type channel portion 31 and the fourth well region 25 connected with the support portion 42 can be the same well region; at least a portion of the second electrode 60 is located on the same well region.

[0104] In some embodiments, as shown in Figure 6 、 Figure 7 The first electrode 50 can include a third portion 53, a fourth portion 54, a fifth portion 55 and a sixth portion 56; the third portion 53 can be arranged on the side of the first semiconductor structure 30 away from the substrate 10; the fourth portion 54 can be arranged on the side of the second semiconductor structure 40 away from the substrate 10; the fifth portion 55 can be arranged on the side of the second well region 23 corresponding to the first device unit 1 away from the substrate 10; and the sixth portion 56 can be arranged on the side of the third well region 24 corresponding to the second device unit 2 away from the substrate 10.

[0105] In some embodiments, as shown in Figure 6 、 Figure 7 The second electrode 60 can extend along the third direction Y and be connected with the cathode pad 100 arranged on the side of the region occupied by the first device unit 1 and the second device unit 2 along the third direction Y.

[0106] The first conductive region a and the second conductive region b of the semiconductor device 1000 are arranged alternately along the second direction X, which can simplify the design and save the cost.

[0107] In some embodiments, a preparation method of a semiconductor device is provided, as shown in Figure 8 The method comprises:

[0108] S1, forming a drift layer on the side of the substrate along a first direction; the P-type channel portion is arranged in the drift layer; the first direction is the thickness direction of the substrate.

[0109] Exemplarily, as shown in Figure 9 The carbonized silicon n+ substrate 10 is prepared, and the carbonized silicon n- first epitaxial layer 20' is epitaxially formed on the side of the substrate 10 along the first direction Z.

[0110] Exemplarily, as shown in Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 The hard mask can be deposited on the carbonized silicon n- first epitaxial layer 20', and the hard mask can be etched by the processes of spin-coating photoresist, exposure, curing, development, etc. to obtain an opening on the hard mask, and then the first epitaxial layer 20' is ion implanted to form the drift layer 20.

[0111] As shown in Figure 10 、 Figure 11As shown, for example, the above steps can be repeated in the first conductive region a to form a p-type moderately doped P-well region (P-well region), and the target doping concentration can be 2e18~5e18 / cm3; the P-well region of the first conductive region a can include a first well region 22 and a second well region 23.

[0112] As shown, for example, the above steps can be repeated in the first conductive region a to form a p-type moderately doped P-well region (P-well region), and the target doping concentration can be 2e18~5e18 / cm3; the P-well region of the first conductive region a can include a first well region 22 and a second well region 23.

[0113] As shown, for example, the above steps can be repeated in the first conductive region a to form a p-type moderately doped P-well region (P-well region), and the target doping concentration can be 2e18~5e18 / cm3; the P-well region of the first conductive region a can include a first well region 22 and a second well region 23. Figure 10 、 Figure 12 As shown, for example, the above steps can be repeated in the first conductive region a to form a p-type moderately doped P-well region (P-well region), and the target doping concentration can be 2e18~5e18 / cm3; the P-well region of the first conductive region a can include a first well region 22 and a second well region 23.

[0114] As shown, for example, the above steps can be repeated in the first conductive region a to form a p-type moderately doped P-well region (P-well region), and the target doping concentration can be 2e18~5e18 / cm3; the P-well region of the first conductive region a can include a first well region 22 and a second well region 23.

[0115] As shown, for example, the above steps can be repeated in the first conductive region a to form a p-type moderately doped P-well region (P-well region), and the target doping concentration can be 2e18~5e18 / cm3; the P-well region of the first conductive region a can include a first well region 22 and a second well region 23.

[0116] S2, forming a first semiconductor structure and a second semiconductor structure on the side of the drift layer away from the substrate; the first semiconductor structure includes an N-type channel portion extending along a first direction and a first P-type connection portion located on the side surface of the N-type channel portion along a second direction; the second direction is perpendicular to the first direction; the second semiconductor structure and the P-type channel portion overlap in the first direction; the second semiconductor structure includes a second P-type connection portion located on the side of the P-type channel portion along the second direction.

[0117] Exemplarily, S2.1, an N-type doped second epitaxial layer can be formed on the side of the drift layer away from the substrate; the second epitaxial layer includes first epitaxial portions and second epitaxial portions arranged alternately along a third direction, and the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0118] As shown, for example, the above steps can be repeated in the first conductive region a to form a p-type moderately doped P-well region (P-well region), and the target doping concentration can be 2e18~5e18 / cm3; the P-well region of the first conductive region a can include a first well region 22 and a second well region 23. Figure 13 、 Figure 14As shown, a layer of n-GaN, for example, can be grown again by an epitaxy process on the side of the drift layer 20 away from the substrate 10. The N-type doping of the second epitaxy layer 30', for example, can be formed by epitaxy, and the target doping concentration can be 5e16~2e17 / cm3. The second epitaxy layer 30' can include a first epitaxy portion 30-1' located at the first conductive region a and a second epitaxy portion 30-2' located at the second conductive region b.

[0119] As shown, a layer of n-GaN, for example, can be grown again by an epitaxy process on the side of the drift layer 20 away from the substrate 10. The N-type doping of the second epitaxy layer 30', for example, can be formed by epitaxy, and the target doping concentration can be 5e16~2e17 / cm3. The second epitaxy layer 30' can include a first epitaxy portion 30-1' located at the first conductive region a and a second epitaxy portion 30-2' located at the second conductive region b.

[0120] As shown, a layer of n-GaN, for example, can be grown again by an epitaxy process on the side of the drift layer 20 away from the substrate 10. The N-type doping of the second epitaxy layer 30', for example, can be formed by epitaxy, and the target doping concentration can be 5e16~2e17 / cm3. The second epitaxy layer 30' can include a first epitaxy portion 30-1' located at the first conductive region a and a second epitaxy portion 30-2' located at the second conductive region b. Figure 13 As shown, a layer of n-GaN, for example, can be grown again by an epitaxy process on the side of the drift layer 20 away from the substrate 10. The N-type doping of the second epitaxy layer 30', for example, can be formed by epitaxy, and the target doping concentration can be 5e16~2e17 / cm3. The second epitaxy layer 30' can include a first epitaxy portion 30-1' located at the first conductive region a and a second epitaxy portion 30-2' located at the second conductive region b.

[0121] Figure 14 As shown, a layer of n-GaN, for example, can be grown again by an epitaxy process on the side of the drift layer 20 away from the substrate 10. The N-type doping of the second epitaxy layer 30', for example, can be formed by epitaxy, and the target doping concentration can be 5e16~2e17 / cm3. The second epitaxy layer 30' can include a first epitaxy portion 30-1' located at the first conductive region a and a second epitaxy portion 30-2' located at the second conductive region b.

[0122] As shown, a layer of n-GaN, for example, can be grown again by an epitaxy process on the side of the drift layer 20 away from the substrate 10. The N-type doping of the second epitaxy layer 30', for example, can be formed by epitaxy, and the target doping concentration can be 5e16~2e17 / cm3. The second epitaxy layer 30' can include a first epitaxy portion 30-1' located at the first conductive region a and a second epitaxy portion 30-2' located at the second conductive region b.

[0123] As shown, a layer of n-GaN, for example, can be grown again by an epitaxy process on the side of the drift layer 20 away from the substrate 10. The N-type doping of the second epitaxy layer 30', for example, can be formed by epitaxy, and the target doping concentration can be 5e16~2e17 / cm3. The second epitaxy layer 30' can include a first epitaxy portion 30-1' located at the first conductive region a and a second epitaxy portion 30-2' located at the second conductive region b. Figure 15 Figure 16 As shown, a layer of n-GaN, for example, can be grown again by an epitaxy process on the side of the drift layer 20 away from the substrate 10. The N-type doping of the second epitaxy layer 30', for example, can be formed by epitaxy, and the target doping concentration can be 5e16~2e17 / cm3. The second epitaxy layer 30' can include a first epitaxy portion 30-1' located at the first conductive region a and a second epitaxy portion 30-2' located at the second conductive region b.

[0124] As shown, a layer of n-GaN, for example, can be grown again by an epitaxy process on the side of the drift layer 20 away from the substrate 10. The N-type doping of the second epitaxy layer 30', for example, can be formed by epitaxy, and the target doping concentration can be 5e16~2e17 / cm3. The second epitaxy layer 30' can include a first epitaxy portion 30-1' located at the first conductive region a and a second epitaxy portion 30-2' located at the second conductive region b. Figure 15 Figure 16 As shown, a layer of n-GaN, for example, can be grown again by an epitaxy process on the side of the drift layer 20 away from the substrate 10. The N-type doping of the second epitaxy layer 30', for example, can be formed by epitaxy, and the target doping concentration can be 5e16~2e17 / cm3. The second epitaxy layer 30' can include a first epitaxy portion 30-1' located at the first conductive region a and a second epitaxy portion 30-2' located at the second conductive region b.

[0125] ​​​In the first conductive region a, the overlap of the first doped portion 32' and the P-well region is staggered overlap, that is, along the second direction X, the first well region 22 and the second well region 23 are arranged alternately, the first doped portion 32' is located only on the second well region 23, and the first doped portion 32' is spaced apart from the adjacent first doped portion 32' by the first well region 22.

[0126] Exemplarily, S2.3, a P-type doped second doped portion can be formed in a target region of the second epitaxial portion, and a portion of the second epitaxial portion other than the second doped portion forms a second epitaxial portion; the second doped portion and the second epitaxial portion are arranged alternately along the second direction, and the first epitaxial portion and the second doped portion are arranged alternately along the third direction, and the first doped portion and the second epitaxial portion are arranged alternately along the third direction.

[0127] As shown in Figure 15 , Figure 17 , the above-mentioned deposition of the hard mask step can be performed to form a P-type doped second doped portion 41' in a target region of the second epitaxial portion 30-2' of the second conductive region b, and the second doped portion 41' is located on the side of the P-type source contact region 90' close to the substrate 10.

[0128] As shown in Figure 15 , Figure 17 , the second doped portion 41' can form an electrical contact with the p-well region (for example, the third well region 24) in the drift layer 20. The size of the second doped portion 41' along the second direction X can be close to the size of the P-well region (for example, the third well region 24) along the second direction X, and the difference in size can be maintained within, for example, ±0.5 μm.

[0129] In the second conductive region b, the overlap of the second doped portion 41' and the P-well region is staggered overlap, that is, along the second direction X, the third well region 24 and the fourth well region 25 are arranged alternately, the second doped portion 41' is located only on the third well region 24, and the second doped portion 41' is spaced apart from the adjacent second doped portion 41' by the fourth well region 25.

[0130] The first doped portion 32' in the first conductive region a and the second doped portion 41' in the second conductive region b can be prepared in the same step.

[0131] It should be noted that, as shown in Figure 15 , the first epitaxial portion and the second doped portion 41' are arranged alternately along the third direction Y, and the first doped portion 32' and the second epitaxial portion are arranged alternately along the third direction Y. Then, carbon film deposition and high-temperature activation annealing can be performed on the wafer, and then the carbon film is removed by ashing.

[0132] Exemplarily, S2.4, the first trench and the second trench can be formed in the second epitaxial layer; the first trench and the second trench both extend along the third direction, the first trench and the second trench are arranged alternately along the second direction, the first trench alternately penetrates the first epitaxial part and the first doped part, and the second trench alternately penetrates the second doped part and the second epitaxial part; the first epitaxial part and the first doped part located between the first trench and the second trench form the first semiconductor structure, and the second epitaxial part and the second doped part located between the first trench and the second trench form the second semiconductor structure.

[0133] The selective etching is performed in the first conductive region a and the second conductive region b, for example, a silicon carbide trench can be etched at a position corresponding to each p-well region, and the size of the silicon carbide trench in the second direction X is smaller than the size of the P-well region in the second direction X, and the silicon carbide trench exposes the surface of the P-well region. At the same time, it is necessary to ensure that the first conductive region a after etching has a residual first doped part 32' on the trench sidewall located at the first doped part 32', and the second conductive region b after etching has a residual second doped part 41' on the trench sidewall located at the second doped part 41'.

[0134] As shown in Figure 18 , Figure 19 , Figure 20 , the first conductive region a and the second conductive region b can share a silicon carbide trench. That is, a one-step trench etching process can be used.

[0135] As shown in Figure 18 , Figure 19 , Figure 20 , and with reference to Figure 16 , Figure 17 , the first trench D1 and the second trench D2 can both extend in the third direction Y and alternately penetrate the first conductive region a and the second conductive region b; the first trench D1 and the second trench D2 are arranged alternately along the second direction X, the first epitaxial part and the first doped part 32' located between the first trench D1 and the second trench D2 form the first semiconductor structure 30, and the N-type source contact region 80' located between the first trench D1 and the second trench D2 forms the N-type source contact part 80; the second epitaxial part and the second doped part 41' located between the first trench D1 and the second trench D2 form the second semiconductor structure 40, and the P-type source contact region 90' located between the first trench D1 and the second trench D2 forms the P-type source contact part 90.

[0136] S3, forming a first electrode; the first electrode is arranged at least on the side of the first semiconductor structure and the second semiconductor structure away from the substrate.

[0137] Exemplarily, as shown in Figure 21 , Figure 22As shown, the original silicon dioxide layer can be deposited on the surface of the device, and then dry anisotropic etching is performed to obtain the silicon dioxide layer 110'. The silicon dioxide layer 110' covers the sidewall of the first semiconductor structure 30 and the sidewall of the second semiconductor structure 40.

[0138] As shown, for example, Figure 23 , Figure 24 , nickel (Ni) deposition can be performed on the surface of the device, and then 1000 degrees Celsius annealing is performed for 25 seconds; the silicon carbide on the surface reacts with nickel (Ni) to form NiSix (nickel silicon compound), and then the remaining nickel (Ni) is removed using a wet process.

[0139] As shown, for example, referring to Figure 2 , Figure 3 , Figure 23 , Figure 24 , the silicon dioxide layer 110' can be removed using a wet etching process, and the passivation layer 120 is filled, which can be, for example, silicon dioxide or silicon nitride. The passivation layer 120 can be used to protect the semiconductor device 1000.

[0140] S4, forming a second electrode; the second electrode is arranged at least on the other side of the P-type channel portion along the second direction.

[0141] The second electrode 60 and the first electrode 50 can be formed in the same step.

[0142] S5, forming a third electrode, the third electrode is arranged on the side of the substrate away from the drift layer.

[0143] As shown, for example, referring to Figure 1 , Figure 4 , in the process of ion implantation of the first epitaxial layer to form the drift layer 20 in the cathode pad 100 region of the semiconductor device 1000, the cathode pad 100 region is not ion implanted. And in the process of forming the first trench and the second trench, the second epitaxial layer of the cathode pad 100 region needs to be etched completely. The formed silicon dioxide layer does not cover the cathode pad 100 region. While nickel (Ni) is deposited on the surface of the device, nickel (Ni) is also deposited on the surface of the drift layer 20 in the cathode pad 100 region, and the silicon carbide on the surface of the drift layer 20 in the cathode pad 100 region reacts with nickel (Ni) to form NiSix (nickel silicon compound). After filling the passivation layer 120, an opening is made on the surface of the passivation layer 120 in the cathode pad 100 region and metallization is performed to form the cathode pad 100.

[0144] Some embodiments of the present disclosure also provide an electronic device. The electronic device can include the semiconductor device 1000 and the circuit board described in some embodiments above, and the circuit board and the semiconductor device 1000 are electrically connected, and the circuit board can be used to provide the required electrical signal to the semiconductor device 1000.

[0145] Exemplarily, the electronic device can be a power electronic device, i.e., a device with power electronic devices (also referred to as semiconductor devices or power semiconductor devices) as main functional elements.

[0146] For example, the electronic device can be a converter, an electronic switch, an electronic AC power controller, a power factor correction (PFC) circuit, etc. The converter includes but is not limited to a DC / DC (direct current / direct current power supply), a rectifier (AC / DC, i.e., an alternating current-direct current converter), an inverter (DC / AC, i.e., a direct current-alternating current converter), etc. The electronic switch includes but is not limited to a power switch power supply circuit, etc. The embodiments of the present application do not specially limit the specific type of the electronic device.

[0147] It can be understood that the electronic device can further include other components, or combine certain components, or split certain components, or different component arrangements, and the structure of the electronic device illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device. The electronic device can be implemented in hardware, software or a combination of software / hardware.

[0148] It should be noted that in some embodiments, the semiconductor device provided by some embodiments of the present disclosure can be applied to the electronic device described above; of course, the specific application scenarios of the semiconductor device described above are not limited thereto, and any electronic device that needs to use a power semiconductor device belongs to the application scenarios of the embodiments of the present application. In other embodiments, the semiconductor device provided by some embodiments of the present disclosure can be used alone.

[0149] The above merely describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; a drift layer provided on one side of the substrate along a first direction, the drift layer being provided with a P-type channel portion; the first direction being a thickness direction of the substrate; a first semiconductor structure provided on a side of the drift layer away from the substrate; the first semiconductor structure comprising an N-type channel portion extending along the first direction and a first P-type connection portion, the first P-type connection portion being located on a side of the N-type channel portion along a second direction; the second direction being perpendicular to the first direction; a second semiconductor structure provided on a side of the drift layer away from the substrate, and the second semiconductor structure and the P-type channel portion overlapping in the first direction; the second semiconductor structure comprising a second P-type connection portion, a projection of the second P-type connection portion on the substrate being located on a side of a projection of the P-type channel portion on the substrate along the second direction; a first electrode provided at least on a side of the first semiconductor structure and the second semiconductor structure away from the substrate; a second electrode, a projection of the second electrode on the substrate being located at least on another side of the projection of the P-type channel portion on the substrate along the second direction; a third electrode provided on a side of the substrate away from the drift layer.

2. The semiconductor device according to claim 1, wherein The drift layer is further provided with a first well region and a second well region, the first well region and the second well region being respectively located on two sides of the first semiconductor structure along the second direction; one end of the N-type channel portion is connected with the first electrode, and the other end of the N-type channel portion is connected with the first well region; one end of the first P-type connection portion is connected with the first electrode, and the other end of the first P-type connection portion is connected with the second well region.

3. The semiconductor device of claim 2, wherein, The semiconductor device comprises a first device unit, the first device unit comprising two first semiconductor structures arranged adjacent along the second direction; of the two first semiconductor structures of the first device unit, the two first P-type connection portions are located between the two N-type channel portions, and the two first P-type connection portions are connected with the same second well region.

4. The semiconductor device according to claim 3, wherein The second semiconductor structure further comprises a support portion, the support portion extending along the first direction, and the second P-type connection portion being located on a side of the support portion along the second direction; The drift layer is further provided with a third well region and a fourth well region, a projection of a part of the third well region and a part of the fourth well region on the substrate being respectively located on two sides of a projection of the second semiconductor structure on the substrate along the second direction; one end of the second P-type connection portion is connected with the first electrode, and the other end of the second P-type connection portion is connected with the third well region; one end of the support portion is connected with the first electrode, and the other end of the support portion is connected with the fourth well region; The second electrode is provided at least on a side of the fourth well region away from the substrate.

5. The semiconductor device of claim 4, wherein, The semiconductor device comprises a second device unit, the second device unit comprising two second semiconductor structures arranged adjacent along the second direction; The two support portions are located between the two second P-type connecting portions in the two second semiconductor structures of the second device unit.

6. The semiconductor device of claim 5, wherein, The first device unit and the second device unit are arranged alternately along a third direction, the third direction being perpendicular to the first direction and perpendicular to the second direction.

7. The semiconductor device of claim 6, wherein, In the first device unit and the second device unit which are arranged along the third direction and adjacent to each other, The N-type channel portion is connected to the support portion. The first well region is connected to the third well region. The second well region is connected to the fourth well region.

8. The semiconductor device of claim 6, wherein, The second electrode extends along the third direction, and alternately passes through the second well region between the two first P-type connecting portions in the first device unit and the fourth well region between the two support portions in the second device unit.

9. The semiconductor device of claim 6, wherein, The first electrode comprises a first portion and a second portion, and the first portion and the second portion both extend along the third direction. The first portion is arranged on the side of the first semiconductor structure and the second semiconductor structure away from the substrate, and the first portion alternately passes through the first semiconductor structure and the second semiconductor structure which are adjacent along the third direction. The second portion is arranged on the side of the first well region and the third well region away from the substrate, and alternately passes through the first well region in the first device unit and the third well region in the second device unit.

10. The semiconductor device of claim 6, wherein A plurality of the first device units are arranged along the second direction, and a plurality of the second device units are arranged along the second direction.

11. The semiconductor device according to claim 10, wherein, In the two first device units which are adjacent along the second direction, the two N-type channel portions are connected to the same first well region. In the two second device units which are adjacent along the second direction, the two second P-type connecting portions are connected to the same third well region.

12. The semiconductor device of claim 4, wherein, The semiconductor device comprises a second device unit, and the second device unit comprises two second semiconductor structures which are arranged adjacent along the second direction. The two second P-type connecting portions are located between the two support portions in the two second semiconductor structures of the second device unit, and the two second P-type connecting portions are connected to the same third well region.

13. The semiconductor device of claim 12, wherein, The first device unit and the second device unit are arranged alternately along the second direction.

14. The semiconductor device of claim 13, wherein, In the first device unit and the second device unit which are adjacent along the second direction, the first well region connected by the N-type channel portion and the fourth well region connected by the support portion are the same well region, and at least part of the second electrode is located on the same well region.

15. The semiconductor device of claim 14, wherein, The first electrode comprises a third portion, a fourth portion, a fifth portion and a sixth portion. The third portion is arranged on the side of the first semiconductor structure away from the substrate, and the fourth portion is arranged on the side of the second semiconductor structure away from the substrate. The fifth portion is arranged on the side of the second well region corresponding to the first device unit away from the substrate, and the sixth portion is arranged on the side of the third well region corresponding to the second device unit away from the substrate.

16. The semiconductor device according to any one of claims 6 to 11 or 13 to 15, wherein The semiconductor device further includes a cathode pad disposed on one side of an area occupied by the first device unit and the second device unit in a third direction perpendicular to the first direction and perpendicular to the second direction. One end of the second electrode is connected to the cathode pad.

17. The semiconductor device according to any one of Claims 1 to 15, wherein The semiconductor device further includes: An N-type source contact portion disposed between the first semiconductor structure and the first electrode; A P-type source contact portion disposed between the second semiconductor structure and the first electrode.

18. An electronic device, comprising: A semiconductor device including any one of the semiconductor devices according to claims 1 to 17.

Images