Method and system for calculating total width of transistor channel in layout and computer readable storage medium
By screening ESD transistors in the original design layout, determining the drain region and forming a rectangular region, and calculating the sum of the areas, the problem of accuracy in calculating the channel width of ESD protection devices is solved, thereby improving the electrostatic protection capability and reliability of the chip.
Patent Information
- Application Number
- CN202511173764.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-20
- Publication Date
- 2025-11-28
AI Technical Summary
Existing technologies cannot accurately calculate the total channel width of ESD protection devices, resulting in insufficient protection capabilities of chips under electrostatic discharge conditions.
By screening the ESD transistors in the original design layout, the drain region is determined, the target boundary between the gate and drain regions is obtained, and a rectangular region is formed using this as the axis. The sum of the areas of the rectangular regions is calculated, and the total channel width of the ESD transistor is obtained based on the area and side length.
Accurately calculate the total channel width of ESD protection devices to ensure that the chip has electrostatic discharge protection capability and improve the reliability of chip performance.
Smart Images
Figure CN121038366A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method, system, and computer-readable storage medium for calculating the total width of transistor channels in a layout. Background Technology
[0002] Electrostatic discharge (ESD) is a natural phenomenon. ESD can occur at any stage of chip manufacturing, testing, and use, leading to chip failure. To avoid ESD damage, ESD protection modules are typically incorporated into circuit and layout designs to reduce the impact of ESD on chips. Common ESD protection devices include N-type metal-oxide-semiconductor transistors (GGNMOS) with their gate grounded and P-type metal-oxide-semiconductor transistors (GPPMOS) with their gate connected to the power supply. The protection capability of ESD protection devices is closely related to the total channel width of the transistor. The larger the total channel width, the stronger the protection capability of the ESD protection device. Therefore, the ESD protection device can only function effectively if the total channel width of the transistor meets the set requirements. However, the activation conditions and application scenarios of ESD protection devices lead to differences in the calculation method of their total channel width compared to that of conventional parallel transistors. Therefore, it is impossible to accurately calculate the total channel width of ESD protection devices.
[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide a method, system, and computer-readable storage medium for calculating the total width of transistor channels in a layout, so as to solve the problem of not being able to accurately calculate the total width of the channels of ESD protection devices.
[0005] To solve the above-mentioned technical problems, the present invention provides a method for calculating the total width of transistor channels in a layout, comprising:
[0006] Provide an original design layout, and select ESD transistors from the original design layout;
[0007] Determine the drain region of the ESD transistor;
[0008] Obtain the target boundary adjacent to the gate and the drain region;
[0009] A rectangular region is formed in the gate and drain regions with the target boundary as the axis;
[0010] Get the sum of the areas of all rectangular regions;
[0011] The total channel width of the ESD transistor is obtained by summing the areas of all rectangular regions and the side length of the rectangular regions.
[0012] Preferably, providing an original design layout and selecting ESD transistors from the original design layout includes:
[0013] The ESD transistor is provided with an identification layer;
[0014] The ESD transistors are selected based on the identification layer.
[0015] Preferably, determining the drain region of the ESD transistor includes:
[0016] Determine the source / drain diffusion regions in the ESD transistor;
[0017] The portion of the source / drain diffusion region connected to the bulk terminal is defined as the source region.
[0018] The source region in the source-drain diffusion region is ignored, and the region in the source-drain diffusion region with via connection is defined as the drain region.
[0019] Preferably, forming a rectangular region in the gate and drain regions with the target boundary as the axis includes:
[0020] Using the target boundary as the axis, a rectangular region is formed by extending a distance X to one side of the target boundary and a distance Y to the other side of the target boundary.
[0021] Preferably, forming a rectangular region in the gate and drain regions with the target boundary as the axis includes:
[0022] Using the target boundary as the central axis, extend a predetermined length X to both sides of the target boundary to form a rectangular region.
[0023] Preferably, obtaining the sum of the areas of all rectangular regions includes:
[0024] Establish the connection relationship between the rectangular region and the drain region;
[0025] Obtain all rectangular regions that have the same connection relationship as the drain region;
[0026] Calculate the sum of the areas of all rectangular regions.
[0027] Preferably, obtaining the total channel width of the ESD transistor based on the sum of the areas of all rectangular regions and the side length of the rectangular regions includes:
[0028] The total channel width of the ESD transistor Where S is the sum of the areas of all rectangular regions, and X+Y is the sum of the distances extended to both sides of the target boundary.
[0029] Preferably, a rectangular region is formed by extending a distance X to one side of the target boundary and a distance Y to the other side of the target boundary, with 1nm < X < 5nm and 1nm < Y < 5nm.
[0030] Based on the same inventive concept, the present invention also provides a system for calculating the total width of transistor channels in a layout, comprising:
[0031] A filtering module is used to provide an original design layout and filter out ESD transistors from the original design layout;
[0032] A logic operation module is used to determine the drain region of the ESD transistor; obtain the target boundary adjacent to the gate and the drain region; form a rectangular region between the gate and the drain region with the target boundary as the axis; obtain the sum of the areas of all rectangular regions; and obtain the total channel width of the ESD transistor based on the sum of the areas of all rectangular regions and the side length of the rectangular region.
[0033] Based on the same inventive concept, the present invention also provides a computer-readable storage medium that stores a set of instructions for an electronic device, characterized in that, when executed, the set of instructions is used to cause the electronic device to perform the method described above.
[0034] Compared with the prior art, the method for calculating the total width of transistor channels in the layout of the present invention has the following advantages:
[0035] This invention provides an original design layout, selects ESD transistors from the original design layout, determines the drain region of the ESD transistor, obtains the target boundary adjacent to the gate and the drain region, forms a rectangular region between the gate and the drain region with the target boundary as the axis, obtains the sum of the areas of all rectangular regions, and obtains the total channel width of the ESD transistor based on the sum of the areas of all rectangular regions and the side length of the rectangular region. This allows for accurate calculation of the total channel width of the transistor in the original design layout, ensuring the chip has electrostatic discharge protection capability and improving the reliability of chip performance.
[0036] The system and computer-readable storage medium for calculating the total transistor channel width in the layout provided by this invention belong to the same inventive concept as the method for calculating the total transistor channel width in the layout provided by this invention. Therefore, the system and computer-readable storage medium for calculating the total transistor channel width in the layout provided by this invention have at least all the advantages of the method for calculating the total transistor channel width in the layout provided by this invention. It can accurately calculate the total transistor channel width in the original design layout, ensure that the chip has electrostatic discharge protection capability, and improve the reliability of chip performance. Attached Figure Description
[0037] Figure 1 This is a flowchart of a method for calculating the total width of transistor channels in a layout according to an embodiment of the present invention;
[0038] Figure 2 This is a schematic diagram of the structure for determining the diffusion region of an ESD transistor in one embodiment of the present invention;
[0039] Figure 3 This is a schematic diagram of the structure for determining the diffusion region of an ESD transistor in another embodiment of the present invention;
[0040] Figure 4 This is a schematic diagram of the structure for determining the source region in one embodiment of the present invention;
[0041] Figure 5 This is a schematic diagram of the structure for determining the source region in another embodiment of the present invention;
[0042] Figure 6 This is a schematic diagram of the structure for determining the drain region in one embodiment of the present invention;
[0043] Figure 7 This is a schematic diagram of the structure for determining the drain region in another embodiment of the present invention;
[0044] Figure 8 This is a schematic diagram of the structure for obtaining the target boundary in one embodiment of the present invention;
[0045] Figure 9 This is a schematic diagram of the structure for obtaining the target boundary in another embodiment of the present invention;
[0046] Figure 10 This is a schematic diagram of the structure forming a rectangular region in one embodiment of the present invention;
[0047] Figure 11 This is a schematic diagram of the structure forming a rectangular region in another embodiment of the present invention;
[0048] Figure 12 This is a schematic diagram of the rectangular region in one embodiment of the present invention;
[0049] In the picture,
[0050] 100 - ESD transistor; 101 - Source / drain diffusion region;
[0051] 102 - Source region; 103 - Drain region;
[0052] 104 - Target boundary; 105 - Rectangular region;
[0053] 106 - Gate; 201 - Bulk terminal. Detailed Implementation
[0054] To make the objectives, advantages, and features of the present invention clearer, the method, system, and computer-readable storage medium for calculating the total width of transistor channels in a layout proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. It should be understood that the accompanying drawings do not necessarily show the specific structure of the present invention to scale, and the illustrative features used to illustrate certain principles of the present invention in the accompanying drawings are also drawn in a slightly simplified manner. Specific design features of the present invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and environment in which they are used. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0056] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0057] The core idea of this invention is to provide a method for calculating the total width of transistor channels in a layout, which can accurately calculate the total width of ESD protection devices, ensure the chip's electrostatic discharge protection capability, and improve the reliability of chip performance.
[0058] To achieve the above idea, this invention provides a method for calculating the total width of transistor channels in a layout, referring to... Figures 1 to 12 A specific implementation of a method for calculating the total width of transistor channels in a layout is disclosed. This method for calculating the total width of transistor channels in a layout includes steps S1 to S6.
[0059] Step S1: Provide an original design layout and select ESD transistors 100 from the original design layout.
[0060] Specifically, refer to Figures 1 to 3 The diagram shows an original design layout. The original design layout includes an ESD transistor 100 and several other transistors. Electrostatic discharge (ESD) can occur at various stages of chip manufacturing, testing, and use. ESD can cause chip failure. To reduce the damage caused by ESD, ESD protection devices, namely the ESD transistor 100, are typically incorporated into the circuit and layout design. Other transistors do not provide protection against ESD and will not be discussed further. Common ESD transistors include N-type metal-oxide-semiconductor transistors (GGNMOS) with their gate grounded and P-type metal-oxide-semiconductor transistors (GPPMOS) with their gate connected to the power supply. The ESD transistor 100 also includes single ESD transistors and transistors composed of multiple ESD transistors connected in series (i.e., cascade ESD transistors).
[0061] Selecting ESD transistors 100 from the original design layout includes:
[0062] The ESD transistor 100 has an identification layer. In the original design layout, an identification layer is provided for the ESD transistor 100. The ESD transistor 100 is identified by a dedicated identification layer. The identification layer can be any layout layer with identification markings.
[0063] ESD transistors 100 are selected based on the identification layer. Transistors with the identification layer in the original design layout are selected as target objects, while some other transistors are omitted.
[0064] It should be noted that, Figure 2 The transistor in it is a single ESD transistor. Figure 3 This is an ESD transistor with a Cascade structure.
[0065] Step S2: Determine the drain region 103 of the ESD transistor 100.
[0066] Specifically, refer to Figures 1 to 7 As shown, defining the drain region 103 of the ESD transistor 100 includes:
[0067] First, the source / drain diffusion region 101 in the ESD transistor 100 is identified. The source / drain diffusion region 101 in the transistor is located based on the identification layer. The source / drain diffusion region 101 retains the same electrical connection relationship as other transistors and can be connected through vias and metal.
[0068] Next, the portion of the source-drain diffusion region 101 connected to the bulk terminal 201 is identified as the source region 102. The portion connected to the bulk terminal 201 in the original design layout is located. This portion is the source region 102 of the ESD transistor 100. Due to the special nature of the ESD transistor, its source region 102 is short-circuited to the bulk terminal 201. The source region 102 can be determined based on this connection.
[0069] Then, the source region 102 in the source-drain diffusion region 101 is ignored, and the region in the source-drain diffusion region 101 with via connection is determined as the drain region 103. Ignoring the source region 102 in the source-drain diffusion region 101, the region in the remaining source-drain diffusion region 101 with via connection is the drain region 103.
[0070] Step S3: Obtain the target boundary 104 adjacent to the gate 106 and the drain region 103.
[0071] Specifically, refer to Figures 1 to 9 As shown, the source 106 and drain region 103 are located on both sides of the gate 106. The location adjacent to the gate 106 and drain region 103 can be obtained from the original design layout. This location is defined as the target boundary 104.
[0072] Step S4: Using the target boundary 104 as the axis, a rectangular region 105 is formed between the gate 106 and the drain region 103.
[0073] Specifically, refer to Figures 1 to 12 As shown, with the target boundary 104 as the axis, the rectangular region 105 formed between the gate 106 and the drain region 103 includes:
[0074] Using the target boundary 104 as an axis, a distance X is extended to one side of the target boundary 104, and a distance Y is extended to the other side of the target boundary 104, forming a rectangular region 105. Here, 1nm < X < 5nm, and 1nm < Y < 5nm. X and Y can be any values within the range of 1nm, 2nm, 3nm, 4nm, 5nm, or 1nm to 5nm. X and Y can be equal or unequal. For ease of subsequent calculations, in this embodiment, X and Y are equal.
[0075] When X and Y are equal, a rectangular region 105 is formed between the gate 106 and the drain region 103, with the target boundary 104 as the axis, including:
[0076] Using the target boundary 104 as the central axis, a rectangular region 105 is formed by extending a predetermined length X to both sides of the target boundary 104. The predetermined length X extending to both sides of the target boundary 104 is: 1 nm < X < 5 nm. That is, X can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, or any value within the range of 1 nm to 5 nm.
[0077] Step S5: Obtain the sum of the areas of all rectangular regions 105.
[0078] Specifically, refer to Figures 1 to 12 As shown, obtaining the sum of the areas of all rectangular regions 105 includes:
[0079] Establish a connection between the rectangular region 105 and the drain region 103. That is, connect the rectangular region 105 and the drain region 103.
[0080] Obtain all rectangular regions 105 that have the same connection relationship as the drain region 103. That is, obtain all rectangular regions 105 connected to the drain region 103 using layout editing software.
[0081] Calculate the sum of the areas S of all rectangular regions 105. Calculate the sum of the areas S of all rectangular regions 105 using a computer system.
[0082] Step S6: Based on the sum of the areas of all rectangular regions 105 and the side length of the rectangular regions 105, obtain the total channel width of the ESD transistor 100.
[0083] Specifically, refer to Figures 1 to 12 As shown. Based on the sum of the areas S of all rectangular regions 105 and the side length of each rectangular region 105, the total channel width of the ESD transistor 100 is obtained, including:
[0084] Total channel width of the ESD transistor 100: X+Y represents the sum of the distances extended to both sides of the target boundary 104.
[0085] When X and Y are equal, the total channel width of the ESD transistor 100 is: Where S is the sum of the areas of all rectangular regions 105, and 2X is the sum of the distances extended to both sides of the target boundary 104.
[0086] It should be noted that, regarding the ones mentioned above... Figure 2 , Figure 4 , Figure 6 , Figure 8 , Figure 10 It is a single ESD transistor. Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 This is an ESD transistor with a Cascade structure.
[0087] This embodiment provides an original design layout, selects ESD transistors from the original design layout, determines the drain region of the ESD transistor, obtains the target boundary adjacent to the gate and the drain region, forms a rectangular region with the target boundary as the axis between the gate and the drain region, obtains the sum of the areas of all rectangular regions, and obtains the total channel width of the ESD transistor based on the sum of the areas of all rectangular regions and the side length of the rectangular region. This allows for accurate calculation of the total channel width of the transistor in the original design layout, ensuring that the chip has electrostatic discharge protection capability and improving the reliability of chip performance.
[0088] To achieve the above-mentioned ideas, this embodiment also discloses a system for calculating the total width of transistor channels in a layout, including:
[0089] A filtering module is used to provide an original design layout and filter out ESD transistors 100 from the original design layout.
[0090] The logic operation module is used to determine the drain region 103 of the ESD transistor 100; obtain the target boundary 104 adjacent to the gate 106 and the drain region 103; form a rectangular region 105 between the gate 106 and the drain region 103 with the target boundary 104 as the axis; obtain the sum of the areas of all rectangular regions 105; and obtain the total channel width of the ESD transistor 100 based on the sum of the areas of all rectangular regions 105 and the side length of the rectangular region 105.
[0091] To achieve the above ideas, this embodiment also discloses a computer-readable storage medium that stores a set of instructions for an electronic device, which, when executed, causes the electronic device to perform the method described above.
[0092] The system and computer-readable storage medium for calculating the total transistor channel width in the layout provided in this embodiment belong to the same inventive concept as the method for calculating the total transistor channel width in the layout provided in this embodiment. Therefore, the system and computer-readable storage medium for calculating the total transistor channel width in the layout provided in this embodiment have at least all the advantages of the method for calculating the total transistor channel width in the layout provided in this embodiment. It can accurately calculate the total transistor channel width in the original design layout, ensure that the chip has electrostatic discharge protection capability, and improve the reliability of chip performance.
[0093] In summary, the above embodiments have provided a detailed description of the methods, systems, and different configurations of computer-readable storage media for calculating the total width of transistor channels in a layout. Of course, the above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure are within the scope of protection of the claims.
Claims
1. A method for calculating the total width of transistor channels in a layout, characterized in that, include: Provide an original design layout, and select ESD transistors from the original design layout; Determine the drain region of the ESD transistor; Obtain the target boundary adjacent to the gate and the drain region; A rectangular region is formed in the gate and drain regions with the target boundary as the axis; Get the sum of the areas of all rectangular regions; The total channel width of the ESD transistor is obtained by summing the areas of all rectangular regions and the side length of the rectangular regions.
2. The method for calculating the total width of transistor channels in a layout according to claim 1, characterized in that, The provision of an original design layout, and the selection of ESD transistors from the original design layout, includes: The ESD transistor is provided with an identification layer; The ESD transistors are selected based on the identification layer.
3. The method for calculating the total width of transistor channels in a layout according to claim 1, characterized in that, Determining the drain region of the ESD transistor includes: Determine the source / drain diffusion regions in the ESD transistor; The portion of the source / drain diffusion region connected to the bulk terminal is defined as the source region. The source region in the source-drain diffusion region is ignored, and the region in the source-drain diffusion region with via connection is defined as the drain region.
4. The method for calculating the total width of transistor channels in a layout according to claim 1, characterized in that, The step of forming a rectangular region in the gate and drain regions with the target boundary as the axis includes: Using the target boundary as the axis, a rectangular region is formed by extending a distance X to one side of the target boundary and a distance Y to the other side of the target boundary.
5. The method for calculating the total width of transistor channels in a layout according to claim 1, characterized in that, The step of forming a rectangular region in the gate and drain regions with the target boundary as the axis includes: Using the target boundary as the central axis, extend a predetermined length X to both sides of the target boundary to form a rectangular region.
6. The method for calculating the total width of transistor channels in a layout according to claim 4, characterized in that, The step of obtaining the sum of the areas of all rectangular regions includes: Establish the connection relationship between the rectangular region and the drain region; Obtain all rectangular regions that have the same connection relationship as the drain region; Calculate the sum of the areas of all rectangular regions.
7. The method for calculating the total width of transistor channels in a layout according to claim 4, characterized in that, The step of obtaining the total channel width of the ESD transistor based on the sum of the areas of all rectangular regions and the side length of the rectangular regions includes: The total channel width of the ESD transistor Where S is the sum of the areas of all rectangular regions, and X+Y is the sum of the distances extended to both sides of the target boundary.
8. The method for calculating the total width of transistor channels in a layout according to claim 4, characterized in that, Using the target boundary as the axis, a rectangular region is formed by extending X to one side of the target boundary and Y to the other side of the target boundary, where 1nm < X < 5nm and 1nm < Y < 5nm.
9. A system for calculating the total width of transistor channels in a layout, characterized in that, include: A filtering module is used to provide an original design layout and filter out ESD transistors from the original design layout; A logic operation module is used to determine the drain region of the ESD transistor; obtain the target boundary adjacent to the gate and the drain region; form a rectangular region between the gate and the drain region with the target boundary as the axis; obtain the sum of the areas of all rectangular regions; and obtain the total channel width of the ESD transistor based on the sum of the areas of all rectangular regions and the side length of the rectangular region.
10. A computer-readable storage medium storing a set of instructions for an electronic device, characterized in that, When executed, this set of instructions is used to cause the electronic device to perform the method as described in any one of claims 1-8.