Battery device, battery management system, and low power mode control method

Abstract

In this battery management system, when a communication failure occurs in a battery monitoring circuit that monitors a battery module, an interrupt is generated in a bridge circuit that transmits a signal between a processor and the battery monitoring circuit. The power supply circuit wakes up and generates a power supply voltage in response to an interrupt input to the enable pin. The processor operates based on the supply voltage and deactivates the enable pin when the error flag is set in the event of poor communication in the battery monitoring circuit.

Description

TECHNICAL FIELD

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0041794, filed on March 27, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

[0003] The disclosure relates to a battery apparatus, a battery management system, and a low power mode control method. BACKGROUND

[0004] An electric vehicle or a hybrid vehicle is a vehicle that obtains power by driving a motor mainly using a battery as a power source. Because the electric vehicle is an alternative solution that can solve pollution and energy problems of an internal combustion engine vehicle, the electric vehicle is being actively researched. In addition, the battery is used in various external apparatuses other than the electric vehicle.

[0005] When the external apparatus does not need power from the battery, for example, when the vehicle is parked, the battery can enter a low power mode. If the battery is in the low power mode, an unintended operation of the battery management system can cause the battery management system to fail to return to the low power mode after waking up from the low power mode. SUMMARY

[0006] TECHNICAL PROBLEM

[0007] Some embodiments can provide a battery apparatus, a battery management system, and a low power mode control method that can return to a low power mode after waking up due to an unintended operation.

[0008] TECHNICAL SOLUTION

[0009] According to some embodiments, a battery management system configured to manage a battery module can be provided. The battery management system can include a battery monitoring circuit configured to monitor the battery module, a power supply circuit configured to wake up in response to an interrupt input to a first enable pin and generate a power supply voltage, a processor configured to operate based on the power supply voltage and deactivate the first enable pin in response to an error flag being set when a communication failure occurs in the battery monitoring circuit, and a bridge circuit configured to transmit a signal between the processor and the battery monitoring circuit and generate the interrupt when the communication failure occurs in the battery monitoring circuit.

[0010] According to some embodiments, a battery apparatus can include a battery module and a battery management system. The battery management system can include a battery monitoring circuit configured to monitor the battery module, a power supply circuit including a first enable pin, a processor, and a bridge circuit configured to transmit signals between the processor and the battery monitoring circuit. The bridge circuit can be further configured to generate an interrupt when a communication failure occurs in the battery monitoring circuit in a low power mode. The power supply circuit can be further configured to wake up and generate a power supply voltage in response to the interrupt input to the first enable pin. The processor can be further configured to wake up based on the power supply voltage, identify the communication failure, set an error flag indicating the communication failure, and request the battery management system to enter the low power mode.

[0011] According to some embodiments, a low power mode control method of a battery management system configured to manage a battery module can be provided. The low power mode control method can include generating an interrupt in response to a communication failure occurring when the battery management system is in a low power mode, generating a power supply voltage in response to the interrupt, setting an error flag indicating the communication failure, and requesting the battery management system to enter the low power mode. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block diagram illustrating an example of a battery apparatus according to some embodiments.

[0013] Figure 2 is a flowchart illustrating an example of a low power mode control method of a battery management system according to some embodiments.

[0014] Figure 3 is a block diagram illustrating an example of a battery apparatus according to some embodiments.

[0015] Figure 4 is a block diagram illustrating an example of a battery apparatus according to some embodiments.

[0016] Figure 5 is a flowchart illustrating an example of a low power mode control method of a battery management system according to some embodiments.

[0017] Figure 6 is a block diagram illustrating an example of a battery apparatus according to some embodiments. DETAILED DESCRIPTION

[0018] In the following detailed description, only certain embodiments of the application are shown and described, by way of illustration. As those skilled in the art will understand, the described embodiments can be modified in various different ways without departing from the spirit or scope of the application. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals denote like elements throughout the specification.

[0019] When an element is described as "connected" or "coupled" to another element, it should be understood that the element can be directly connected or coupled to the other element or intervening elements can be present. On the other hand, when an element is described as being "directly connected" or "directly coupled" to another element, it should be understood that the element can be connected or coupled to the other element without intervening elements present.

[0020] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0021] In the flowcharts described in the detailed description, the order of the operations or steps can be changed, several operations or steps can be merged into one operation or step, one operation or step can be split into several operations or steps, and certain operations or steps can not be performed.

[0022] Figure 1 is a block diagram illustrating an example of a battery apparatus according to some embodiments.

[0023] Referring to Figure 1 The battery apparatus 100 can include a battery module 110 and a battery management system (BMS) 120. The battery apparatus 100 can be connected to an external apparatus. The external apparatus can be, for example, a mobile device, an electronic device, or an energy storage system (ESS). The mobile device can be, for example, a vehicle such as an electric vehicle, a hybrid vehicle, or a smart mobility device. Hereinafter, for convenience of description, the external apparatus will be described as a vehicle.

[0024] In some embodiments, the battery apparatus 100 can include a plurality of battery modules 110. The plurality of battery modules 110 can be connected in series or in parallel. The battery module 110 can include a plurality of battery cells. The plurality of battery cells can be connected, for example, in series.

[0025] The battery management system 120 can be connected to the battery module 110 to monitor and manage the battery module 110. The battery management system 120 can include a battery monitoring circuit 121, a bridge circuit 122, a processor 123, and a power supply circuit 124.

[0026] The battery monitoring circuit 121 can be connected to the battery module 110 to monitor the state (e.g., cell voltage) of the battery cells included in the battery module 110. In some embodiments, the battery monitoring circuit 121 can include a plurality of battery monitoring circuits 121 corresponding to a plurality of battery modules 110, respectively. In some embodiments, one battery monitoring circuit 121 can correspond to two or more battery modules 110, or two or more battery monitoring circuits 121 can correspond to one battery module 110. For convenience, three battery modules 110 and three battery monitoring circuits 121 are shown in FIG. 1. Figure 1 In some embodiments, the battery monitoring circuit 121 can be provided as an integrated circuit (IC), and the battery monitoring circuit 121 provided as an IC is referred to as a battery monitoring IC (BMIC).

[0027] In some embodiments, a plurality of battery monitoring circuits 121 can be connected in series to communicate with each other. In some embodiments, the plurality of battery monitoring circuits 121 can be connected through a serial peripheral interface (SPI) bus to provide bidirectional communication between two battery monitoring circuits 121. In some embodiments, the SPI bus can be an isolated SPI (ISO-SPI) bus.

[0028] The bridge circuit 122 can convert and deliver a signal from the processor 123 to the battery monitoring circuit 121, or can convert and deliver a signal from the battery monitoring circuit 121 to the processor 123. In some embodiments, the bridge circuit 122 can be connected to the battery monitoring circuit 121, for example, to a first battery monitoring circuit 121 of a plurality of battery monitoring circuits 121, via an SPI bus. In some embodiments, the SPI bus can be an isolated SPI (ISO-SPI) bus. In some embodiments, the bridge circuit 122 can be provided as an IC. The bridge circuit 122 provided as an IC is referred to as a bridge IC. When a loss of communication (LOC) occurs in the battery monitoring circuit 121 while the battery management system 120 is in a sleep mode, the bridge circuit 122 can identify the LOC and generate an interrupt INTR (e.g., an advanced interrupt (INTR)).

[0029] The processor 123 can control the overall operation of the battery management system 120. The processor 123 can be connected to the bridge circuit 122 and can transmit a signal to control the battery monitoring circuit 121 to the bridge circuit 122 or receive monitoring information provided by the battery monitoring circuit 121 through the bridge circuit 122 to manage the state of the battery module 110 or the state of the battery cells of the battery module 110. The processor 123 can be equipped with a non-volatile memory (NMV) 123a. In some embodiments, the non-volatile memory 123a can be embedded in the processor 123. In some embodiments, the non-volatile memory 123a can be installed outside the processor 123 and connected to the processor 123 via a bus. In some embodiments, the processor 123 and the bridge circuit 122 can be connected via an SPI bus. In some embodiments, the processor 123 can be a processing circuit such as a microcontroller unit (MCU).

[0030] The power supply circuit 124 can supply a power supply voltage (e.g., 5V) VDD to the processor 123. The power supply circuit 124 can convert a voltage supplied from the external battery 10 (e.g., an auxiliary battery 10 of an external device) into the power supply voltage VDD. When the battery management system 120 enters a sleep mode, the power supply circuit 124 can enter a low-power mode. When in the low-power mode, the power supply circuit 124 can wake up in response to an interrupt INTR from the bridge circuit 122. The power supply circuit 124 can also wake up in response to an activation signal (e.g., a start signal of a vehicle) IG of the external device. In some embodiments, the processor 123 and the power supply circuit 124 can be connected via an SPI bus.

[0031] In some embodiments, the power supply circuit 124 can include a power management IC (PMIC). The PMIC 124 can include a power supply pin VSUP that receives a power supply voltage from the auxiliary battery 10 and enable pins EN1 and EN2. In some embodiments, the voltage from the auxiliary battery 10 can be supplied to the power supply pin VSUP via a diode D1. The start signal IG can be input to the enable pin EN1, and the interrupt INTR can be input to the enable pin EN2. Accordingly, the PMIC 124 in the low-power mode can wake up in response to the start signal IG (e.g., the start signal IG having a high level) input to the enable pin EN1 or the interrupt INTR (e.g., the interrupt INTR having a high level) input to the enable pin EN2, and convert the voltage input to the power supply pin VSUP into the power supply voltage VDD of the processor 123. When the processor 123 operates using the power supply voltage VDD as a power source, the battery management system 120 can wake up from the sleep mode.

[0032] In some embodiments, the voltage supplied from the auxiliary battery 10 (e.g., the voltage supplied from the auxiliary battery 10 through the diode Dl) can be provided as a power supply voltage Vs for the bridge circuit 122.

[0033] In some embodiments, the unit 120a including the battery monitoring circuit 121 can be referred to as a cell monitoring unit (CMU) or a high voltage (HV) unit, and the unit 120b including the bridge circuit 122, the processor 123, and the power supply circuit 124 can be referred to as a battery monitoring unit (BMU) or a low voltage (LV) unit.

[0034] Figure 2 is a flowchart illustrating an example of a low-power mode control method of a battery management system according to some embodiments.

[0035] Reference Signs Figure 1 and Figure 2 If a communication failure occurs in the battery monitoring circuit 121 (S210), the bridge circuit 122 can recognize the communication failure (S215). The bridge circuit 122 can generate an interrupt INTR in response to the communication failure (S220). The power supply circuit 124 (e.g., the PMIC 124) can wake up in response to the interrupt INTR, and convert the voltage from the auxiliary battery 10 into a power supply voltage VDD (S225).

[0036] When the power supply voltage VDD is input from the PMIC 124, the processor 123 can wake up, and operate using the power supply voltage VDD as a power source (S230). Accordingly, the processor 123 can recognize the communication failure in the battery monitoring circuit 121, and refer to a non-volatile memory 123a equipped to the processor 123 (S235). If an error flag indicating the communication failure in the battery monitoring circuit 121 has not been set in the non-volatile memory 123a, the processor 123 can set (i.e., store) the error flag in the non-volatile memory 123a (S240). Since the battery management system 120 has woken up due to the communication failure, the processor 123 can request the battery management system 120 to enter a sleep mode (S245). Accordingly, the PMIC 124 can enter a low-power mode, and since the power supply voltage VDD is not supplied from the PMIC 124, the processor 123 can also enter a low-power mode (S250).

[0037] On the other hand, if communication failure persists in the battery monitoring circuit 121 after the battery management system 120 enters sleep mode (i.e., low power mode), the bridge circuit 122 can generate an interrupt INTR. Therefore, the PMIC 124, which has re-entered low power mode, can be woken up in response to the interrupt INTR (S255), and the processor 123 can also be woken up when the power supply voltage VDD is supplied from the PMIC 124 (S260).

[0038] Processor 123 can refer to non-volatile memory 123a after waking up, and if an error flag is set in non-volatile memory 123a, processor 123 can disable the enable pin EN2 of PMIC 124 (S265). That is, if an error flag is set, processor 123 can disable receiving interrupt INTR from PMIC 124 (S265). In some embodiments, processor 123 can use SPI communication to disable the enable pin EN2 of PMIC 124. Since battery management system 120 wakes up due to poor communication, processor 123 can request battery management system 120 to enter sleep mode (S270). Therefore, PMIC 124 can enter low-power mode, and since no power supply voltage VDD is supplied from PMIC 124, processor 123 can also enter low-power mode (S275). On the other hand, even if communication problems persist in the battery monitoring circuit 121 after the battery management system 120 enters sleep mode, the PMIC 124 can remain in low power mode without being woken up by the interrupt INTR because the enable pin EN2 of the PMIC 124 has been disabled (S275).

[0039] As described above, if an error flag is not set in the non-volatile memory 123a, unintentional faults such as poor communication may prevent the battery management system from maintaining a low-power mode. However, in some embodiments, if an error flag is set in the non-volatile memory 123a, the battery management system can remain in a low-power mode because interrupt INTRs are disabled from being received from the power supply circuit 124.

[0040] Figure 3 This is a block diagram illustrating examples of battery devices according to some implementation methods.

[0041] refer to Figure 3 , and reference Figure 1Compared to the described battery management system 120, the battery management system 320 of the battery device 300 may further include a transformer 125 connecting the HV unit (i.e., the first battery monitoring circuit 121) 320b and the LV unit (i.e., the bridging circuit 122) 320a. Therefore, the bridging circuit 122 can receive monitoring information from the battery monitoring circuit 121 via the transformer 125.

[0042] Figure 4 This is a block diagram illustrating examples of battery devices according to some implementation methods.

[0043] refer to Figure 4 The battery device 400 may include a battery module 410 and a battery management system 420. The battery device 400 may be connected to an external device. In some embodiments, the battery device 400 may include multiple battery modules 410.

[0044] The battery management system 420 can be connected to the battery module 410 to monitor and manage the battery module 410. The battery management system 420 may include battery monitoring circuitry 421, bridging circuitry 422, processor 423, and power supply circuitry 424.

[0045] Battery module 410, battery monitoring circuit 421, bridge circuit 422, and processor 423 execute and reference Figure 1 The battery module 110, battery monitoring circuit 121, bridging circuit 122 and processor 123 operate the same or similarly, so they will not be described in detail.

[0046] The power supply circuit 424 can supply the power supply voltage VDD to the processor 423. The power supply circuit 424 can convert the voltage supplied from the external battery 40 (e.g., the auxiliary battery 40 of an external device) into the power supply voltage VDD. When the battery management system 420 enters sleep mode, the power supply circuit 424 can enter a low-power mode.

[0047] In some implementations, the power supply circuit 424 may include a DC / DC converter 424a and a PMIC 424b. The DC / DC converter 424a may receive voltage from the auxiliary battery 40 and convert the voltage from the auxiliary battery 40 to a predetermined voltage, such as 12V. The DC / DC converter 424a may be, for example, a buck / boost converter. The PMIC 424b may receive the predetermined voltage from the DC / DC converter 424a and convert the predetermined voltage to a power supply voltage (e.g., 5V) VDD.

[0048] The power supply circuit 424, in low-power mode, can be woken up in response to an interrupt INTR from the bridge circuit 422. The power supply circuit 424 can also be woken up in response to a signal activating an external device IG (e.g., a vehicle start signal). In some embodiments, the processor 423 and the power supply circuit 424 (e.g., PMIC 424b) can be connected via an SPI bus.

[0049] In some embodiments, the DC / DC converter 424a may include a power supply pin VN for receiving voltage from the auxiliary battery 40 and an enable pin EN for enabling the DC / DC converter 424a. In some embodiments, the power supply circuit 424 may also include a transistor TR2 that turns on in response to a start signal IG, a transistor TR3 that turns on in response to an interrupt INTR, and a transistor TR1 that transfers voltage from the auxiliary battery 40 to the power supply pin VN and the enable pin EN of the DC / DC converter 424a in response to the conduction of transistors TR2 or TR3.

[0050] For example, transistors TR1, TR2, and TR3 can be n-channel field-effect transistors (FETs). In this case, the drains of transistors TR2 and TR3 can be connected to node N1, and the sources of transistors TR2 and TR3 can be connected to the ground terminal. Resistors R1 and R2 can be connected in series between the input terminal of the input start signal IG and the ground terminal, and the contacts of resistors R1 and R2 can be connected to the gate of transistor TR2. That is, the voltage of the start signal IG can be divided by resistors R1 and R2 and input to the gate of transistor TR2. The interrupt INTR can be input to the gate of transistor TR3. Resistors R3 and R4 can be connected in series between the drain of transistor TR1 and node N1, and the contacts of resistors R3 and R4 can be connected to the gate of transistor TR1. The drain of transistor TR1 can be supplied with the voltage of auxiliary battery 40, and the source of transistor TR1 can be connected to the power supply pin VN and the enable pin EN. The source of transistor TR1 can be connected to the enable pin EN via resistor R5. In addition, the voltage from the auxiliary battery 40 can be supplied to the drain of the transistor TR1 via diode D1.

[0051] Therefore, when the input start signal IG is received, transistor TR1 can be turned on. With transistor TR1 turned on, the voltage of the auxiliary battery 40, divided by resistors R3 and R4, can be applied to the gate of transistor TR3, causing transistor TR3 to turn on. Similarly, when the input interrupt INTR is received, transistor TR1 can be turned on. With transistor TR1 turned on, the voltage of the auxiliary battery 40, divided by resistors R3 and R4, can be applied to the gate of transistor TR3, causing transistor TR3 to turn on. By turning on transistor TR3, the voltage of the auxiliary battery 40 can be input to the enable pin EN, waking up the DC / DC converter 424a and converting the voltage of the auxiliary battery 40 supplied to the power supply pin VN to a predetermined voltage.

[0052] In some implementations, PMIC 424b may include a power supply pin VSUP that receives a predetermined voltage from DC / DC converter 424a, and enable pins EN1 and EN2. A startup signal IG may be input to enable pin EN1, and an interrupt INTR may be input to enable pin EN2. Therefore, PMIC 424b in low-power mode can be woken up in response to a startup signal IG input to enable pin EN1 or an interrupt INTR input to enable pin EN2, and converts the voltage input to power supply pin VSUP to the power supply voltage VDD of processor 423. When processor 423 operates using power supply voltage VDD as its power source, battery management system 420 can be woken up from sleep mode.

[0053] Figure 5 This is a flowchart illustrating an example of a low-power mode control method for a battery management system according to some implementations.

[0054] refer to Figure 4 and Figure 5 If a communication failure occurs in the battery monitoring circuit 421 (S510), the bridging circuit 422 can identify the communication failure (S515). The bridging circuit 422 can generate an interrupt INTR in response to the communication failure (S520). The DC / DC converter 424a of the power supply circuit 424 can be woken up in response to the interrupt INTR and convert the voltage of the auxiliary battery 40 to a predetermined voltage (S525). The PMIC 424b can be woken up in response to the interrupt INTR and convert the predetermined voltage supplied from the DC / DC converter 424a to the power supply voltage VDD (S530).

[0055] When the power supply voltage VDD is input from the PMIC 424b, the processor 423 can be woken up and operate using the power supply voltage VDD as its power source (S535). Therefore, the processor 423 can identify a communication failure in the battery monitoring circuit 421 and refer to the non-volatile memory 423a provided to the processor 423 (S540). If an error flag indicating a communication failure in the battery monitoring circuit 421 has not yet been set in the non-volatile memory 423a, the processor 423 can set (i.e., store) the error flag in the non-volatile memory 423a (S545). Since the battery management system 420 has been woken up due to the communication failure, the processor 423 can request the battery management system 420 to enter a sleep mode (S550). Therefore, the PMIC 424b can enter a low-power mode, and since no power supply voltage VDD is supplied from the PMIC 424b, the processor 423 can also enter a low-power mode (S555). In some embodiments, the DC / DC converter 424a can also enter a low-power mode (S555).

[0056] On the other hand, if communication problems persist in the battery monitoring circuit 421 after the battery management system 420 enters sleep mode (i.e., low power mode), the bridge circuit 422 can generate an interrupt INTR. Therefore, the PMIC 424b, which has re-entered low power mode, can be woken up in response to the interrupt INTR (S560), and the processor 423 can also be woken up when the power supply voltage VDD is supplied from the PMIC 424b (S565). In some embodiments, the DC / DC converter 424a, which has entered low power mode, can also be woken up in response to the interrupt INTR (S560).

[0057] Processor 423 can refer to non-volatile memory 423a after waking up, and if an error flag is set in non-volatile memory 423a, disable the enable pin EN2 of PMIC 424b (S570). That is, if an error flag is set, processor 423 can disable receiving interrupt INTR from PMIC 424b (S570). In some embodiments, processor 423 can use SPI communication to disable the enable pin EN2 of PMIC 424b. Since battery management system 420 has been woken up due to poor communication, processor 423 can request battery management system 420 to enter sleep mode (S575). Therefore, PMIC 424b can enter low-power mode, and since no power supply voltage VDD is supplied from PMIC 424b, processor 423 can also enter low-power mode (S580). On the other hand, even if communication problems persist in the battery monitoring circuit 421 after the battery management system 420 enters sleep mode, the PMIC 424b can remain in low-power mode without being woken up by the interrupt INTR because the enable pin EN2 of the PMIC 424b has been disabled (S580).

[0058] As described above, if an error flag is not set in the non-volatile memory 423a, unintentional faults such as poor communication may prevent the battery management system from maintaining a low-power mode. However, in some embodiments, if an error flag is set in the non-volatile memory 423a, the battery management system can remain in a low-power mode because interrupt INTRs are disabled from being received from the power supply circuit 424.

[0059] Figure 6 This is a block diagram illustrating examples of battery devices according to some implementation methods.

[0060] refer to Figure 6 , and reference Figure 4 Compared to the described battery management system 420, the battery management system 620 of the battery device 600 may further include a transformer 625 connecting the HV unit (i.e., the first battery monitoring circuit 621) and the LV unit (i.e., the bridging circuit 622). Therefore, the bridging circuit 622 can receive monitoring information from the battery monitoring circuit 121 via the transformer 425.

[0061] While the invention has been described in conjunction with embodiments now considered practical, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A battery management system configured to manage a battery module, the battery management system comprising: A battery monitoring circuit, configured to monitor the battery module; A power supply circuit configured to wake up in response to an interrupt input to a first enable pin and to generate a power supply voltage; A processor configured to operate based on the power supply voltage and to disable the first enable pin when an error flag is set in the event of a communication failure in the battery monitoring circuit. as well as A bridging circuit configured to transmit signals between the processor and the battery monitoring circuit, and to generate the interrupt in the event of a communication failure in the battery monitoring circuit.

2. The battery management system according to claim 1, wherein, The processor is also configured to set the error flag when the communication is faulty, even if the error flag is not set.

3. The battery management system according to claim 1, wherein, The processor includes non-volatile memory and is also configured to store the error flag in the non-volatile memory.

4. The battery management system according to claim 1, further comprising non-volatile memory. in, The processor is also configured to store the error flag in the non-volatile memory.

5. The battery management system according to claim 1, wherein, The processor is also configured to: Wake up in response to the power supply voltage and identify the communication failure; and If the error flag is not set, set the error flag, and then request the battery management system to enter low-power mode. The power supply circuit is also configured to enter the low-power mode upon a request to do so.

6. The battery management system according to claim 5, wherein, In the event that the power circuit is woken up again in response to the interrupt, the processor is further configured to: The device wakes up in response to the power supply voltage and identifies the communication failure. In response to the error flag, disable the first enable pin; and The request is made to the battery management system to enter the low-power mode, and The power supply circuit is also configured to enter the low-power mode upon a request to do so.

7. The battery management system according to claim 1, wherein, The power supply circuit includes a power management integrated circuit configured to generate the power supply voltage based on the voltage from an external battery. The power management integrated circuit includes: A power supply pin is provided, to which the voltage from the external battery is input. The first enable pin; and The second enable pin is input to the start signal of the external device.

8. The battery management system according to claim 1, wherein, The power supply circuit includes: A DC / DC converter configured to convert a first voltage from an external battery into a second voltage; and A power management integrated circuit, configured to generate the power supply voltage based on the second voltage, and The power management integrated circuit includes: The first power supply pin is used to input the second voltage to the first power supply pin. The first enable pin; and The second enable pin is input to the start signal of the external device.

9. The battery management system according to claim 8, wherein, The power supply circuit further includes a first transistor configured to turn on in response to the startup signal or the interruption to transfer the first voltage from the external battery. The DC / DC converter includes: A second power supply pin is provided, to which the first voltage is input; and Enable pin, to which the first voltage is input.

10. The battery management system according to claim 9, wherein, The power supply circuit also includes: A second transistor, configured to turn on in response to the activation signal; and A third transistor, configured to turn on in response to the interrupt, and The first transistor is further configured to turn on in response to the turning on of the second transistor or the turning on of the third transistor.

11. A battery device, the battery device comprising: Battery module; as well as Battery management system The battery management system includes: A battery monitoring circuit, configured to monitor the battery module; A power supply circuit, the power supply circuit including a first enable pin; Processor; and A bridging circuit configured to transmit signals between the processor and the battery monitoring circuit. The bridging circuit is further configured to generate an interrupt in the event of a communication failure in the battery monitoring circuit when the battery management system is in a low-power mode. The power supply circuit is further configured to wake up in response to an interrupt input to the first enable pin and to generate a power supply voltage. The processor is also configured to wake up based on the power supply voltage, identify the communication failure, set an error flag indicating the communication failure, and request the battery management system to enter a low-power mode.

12. The battery device according to claim 11, wherein, The bridging circuit is also configured to generate the interrupt in the event of persistent communication failure in the battery monitoring circuit after the battery management system enters the low-power mode. The power supply circuit is further configured to wake up in response to an interrupt input to the first enable pin and to generate the power supply voltage. The processor is also configured to wake up based on the power supply voltage, identify the communication failure, disable the first enable pin when the error flag is set, and request the battery management system to enter the low power mode.

13. The battery device according to claim 11, wherein, The processor includes non-volatile memory and is also configured to store the error flag in the non-volatile memory.

14. The battery device according to claim 11, wherein, The battery management system also includes non-volatile memory. The processor is further configured to store the error flag in the non-volatile memory.

15. The battery device according to claim 11, wherein, The power supply circuit includes a power management integrated circuit configured to generate the power supply voltage based on the voltage from an external battery. The power management integrated circuit includes: A power supply pin is provided, to which the voltage from the external battery is input. The first enable pin; and The second enable pin is input to the start signal of the external device.

16. The battery device according to claim 11, wherein, The power supply circuit includes: A DC / DC converter configured to convert a first voltage from an external battery into a second voltage; and A power management integrated circuit, configured to generate the power supply voltage based on the second voltage, and The power management integrated circuit includes: First power supply pin, the first voltage is input to the first power supply pin; The first enable pin; and The second enable pin is input to the start signal of the external device.

17. A low-power mode control method for a battery management system, the battery management system being configured to manage battery modules, the low-power mode control method comprising the following steps: An interrupt is generated in response to a communication failure that occurs when the battery management system is in low-power mode; A power supply voltage is generated in response to the interruption. Set an error flag to indicate poor communication; as well as The battery management system is requested to enter the low-power mode.

18. The low-power mode control method according to claim 17, further comprising the following steps: After the battery management system enters the low-power mode, the interrupt is generated if the communication failure persists in the battery monitoring circuit. The power supply voltage is generated in response to the interruption; When the error flag is set, the interrupt is disabled. as well as The battery management system is requested to enter the low-power mode.

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