Optical receiver device

Abstract

The optical receiver device has a photodiode or a link to an external photodiode, a TIA, and an analog-to-digital converter to provide a digital output. A constant delay filter (CDF) (3) receives a digital representation of the received optical signal and provides a digital output, whereby the apparatus is robust to electromagnetic interference. The CDF provides a finite delay time, receives a digital input signal and outputs a digital signal to the digital output delayed by the finite delay time, and filters out any pulses that are shorter than a duration of the finite delay time. The receiver device may also have an input emulation circuit for testing, and / or measures for adjusting the bandwidth of the TI.

Description

TECHNICAL FIELD

[0001] The present invention relates to an optical receiver circuit for optical to electronic digital communication, in particular for industrial applications. BACKGROUND

[0002] Optical receivers are typically designed for communication systems using fiber or waveguide media. Many industrial applications use plastic optical fiber (POF) as the medium. The receiving element is usually a photodiode. A transimpedance amplifier (TIA) converts the current generated by the photodiode into an analog voltage signal. A typical TIA consists of an amplifier with shunt feedback. The feedback network can consist of a resistor in parallel with a capacitor. A limiting amplifier or comparator usually follows the TIA to convert the signal to an analog representation of the digital signal. A decision threshold circuit is typically used to detect the signal level and adjust the limiting amplifier or comparator to give a digital output that transitions at 50% of the optical input threshold. The decision threshold circuit usually employs a peak detector or integrator. There is typically a driver circuit after the limiting amplifier or comparator to transmit the digital output to another circuit, usually using a standard protocol, such as transistor-transistor logic (TTL) levels for single-ended transmission, or one of several well-known differential signaling protocols (LVDS, LVECL, CML, etc.). The driver circuit is usually implicit in the optical receiver without elaboration.

[0003] Industrial optical receivers can operate over a wide dynamic range of input light, for example from -30 dBm to +2 dBm. An automatic gain control (AGC) circuit is typically used to adjust the transimpedance gain to prevent overload over the wide dynamic range. The AGC circuit typically influences control of the transimpedance gain by adjusting the TIA feedback network. The TIA feedback network can employ variable resistors and capacitors that can change the gain and frequency compensation according to a control signal from the AGC. A typical variable resistor circuit is a transistor whose gate or base voltage is adjusted by the AGC. It is common practice to limit the receiver bandwidth to be sufficient to apply to filter out frequencies of interest. This reduces the total integrated noise, but must be balanced to not introduce too much inter-symbol interference (ISI), as described in [1] page 65.

[0004] One advantage of fiber as a transmission medium is its inherent robustness to electromagnetic interference (EMI). However, the integrated circuit of the optical receiver can be exposed to EMI and can have erroneous output due to EMI. Industrial receivers should be robust to EMI.

[0005] Many electronic circuits that process digital signals subject to interference employ filters, such as the "glitch" filter in [2]. Glitch filters such as described in [2] use a technique that creates a voltage ramp that is input into a decision threshold circuit that has a trip dependency on the transistor threshold voltage (Vth). The Vth of a transistor is a well-known variable that is subject to significant intra-part mismatch and variation due to its dependency on temperature, doping concentration, operating conditions (back-gate effect), etc. The dependency on Vth will result in pulse width distortion (PWD), especially when such parameters vary significantly with temperature and suffer from significant process and mismatch effects. The invention described in [3] incorporates a comparator and a reference voltage. Mismatch in the components in [3] results in PWD.

[0006] Propagation delay is a fundamental property of optical communications. Optical receivers introduce a finite propagation delay. This propagation delay can vary and is subject to many variables, including process variations, device mismatch, optical power, power supply variations, and environmental conditions. The circuit of [4] addresses circuit delay compensation. An ideal optical receiver does not have any intra-part variation in propagation delay. Some modern industrial optical receivers, such as [5], include a maximum skew as a specification.

[0007] Testing the basic performance metrics of PWD or propagation delay of an optical receiver is typically a challenge. Providing an optical input to an optical receiver for testing can be expensive, or simply impractical for mass production. Standard measures of measuring propagation delay involve the use of a high-speed digital oscilloscope, an expensive piece of equipment, as described in [6]. The technique known as pulse-reflect-oscillation (PRO) and the technique known as time- transit-oscillation (TTO) are employed in laboratory conditions to measure propagation delay in optical fibers, as described in [7].

[0008] A standard practice is to probe an IC while it is still on a silicon wafer, and to record faulty ICs to avoid further processing of the IC. This is a standard cost-saving alternative to performing testing on an IC after it is packaged. Many fabless IC businesses outsource IC probing. Third-party probe facilities typically do not have the means to provide optical signal inputs to integrated circuits on wafers, and do not have any specialized test equipment for complex testing.

[0009] The circuit of [8] emulates a photodiode input to a TIA circuit. The method of [9] provides a photodiode emulator circuit to provide a current input to a device under test (DUT).

[0010] The present invention aims to achieve any one or more of the following objectives:

[0011] Industrial optical receivers require high EMI robustness,

[0012] Low propagation delay variation between parts, and

[0013] Low-cost measures for testing optical receivers, suitable for economical mass production, ideally requiring no specialized equipment, and ideally having measures for measuring key specifications such as propagation delay and pulse width distortion.

[0014] The primary technical challenge EMI poses a challenge to the design of industrial optical receivers. Many sources of EMI exist, but a common one is EMI generated by high-energy switching events. EMI generated by these events can interfere with the optical receiver, causing erroneous output. The erroneous output caused by high-frequency, short-burst EMI is characterized by… Figure 1 The image depicts a receiver where the photodiode is connected to a high-sensitivity input and is therefore susceptible to EMI. EMI at the optical receiver input appears to the receiver as a characteristic light pulse, which is difficult to distinguish from a real light pulse.

[0015] Industrial optical receivers must be robust to EMI. The adverse effects of EMI typically manifest as incorrect data output. Depending on the characteristics of the EMI and the receiver, typical EMI results can take the form of brief output glitches or short-duration oscillations. In less typical cases, prolonged erroneous output, or even receiver failure, may occur. In some applications, erroneous output can cause destructive circuit failure, for example, by causing a short circuit in switching elements.

[0016] Reducing the bandwidth in the front end (RC filter, active filter, bandwidth-limited TIA, etc.) is a typical strategy for reducing circuit noise. A known tradeoff in circuit design is that propagation delay increases as bandwidth decreases. This is illustrated by the well-known first-order system relationship between bandwidth and time constant:

[0017] f 3dB =1 / 2πf; f 3dB = Bandwidth, 𝜏 = Time constant

[0018] Increased propagation delay is typically undesirable for several possible reasons: the receiver IC may have applications that require specific maximum propagation delay specifications, limiting the maximum permissible propagation delay; some applications may require short propagation delays; increased propagation delay is undesirable because many applications require low skew, and increased propagation delay often leads to more skew.

[0019] This leads to a second technical problem, that of skew in the propagation delay. Skew does not have an industry standard definition. Generally, it is described as the maximum possible variation in the propagation delay in optical receivers operating under the same conditions. There is no standard that defines any allowable variation in conditions, but in practice such variation must occur. While two receivers are ostensibly operating at the same optical input power, in practice no two transmitters have the same optical power output, and due to misalignment of lenses or poorly polished POF or any number of other possible differences, the coupling efficiency can vary from part to part. The end result is that there can be large variations in the optical power received between two ICs. It would not be surprising to expect variations of greater than 3 dB in the same optical link.

[0020] Some optical receiver applications greatly benefit from tightly controlled variations in the propagation delay, i.e., low skew. Many industrial power conversion applications, such as wind turbines and power transmission, use optical fiber to provide electrical isolation between low voltage control circuitry and high voltage power conversion circuitry. These applications employ circuits that are very sensitive to variations in the propagation delay. For example, Figure 2 Shown in FIG. 1 is a simplified H-bridge circuit. In such circuits, the timing of the opening and closing of the switches is critical to both protecting the circuit and optimizing the power conversion efficiency. In these circuits, the switching speeds in the prior art are typically less than 100 kilobits per second (Kbps). While there is a trend in this technology to increase the switching speed, these speeds are relatively low in terms of the state of the art capability of optical receiver design. Variations in the propagation delay in the optical receivers in this application have a direct impact on performance, while the absolute propagation delay has little impact. For example, if four optical receivers are employed to control four switches as in Figure 2 FIG. 2, ideally they would all have the same propagation delay. The control of the break-before-make switching in this H-bridge is standard and necessary to avoid causing short circuit currents that can destroy the circuit. There is significant power dissipation (typically in the form of heat) during the off time, which in itself can limit the switching frequency and conversion efficiency, so the off time is important to the power conversion efficiency. Large skew between receivers would require long and inefficient off times to prevent any possibility of a short circuit. In this example, the absolute value of the propagation delay would not affect the power conversion efficiency. Only the propagation delay skew would affect the power conversion efficiency.

[0021] As power conversion technology improves, there is a trend toward faster switching speeds, but this can be limited by the propagation delay skew. This refers both to the on and off times of the switches and to the absolute data rate. Technologies such as high voltage insulated gate bipolar transistors (IGBTs) allow very short on times. The effect of faster switching is to increase the EMI generated by the switching action. This increases the requirement of these technologies for EMI robustness of the optical receiver.

[0022] Propagation delay is affected by many parameters that can cause variations in the propagation delay. These include process variations, device mismatches, optical power, etc. A common approach for IC design is to ensure that worst case variations of these parameters still result in a maximum propagation delay that meets the requirements.

[0023] A third technical problem of electrical testing and measurement of propagation delay for large scale production presents significant challenges. There is currently no industry standard defining the conditions that will be used to measure the propagation skew. One approach is to define the skew in the optical receiver as a fractional variation between parts in a finite set of conditions, for example, limiting environmental variations such as ambient temperature and humidity, and limiting the finite variation of the optical receiver supply voltage and received optical power.

[0024] In the IC industry, physical testing of performance specifications is not typically performed on every IC, but rather a representative subset of ICs selected from a series of wafers are characterized. This is typically because the specific testing required is not possible or practical to perform on every IC, but if possible, would typically be the preferred test of the performance specification. This type of specification is typically considered to be guaranteed by design, and is thoroughly characterized to guarantee compliance with the specification. However, the variation limits of this type of performance specification must be wide enough to guarantee that all parts meet the specification. Because the exceptional parts cannot be identified individually, the data sheet limits must be chosen conservatively to guarantee that even the exceptional parts fall within the specification limits. This results in wider specification limits compared to all parts can be tested and the exceptional values removed. A strategy to allow for tighter specification limits is to ensure that all parts are subjected to testing for the specification. A tight specification can be defined, and parts that fail to perform within these limits can be culled. This allows for tighter performance specifications of the product. Due to the lack of shown large scale testing of the propagation delay in every IC, the data sheet limits must be chosen more conservatively (wider), increasing the skew.

[0025] Measuring the propagation delay in a receiver can be difficult and expensive, and performing such a measurement as part of a standard test for all optical receiver ICs is particularly burdensome. The propagation delay in a receiver can be defined as the time between the optical signal reaching 50% of its output high value and the electrical measurement of the digital output of the receiver reaching 50% of its supply voltage. Measuring this is most typically done with a high performance oscilloscope, and requires an optical test input signal. Doing this with high accuracy in a high speed receiver typically requires expensive test equipment, which can include a high performance oscilloscope to perform automatic measurements of the propagation delay, and provisions to input the optical signal in a wafer probe or test environment. Testing the propagation delay in high volume production is very challenging. In the increasingly common waferless IC industry, the probe testing of IC wafers is typically performed by a dedicated third party company that does not provide the option of optical testing. This is problematic for optical receiver ICs.

[0026] REFERENCES

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[0051] Published in: Optics & Laser Technology 36 (2004) 81-84

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[0058] [9] Title: Electrically Testing an Optical Receiver

[0059] Patent: US9960844B1

[0060] Inventors: Raj et al SUMMARY

[0061] In various embodiments, we describe an optical receiver apparatus comprising: an optical receiver comprising a TIA, and an analog-to-digital converter for providing a digital output.

[0062] In some embodiments, the apparatus further comprises: a constant delay filter CDF for receiving a digital representation of a received optical signal and providing a digital output, wherein the constant delay filter receives a digital input signal and outputs a digital signal to the digital output delayed by a delay time, and prevents any pulse of a duration shorter than the delay time from being sent to the output.

[0063] In some embodiments, the CDF comprises a differential voltage ramp generator having a differential voltage output connected to at least one comparator.

[0064] In some embodiments, the differential voltage ramp generator further comprises a first charging element to a positive power supply, a second charging element to a negative power supply, and wherein a first output is connected to the first charging element through a first switch and to the second charging element through a second switch, and wherein a second output is connected to the first charging element through a third switch and to the second charging element through a fourth switch, and the differential voltage ramp generator further comprises a switch control circuit for opening and closing the switches to generate the differential voltage output whose polarity depends on the digital input.

[0065] In some embodiments, the first output of the differential voltage ramp generator is connected to a first capacitor, and the second output of the differential voltage ramp generator is connected to a second capacitor.

[0066] In some embodiments, a capacitor is connected between the outputs of the differential voltage ramp generator.

[0067] In some embodiments, the differential voltage ramp generator has two charging states selected by a polarity of the digital input, wherein in a first charging state the first and fourth switches are closed and the second and third switches are open, and in a second charging state the first and fourth switches are open and the second and third switches are closed.

[0068] In some embodiments, the switch control circuit is configured to implement a pre- post control of the switches.

[0069] In some embodiments, the CDF is configured to reset the voltage ramp of the CDF as soon as the comparator has detected that the differential ramp voltage has reached a target differential voltage, so that the CDF is ready to start the next ramp as soon as possible.

[0070] In some embodiments, the differential voltage ramp generator comprises two linear voltage ramp generation circuits of opposite polarity.

[0071] In some embodiments, the apparatus further comprises a double differential amplifier taking as input two pairs of differential signals, applying the same gain to the two pairs of differential signals and summing the two pairs of differential signals to provide a single differential pair output to a comparator, and a circuit providing a reference differential voltage of a polarity selected by an output of the comparator, and providing one differential input to the double differential amplifier DDA, and providing means to adjust the delay time and to act as a hysteresis voltage for the comparator, and wherein the other differential input to the DDA is provided by the differential voltage ramp generator.

[0072] In some embodiments, the differential voltage ramp generator comprises two single-ended voltage ramp generators, and each single-ended voltage ramp generator comprises a charging element and a discharging element and a charging capacitor, wherein one or more of the charging element / the discharging element or the capacitor is adjustable.

[0073] In some embodiments, the capacitor is adjustable in order to adjust the delay time. In some embodiments, the charging element is adjustable in order to adjust the delay time. In some embodiments, the charging element and the discharging element in the voltage ramp generator are resistors or current sources.

[0074] In some embodiments, the apparatus further comprises means to adjust or adjust a propagation delay of a signal through the optical receiver apparatus.

[0075] In some embodiments, the apparatus further comprises a CDF and adjusting or adjusting circuitry for adjusting the delay time of the CDF.

[0076] In some embodiments, the apparatus further comprises a digital filter and an adjustment or tuning circuit for adjusting the propagation delay of the digital filter.

[0077] In some embodiments, the apparatus further comprises an adjustable capacitance to adjust the propagation delay of the apparatus by adjusting the input capacitance seen by the receiver at the photodiode.

[0078] In some embodiments, the apparatus comprises an adjustable capacitance to adjust the propagation delay of the apparatus by adjusting the input capacitance seen by the receiver at the photodiode, wherein an adjustment of the area of the photodiode is adjustable by connecting or disconnecting the photodiode in parallel, thereby changing the input capacitance and affecting the propagation delay.

[0079] In some embodiments, the TIA has an adjustable or tunable bandwidth.

[0080] In some embodiments, the apparatus comprises a feedback network for adjusting the transimpedance bandwidth of the TIA.

[0081] In some embodiments, the apparatus comprises an adjustable capacitor connected in the feedback network of the TIA to adjust the bandwidth of the TIA.

[0082] In some embodiments, the apparatus comprises a circuit configured to adjust the transimpedance bandwidth of the TIA by adjusting a feedback network comprising an RC combination across the TIA, the TIA receiving an input from an adjustment memory.

[0083] In some embodiments, the apparatus is configured to adjust the bandwidth of the TIA by an adjustable analog filter of the output of the TIA, and preferably the filter comprises a low pass RC filter with adjustable components.

[0084] In some embodiments, the TIA comprises an adjustable resistor connected between the TIA output and the TIA input.

[0085] In some embodiments, the apparatus comprises an integrated photodiode, wherein the area of the photodiode is adjustable.

[0086] In some embodiments, the apparatus further comprises an optical input emulation circuit connectable to the TIA via a test mode switch, wherein the optical input emulation circuit comprises at least a current source that can be modulated on and off.

[0087] In some embodiments, the optical input emulation circuit further comprises a load network for emulating a photodiode load.

[0088] In some embodiments, the digital output is coupled to the optical input emulation circuit to set the digital output of the receiver to oscillate.

[0089] In some embodiments, the optical input emulation circuit comprises an adjustable current source and a switch.

[0090] In some embodiments, the optical input emulation circuit comprises an adjustable current source, a switch, and a load network.

[0091] In some embodiments, the optical input emulation circuit comprises an adjustable current source, a switch, and a load network, the load network comprising a load capacitor for emulating the photodiode capacitance load, a load resistor for emulating photodiode leakage, and a series resistor for emulating photodiode output impedance.

[0092] In some embodiments, the optical input emulation circuit comprises a digital control input to turn on and turn off modulation of the test current, wherein the input signal to this digital control input can be configured to be either from outside the optical receiver device or from an internal source within the optical receiver device.

[0093] In some embodiments, the device further comprises a circuit configured to electrically test the propagation delay, and the output digital signal is arranged to couple to the input signal on the digital control input on the optical input emulation circuit with the polarity such that the optical receiver device oscillates.

[0094] In some embodiments, the receiver device comprises an external delay circuit between the output digital signal and the input of the optical input emulation circuit, the external delay circuit configured to add a known constant propagation delay to the oscillating signal.

[0095] In some embodiments, the device comprises: a PD emulator connected to the optical receiver via a switch; a test mode enable switch for allowing a turn on / off signal to be coupled to the switch; a test mode select switch for selecting between an internal signal input to the switch or an external input to the switch; and an internal feedback logic inverter for coupling the correct polarity to cause oscillation when the internal test mode is selected and the test mode is enabled. BRIEF DESCRIPTION OF DRAWINGS

[0096] The application will be more clearly understood from the following description thereof, given by way of example only, with reference to the accompanying drawings, in which:

[0097] Figure 1 is a graph showing prior art EMI output,

[0098] Figure 2 is a graph of a typical prior art H-bridge,

[0099] Figure 3 is a graph showing a prior art self-induction EMI switching arrangement as described in the description below,

[0100] Figures 4 to 20 aspects of an optical receiver device having a constant delay filter ("CDF") are shown:

[0101] Figure 4 is a high level block diagram of a receiver having a constant delay filter ("CDF") located after the analog to digital conversion circuitry (comparator) and receiving a digital input,

[0102] Figure 5 CDF standard operation with fixed delay is shown,

[0103] Figure 6 is a set of graphs showing EMI filtering due to the CDF,

[0104] Figure 7 is a graph showing typical prior art propagation delay versus optical power in the presence of an automatic gain control circuit that reduces TIA transimpedance gain and increases TIA bandwidth as optical power increases,

[0105] Figure 8 is a block diagram of a CDF having a differential voltage ramp generator and comparator,

[0106] Figure 9 is a more detailed CDF block diagram having two ramp capacitors (CO, CI), resistive current sources (RO, Rl), ideal switches (SO, SI, S2, S3), and a switch control circuit to control switch open and close timing,

[0107] Figure 10 CDF RC voltage ramp curve is shown,

[0108] Figure 11 CDF embodiment with current mirror sources (IO, II) is shown,

[0109] Figure 12 differential cap embodiment of CDF and simplified switch control circuit are shown,

[0110] Figure 13 is a graph showing a CDF with reset,

[0111] Figure 14 is a set of graphs showing a CDF linear voltage ramp waveform with a reset,

[0112] Figure 15 is an embodiment with a CDF and a pulse reset,

[0113] Figure 16 is a set of graphs showing a CDF linear voltage ramp waveform with a pulse reset,

[0114] Figure 17 is a set of graphs showing a CDF linear voltage ramp waveform with a reset in the presence of EMI,

[0115] Figure 18 is an embodiment with a switch implementation using MOS devices,

[0116] Figure 19 is an embodiment with a CDF with a dual single-ended slope generator,

[0117] Figure 20 is an embodiment with a CDF and a dual differential amplifier and a reference voltage generator,

[0118] Figures 21 to 27 is an illustration showing aspects of a tunable propagation delay, as follows:

[0119] Figure 21 shows a tunable TIA feedback network,

[0120] Figure 22 shows a tunable analog low pass filter,

[0121] Figure 23 shows a tunable photodiode area,

[0122] Figure 24 shows a tunable capacitor at the TIA input, Figure 25 shows a receiver incorporating a tunable CDF to tune the propagation delay, and

[0123] Figure 26 shows a receiver incorporating a tunable digital filter,

[0124] Figure 27 shows an optical receiver with a PD emulator,

[0125] Figure 28 shows an optical receiver with a PD and an optical input emulator and configured to use an externally connected oscillator,

[0126] Figure 29An optical receiver configured to oscillate is shown, with a delay incorporated in the feedback path,

[0127] Figure 30 An oscillation test mode is shown integrated and using PD emulation circuitry,

[0128] Figure 31 A TIA conditioning and test mode circuit is shown.

[0129] Figure 32 An oscillation test mode circuit is shown with fuse memory,

[0130] Figure 33 An embodiment is shown incorporating optical emulation circuitry with test mode options to enter oscillation mode, incorporating CDFs and incorporating propagation delay conditioning,

[0131] Figure 34 A circuit is shown with CDFs and conditioning, and

[0132] Figure 35 An embodiment is shown with oscillation setup with external connections from Vo to Din. DETAILED DESCRIPTION

[0133] In applications requiring low propagation delay skew, it is generally avoided to increase the propagation delay, as prior art receivers intended for low skew are generally designed to have low propagation delay to minimize skew, however, such receivers still need to be EMI robust in nature. The present invention provides a filtering technique that, while imparting a small propagation delay to the circuit, can improve EMI robustness.

[0134] In power converter applications, characteristic EMI is EMI generated by the application circuit itself; switching events generate EMI, as Figure 3 shown. There are two characteristics of this EMI event that are notable with respect to the present invention. First, the EMI tends to have most of its power in high frequencies. Second, the EMI event occurs after the receiver has propagated the valid control signal to its output. The effect of this EMI on the digital output of the optical receiver is typically a few short duration glitches, as Figure 1 shown.

[0135] Constant delay filter

[0136] In the present invention, a constant delay filter (CDF) is employed in some embodiments, and Figure 4A receiver device 1 is shown which includes an optical receiver 2 followed by a CDF 3 which provides an output voltage Vo. An ideal CDF receives a digital input and outputs a digital output which is delayed by a finite filter time. The ideal CDF is characterized in that it applies the same propagation delay to rising and falling edge inputs, and it filters out any signal whose duration is less than its delay time. That is, it removes any input pulse whose duration is shorter than the delay and prevents these pulses from being output. The ideal CDF is also characterized in that the delay time of the filter is time-invariant, i.e. the delay time does not vary according to the period between input edges provided that this period is greater than the delay time of the filter. Thus, the filter delay time of the CDF is also invariant to the input data rate (constant delay) provided that the time between input data edges is greater than the filter time. In other words, the ideal CDF does not introduce pulse width distortion (PWD) into the signal. This is typically not the case in known prior art circuits.

[0137] In Figure 4 a device, the CDF introduces an additional fixed propagation delay to the optical receiver as shown in Figure 5 The added propagation delay is typically undesirable in an optical receiver, but in the present invention the benefits of the delay filter EMI outweigh any disadvantages. The function of the constant delay filter is to filter out any EMI event whose duration is less than the constant delay as shown in Figure 6 Figure 6 The EMI event shown at DIN (original output) in Figure 3 does not affect the output signal Vo (output after CDF). In the case where the EMI event is self-induced due to a controlled switching event, for example shown in

[0138] The constant delay filter preferably does not introduce any PWD in normal operation. The maximum allowable PWD requirement of the CDF can be less than a nanosecond. Prior art CDF (or glitch filter) architectures will introduce PWD when examined in detail because they do not delay rising and falling edges equally. Some CDF architectures depend on undesirable complex oscillator circuits.

[0139] In one embodiment of the present invention, an integrated optical receiver circuit outputs a digital output signal to a constant delay filter circuit which provides a filtered digital output as shown in Figure 6 The CDF applies a fixed delay to both rising and falling edges. Input pulses to the CDF which are shorter than the fixed delay are filtered. Since EMI pulses typically have short duration, this is an effective EMI filter. Furthermore, the use of the CDF facilitates a change in design philosophy to improve skew. As shown in Figure 7 ​As shown, the propagation delay through an optical receiver with AGC typically experiences significant variations in optical input power. An optical receiver operating with small variations in optical input power can have significant propagation delay skew. A strategy to increase the TIA bandwidth will reduce the absolute propagation delay variation through the TIA due to AGC. However, increasing the TIA bandwidth can compromise EMI performance. The introduction of the CDF facilitates a strategy to use a high bandwidth optical receiver architecture with little variation in the received optical power. The CDF provides an effective EMI filter and does not introduce any propagation delay variation in the optical receive power. Preferably, the propagation delay of the constant delay filter is adjustable.

[0140] In some preferred embodiments, the present application uses a constant delay filter based on generating a differential voltage ramp, the output of which is connected to a comparator, as shown in Figure 8 In this example, the CDF 10 includes a differential ramp generator 11 that receives Din and is linked at its output to a comparator 12 that provides DOUT. The delay time of the CDF is set by choosing the charging speed of the ramp and the level of the comparator hysteresis. Any input that is shorter than the delay time at the input during the ramp change process will be rejected.

[0141] The differential nature of the ramp 11 eliminates any non-linearities or mismatches of the circuit and components, thereby ensuring equal propagation delay of rising and falling input edges.

[0142] Non-linearities in circuit components are common. For example, MOS-based capacitors are often cheaper to use in MOS processes because they do not require additional expensive mask steps, such as for metal-insulator-metal capacitors or poly-poly capacitors, both of which require additional expensive process layers compared to a simple MOS process. MOS capacitors exhibit strong non-linear capacitance with respect to differential voltage. This introduces non-linear effects into a typical current-capacitor ramp circuit. The differential ramp can be a linear voltage ramp with respect to time, such as generated by a constant current charging a capacitor. The ramp can also be non-linear, for example an R-C curve generated by a resistor connection charging a capacitor.

[0143] In some preferred embodiments, the present application uses a constant delay filter based on generating a differential voltage ramp, the output of which is connected to a comparator, as shown in Figure 9A preferred method for generating a differential ramp voltage is illustrated. As shown, the differential ramp generator 11 includes a switch control circuit 21 that receives DIN and controls switches S0, S1, S2, and S3 in an H-bridge. Switches S0, S1, S2, and S3 provide RAMP_P and RAMP_M signals to comparator 12. These links have charging capacitors C0 and C1 connected to RAMP_P and RAMP_M, respectively. C0 and C1 are shown as connected to ground, but can be connected to any AC ground or dummy ground, such as the negative supply voltage (VSS) or the positive supply voltage (VDD). One side of switches S0 and S1 is shared and connected to the positive supply voltage (VDD) via resistor R0. The other switch connections of S0 and S1 are connected to nodes RAMP_M and RAMP_P, respectively. Similarly, switches S2 and S3 share a connection to the negative supply voltage (VSS) via R1, while another connection of S2 and S3 is connected to RAMP_M and RAMP_P, respectively. For clarity, the physical connection between the switch control circuit 21 and switches S0, S1, S2, and S4 is not shown, but is implied. By opening or closing switches S0, S1, S2, and S3 in a standard H-bridge configuration, capacitors C0 and C1 are charged or discharged through resistors R0 or R1, thereby generating a differential voltage ramp with a characteristic RC curve. Because the voltage ramp is differential, the PWD is robust to component mismatch.

[0144] like Figure 10 As shown, there are two charging states selected by the polarity of the digital input at DIN. In the first charging state, switches S0 and S3 are closed, while S1 and S2 are open. In the second charging state, conversely, switches S1 and S2 are closed, while switches S0 and S3 are open. The switch control circuit controls the charging state according to the input signal on DIN. The switch control circuit can implement open-before-close control of the switches. The first output of the ramp voltage is generated by charging the first capacitor starting from the negative supply voltage (VSS) by connecting the capacitor to the first resistor associated with the positive supply voltage (VDD). The second output of the ramp voltage is similarly generated by charging (or discharging with the opposite polarity given) the second capacitor starting from the positive supply voltage by connecting the capacitor to the second resistor associated with the negative supply voltage. The characteristic ramp generated using the charging resistor and capacitor is a well-known RC curve with an RC time constant, such as... Figure 10 As shown. If the comparator detects the differential crossover point of this curve, the characteristic delay of this circuit is set by the resistor and capacitor values ​​and is independent of the supply voltage. This is advantageous because it maintains a propagation delay that is robust to changes in the supply voltage.

[0145] like Figure 11As shown, the charging resistors R0, R1 can be replaced with current sources I0, I1 to produce a linear differential voltage ramp. Current sources can be advantageous because they typically require less IC area than large resistor values. Figure 11 An embodiment includes a digital input (DIN), a differential voltage ramp generator circuit having differential voltage output terminals (RAMP_P, RAMP_M), and a comparator having a digital output (DOUT). The differential voltage ramp generator circuit further includes capacitors CO, CI connected between the voltage ramp generator output terminals (RAMP_P, RAMP_M) and AC ground, a first current source (I0) coupled to a positive supply rail (VDD), and a second current source (II) coupled to a negative supply rail (VSS). The current sources are connected to the capacitors through a network of switches (SO, SI, S2, S3) such that there are two logic connection states, a first state and a second state. In the first state, when the digital input (DIN) is a logic one, the first current source (I0) is connected to the positive output terminal (RAMP_P) of the voltage ramp generator and the second current source (II) is connected to the negative output terminal (RAMP_P) of the voltage ramp generator and the comparator output (DOUT) is also a logic one. In the second state, when the digital input (DIN) is a logic zero, the current sources are connected to the opposite output terminals, i.e., the first current source (I0) is connected to the negative output (RAMP_M) of the voltage ramp generator and the second current source (II) is connected to the positive output (RAMP_P) of the voltage ramp generator and the comparator digital output (DOUT) is a logic zero. The comparator digital output changes state when the voltage ramp generator differential voltage changes polarity. When the digital input logic transitions from one state to the other, the current sources supply current to the capacitors such that a differential voltage ramp is generated and thus a known filter delay is generated between the change in DIN to the differential voltage RAMP_P-RAMP_M reaching zero. The voltage ramp (RAMP_P-RAMP_M) is linear and governed by the well-known formula:

[0146] V = I.t / C

[0147] where V = differential ramp voltage; I = sum of the amplitudes of I0 and II; t = time; C = CO in farads,

[0148] The starting voltage of the differential voltage ramp is the potential difference between the supply rails (VDD-VSS). When the comparator will trip at V = 0, the filter delay can be calculated using the following formula:

[0149] Filter delay = V.C / I;

[0150] where V = VDD-VSS; I = sum of the amplitudes of I0 and II; C = CO in farads

[0151] Because the starting voltage is VDD-VSS or VSS-VDD, the amplitude is always the same. Therefore, the positive and negative ramps will have equal delays, regardless of the values ​​of I0 and I1. In practice, it is preferable that they are chosen to have similar amplitudes such that the common-mode voltage when RAMP_P and RAMP_M are equal is sufficient for the comparator input bias.

[0152] If needed, a hysteresis can be incorporated into the comparator, which will change the trip voltage accordingly. Many components of the embodiment can be designed to be adjustable to allow for adjustment of propagation delays, such as the size of the current mirror, the value of capacitor C0, or the hysteresis voltage in the comparator. Control of switches S0, S1, S2, and S3 is preferably implemented in an open-before-close topology to prevent any short-circuit current.

[0153] In an alternative embodiment, the ramp voltage can be generated across a single capacitor connected across the differential ramp output, such as... Figure 12 The capacitor CD is shown in the diagram. This illustrates a receiver device 30 with a differential ramp generator 31, which also has an H-bridge with switches S0 to S3, and a current source I0 linked to VDD and a current source I1 linked to VSS, the current sources (I0, I1) replacing the charging capacitor. Using current sources to charge the capacitor instead of using resistors will result in a linear ramp voltage. Figure 12 A very simple switch control mechanism is also shown, wherein DIN is connected to the OPEN switch S0 when the input is low, and DIN is also connected to the OFF switch S2 when the input is low. DIN is connected to switch S1 via a logic inverter, which is OPEN when the input is low, and to switch S3, which is OFF when the input is low. This is a very simple H-bridge control for illustrative purposes. Preferably, the break-before-make timing circuit system is used to avoid any short-circuit current.

[0154] Figure 13 A preferred embodiment with a reset function is described. Once the comparator has detected that the differential ramp voltage has reached its target differential voltage, the CDF should reset its voltage ramp so that it is ready to start the next ramp from the same voltage as quickly as possible. This enhancement allows nodes RAMP_P and RAMP_M to quickly reach their final voltages to prepare the CDF to receive another input pulse without causing a PWD. Figure 13 The document describes one possible measure for providing this reset. In this case, the differential ramp generator 41 includes a switch control circuit 42, a feedback XOR gate 43, H-bridges S0 to S3, charging resistors R0 and R1, and outputs RAMP_P and RAMP_M with capacitors C0 and C1, respectively.

[0155] The generated waveforms are shown in Figure 14 When the digital input and digital output have the same polarity, the charge elements (R0, R1, I0, I1) are bypassed by closing the reset switches (S4, S5) across them. When the digital input DIN to the CDF 12 and the output from the CDF comparator 12 have different polarities, the discharge switches are open and do not affect the charging of the voltage ramp.

[0156] An alternative measure to provide this reset is depicted in Figure 15 In this figure, the same parts are given the same reference numerals, and in this case, there are switches S4 and S5 across the current sources I0 and I1, respectively. When the comparator output polarity changes, the pulse generator circuit can generate a short pulse. This pulse can be used to close the discharge switches in the ramp generator for a short period. As Figure 15 shown, a further enhancement of the CDF circuit includes a reset circuit that includes a reset pulse generator that has an input from the comparator output (DOUT) and provides an output to close the switches S4 and S5 across the charge current sources (I0, I1, R0, R1). The reset pulse generator outputs a short digital pulse in response to a digital edge at its input. This form of reset generator is advantageous in the presence of EMI events.

[0157] Figure 16 The input, output, and voltage ramp waveforms of the receiver in Figure 15 normal operation are depicted.

[0158] Figure 17 A set of diagrams of the operation of Figure 15 in the presence of an EMI event, showing EMI mitigation affecting the propagation delay. In more detail, this depicts that the duration of the EMI event increases the propagation delay by an amount equal to twice the duration of the EMI event.

[0159] Embodiments Figure 18 A CDF is depicted with a simplified implementation of the switches (S0, S1, S2, S3) using MOS transistors (M0, M1, M2, M3) as switches. Preferably t-gate MOS switches are used. C0 and C1 are preferably identical. C0 and C1 advantageously define the common mode voltage of the differential voltage ramp output, independent of the switch impedances and little affected by the parasitic capacitance switching transients from the switches M0, M1, M2, and M3.

[0160] Figure 19An embodiment of a CDF for an optical receiver device 200 is shown. The device 200 comprises a double differential amplifier 201 that takes as input two pairs of differential signals, applies the same gain to them and sums them to provide a single differential pair output to a comparator 202. A circuit 203 provides a reference differential voltage REF_P, REF_M, the polarity of which is selected by the output of the comparator 202, and provides one differential input to the double differential amplifier (DDA) 201, and provides means to adjust the delay time as well as to act as a hysteresis voltage to the comparator. The other differential input to the DDA is provided by a differential voltage ramp generator 204 comprising two single-ended voltage ramp generators 205, 206. Each single-ended voltage ramp generator comprises a charging element (IT2, IT4) and a discharging element (IT3, IT5), which can be a current source or a resistor, and a charging capacitor (CT3, CT4). One or more of the charging / discharging elements (IT2, IT3, IT4, IT5) or capacitors (CT3, CT4) can be adjustable. This can advantageously allow for adjustment that intentionally unbalances the ramp times of the voltages RAMP_P and RAMP_M and intentionally introduces a PWD that can be used to compensate for a PWD in the input signal, thereby cancelling the overall PWD of the receiver.

[0161] Figure 20 Another CDF 210 is shown with a DDA 211, a comparator 212 at the output of the DDA 211, a reference differential voltage circuit 213, and a differential ramp generator 214. The reference differential voltage circuit is made up of a current source (I6) that inputs current into a reference resistor (R2) and a common mode setting resistor (R3). The differential voltage produced by the IR combination of R2 and I6 is input to the DDA and sets the trip voltage of the comparator for the input differential ramps (RAMP_P, RAMP_M). This advantageously allows for a method of adjusting the propagation delay by adjusting the value of R2 or I6.

[0162] Skew / propagation delay adjustment

[0163] The present invention provides a receiver with improved skew performance. Skew is a specification that currently has no industry standard definition and is not something that is easily measured. Large production measurements of propagation delay are difficult and the typical approach is to accept a large amount of skew inherent in the optical receiver. For simplicity, the depicted embodiments show single-ended circuits, but can be fully differential circuits. For example, two single-ended TIAs can be combined to form a differential TIA, with one TIA serving as a reference. Alternatively, a fully differential amplifier can have two photodiodes at its input, with one photodiode acting as a "dark" reference. Differential circuitry after the TIA can be employed, rather than the single-ended circuitry depicted for simplicity. It is also worth noting that the interchange of MOS or bipolar transistor technology is generally trivial, regardless of which transistor is used.

[0164] The propagation delay of an optical receiver can be adjusted by adjusting the transimpedance bandwidth of the TIA, particularly by adjusting the feedback network, as shown in Figure 21 This figure shows a TIA feedback network 60 that can be adjusted, where the TIA has a PD 62 at its input, and there is an RC combination 63 across the amplifier 61, which receives input from an adjustment memory 64. The output of the TIA is linked to circuitry 65 for gain, decision threshold, and digital output control. The bandwidth of the TIA can be adjusted by adjusting the capacitor or resistor or both in the feedback network 63. The adjustment memory is typically a one-time programmable memory that is adjusted during the test phase of the IC, preferably during wafer probe testing. Alternative adjustment methods include resistor laser adjustment, polysilicon fuse memory, or flash memory.

[0165] In one embodiment of the present invention, an optical receiver includes a TIA with an adjustable feedback resistor. There can additionally be an automatic gain control circuit present. The propagation delay of the optical receiver can be adjusted by the adjustable resistor element in the shunt feedback of the TIA. This has the benefit of reducing the part-to-part variation in the TIA transimpedance bandwidth. Figure 7 A typical relationship between propagation delay and optical power in an optical receiver with automatic gain control (AGC) is shown. For relatively low power, there is no impact from the AGC, and due to the increased drive strength from the analog sense signal, a small decrease in propagation delay can be seen, but ideally the propagation delay does not vary due to optical power received before the AGC affects the bandwidth. Once the AGC starts to decrease the shunt feedback impedance, the transimpedance bandwidth increases. The propagation delay decreases as the bandwidth increases, but the decrease is not as large as the decrease in bandwidth. Figure 7The resulting variation in transit delay that is typically caused is depicted. If the optical receiver has a part-to-part variation in its transimpedance bandwidth, this will affect the characteristic transit delay variation over the optical receive power range. Then, with automatic gain control present, an optical receiver with an adjusted TIA shunt feedback impedance can have a better matched transit delay over the optical power range.

[0166] In some embodiments of the invention, the optical receiver includes a connected adjustable capacitor to affect the transimpedance bandwidth of the TIA. Preferably, the TIA features an AGC circuit. Figure 7 An example variation in transit delay with respect to received input optical power is shown. With automatic gain control present, it can be advantageous to adjust the transimpedance bandwidth of the TIA using a capacitor. The capacitor can be adjusted to make the operation of the AGC necessary in the presence of an input signal of sufficient amplitude. The AGC can be configured to adjust the transimpedance gain in order to output a target voltage when operating. This requires that for a given signal, there must be a definite transimpedance value. If the part is adjusted using an adjustable capacitor with the same input signal amplitude applied to the TIA, the transit delay versus input optical power relationship curve can be closely matched.

[0167] In one embodiment of the invention, the optical receiver includes a TIA with an adjustable feedback capacitor connected in parallel with a negative feedback resistor between the TIA input and output. The capacitor value can be adjusted by adding or subtracting parallel capacitors using a switch. Adjusting the capacitor adjusts the transimpedance bandwidth of the TIA in the optical receiver.

[0168] In one embodiment of the invention, the optical receiver includes a TIA with an adjustable feedback capacitor connected between the TIA input and an AC ground, such as a positive or negative voltage source. The capacitor value can be adjusted by adding or subtracting parallel capacitors using a switch. Adjusting the capacitor adjusts the transimpedance bandwidth of the TIA in the optical receiver.

[0169] In one embodiment of the invention, the optical receiver includes a TIA with a combination of an adjustable feedback resistor and an adjustable capacitor connected to the TIA input.

[0170] Alternatively, as Figure 22As shown in the middle, the bandwidth of the signal from TIA 63 can be adjusted by employing an adjustable analog filter between the output of TIA 63 and the decision circuitry 65. For example, a simple low-pass RC filter 67 with adjustable components can be employed to filter the analog signal. An active filter can also be used as the low-pass filter. The low-pass filter provides a measure of EMI filtering, so adjusting the filter to adjust the propagation delay to a target value improves EMI robustness while minimizing propagation delay skew.

[0171] The propagation delay of an optical receiver can be adjusted by adjusting the input capacitance seen by the receiver at the photodiode, i.e., the adjustment of the area of the photodiode can be adjusted by connecting or disconnecting additional parallel photodiodes, thereby changing the input capacitance and affecting the propagation delay. Figure 23 A receiver with differential photodiodes 73, 75 with adjustable photodiode area is depicted. Both photodiodes will be adjusted with the same adjustment code. Only one of the photodiodes will be configured to receive the optical input signal (active PD), while the other photodiode will not receive the optical input signal, for example by an opaque cover (such as metal) over the dark (or non-active) photodiode, or by placing in a position that does not receive the optical signal. The receiver device 70 has an adjustment memory linked through switch 72 to the active PD with adjustable area 73 and through switch 74 to the non-active PD with adjustable area 75. Photodiodes 73 and 75 are linked to the input of an optical receiver 76 that provides an output Vo. Adjusting the photodiode area to adjust the TIA bandwidth and thus the propagation delay has the beneficial effect of increasing the received light when the bandwidth is slow, thereby optimizing the receiver sensitivity for a given propagation delay target. The low-bandwidth photodiode provides a measure of EMI filtering, so adjusting the photodiode area to adjust the propagation delay to a target value improves EMI robustness while minimizing propagation delay skew.

[0172] A capacitance connected in parallel with the input photodiode can be adjusted by connecting or disconnecting the capacitance element to change the input capacitance of the optical receiver, and thereby change the propagation delay of the receiver, as shown in Figure 24 . Figure 24 An input PD 83 coupled to a TIA 81 is depicted. The PD 83 has an adjustable capacitance 84 across it. This adjustment method has the benefit of requiring less on-chip area than other measures that affect the input capacitance.

[0173] Cdf and propagation (PROP) delay adjustment

[0174] Figure 25A block diagram of a receiver is shown in which the propagation delay can be influenced by incorporating a constant delay filter 86 with an adjustable propagation delay time. Figure 25 An input PD 83 is depicted coupled to a TIA 81, the output of which is linked to circuitry 65 for gain, decision threshold, and digital output control, which is linked to an adjustable CDF block 86. This is advantageous because this embodiment incorporates propagation delay adjustment to improve skew performance as well as the EMI filtering advantages of CDF. The CDF is also advantageous in that the CDF provides constant delay which is ideal for low skew.

[0175] Figure 26 is an embodiment of a receiver 88 in which the gain, decision threshold, and digital output control circuitry 65 is linked to an adjustable digital filter 89. The receiver propagation delay can be changed by introducing an adjustable digital filter 87. This has the disadvantage of requiring additional digital circuitry, but has the advantage of the various advantages of digital filters, such as the precision of the filter.

[0176] Optical input emulation circuit

[0177] The present invention provides a means to emulate optical testing of an integrated circuit without the need for an optical input. In the case of a receiver without integrated photodiodes, the present invention can also emulate the presence of a photodiode load. Secondly, the present invention provides a test configuration that allows for electrical testing of propagation delay and PWD.

[0178] To emulate optical testing, an optical input emulation circuit is used to provide a test mode whereby the on-chip circuitry provides the test function. It consists of an adjustable current source, such as a current output digital to analog converter (IDAC), and switches. In the case of an integrated photodiode on the same substrate as the integrated receiver, no further load is needed to emulate the photodiode. Alternatively, in the case of an integrated receiver without incorporated photodiodes, the optical input emulation circuit can include a load network, such as a load capacitance to emulate the photodiode capacitance load, a load resistor to emulate the photodiode leakage, and a series resistor to emulate the photodiode output impedance. When using a test mode with the photodiode load network emulating the photodiode load, the load is connected to the input of the TIA via test mode switches. Then, using different test mode switches, the photodiode optical current emulation circuit is modulated while the load network remains connected to the input of the TIA.

[0179] REFERENCE Figure 27The receiver device 90 has an optical receiver 91 at the input of which there is an optical input emulation circuit 92 with a digital controller. The optical input emulation circuit and the optical receiver circuit 91 are fully integrated on the substrate. It is disconnected from the optical receiver during normal operation by the controller 93. The chip can be configured to enter a test mode in which it connects the optical input emulation circuit to the input of the optical receiver via a switch as shown in Figure 27 The purpose of the optical emulation circuit is to input a current signal to the TIA that emulates the optically induced current from the photodiode to perform tests without the need for optical input to the IC. If needed, the optical emulation circuit can additionally emulate the load presented by the photodiode. The optical input emulation circuit has a digital control input to conduct on and off modulation of the test current. The input signal to this digital control input can be configured to come from outside the IC or from an internal source within the IC. Figure 27 The photodiode is not explicitly depicted but can be present integrated into the optical receiver, in which case the optical input emulation circuit only needs to emulate the photodiode input current or alternatively the IC can be intended to be connected to an external discrete photodiode, in which case the optical input emulation circuit can additionally emulate the load circuit of the external photodiode.

[0180] To electrically test the propagation delay, the IC can be configured via a test mode to couple the output digital signal to the input signal on the digital control input on the optical input emulation circuit with a polarity such that the receiver IC oscillates as shown in Figure 28 The figure shows a receiver device 100 that has an optical receiver 101 connected via a switch 102 to a PD emulator that includes a current source 103. The optical receiver 101 also includes an integrated photodiode 104 at its input. In Figure 28 The connection between the receiver output and the optical emulation circuit test mode input is made externally.

[0181] The propagation delay from the signal input to the optical emulation circuit to the output of the receiver IC will determine the period of oscillation on the output signal. In the case that both the rising edge input and the falling edge input experience the same propagation delay, the duty cycle of the oscillation will be 50%. In the case that the rising edge input and the falling edge input experience different propagation delays, the duty cycle will not be 50% and will indicate a pulse width distortion.

[0182] The measurement of oscillator frequency and duty cycle is a standard test procedure and is usually performed in a wafer probe or test environment. With standard test equipment that is usually available for third party wafer probe test services, highly accurate measurements are possible. Thus, the problem of how to measure the propagation delay and pulse width distortion in a test environment without the need for optical input or expensive dedicated test equipment is solved. Thus, the propagation delay of an optical receiver can be measured economically and accurately in mass production of optical receiver ICs, providing a practical measure that can perform propagation delay adjustment.

[0183] Figure 29 An embodiment similar to Figure 28 is shown with an added external delay circuit. The purpose of the delay circuit is to add a known constant propagation delay to the oscillating signal. This known delay can simply be subtracted from the propagation delay calculated from the measurement of the oscillation frequency. This is advantageous in the case of a receiver, where some analog elements, such as a TIA or a peak detector or automatic gain control, do not have time to reach a steady value. For example, if the propagation delay after the TIA is very small, the input signal to the TIA can change polarity while in the oscillating mode before the TIA has reached its final value, as it is limited by its bandwidth. This is problematic, as the propagation delay in this case will not reflect the actual operating conditions, where the input signal has a long enough duration to allow the TIA to stabilize, and thus the decision circuitry to accurately determine the signal strength, and thus the 50% crossing value, and also apply the correct automatic gain setting. Thus, this additional delay time allows the analog circuitry to stabilize before the polarity change of the input signal pulse arrives. Thus, the resulting propagation delay of the receiver will better match the propagation delay expected in actual operating conditions. Thus, the external delay element can improve the accuracy of the propagation delay measurement. It is also possible to introduce this delay internally in the IC. This can be advantageous, as it results in less external test circuitry.

[0184] Optionally, the test mode can be configurable, such that the coupling of the receiver output signal to the input of the optical emulation circuit is performed internally, as shown in Figure 30 .

[0185] Figure 30The device 110 is shown with an optical receiver 101, a PD emulator 103 connected to the optical receiver 101 via a switch 102, a test mode enable switch 105 to allow coupling of a turn-on / off signal to the switch 102, a test mode selection switch 106 to select between an internal signal input to the switch 102 or an external input to the switch 102, and an internal feedback logic inverter 107 to couple the correct polarity to cause oscillation when the internal test mode is selected and the test mode is enabled. The internal coupling of Vo advantageously requires less external connections in the test environment. The test mode selection switch 102 can be configured to provide an input to the IC from the outside, and thus the connections needed to set the receiver to oscillate can instead be made outside the device. The oscillation signal will be driven by the IC driver output and can be measured on the IC output pin.

[0186] Figure 30 The switchable current source in the PD emulator circuit 103 is additionally depicted as adjustable. The adjustable current source allows emulation of a range of input optical power that allows measurement of the propagation delay over a range of optical power, thus providing a measure of the skew of the propagation delay over a range of optical power.

[0187] Furthermore, since the switchable current source in the optical input emulation circuit is adjustable, it is possible to adjust the part to particularly low skew at a desired optical power that can be suitable for the receiver application.

[0188] Figure 30 A voltage buffer is additionally depicted with an input from the oscillation output signal and with an output into a low pass RC filter incorporating a resistor load RL and a capacitor load CL and generating a voltage VI. The DC component of the voltage VI is proportional to the duty cycle of the square wave output in the oscillation mode. For example, in case of a 50% duty cycle, the voltage is 50% of the supply voltage. The duty cycle of the output oscillation signal is indicative of the PWD of the receiver, where a 50% duty cycle is indicative of zero PWD. Deviation from the 50% duty cycle is indicative of the PWD. The measurement of the duty cycle and the oscillation period allows calculation of the PWD. This voltage VI can be measured in a test as a convenient measure of measuring the PWD.

[0189] Combination features

[0190] Embodiments of the invention can have one or any desired combination of features selected from the CDF circuit, the propagation delay adjustment, and the optical input emulation. The above description focuses on a receiver device with one of these aspects, however the following describes devices with some preferred combinations.

[0191] Optical input emulation and propagation delay adjustment

[0192] Optical input emulator circuitry configured to oscillate can be combined with methods of adjusting propagation skew to provide measures of measuring propagation delay in order to reduce propagation delay skew prior to adjusting propagation delay to a target. Figure 31 An optical input emulator test mode circuit combined with adjusting the propagation delay of the feedback network (resistor or capacitor) in the TIA is shown. In particular, this figure shows an apparatus 120 with gain, decision and digital output circuitry 121 fed by a TIA 122. There is an RC combination 123 in parallel with the amplifier and this is linked with an adjustment memory 124. In addition, there is a PD / optical input emulator combination 125 at the input to the TIA 122.

[0193] Figure 32 An optical receiver apparatus 130 is shown that can be configured by a test mode switch 135 to provide an oscillating mode of operation and has an optical receiver 131, a photodiode 134, an optical input emulator 132 and a fuse memory 133. The polarity of the photodiode is such that the cathode is connected to a positive voltage (VDD) and the anode is connected to the optical receiver input. The output polarity of the receiver in Figure 32 is shown with an output polarity at Vo that is inverted with respect to the input signal. The optical receiver can be programmed by the fuse memory to adjust its propagation delay.

[0194] CDF, optical input emulation and propagation delay adjustment

[0195] Figure 33 An optical receiver apparatus is shown with an optical input emulator circuit 153 coupled to the input of an optical receiver circuit 151 that outputs to a CDS 152 that can be adjusted. A constant delay filter can be effective to filter characteristics EMI in power converter applications. A CDF with adjustable delay time makes it an effective method to implement propagation delay to reduce skew. Using an optical input emulator test mode circuit configured to oscillate the receiver allows practical measures to implement mass production adjustment and testing of optical receivers. Apparatus 150 has various advantages of these components as described above in a synergistic manner. In particular, the EMI filtering capability of the CDF is incorporated and the CDF circuit is utilized to provide convenient measures to apply propagation delay adjustment.

[0196] Advantageously, the CDF architecture described previously can be easily modified to provide several measures to adjust the delay time of the filter as shown in Figure 34 . Figure 34Consists of a constant delay filter 140 similar to that described in other embodiments with enhancements to several adjustable components to allow implementation of an adjustable delay. It has a differential voltage ramp generator 141 linked to the input of comparator 142. Generator 141 has an H-bridge 143 (S0, S1, S2, S3, CT0, CT1), a switch control circuit 144, and a reset pulse generator 145 and reset switches (S4, S5) as described for the ramp generator of other embodiments. Adjustable charge elements RT0 and RT1 are shown, which can be adjustable resistors or adjustable current sources. CT0 and CT1 are adjustable capacitors, which can adjust their capacitance, for example, by connecting or disconnecting parallel capacitors using switches. Comparator 142 can have an adjustable hysteresis, which can increase or decrease the trip voltage, thus changing the propagation delay. The propagation delay can be adjusted during testing by adjusting one or more of the adjustable elements outlined.

[0197] Adjusting the CDF allows a measure to maximize EMI robustness while minimizing propagation delay skew. For example, an optical receiver can have a data sheet maximum propagation delay specification of 100 ns. Without the CDF, the receiver front end can have a propagation delay between, for example, 40 ns and 70 ns. This is a skew of 30 ns. The CDF is included before the digital output of the optical receiver. The CDF can have an adjustable delay between 30 ns and 60 ns. A section in the front end with a 40 ns propagation delay can be combined with a CDF adjusted to 60 ns to give a total propagation delay of 100 ns. A section with a 70 ns front end propagation delay can be combined with a CDF adjusted to a propagation delay of 30 ns, again giving a total propagation delay of 100 ns. Thus, all sections can be adjusted to have exactly a 100 ns propagation delay, eliminating skew and improving EMI robustness.

[0198] The target voltage can be adjusted. Another advantage of this CDF is that it is relatively easy to design with a certain temperature coefficient to increase or decrease the delay time to compensate for any temperature coefficient in the propagation delay in the previous circuitry to achieve a constant propagation delay as temperature varies.

[0199] In one embodiment of the invention, the optical receiver includes an integrated photodiode with an adjustable area that can be selected via a switch coupling the photodiode to the TIA input. Changing the photodiode area adjusts the transimpedance bandwidth, thus adjusting the propagation delay. This has the potential advantage of also optimizing the sensitivity of the receiver by increasing the received light.

[0200] The optical input emulation circuit allows an adjustable current source to be connected as input to the optical receiver. The current source can be turned on and off modulated by means of a switch. The value of the current can be adjusted to emulate light of varying optical power. The section will respond to the modulated current input as it would to a modulated optical input. The circuit can be integrated into the optical receiver integrated circuit, eliminating the need to provide any optical input to the test or wafer probe environment. The digital control input to the switch can be controlled from the test environment.

[0201] Advantages

[0202] The present invention improves the robustness to EMI. The present invention reduces the propagation delay skew. The present invention provides a measure of electrical testing of the integrated receiver propagation delay. The solutions to these technical problems are combined synergistically to improve EMI, reduce skew, while providing a measure of electrical testing of the receiver to affect these improvements.

[0203] The improvement in robustness to EMI provided by the present invention allows the optical receiver of the present invention to be used in increasingly harsh industrial environments, such as in power converters with ever increasing switching speeds. Devices sensitive to EMI cannot be used in these environments.

[0204] The improvement in skew will translate into higher conversion efficiency of power converters used, for example, in wind turbines.

[0205] The present invention increases the test coverage of the section by having a test mode with an optical input emulation circuit, increasing the industrial robustness. This circuit also reduces manufacturing costs, as it can be used in wafer probes to identify out-of-spec dies at the most economic point in the manufacturing process.

Claims

1. An optical receiver device comprising an optical receiver and an analog-to-digital converter, the optical receiver including a TIA, the analog-to-digital converter being used to provide digital output.

2. The optical receiver device as claimed in claim 1, further comprising: A constant delay filter (CDF) (3) is used to receive a digital representation of the received optical signal (DIN) and provide a digital output (Vo), wherein the constant delay filter receives a digital input signal and outputs the digital signal to the digital output which is delayed by a delay time, and prevents any pulse with a duration shorter than the delay time from being sent to the output.

3. The optical receiver device as claimed in claim 2, wherein, The CDF includes a differential voltage ramp generator (11) having differential voltage outputs (RAMP_P, RAMP_M) connected to at least one comparator.

4. The optical receiver device as claimed in claim 3, wherein, The differential voltage ramp generator further includes a first charging element (R0, I0) to a positive power supply and a second charging element (R1, I1) to a negative power supply, wherein a first output (RAMP_P) is connected to the first charging element via a first switch (S1) and to the second charging element via a second switch (S3), wherein a second output (RAMP_M) is connected to the first charging element via a third switch (S0) and to the second charging element via a fourth switch (S2), and the differential voltage ramp generator further includes a switch control circuit (21) for opening and closing the switch to generate the differential voltage output whose polarity depends on the digital input (DIN).

5. The optical receiver device as described in claims 3 to 4, wherein, The first output (RAMP_P) of the differential voltage ramp generator is connected to the first capacitor (C0), and the second output (RAMP_M) of the differential voltage ramp generator is connected to the second capacitor (C1).

6. The optical receiver device as claimed in any one of claims 3 to 5, wherein, A capacitor (CD) is connected between the outputs (RAMP_P, RAMP_M) of the differential voltage ramp generator.

7. The optical receiver device as claimed in any one of claims 3 to 6, wherein, The differential voltage ramp generator has a digital input (D) IN The two charging states are selected by polarity, wherein in the first charging state, the first switch (S1) and the fourth switch (S2) are closed, while the second switch (S3) and the third switch (S0) are open, and in the second charging state, the first switch (S1) and the fourth switch (S2) are open, while the second switch (S3) and the third switch (S0) are closed.

8. The optical receiver device as claimed in any one of claims 3 to 7, wherein, The switch control circuit (21) is configured to implement a first-off-then-close control of the switch.

9. The optical receiver device as claimed in any one of claims 3 to 8, wherein, The CDF is configured to reset the voltage ramp of the CDF (S4, S5) once the comparator has detected that the differential ramp voltage has reached the target differential voltage, so that the CDF is ready to start the next ramp as soon as possible.

10. The optical receiver device (200) as claimed in any one of claims 3 to 9, wherein, The differential voltage ramp generator includes two linear voltage ramp generating circuits (204) with opposite polarities.

11. The optical receiver device (200, 210) as described in claims 3 to 10, further comprising: The dual differential amplifier (201) takes two pairs of differential signals as inputs, applies the same gain to the two pairs of differential signals, and sums the two pairs of differential signals to provide a single differential pair output to the comparator (202); And circuit (203) provides a reference differential voltage (REF_P, REF_M) whose polarity is selected by the output of the comparator (202), and provides a differential input to the dual differential amplifier DDA (201), and provides measures to adjust the delay time and act as the hysteresis voltage of the comparator, wherein the other differential input to the DDA is provided by the differential voltage ramp generator.

12. The optical receiver device according to any one of claims 3 to 11, wherein, The differential voltage ramp generator (204) includes two single-ended voltage ramp generators (205, 206), and each single-ended voltage ramp generator includes a charging element (IT2, IT4) and a discharging element (IT3, IT5) and a charging capacitor (CT3, CT4), wherein one or more of the charging element / discharging element (IT2, IT3, IT4, IT5) or the capacitor (CT3, CT4) are adjustable.

13. The optical receiver device (140) as claimed in any one of claims 5 to 12, wherein, The capacitor is adjustable in order to adjust the delay time.

14. The optical receiver device (140) as claimed in any one of claims 4 to 13, wherein, The charging elements (RT0, RT1) are adjustable in order to adjust the delay time.

15. The optical receiver device according to any one of claims 4 to 14, wherein, The charging element and the discharging element in the voltage ramp generator are resistors or current sources.

16. The optical receiver device as claimed in any of the preceding claims further includes measures for adjusting or modifying the propagation delay of a signal through the optical receiver device.

17. The optical receiver device of claim 16, further comprising a CDF and an adjustment or regulating circuit for adjusting the delay time of the CDF (86).

18. The optical receiver device of claim 16 or claim 17, further comprising a digital filter and adjustment or regulation circuitry for adjusting the propagation delay of the digital filter (89).

19. The optical receiver device of any one of claims 16 to 18, further comprising an adjustable capacitor to adjust the propagation delay of the device by adjusting the input capacitance seen by the receiver at the input to the TIA.

20. The optical receiver device of any one of claims 16 to 19, further comprising a photodiode connected to the input of the TIA, wherein, The area of ​​the photodiode can be adjusted by connecting or disconnecting the photodiodes in parallel, thereby changing the input capacitance and affecting the propagation delay.

21. The optical receiver device as claimed in any of the preceding claims, wherein, The TIA has adjustable or modifiable bandwidth.

22. The optical receiver device of claim 21, further comprising a feedback network for adjusting the transimpedance bandwidth of the TIA.

23. The optical receiver device of claim 22, comprising an adjustable capacitor connected in the feedback network of the TIA to adjust the bandwidth of the TIA.

24. The optical receiver device according to any one of claims 21 to 23, wherein, The device includes circuitry configured to adjust the transimpedance bandwidth of the TIA (61) by adjusting a feedback network comprising an RC combination (63) across the TIA (61), the TIA (61) receiving input from a regulation memory (64).

25. The optical receiver device according to any one of claims 16 to 24, further comprising an analog filter and adjustment or regulation circuitry for adjusting the propagation delay of the analog filter (89).

26. The optical receiver device as claimed in claim 25, wherein, The analog filter includes a low-pass RC filter with adjustable components.

27. The optical receiver device according to any one of claims 21 to 26, wherein, The TIA includes an adjustable resistor connected between the TIA output and the TIA input.

28. The optical receiver device according to any of the preceding claims, further comprising an optical input emulation circuit, the optical input emulation circuit being connectable to the TIA via a test mode switch, wherein, The optical input simulation circuit includes at least a current source that can be modulated to be turned on and off.

29. The optical receiver device as claimed in claim 28, wherein, The optical input simulation circuit also includes a load network for simulating the load of a photodiode.

30. The optical receiver device as claimed in any one of claims 28 or 29, wherein, The digital output is coupled to the optical input emulation circuit so as to set the digital output of the receiver to oscillate.

31. The optical receiver device according to any one of claims 28 to 30, wherein, The optical input simulation circuit includes an adjustable current source and a switch.

32. The optical receiver device according to any one of claims 28 to 31, wherein, The optical input simulation circuit includes an adjustable current source, switches, and a load network.

33. The optical receiver device according to any one of claims 28 to 32, wherein, The optical input simulation circuit includes an adjustable current source and switch, as well as a load network. The load network includes a load capacitor for simulating the capacitive load of the photodiode, a load resistor for simulating photodiode leakage, and a series resistor for simulating the output impedance of the photodiode.

34. The optical receiver device according to any one of claims 28 to 33, wherein, The optical input simulation circuit includes a digital control input for modulating the test current to be turned on and off, wherein the input signal to the digital control input can be configured to originate from an external source or from an internal source within the optical receiver device.

35. The optical receiver device of any one of claims 28 to 34, further comprising circuitry configured to electrically test the propagation delay, and the output digital signal being arranged to be coupled to the input signal on the digital control input of the optical input emulation circuit, having the polarity such that the optical receiver device oscillates.

36. The optical receiver device according to any one of claims 30 to 35, wherein, The receiver device includes an external delay circuit between the output digital signal and the input of the optical input emulation circuit, the external delay circuit being configured to add a known constant propagation delay to the oscillating signal.

37. The optical receiver device as claimed in any of the preceding claims, comprising: A PD emulator (103) is connected to the optical receiver (101) via a switch (102); a test mode enable switch (105) is used to allow an on / off signal to be coupled to the switch (102); and a test mode selection switch (106) is used to select between an internal signal input to the switch (102) or an external input to the switch (102). And an internal feedback logic inverter (107) for coupling the correct polarity to induce oscillation when the internal test mode is selected and the test mode is enabled.

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