Power saving circuit and control method for a GPU server

Abstract

The application provides a power saving circuit and control method of a GPU server, and belongs to the field of server power management. The power saving circuit comprises: a power supply module for providing power supply for the GPU server; a power supply transmission circuit for transmitting the power supply of the power supply module to a target power feeding module; a plurality of functional units receiving the power supply of the power supply transmission circuit and entering a working state; the target power feeding module is one or more of the plurality of functional units; the power supply transmission circuit at least comprises a first transmission path and a second transmission path, the power supply input port connected with the power supply module is different from the first transmission path and the second transmission path, the power supply output port of the first transmission path is connected to one functional unit, and the power supply output port of the second transmission path is simultaneously connected to all functional units. The power saving circuit and control method of the GPU server provided by the application can realize accurate transmission control and timing management of the power supply while reducing the cost.

Description

Technical Field

[0001] This application relates to the field of server power management technology, and in particular to a power-saving circuit and control method for a GPU server. Background Technology

[0002] In GPU server power management, when multiple GPUs are present within the server, traditional power management methods typically rely on dedicated chip modules to manage the power supply of each GPU individually. While this approach achieves some power control functionality, the chip itself integrates multiple complex functions, resulting in high costs.

[0003] In practical applications, some customers have proposed a costdown mode to reduce costs, which involves removing the power management chip. However, in traditional solutions, removing the chip results in power being directly supplied to the GPU, with inputs and outputs shorted, leading to a pass-through state. All modules are connected to the same control circuit, meaning all functional units can only be powered on or off simultaneously, making it impossible to control the power of individual functional units. This pass-through method makes it impossible to effectively control the GPU's power supply time and lacks necessary timing management. During server operation, issues such as device initialization anomalies and unstable power supply may occur, failing to meet the server's reliability requirements for power management.

[0004] Furthermore, servers have different power requirements in different operating states. For example, in S5 state (soft shutdown state), power is only needed for system monitoring devices such as network cards, BMC chips, and CPLDs; while in normal operation state, power is needed for main operating devices such as GPUs, fans, memory, and CPUs. Traditional power management solutions in costdown mode struggle to achieve precise control and timing management of power supply in different states, affecting the server's energy-saving performance and operational stability. Summary of the Invention

[0005] In view of this, this application provides a power saving circuit and control method for a GPU server, which can reduce costs while achieving precise power transmission control and timing management, thereby improving the server's operational stability and energy-saving effect.

[0006] Specifically, this application is implemented through the following technical solution:

[0007] The first aspect of this application provides a power-saving circuit for a GPU server, the power-saving circuit comprising:

[0008] The power supply module is used to provide power to the GPU server;

[0009] A power transmission path is used to transmit the power from the power supply module to the target power supply module;

[0010] Multiple functional units receive power from the power transmission path, enter the working state, and complete the server functions corresponding to the functional units.

[0011] The target power supply module is one or more of the plurality of functional units. The power transmission path includes at least a first transmission path and a second transmission path. The first transmission path and the second transmission path are different from the power input port connected to the power supply module. The power output port of the first transmission path is connected to one functional unit, and the power output port of the second transmission path is connected to all functional units simultaneously.

[0012] A second aspect of this application provides a power-saving control method for a GPU server, the method comprising:

[0013] When the GPU server is connected to a power source, the power supply module outputs standby power, which is transmitted to the target power supply module connected to the first transmission path via the first transmission path.

[0014] In response to an external power-on signal, the control unit in the target power supply module outputs a power-on signal to the power supply module and simultaneously outputs a motherboard power switch enable signal to the second transmission path; the power-on signal controls the power supply module to switch to output the main power supply, and the motherboard power switch enable signal controls the second transmission path to be turned on.

[0015] The main power supply is transmitted to all functional units via the second transmission path, and the GPU server enters the running state.

[0016] The power-saving circuit and control method for GPU servers provided in this application achieve flexible power distribution and scenario adaptation through a dual-transmission circuit and differentiated power supply design. The input and output ports of the first and second transmission paths are completely different and independent of each other. The transmission circuit can switch power supply modes according to server needs through the on / off control of MOSFETs. The two independent transmission circuits also cooperate to achieve power supply under different power requirements, such as low power consumption and full power-on. That is, it can supply power to a single core functional unit individually through the first transmission path, and collectively supply power to all functional units through the second transmission path, solving the problem of full on or full off in traditional power management and achieving precise power supply under different working scenarios. Furthermore, by designing the first transmission path to supply power to only a single functional unit, the remaining functional units can be kept powered off under non-full load conditions, reducing ineffective power consumption and significantly reducing energy consumption during server standby or low load. Simultaneously, the second transmission path transmits power to all functional units at the same time, and combined with timing control, it can avoid power surges caused by disordered power-on of multiple functional units. Finally, the method provided in this application can achieve power supply control in multiple scenarios without relying on complex integrated power management chips, which simplifies the circuit structure and reduces costs. Attached Figure Description

[0017] Figure 1 A schematic diagram of the power saving circuit structure of the GPU server provided in this application;

[0018] Figure 2 A power-saving circuit connection diagram for the GPU server provided in this application;

[0019] Figure 3 A power-saving circuit connection diagram of the GPU server provided in this application;

[0020] Figure 4 A flowchart of Embodiment 2 of the power saving control method for the GPU server provided in this application. Detailed Implementation

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0022] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0023] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0024] The following specific embodiments are given to illustrate the technical solution of this application in detail.

[0025] Example 1

[0026] Figure 1 This is a schematic diagram of the power-saving circuit structure of the GPU server provided in this application. Please refer to... Figure 1 The power saving circuit provided in this embodiment includes:

[0027] The power supply module is used to provide power to the GPU server;

[0028] A power transmission path is used to transmit the power from the power supply module to the target power supply module;

[0029] Multiple functional units receive power from the power transmission path, enter the working state, and complete the server functions corresponding to the functional units.

[0030] The target power supply module is one or more of the plurality of functional units. The power transmission path includes at least a first transmission path and a second transmission path. The first transmission path and the second transmission path are different from the power input port connected to the power supply module. The power output port of the first transmission path is connected to one functional unit, and the power output port of the second transmission path is connected to all functional units simultaneously.

[0031] Please refer to Figure 1 The power supply module generates electricity and delivers it to the designated target functional unit through the power transmission path. The server then completes its functions through the specific functional unit connected to the power supply (i.e., the target power supply module).

[0032] It should be noted that the power supply module provides power to the entire GPU server and has different power output ports: a standby power output port and a main power output port. Specifically, the power supply module uses multiple power units, each operating independently and serving as a backup for the others, ensuring that the server can still maintain power supply in the event of a partial power failure, thus improving system reliability.

[0033] Figure 2 For the power-saving circuit connection diagram of the GPU server provided in this application, please refer to... Figure 2 This application processes one control signal and two power supplies for the power supply unit (power-on control pin PSx_ON#, main power output pin P12V_MAIN, and standby power output pin P12V_STBY). When an external control signal is connected to the power-on control pin, the internal startup circuit of the power supply unit is triggered, causing the power supply unit to switch from standby state to main power + standby power output state. The power-on control pin is directly connected to the power transmission board (PDB). Figure 2 The corresponding control port of the power transmission path module receives power enable commands from the server control system via the PDB. The main power output pin outputs a stable DC main power supply to power the server's high-load functional units. The main power output dynamically adjusts with the server load, and this pin is directly connected to the power input port of the second transmission path. The standby power output pin outputs a stable DC standby power supply to power the server's standby monitoring units (such as the CPLD and basic network modules within the computing unit). This pin is connected to the power input port of the first transmission path.

[0034] Furthermore, it should be noted that the power-saving circuit provided in this application includes at least an energy-saving power-off state and a full power-off state. The energy-saving power-off state refers to a low-power operation mode where the power-saving circuit maintains power supply only for a single necessary functional unit. In this state, the power supply module transmits standby power to one functional unit (used to maintain core functions such as basic system monitoring and CPLD operation) via a first transmission path. The remaining functional units are in a power-off and off-line state because they are not connected to an effective power transmission path. The full power-off state refers to a full-load operation mode where the power-saving circuit provides main power to all functional units. The power supply module synchronously transmits main power to all functional units via a second transmission path; simultaneously, with the help of circuit timing control logic (such as the CPLD's scheduling of the MOS transistor turn-on timing), each functional unit is powered on and started sequentially according to a preset power-on order, collaboratively executing server business functions.

[0035] The multiple functional units typically include at least a computing unit, an accelerator card unit, and a cooling unit. In this application, the power output port of the first transmission path is dedicated to the computing unit, ensuring that the computing unit receives priority power supply in energy-saving power-down mode to maintain the server's basic monitoring and management functions. The power output ports of the second transmission path are connected to the computing unit, the accelerator card unit, and the cooling unit respectively, so that power can be provided to these functional units simultaneously in all power-down states to meet the server's high-load operation requirements.

[0036] Please continue to refer to Figure 2 The first transmission path corresponds to the standby power supply branch in the power transmission path, specifically including the standby power bus, the parallel MOSFET circuit (the switching element of the standby power supply branch), the signal connector connected to the computing unit CPLD, and the power connector. The second transmission path corresponds to the main power supply branch in the power transmission path, specifically including the main power bus, the parallel MOSFET circuit (the switching element of the main power supply branch), the signal connector connected to the computing unit CPLD, and the power connector.

[0037] Circuit connection Figure 1 The side connects the Power Delivery Path (PDB) to multiple CRPS power units, involving two types of interactions: power enable control and power delivery. Specifically, the PSx_ON# pin in the CRPS power connector (where PSx_ON# refers to a series of signals, such as PS0_ON#, PS1_ON#, PS2_ON#, PS3_ON#, PS4_ON#, PS5_ON#) receives the power enable signal (high / low level) output from the PDB, controlling whether the power unit outputs power. When the effective level of PSx_ON# is low, the CPLD drives the signal through the PDB to the power source, and P12V_MAIN is output. When PSx_ON# is high by default, an external pull-up circuit prevents P12V_MAIN from outputting. In addition, P12V_STBY outputs the moment the power line is inserted. The main power bus on the PDB outputs main power, which is then distributed to the server's high-load functional units via the PDB. P12V_MAIN outputs stable power only when PSx_ON# is low; when high, there is no output (or it maintains minimum standby power consumption). The standby power bus on the PDB outputs standby power, which is then distributed to the server's standby monitoring units via the PDB. Regardless of the PSx_ON# level (energy saving / full power supply), P12V_STBY always outputs standby power (ensuring the operation of core monitoring circuits such as the CPLD).

[0038] The other side of the circuit connection diagram shows the connection between the PDB and the computing unit, accelerator card unit, and heat dissipation unit, involving power transmission and control signal interaction. Specifically, the computing unit's power connector connects to the P12V_STBY output port (first transmission path) and the P12V_MAIN output port (second transmission path) on the PDB. In energy-saving power-off mode, it receives P12V_STBY standby power (via the first transmission path) to power the CPLD within the computing unit. In fully powered-off mode, it receives P12V_MAIN main power (via the second transmission path), which, together with P12V_STBY, powers the processor (CPU), network module, etc. Specifically, when the power connector is connected to P12V_STBY (low power), only the monitoring circuits such as the CPLD operate, while the CPU / HDD is powered off. When the power connector is connected to P12V_MAIN (high power), all modules of the computing unit are powered on, performing data processing tasks. The signal connector of the computing unit connects to the control signal port on the PDB (the signal connector in the PDB) to transmit control signals (such as power-on enable and timing instructions) between the CPLD and the PDB. Specifically, when a power-on signal (low level) is sent, the PDB is triggered to output a low level to the PSx_ON# pin, starting the main power transmission of the second transmission path; the CPLD achieves staggered power-on by controlling the different times of the PS_ON# signals output by each power supply.

[0039] In addition, the accelerator card unit and the heat dissipation unit are connected to the main power bus (second transmission path) on the PDB to receive power from the main power supply for GPU computing and fan cooling. Specifically, in response to the CPLD timing signal (transmitted via the signal connector), the power connector of the accelerator card unit is powered on before the heat dissipation unit (or adjusted as needed). When the main power supply is normal (P12V_MAIN has output), the accelerator card unit (which includes multiple accelerator cards to provide large-scale parallel computing capabilities) performs tasks such as graphics rendering and AI training assistance. The fan (the fan in the heat dissipation unit, which is a dedicated heat dissipation component for the accelerator card unit and only serves the heat dissipation needs of the accelerator card unit; while the computing unit, as an independent functional unit, integrates its own dedicated heat dissipation component) starts to dissipate heat. When the main power supply is disconnected (energy-saving state), there is no power input and the module stops operating.

[0040] Figure 3 For the power saving circuit connection diagram of the GPU server provided in this application, please refer to... Figure 3The first transmission path mainly consists of at least two parallel first MOSFETs and a gate voltage divider resistor. Its power input port is connected to the standby power output port of the power supply module, and the power output port of the first transmission path is connected to the target power supply module (in this embodiment, a computing unit). The source of the first MOSFET is connected to the power input port of the first transmission path to receive the standby power signal; the drain of the first transmission path is connected to the power output port to transmit power to the target power supply module. The gate of the first MOSFET is connected to the power input port of the first transmission path through the gate voltage divider resistor. When a standby power signal is input to the power input port of the first transmission path (at a high level), the gate voltage is higher than the source voltage, forming an effective gate-source voltage, causing the first MOSFET to conduct. The standby power signal can then flow from the source through the drain and be successfully transmitted to the target power supply module, providing continuous power. Conversely, when there is no standby power signal at the power input port of the first transmission path (low power or power off), the voltage between the gate and source is lower than the conduction threshold, the first MOSFET is turned off, thereby blocking the transmission of standby power and achieving precise power control.

[0041] The first transmission path refers to a dedicated path in the power-saving circuit used to transmit standby power. It consists of at least two parallel first MOSFETs and gate voltage divider resistors. Its core function is to accurately transmit or block the standby power to the target power supply module based on the level of the control signal. A MOSFET, or Metal-Oxide-Semiconductor Field-Effect Transistor, is a semiconductor device that controls the current flow between its source and drain by the gate voltage. In this circuit, the first MOSFET acts as an electronic switch, and its on / off state is determined by the voltage difference between its gate and source (gate-source voltage, Vgs), used to control the on / off state of the standby power transmission path. The source is the current input terminal of the MOSFET, connected to the power input port of the first transmission path, used to receive the standby power signal output by the power supply module, marking the starting point for the standby power to enter the MOSFET. The drain is the current output terminal of the MOSFET, connected to the power output port of the first transmission path, used to transmit the standby power signal after it has been turned on by the MOSFET to the target power supply module, marking the ending point for the standby power to leave the MOSFET. The gate is the control terminal of the MOSFET, controlling the formation or disappearance of the conductive channel between the source and drain by applying a voltage. Here, the gate is connected to the power input port of the first transmission path via a gate voltage divider resistor, receiving control signals to determine the on or off state of the first MOSFET. The gate voltage divider resistor is a resistive element connected between the power input port of the first transmission path and the gate of the MOSFET. Its function is to stabilize the gate voltage, limit the gate current, prevent malfunctions of the first MOSFET due to fluctuations in the control signal voltage, and ensure the reliability of gate control.

[0042] It should be noted that the power input port of the first transmission path is directly connected to the standby power output of the power supply module, and its voltage level is determined by the operating state of the power supply module itself, without relying on an external control chip. Specifically, when the GPU server is connected to an external power supply, the standby power output port of the power supply module immediately outputs the P12V_STBY standby power signal, which directly acts on the power input port of the first transmission path. At the same time, the gate of the first MOSFET is directly pulled up to P12V_STBY through the gate voltage divider resistor, making the gate voltage and the source voltage (both equal to the standby power supply voltage) basically the same, thus forming a gate-source voltage (Vgs ≥ turn-on threshold) that meets the MOSFET's turn-on threshold. At this time, a conductive channel is formed inside the MOSFET, and the source and drain are connected. The standby power signal can flow from the source through the drain to the target power supply module, achieving continuous power supply.

[0043] When the GPU server disconnects the external power supply or the power supply module stops outputting standby power, there is no P12V_STBY signal input at the power input port of the first transmission path. At this time, the voltage difference between the gate and the source disappears, the internal conductive channel of the MOS transistor disappears, the source and drain are cut off, the standby power transmission path is blocked, and the target power supply module stops receiving standby power.

[0044] Please continue to refer to Figure 3 The second transmission path includes multiple second MOSFETs and control resistors. Its power input port is connected to the main power output of the power supply module, and each power output port is connected to a different functional unit. The sources of the multiple second MOSFETs are all connected to the power input port of the second transmission path to receive the main power signal; their drains are connected to the respective power output ports of the second transmission path, responsible for transmitting the main power to the corresponding multiple target power supply modules. The gates of the multiple second MOSFETs are connected to the main power control signal line through the control resistor. When the main power control signal line is high, the gate voltage is higher than the source voltage, forming an effective gate-source voltage that meets the conduction threshold, turning on the second MOSFETs. The main power signal can then flow from the source through the drain to the corresponding multiple target power supply modules, powering on each functional unit. When the main power control signal line is low, the voltage between the gate and source is lower than the conduction threshold, the second MOSFETs are turned off, blocking the transmission of the main power, thus achieving effective control of the main power.

[0045] It should be noted that the second transmission path refers to a dedicated path in the power saving circuit used to transmit the main power supply. It consists of multiple second MOSFETs and control resistors. Its core function is to synchronously transmit or block the main power supply to multiple functional units based on the level state of the main power control signal line. The control resistor is a resistor element connected between the main power control signal line and the gates of multiple MOSFETs. Its function is to stabilize the gate voltage, limit the gate current, prevent MOSFET malfunctions caused by control signal voltage fluctuations, and ensure the reliability of synchronous control of multiple MOSFETs. The main power control signal line is the electrical signal path for transmitting main power control commands. Its output level (high or low) determines the gate voltage of multiple MOSFETs, thereby synchronously controlling the main power transmission state of the second transmission path. Furthermore, the power input port of the second transmission path receives the main power signal output from the power supply module and is the starting point for the main power supply entering the second transmission path. Each power output port of the second transmission path is the connection interface with each functional unit. Each port corresponds to one functional unit and is used to transmit the main power signal after the MOSFETs are turned on to the target functional unit. This is the ending point for the main power supply leaving the second transmission path.

[0046] Please continue to refer to Figure 3 The computing unit integrates a CPLD (Complex Programmable Logic Device) and multiple signal interfaces connected to the CPLD. These signal interfaces include at least a power-on signal receiver and a power control signal output. The power-on signal receiver receives the external power-on signal and quickly transmits it to the CPLD. The power control signal output is connected to the control port of the power supply module and the gates of the second MOSFETs in the second transmission path, respectively, to output a power-on signal and a motherboard power switch enable signal. The power-on signal controls the power supply module to switch from standby power output to standby power output combined with the main power output, meeting the power requirements of the server under high load. The motherboard power switch enable signal controls the on / off state of the second MOSFETs in the second transmission path, thereby controlling the transmission of main power to each functional unit and ensuring that each functional unit receives power according to a predetermined timing.

[0047] Specifically, the CPLD inside the computing unit acts as the core control hub in the entire power-saving circuit. Its role goes beyond simply forwarding signals; it performs logical judgments and timing processing on the received power-on signals and generates control commands accordingly. The power-on signal is first input to the CPLD through the power-on signal receiver. After analyzing the signal, the CPLD outputs a power-on signal to the control port of the power supply module, controlling the power supply module to switch from standby power output to a combined standby and main power output to meet the power requirements of the GPU server under high load. Simultaneously, it outputs a motherboard power switch enable signal to the second transmission path, controlling the second transmission path to ensure stable main power supply to all functional units. This centralized logic and timing control based on the CPLD effectively achieves peak-shaving power-on, significantly reducing the current surge at power-on. In a GPU server, the accelerator card unit consumes the most power, followed by the computing unit. When the power button is pressed and the server is powered on, the computing units, accelerator card units, and cooling units contain a large amount of capacitive load, causing a sharp increase in the current drawn from the power supply. The instantaneous current can be several times that of normal operation, easily exceeding the capacity limits of the CRPS (Common Redundant Power Supply) and the data center power supply, leading to circuit failures. The CPLD precisely controls the power-on sequence of each functional unit (especially the GPU accelerator card unit) to achieve staggered power-on, effectively reducing the inrush current at startup and alleviating the pressure on all power supply units. Simultaneously, the staggered power-on of all power supply units also helps alleviate the instantaneous pressure on the data center's energy output, stabilizing voltage and protecting the power grid's safety and stability, thus achieving energy savings while ensuring reliable server operation.

[0048] Based on the above description of the energy-saving control circuit, the power transmission in the energy-saving state is as follows: When the GPU server is in the energy-saving state, such as in a soft shutdown state, the server only needs to maintain basic monitoring and management functions. At this time, the power supply module starts working, and its standby power output port outputs a standby power signal. This standby power signal is first transmitted to the power input port of the first transmission path. In the first transmission path, the source of the first MOSFET is connected to the power input port. After receiving the standby power signal, the source potential becomes high. Since the power input port of the first transmission path is also in a high-level state (this is determined by the preset logic of the system in the energy-saving state), the gate of the first MOSFET also obtains a high-level input through the gate voltage divider resistor. At this time, an effective gate-source voltage that meets the conduction threshold is formed between the gate and the source, that is, the gate voltage of the first MOSFET is higher than the source voltage and meets the conduction threshold, so that the first MOSFET is turned on. After being turned on, the first MOSFET outputs the standby power signal from the drain and transmits it to the target power supply module, which in this embodiment is the standby power input terminal of the computing unit. Once the CPLD and related network devices in the computing unit receive standby power, they begin to operate, maintaining the server's basic monitoring, management, and network communication functions. Meanwhile, other functional units such as the accelerator card and cooling unit remain powered down, thus enabling the server to operate at low power in an energy-saving, powered-supply mode.

[0049] It should be noted that the power transmission and server startup process in the fully powered state is as follows: When the user needs to start the GPU server, put it into the fully powered state, and begin normal operation, they first press the server's power button, generating an external power-on signal. This power-on signal is transmitted to the CPLD through the computing unit's power-on signal receiver. As the core control component of the computing unit, the CPLD responds immediately upon receiving the power-on signal. The CPLD sends a power-on signal to the power supply module through its power control signal output terminal. Upon receiving this signal, the power supply module quickly switches the power output mode from standby power-only output to standby power and main power output simultaneously. Simultaneously, the CPLD outputs a motherboard power switch enable signal to the second transmission path through its power control signal output terminal, pulling this signal high. In the second transmission path, the gates of multiple second MOSFETs are connected to the main power control signal line through control resistors. Upon receiving the high-level motherboard power switch enable signal, the gate voltage of each second MOSFET increases. Since the source of the second MOSFET is connected to the power input port of the second transmission path, it has now received the main power signal output from the power supply module, and its source potential is also high. When the gate voltage is higher than the source voltage, and an effective gate-source voltage that meets the turn-on threshold is formed, each MOSFET turns on sequentially according to a preset timing sequence. The main power signal is output from the drain of the turned-on MOSFETs and transmitted to the main power input terminals of each functional unit, such as the computing unit, accelerator card unit, and heat dissipation unit. For example, the main power is transmitted to all functional units simultaneously via a second transmission path. After receiving the main power, each functional unit starts up according to its own initialization process and works together to complete the server business functions.

[0050] After receiving main power, each functional unit starts and initializes according to its own initialization process, working together to bring the GPU server into normal operation and meet the user's performance requirements. Specifically, in the energy-saving power-down state, the computing unit continuously receives standby power through the first transmission path, and its internal core components (such as the CPLD) remain operational. When switching to the fully powered-down state, the second transmission path delivers main power to each functional unit. The second MOSFET connected to the computing unit is turned on, while other functional units are powered on by their internal Efuse chips according to a preset timing sequence. The MOSFET corresponding to the computing unit is turned on 0.5-2 seconds earlier than other functional units (the specific interval can be adjusted through CPLD programming). This design ensures that the computing unit has no power interruption when main power is connected, and the core functions continue to operate during the transition from standby power-only output to standby power and main power output together. This avoids system initialization anomalies or data loss caused by power supply switching, ensuring a smooth transition of the server from low power consumption to high load. In this application, the initial state of the GPU server is the energy-saving power-down state, which is the default operating mode when the server is connected to an external power source but has not received a power-on signal.

[0051] Furthermore, the power-off control logic is as follows: when the GPU server needs to be shut down, the CPLD outputs a low-level motherboard power switch enable signal to the second transmission path through the power control signal output terminal, while simultaneously pulling the PS_ON# signal high, causing the power supply unit to stop the main power output. At this time, the voltage between the gate and source of each MOSFET in the second transmission path is lower than the conduction threshold, the MOSFETs are turned off, blocking the transmission of main power to each functional unit, and each functional unit stops working. With the main power off, the standby power is also cut off. The gate voltage of the MOSFETs in the first transmission path disappears due to the loss of the standby power pull-up, and the MOSFETs are turned off accordingly. This process is completed autonomously by the hardware circuitry, rather than being controlled by the CPLD program. Thus, the power supply to the entire GPU server is completely cut off, and the server enters a shutdown state.

[0052] It should also be noted that when the server detects low-load operation requirements (such as no GPU computing tasks) or a user triggers a hibernation command, the CPLD determines the startup state switching process through internal logic. First, the CPLD outputs a low-level motherboard power switch enable signal to the second transmission path, but only controls the second MOSFETs connected to non-core functional units such as the accelerator card unit and heat dissipation unit to be preferentially turned off (selective shutdown is achieved through preset timing logic), blocking the transmission of main power to these units and causing them to stop working to reduce power consumption; during the shutdown process, all second MOSFETs are synchronously turned off due to the control of the same enable signal. The computing unit and other functional units stop receiving main power, and then the system switches to standby power provided by the first transmission path to maintain its basic monitoring functions. After the non-core functional units are completely powered off, the CPLD outputs a power switching signal to the power supply module, controlling the power supply module to switch from main power output mode to standby power output mode; simultaneously, the motherboard power switch enable signal is kept low, causing the second MOSFETs connected to the computing unit to be turned off, cutting off the transmission of main power to the computing unit. Finally, ensure that the MOSFET in the first transmission path (via hardware circuitry) is turned on, and that standby power is continuously transmitted to the computing unit via the first transmission path, maintaining only the operation of core components such as the CPLD and basic monitoring modules within the computing unit. At this point, the server switches from a fully powered-off state to an energy-saving powered-off state, ensuring basic monitoring and response capabilities while achieving power-off energy saving for non-essential functional units.

[0053] The power-saving circuit provided in this embodiment utilizes the differentiated design of the first and second transmission paths to construct a flexible power distribution mechanism. The first transmission path supplies power to only a single functional unit (such as a computing unit), while the second transmission path supplies power to all functional units simultaneously. Furthermore, the connection ports of the two paths to the power supply module are different, ensuring precise adaptation to energy saving and full-load scenarios. In energy-saving power-off mode, only the first transmission path provides standby power to the core functional unit, while the remaining units are powered off, significantly reducing power consumption during server standby or low load. In full-load power-off mode, the second transmission path synchronously transmits main power to all functional units. Combined with the timing control logic of the CPLD, each unit is powered on in a preset order, avoiding power instability caused by instantaneous high current surges and ensuring reliability during high-load operation. Simultaneously, this circuit does not rely on complex power management chips, achieving precise control only through basic components such as MOSFETs, resistors, and the CPLD. This adapts to the requirement of removing dedicated power management chips in energy-saving mode, reducing hardware costs while balancing energy saving and system stability. Furthermore, through a smooth switching mechanism from energy-saving power supply state to full power supply state and back to energy-saving power supply state, dynamic power management is achieved throughout the server's entire lifecycle. This not only meets the energy-saving requirements under low load but also ensures performance output under high load. It solves the problems of disordered power-on and abrupt state switching in traditional pass-through power supply solutions, further improving the safety and energy efficiency of server operation.

[0054] Example 2

[0055] Corresponding to the aforementioned embodiment of a power-saving circuit for a GPU server, this application also provides an embodiment of a power-saving control method for a GPU server.

[0056] Figure 4 This is a flowchart of Embodiment 2 of the power saving control method for the GPU server provided in this application. Please refer to... Figure 4 The control method provided in this embodiment includes:

[0057] S401. When the GPU server is connected to a power source, the power supply module outputs standby power, which is transmitted to the target power supply module connected to the first transmission path via the first transmission path.

[0058] It should be noted that this step is the initial power supply process after the server is connected to the power supply. The core is to provide standby power to the target power supply module through the first transmission path to maintain basic functions.

[0059] It should be noted that the standby power supply is transmitted to the target power supply module connected to the first transmission path via the first transmission path, including: when the GPU server is connected to an external power supply, the standby power supply output port of the power supply module outputs a standby power supply signal, and the standby power supply signal is transmitted to the power input port of the first transmission path; in response to the output of the standby power supply signal, the source becomes high level; the gate of the first MOSFET becomes high level, and the first MOSFET is turned on; the standby power supply signal is output from the drain of the first MOSFET to the power output port of the first transmission path, and then transmitted to the standby power input terminal of the target power supply module, thereby completing the continuous power supply to the target power supply module.

[0060] Specifically, the power supply module first outputs a standby power signal through its own standby power output port. This signal, as the initial power source, is transmitted to the power input port of the first transmission path, becoming the starting point of the circuit power supply. At this time, the source of the first MOSFET in the first transmission path directly receives this standby power signal, and the source voltage becomes a high level consistent with the standby power supply. Simultaneously, the gate of the first MOSFET also receives a high level (this level must be higher than the source voltage and meet the conduction threshold), creating an effective voltage difference between the gate and the source, thus turning on the first MOSFET. The turned-on MOSFET forms a power transmission path, and the standby power signal flows from the source through the drain, then is output through the power output port of the first transmission path, and finally transmitted to the standby power input terminal of the target power supply module (usually a computing unit). Through this process, the target power supply module obtains continuous standby power, and its internal core components (such as CPLD and basic monitoring circuits) can maintain operation, while other functional units of the server are in a power-off state because they are not connected to power, realizing precise power supply control in energy-saving power supply mode. The standby power signal is first transmitted to the power input port of the first transmission path and directly acts on the source of the first MOSFET.

[0061] It should be noted that the target power supply module (computing unit) receives external power-on signals (such as signals generated by the user pressing the power button) through its power-on signal receiving terminal. After signal shaping, level conversion and other adaptation processing, the signal is transmitted to the control unit (CPLD) inside the computing unit as a trigger command to start the main power transmission.

[0062] S402. In response to an external power-on signal, the control unit in the target power supply module outputs a power-on signal to the power supply module and simultaneously outputs a motherboard power switch enable signal to the second transmission path; the power-on signal controls the power supply module to switch to outputting both main power and standby power, and the motherboard power switch enable signal controls the second transmission path to be turned on.

[0063] It should be noted that this step coordinates power mode switching and transmission path activation through the control unit's output signal. Specifically, after parsing the power-on signal, the control unit within the target power supply module synchronously outputs two types of control signals: a power-on signal and a motherboard power switch enable signal. The power-on signal is transmitted to the control port of the power supply module, triggering the internal power switching circuit to switch from continuously outputting low-power standby power to simultaneously outputting high-power main power in addition to the continuous low-power standby power, thus meeting the full-load operation requirements. The motherboard power switch enable signal is transmitted to the second transmission path, serving as the core of the main power control signal and controlling the conduction state of the MOSFETs in the circuit.

[0064] It should be noted that in this step, the control unit ensures the timing matching of the power supply module switching the main power supply and the second transmission path through logic design (such as first confirming that the main power supply output is stable before triggering the conduction signal), avoiding impact or invalid power supply when the power supply is unstable.

[0065] S403: The main power supply is transmitted to all functional units via the second transmission path, and the GPU server enters the running state.

[0066] It should be noted that the main power supply is transmitted to all functional units via the second transmission path, including: the control unit in the target power supply module adjusts the motherboard power switch enable signal to a high level, the high level signal is transmitted to the gate of multiple second MOSFETs in the second transmission path through the control resistor, and the multiple second MOSFETs are turned on sequentially according to a preset timing sequence; the main power supply signal is output from the drain of each turned second MOSFET to the corresponding power output port of the second transmission path, and is transmitted to the main power input terminal of each functional unit to complete the power-on of each functional unit.

[0067] Specifically, when the control unit within the target power supply module receives a power-on command, it pulls the motherboard power switch enable signal high. This high level is transmitted to the gates of multiple MOSFETs in the second transmission path via control resistors. The high level causes the gate voltage of the MOSFETs to be higher than the source voltage, forming a gate-source voltage difference that satisfies the turn-on threshold, thereby synchronously turning on all MOSFETs. The main power signal is then output from the drain of each MOSFET, transmitted to the main power input of all functional units via the corresponding power output port. The number of MOSFETs is determined by the total load current and the current-carrying capacity of a single MOSFET, and is independent of the number of load units. All MOSFETs are controlled by a common signal, ensuring the synchronization and consistency of the main power distribution.

[0068] The power-saving control method provided in this embodiment, after the server is connected to power, firstly transmits standby power to the target power supply module precisely through the first transmission path, ensuring stable operation of core functional units in energy-saving mode, while powering off other units to reduce standby power consumption. Upon receiving the power-on signal, the control unit synchronously outputs a power-on signal and a motherboard power switch enable signal, realizing a smooth switch from outputting only standby power to simultaneously outputting standby power and main power, as well as synchronous conduction of the second transmission path. During the main power transmission phase, all second MOSFETs are synchronously turned on by a common signal, and the main power is simultaneously transmitted to all functional units. Based on this, high-configuration versions can achieve time-sharing power-on timing control through the Efuse chip inside each functional unit, effectively preventing voltage instability caused by instantaneous high current and ensuring the reliability of high-load startup. The entire control process does not rely on a dedicated power management chip, but only achieves precise power management through the coordinated control of basic circuit logic and CPLD, adapting to the needs of energy-saving mode. While reducing costs, it also takes into account energy-saving effect and system operation stability, ensuring high efficiency and reliability of the server from low-power standby to high-load operation.

[0069] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A power-saving circuit for a GPU server, characterized in that, The power saving circuit includes: The power supply module is used to provide power to the GPU server; A power transmission path is used to transmit the power from the power supply module to the target power supply module; Multiple functional units receive power from the power transmission path, enter a working state, and complete the server functions corresponding to the functional units; the multiple functional units include at least a computing unit, an accelerator card unit, and a heat dissipation unit; The target power supply module is one or more of the plurality of functional units. The power transmission path includes at least a first transmission path and a second transmission path. The first transmission path and the second transmission path are different from the power input port connected to the power supply module. The power output port of the first transmission path is connected to one functional unit, and the power output port of the second transmission path is connected to all functional units simultaneously.

2. The power saving circuit according to claim 1, characterized in that, The power output port of the first transmission path is connected only to the computing unit; The power output ports of the second transmission path are connected to the computing unit, the accelerator card unit, and the heat dissipation unit, respectively.

3. The power saving circuit according to claim 1, characterized in that, The first transmission path includes at least two first MOS transistors connected in parallel, and a gate voltage divider resistor; Wherein, the power input port of the first transmission path is connected to the standby power output port of the power supply module, and the power output port of the first transmission path is connected to the target power supply module; the source of the first MOSFET is connected to the power input port of the first transmission path to receive the standby power signal, and the drain is connected to the power output port of the first transmission path to transmit power to the target power supply module; the gate of the first MOSFET is connected to the power input port of the first transmission path through the gate voltage divider resistor. When a standby power signal is input to the power input port of the first transmission path, the gate voltage is higher than the source voltage, the first MOS transistor is turned on, and the standby power signal flows from the source through the drain to the target power supply module. When there is no standby power signal at the power input port of the first transmission path, the first MOSFET is turned off, blocking the standby power transmission.

4. The power saving circuit according to claim 1, characterized in that, The second transmission path includes multiple second MOSFETs and control resistors; Wherein, the power input port of the second transmission path is connected to the main power output port of the power supply module, and each power output port is connected to the corresponding functional unit; the source of each of the plurality of second MOS transistors is connected to the power input port of the second transmission path to receive the main power signal, and the drain is connected to each power output port of the second transmission path to transmit the main power to the corresponding plurality of target power supply modules; the gate of each of the plurality of second MOS transistors is connected to the main power control signal line through the control resistor. When the main power control signal line is at a high level, the second MOSFET is turned on, and the main power signal flows from the source through the drain to the corresponding multiple target power supply modules. When the main power control signal line is at a low level, the second MOSFET is turned off, blocking the transmission of main power.

5. The power saving circuit according to claim 2, characterized in that, The computing unit internally includes a CPLD and multiple signal interfaces connected to the CPLD; The signal interface includes at least a power-on signal receiving end and a power control signal output end; The power-on signal receiver is used to receive an external power-on signal and transmit the signal to the CPLD; The power control signal output terminal is connected to the control port of the power supply module and the gate of each second MOS transistor in the second transmission path, respectively, and is used to output the power-on signal and the motherboard power switch enable signal; wherein, the power-on signal is used to control the power supply module to switch the output of the main power supply; the motherboard power switch enable signal is used to control the conduction and cutoff of each second MOS transistor in the second transmission path, so as to realize the transmission and cutoff of the main power supply to each functional unit.

6. The power saving circuit according to claim 1, characterized in that, The power saving circuit includes at least an energy-saving power supply state and a full power supply state: In the energy-saving power supply state, there is one target power supply module. The target power supply module monitors the state adjustment signal and switches the power transmission path based on the state adjustment signal. In all power supply states, there are multiple target power supply modules.

7. The power saving circuit according to claim 1, characterized in that, The power saving circuit includes at least an energy-saving power supply state and a full power supply state: In the energy-saving power supply state, the power supply module transmits power to a functional unit through the first transmission path, while the other functional units are in a power-off state. In all power-feeding states, the power supply module transmits power to all functional units simultaneously through the second transmission path. Multiple functional units receive power sequentially according to a preset timing sequence and enter the working state to complete their respective server functions.

8. A power-saving control method for a GPU server, characterized in that, The method is implemented based on the power saving circuit as described in any one of claims 1 to 7, and the method includes: When the GPU server is connected to a power source, the power supply module outputs standby power, which is transmitted to the target power supply module connected to the first transmission path via the first transmission path. In response to an external power-on signal, the control unit in the target power supply module outputs a power-on signal to the power supply module and simultaneously outputs a motherboard power switch enable signal to the second transmission path; the power-on signal controls the power supply module to switch to outputting both main power and standby power, and the motherboard power switch enable signal controls the second transmission path to be turned on. The main power supply is transmitted to all functional units via the second transmission path, and the GPU server enters the running state.

9. The method according to claim 8, characterized in that, The standby power supply is transmitted via a first transmission path to a target power supply module connected to the first transmission path, including: When the GPU server is connected to an external power source, the standby power output port of the power supply module outputs a standby power signal, which is transmitted to the power input port of the first transmission path. In response to the standby power signal output, the source of the first MOSFET becomes high; the gate of the first MOSFET becomes high, and the first MOSFET is turned on. The standby power signal is output from the drain of the first MOSFET to the power output port of the first transmission path, and then transmitted to the standby power input terminal of the target power supply module to complete the continuous power supply to the target power supply module.

10. The method according to claim 8, characterized in that, The main power supply is transmitted to all functional units via a second transmission path, including: The control unit in the target power supply module adjusts the motherboard power switch enable signal to a high level. The high-level signal is transmitted to the gate of multiple second MOS transistors in the second transmission path through the control resistor. The multiple second MOS transistors are turned on sequentially according to a preset timing sequence. The main power signal is output from the drain of each of the second MOSFETs that are turned on to the corresponding power output port of the second transmission path, and then transmitted to the main power input terminal of each functional unit to complete the power-on of each functional unit.

Images