Memory resource processing method and electronic device

Abstract

This invention provides a memory resource processing method and electronic device, applicable to the field of computer technology. The method includes: obtaining initial allocation information for multiple memory nodes according to a user's memory requirement information and a preset allocation rule; obtaining memory allocation information for each of the multiple memory nodes based on the memory requirements of the initial allocation information and reserved memory information; creating corresponding management instances for the memory allocation information, and obtaining available page number information for each of the multiple memory nodes by encoding the identifiers of the multiple memory nodes and their logical page numbers within the management instance; based on the mapping relationship between logical page numbers and physical page numbers, and the available page numbers of each of the multiple memory nodes, converting the physical memory information corresponding to the physical page numbers into the user's virtual address information; and allowing the user to obtain memory resources for a target node through the virtual address information, where the target node is the node corresponding to the user among the multiple memory nodes.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a memory resource processing method and electronic device. Background Technology

[0002] In computer system architecture, Non-Uniform Memory Access (NUMA) architecture is a widely used architecture in multiprocessor systems. The characteristic of NUMA is that the system consists of multiple processor nodes, each containing a local processor core and local memory.

[0003] Currently, in NUMA memory architectures, memory allocation relies on the default memory allocator provided by the operating system kernel. On one hand, because the memory allocator cannot identify the thread's local node when allocating memory, frequent cross-node accesses occur, leading to high latency in memory access. On the other hand, the complex metadata structure and mapping mechanism required for NUMA memory management introduce significant memory and Central Processing Unit (CPU) management overhead, resulting in low memory access efficiency. Summary of the Invention

[0004] In view of the above problems, the present invention provides a memory resource processing method and electronic device that improve memory access efficiency and reduce access latency.

[0005] According to a first aspect of the present invention, a memory resource processing method is provided, comprising: obtaining initial allocation information for multiple memory nodes according to memory demand information from a user and a preset allocation rule, wherein the preset allocation rule includes any one of a preset allocation ratio and a weight-based allocation rule; obtaining memory allocation information for multiple memory nodes according to the memory demand amounts of the initial allocation information and reserved memory information; creating a corresponding management instance for the memory allocation information, and obtaining available page number information for each of the multiple memory nodes by encoding the identifiers of the multiple memory nodes and the logical page numbers of the multiple memory nodes in the management instance; converting the physical memory information corresponding to the physical page number into the user's virtual address information based on the mapping relationship between the logical page number and the physical page number and the available page number of each of the multiple memory nodes, wherein the user obtains the memory resources of a target node through the virtual address information, wherein the target node is the node corresponding to the user among the multiple memory nodes.

[0006] According to a second aspect of the present invention, an electronic device is provided, comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.

[0007] According to embodiments of the present invention, since memory allocation information is obtained by allocating memory demand information through either a preset allocation ratio or a weighted allocation rule during memory resource processing, the allocation of memory demand information among multiple memory nodes can be load-balanced and predictable. By generating available page number information based on memory node identifiers and logical page numbers in the management instance created based on memory allocation information, fine-grained management of memory resources can be achieved. By converting the physical memory information corresponding to the physical page number into the user's virtual address information based on the mapping relationship between logical page numbers and physical page numbers and the available page numbers of each of the multiple memory nodes, the user can obtain memory resources using the mapping mechanism from logical page numbers to virtual addresses. This allows applications to efficiently and with low latency access the memory of the target node through virtual addresses without kernel intervention, achieving the technical effect of improving memory access efficiency and reducing access latency. Attached Figure Description

[0008] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0009] Figure 1 An application scenario diagram of the memory resource processing method according to an embodiment of the present invention is shown.

[0010] Figure 2 A flowchart of a memory resource processing method according to an embodiment of the present invention is shown.

[0011] Figure 3 A schematic diagram of the logical page number encoding rule according to an embodiment of the present invention is shown.

[0012] Figure 4 A schematic diagram illustrating the memory segmentation and management instance mapping according to an embodiment of the present invention is shown.

[0013] Figure 5 A flowchart of a memory resource processing method according to another embodiment of the present invention is shown.

[0014] Figure 6 An architecture diagram of a memory resource processing method according to an embodiment of the present invention is shown.

[0015] Figure 7 A structural block diagram of a memory resource processing apparatus according to an embodiment of the present invention is shown.

[0016] Figure 8 A block diagram of an electronic device suitable for implementing a memory resource processing method according to an embodiment of the present invention is shown. Detailed Implementation

[0017] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0019] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0020] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0021] In computer system architecture, each processor node in a NUMA architecture includes a local processor core and local memory. These nodes are connected via a high-speed interconnect network, forming a unified whole sharing a global address space. In a NUMA architecture, accessing local node memory is significantly faster than accessing remote node memory. This is because remote access involves additional network latency and bandwidth limitations, leading to performance bottlenecks, especially in massively parallel computing, servers, and high-performance computing (HPC) applications. While this architecture aims to improve scalability, it also introduces the challenge of uneven memory access, requiring efficient memory management mechanisms to optimize performance.

[0022] Currently, memory allocation typically relies on the default allocator provided by the operating system kernel. These allocators operate on a global memory pool when allocating physical memory, regardless of the NUMA node location of the requesting thread. Other memory management schemes interleave NUMA memory and partition it according to different functions; for example, a storage system might divide memory into a Page Directory (PD) region, a logical page number region, a data region, and a global region. On the other hand, some schemes employ complex metadata structures and mapping mechanisms (such as physical memory regions divided by NUMA nodes) to manage memory, achieving fine-grained control through kernel-level interfaces. However, these schemes primarily run in kernel mode, with user-space programs accessing memory indirectly through standard APIs (such as memory allocation, malloc), lacking the ability to directly optimize allocation for specific NUMA nodes.

[0023] In some examples, memory configuration information during the system kernel startup process is obtained. Based on this information, a reserved memory range is determined. The reserved memory is then segmented based on the hot-plug framework and the reserved memory range. Corresponding target metadata is allocated to each reserved memory segment. This target metadata is dynamically allocated based on the hot-plug framework, enabling developers to manipulate the reserved memory using standard kernel page operation interfaces while preserving reserved attributes. A target mapping array is established based on the memory configuration information to ensure efficient memory access. This allows for efficient virtual address and physical address translation in user space, maintaining the original isolation characteristics. The target mapping array is used to respond to target memory access requests, completing the corresponding memory access operations and improving memory management efficiency to some extent.

[0024] However, this scheme lacks consideration for NUMA architecture when allocating reserved memory. In NUMA systems, the CPU accesses local memory nodes much faster than remote nodes. If a reserved memory segment happens to be located on a remote NUMA node of the CPU where the process is running, then each access to that reserved memory will incur significant remote access latency. This is fatal for low-latency applications such as high-performance computing, real-time systems, or databases. Furthermore, pre-allocated fixed-size reserved memory blocks may not be fully utilized, leading to internal fragmentation. This locked memory cannot be used by the system's ordinary memory allocator, exacerbating memory shortages, especially in memory-constrained systems.

[0025] In some examples, the firmware's low-level hardware control capabilities are used to determine the physical memory to be reserved in system memory, thus mitigating issues such as operating system memory reclamation and process preemption to some extent. However, the core operations of this approach (such as contiguous partitioning, partition alignment, mapping establishment, and page table generation) are one-time operations completed during system initialization or process startup. This is a static or semi-static mapping. Pre-partitioning large blocks of contiguous memory and establishing complete page tables consumes a significant amount of memory metadata (such as the page tables themselves). In a 64-bit address space, multi-level page tables can become extremely large, failing to efficiently handle dynamic changes in workload. If a process's memory access patterns change, or if some data needs to be migrated to optimize performance, this static mapping cannot be adjusted dynamically and finely, potentially requiring the entire memory region to be remapped, resulting in substantial overhead.

[0026] Overall, current memory allocators lack NUMA topology awareness, resulting in the inability to identify thread-local nodes during memory allocation. This leads to frequent cross-node accesses, significantly increasing memory access latency and reducing overall system performance. Secondly, the interleaved NUMA encoding method does not achieve complete NUMA awareness, and cross-NUMA accesses still occur in user-space usage. Furthermore, fine-grained NUMA memory management requires complex metadata structures and mapping mechanisms, which introduce significant memory and CPU management overhead, reducing efficiency and increasing system resource consumption. Moreover, user-space program interfaces struggle to efficiently and conveniently allocate and access memory on specific NUMA nodes, especially in scenarios requiring large-scale, low-latency operations (such as high-performance computing, large databases, or real-time analytics). Existing API limitations prevent applications from fully leveraging the advantages of the NUMA architecture, restricting performance optimization potential.

[0027] In view of this, embodiments of the present invention address the problem of cross-node remote access latency caused by the lack of NUMA topology awareness in current memory allocators; solve the problem of high management overhead (including memory usage and CPU resource consumption) caused by optimizing complex metadata structures; and overcome the defect that user-space programs cannot efficiently allocate and access memory on specific NUMA nodes, especially in scenarios requiring large-scale low-latency operations (such as high-performance computing and database systems), thereby improving memory access efficiency and reducing memory access latency.

[0028] Figure 1 An application scenario diagram of the memory resource processing method according to an embodiment of the present invention is shown.

[0029] like Figure 1As shown, application scenario 100 according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 serves as a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0030] Users can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages, such as sending memory requirement information or obtaining memory resources from a target node. Various communication client applications can be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, and social media platform software (for example only).

[0031] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with displays and support web browsing, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0032] Server 105 can be a server that provides various services, such as a backend management server that supports websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103 (this is just an example). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0033] It should be noted that the memory resource processing method provided in the embodiments of the present invention can generally be executed by server 105. Correspondingly, the memory resource processing device provided in the embodiments of the present invention can generally be located in server 105. The memory processing method provided in the embodiments of the present invention can also be executed by a server or server cluster that is different from server 105 and capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103, and / or server 105. Correspondingly, the memory processing device provided in the embodiments of the present invention can also be located in a server or server cluster that is different from server 105 and capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103, and / or server 105.

[0034] It should be understood that Figure 1The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0035] The following will be based on Figure 1 The described scene, through Figures 2-6 The memory resource processing method of this invention will be described in detail.

[0036] Figure 2 A flowchart of a memory resource processing method according to an embodiment of the present invention is shown.

[0037] like Figure 2 As shown, the memory resource processing method of this embodiment includes operations S210 to S240.

[0038] In operation S210, based on the memory requirement information from the user, the initial allocation information of multiple memory nodes is obtained according to the preset allocation rules. The preset allocation rules include either a preset allocation ratio or a weight-based allocation rule.

[0039] During operation S220, based on the initial allocation information and reserved memory information, the memory allocation information of each of the multiple memory nodes is obtained.

[0040] In operation S230, for memory allocation information, a corresponding management instance is created, and by encoding the identifiers of multiple memory nodes and the logical page numbers of multiple memory nodes in the management instance, the available page number information of each of the multiple memory nodes is obtained.

[0041] In operation S240, based on the mapping relationship between logical page numbers and physical page numbers and the available page numbers of each of the multiple memory nodes, the physical memory information corresponding to the physical page number is converted into the user's virtual address information. The user obtains the memory resources of the target node through the virtual address information, where the target node is the node corresponding to the user among the multiple memory nodes.

[0042] In some embodiments, the user's memory requirement information may be the information provided by the user program (or process) when requesting memory from the operating system, such as the user needing to request 1GB of memory.

[0043] A memory node can be the basic unit of memory allocation. In the NUMA architecture of a multiprocessor system, each CPU can have its own local memory node that is faster to access. Each CPU can also access the memory nodes of other CPUs, but accessing the memory nodes of other CPUs is slower than accessing its own memory nodes.

[0044] A preset allocation rule can be a rule pre-set by the system to determine the strategy for allocating memory among multiple memory nodes. Preset allocation rules can include either a preset allocation ratio or a weight-based allocation rule. For example, 70% of the memory could be allocated from local nodes and 30% from remote nodes; another example is assigning a node weight to each node and calculating the allocated memory based on that weight.

[0045] The initial allocation information can be the planned initial memory allocation for each memory node, calculated according to preset allocation rules. This initial allocation information needs to be adjusted based on the individual memory requirements of the reserved memory information to obtain the memory allocation information for each of the multiple memory nodes.

[0046] Reserved memory information can be memory reserved by the operating system to limit the memory used by users. For example, it can be unavailable memory that is not provided to users for managing metadata. The memory requirement of each reserved memory information can be the size of this unavailable memory.

[0047] Memory allocation information can be the actual amount of memory that will be allocated to users for each memory node, taking into account reserved memory limits. For example, if the initial allocation information is that node A's allocated memory is x1, and node A's reserved memory requirement is x2, then the memory allocation information for node A is x1-x2.

[0048] To address the memory allocation information for different NUMA nodes, corresponding management instances can be created for the independent reserved memory segments of each NUMA node. In the operating system, when a process requests contiguous memory, the kernel creates a data structure to manage information about this memory region, including memory size, permissions, and mappings to the underlying physical pages. This data structure is a management instance.

[0049] Memory node identifiers distinguish which physical memory originates from which node; for example, each memory node has a unique ID, such as 000. Logical page numbers provide a continuous, linear view of pages for user programs. Within a management instance, a logical page number is the number of each page after paging the contiguous virtual memory allocated to the user. Logical page numbers can start from 0, are consecutive, and represent the page order from the perspective of this management instance. Encoding can transform complex information, such as memory node identifiers and logical page numbers, into a single, compact numerical value using algorithms or rules (such as binary).

[0050] Available page number information can be an encoded value that contains both the memory node to which the page belongs (determined by the memory node's identifier) ​​and the page's logical location in the user's virtual address space (e.g., the logical location within a management instance determined by the logical page number). Available page number information can serve as efficient metadata, allowing for the decoding of crucial information when subsequently looking up physical addresses.

[0051] In some embodiments, page number information such as "0001 1111 1111 1111 1111 1111 11111111" can be used, where the identifier of the memory node can be the high 3 bits "000" and the logical page number can be the low 29 bits "1 111111111 1111 1111 1111 1111 1111 1111".

[0052] A physical page number can be a unique identifier for each fixed-size memory block in physical memory, such as a physical page frame number (PFN). The mapping between logical page numbers and physical page numbers is the core of memory virtualization. When the CPU accesses memory using virtual addresses, the memory management unit uses this mapping to find the corresponding physical address.

[0053] Each node has its own available page number, which can be a data structure within each memory node used to manage and track all free physical pages. This could be the contents of an Available Page Space (APS) or array specific to each node. The physical page number corresponds to the physical memory information, which can be the actual data storage unit within the hardware memory processor—the location where the data is actually stored.

[0054] Virtual address information refers to the addresses used by user programs to access memory. Each process has its own independent virtual address space. The operating system is responsible for translating virtual addresses into physical addresses. User programs can access and perform read and write operations based on virtual addresses without needing to know the underlying physical memory distribution.

[0055] The target node can be a local memory node associated with the CPU where the user program that issued the memory request is currently running, among multiple memory nodes. In a NUMA architecture, accessing the local node is the fastest. Users can obtain the memory resources of the target node through a virtual address and perform read and write operations.

[0056] The memory resource processing method of this invention can be as follows: First, calculate the amount of memory to be reserved on each NUMA segment based on the specified amount of memory to be reserved, and modify the operating system configuration to complete the memory reservation operation. For memory allocation information of different NUMA memory nodes, obtain independent reserved memory segments. Create corresponding management instances for each independent reserved memory segment, and divide each memory segment into 4KB page units and number them to form a global logical page number space. A 32-bit encoding scheme is used to simultaneously identify the logical page number index and the corresponding NUMA; a mapping table between logical page numbers and physical page frame numbers (PFNs) is established as core metadata; an independent one-dimensional array is maintained in user space for each NUMA node to store logical page numbers for convenient memory allocation; when requesting memory, the NUMA memory node where the requesting thread is located is identified, a logical page number is allocated from the corresponding node array, and the array value is set to zero to ensure that the memory strictly comes from the local node; when releasing memory, the high 3 bits of the logical page number are parsed to determine the target NUMA node, the page number is returned to the original index position of the corresponding node array, and the initial value is restored. Cross-node access is eliminated through a localized allocation mechanism, and a lightweight metadata structure significantly reduces management overhead.

[0057] According to embodiments of the present invention, since memory allocation information is obtained by allocating memory demand information through either a preset allocation ratio or a weighted allocation rule during memory resource processing, the allocation of memory demand information among multiple memory nodes can be load-balanced and predictable. By generating available page number information based on memory node identifiers and logical page numbers in the management instance created based on memory allocation information, fine-grained management of memory resources can be achieved. By converting the physical memory information corresponding to the physical page number into the user's virtual address information based on the mapping relationship between logical page numbers and physical page numbers and the available page numbers of each of the multiple memory nodes, the user can obtain memory resources using the mapping mechanism from logical page numbers to virtual addresses. This allows applications to efficiently and with low latency access the memory of the target node through virtual addresses without kernel intervention, achieving the technical effect of improving memory access efficiency and reducing access latency.

[0058] In some embodiments, the process of obtaining initial allocation information in operation S210 may include the following operations: determining the node allocation information of each of the multiple memory nodes according to the memory demand information and the allocation ratio of each of the multiple memory nodes for the memory demand information; when the node allocation information indicates that the available resources of the node are greater than a preset threshold, updating the initial allocation information based on the allocation weight of each of the multiple memory nodes until the available resources of the node are less than or equal to the preset threshold, thereby obtaining the initial allocation information.

[0059] In some embodiments, the node allocation information can be a theoretical allocation scheme calculated based on a preset allocation ratio. For example, the node allocation information of NUMA memory nodes can be calculated based on a specified reserved memory size. This calculation operation can be divided into two stages. The initial segmentation calculation can calculate the theoretical segment size of each NUMA, and this process can be as shown in formula (1).

[0060] (1);

[0061] If there is no preset allocation ratio, the reserved memory can be evenly distributed among each memory node by default.

[0062] The second calculation stage can calculate the maximum memory that can be allocated to a node. The maximum allocatable amount of a node can be shown in formula (2).

[0063] (2);

[0064] Based on the theoretical allocation of nodes determined by formula (1) and the maximum allocatable amount of nodes determined by formula (2), the actual allocation of nodes can be determined, as shown in formula (3).

[0065] (3);

[0066] Calculate the total amount of memory allocated across all nodes in a NUMA architecture and determine if the total allocation meets the specified memory size.

[0067] In cases where the initial allocation is insufficient—that is, when the node allocation information indicates that the available resources of a node exceed a preset threshold—an intelligent reallocation phase can be initiated. This phase involves dynamically adjusting the allocation scheme through multiple iterations to obtain the initial allocation information. The initial allocation information can be an executable preliminary allocation scheme obtained after dynamic weight adjustments.

[0068] For example, traversing all nodes to calculate the available resources of each node (e.g., available space of each node) can be done as shown in formula (4).

[0069] (4);

[0070] The total available space is obtained by summing all available spaces. If the available space of a node is greater than a preset threshold (e.g., 0), the node allocation weight can be calculated using formula (5).

[0071] (5);

[0072] Based on the node allocation weights, the node allocation amount can be calculated using formula (6).

[0073] (6);

[0074] Calculate memory allocation for all nodes until insufficient memory is allocated (returning to zero) or the maximum number of iterations is reached. Memory is aligned to 128MB during each allocation. After completion, provide memory segmentation information for each NUMA node.

[0075] According to an embodiment of the present invention, by using a preset allocation ratio to allocate memory, and when the node allocation information obtained based on the preset allocation ratio indicates that the available resources of the node are greater than a preset threshold, the allocation is performed using weights. This avoids the situation in a NUMA system where some memory nodes are overwhelmed due to a high preset ratio or many local requests, while other nodes are idle. Such a flexible allocation method can make the allocation between each memory node load-balanced and predictable, thereby improving the utilization rate of memory resources.

[0076] In some embodiments, the initial allocation information may include multiple physical addresses corresponding to memory resources. The process of creating a corresponding management instance for the memory allocation information may include the following operations: for the available memory information of a single node among multiple memory nodes, the memory allocation information and reserved memory information of that single node are divided separately to obtain a management instance indicating the division results of the memory allocation information and reserved memory information.

[0077] In some embodiments, before building the management instance, a memory reservation operation can be performed to isolate specified NUMA memory nodes from the operating system. The physical address range of each NUMA memory node is obtained based on the explicit kernel ring buffer (dmesg) message. Starting from the high address of each node (e.g., the end address of the physical address), the node's reserved memory size is subtracted from the high address based on the allocated memory size to obtain the starting address of the node's reserved memory. The memory reservation operation is completed by modifying the operating system's multi-system boot manager (GRand Unified Bootloader, grub) boot menu configuration file.

[0078] In some embodiments, corresponding management instances can be created for the independent reserved memory segments of different NUMA memory nodes, and logical page number spaces can be encoded. That is, by encoding the identifiers of multiple memory nodes and their logical page numbers within the management instances, the available page number information for each of the multiple memory nodes is obtained. This process may include the following operations: determining the identifiers of the multiple memory nodes as the high-order encoded information in the encoding scheme, determining the logical page numbers in the management instances as the low-order encoded information in the encoding scheme, and combining the high-order and low-order encoded information to obtain the available page number information.

[0079] Figure 3 A schematic diagram of the logical page number encoding rule according to an embodiment of the present invention is shown.

[0080] In some embodiments, the reserved memory segment of each NUMA node can be divided into 4KB page units, and the available page number information of the node can be represented using a 32-bit encoding scheme. For example... Figure 3 As shown, the encoding scheme can be implemented based on binary, for example, page number information such as "0001 1111 1111 1111 1111 1111 1111 1111 1111", where the memory node identifier can be the high 3 bits "000" and the logical page number can be the low 29 bits "1 1111 1111 1111 1111 1111 1111 1111 1111 1111".

[0081] According to an embodiment of the present invention, by determining the identifiers of multiple memory nodes as the high-order encoded information in the encoding scheme and determining the logical page number in the management instance as the low-order encoded information in the encoding scheme, the high-order encoded information and the low-order encoded information are combined to obtain the available page number information. This encoding method can quickly parse the memory node identifiers and page indexes through bitmasks and bit shift operations, which not only improves the processing speed but also facilitates its use as core data storage in array structures, thereby improving the processing efficiency of memory resources.

[0082] Figure 4 A schematic diagram illustrating the memory segmentation and management instance mapping according to an embodiment of the present invention is shown.

[0083] like Figure 4 As shown, this mapping architecture can include NUMA 0 memory node 401 and NUMA n memory node 402 located in the NUMA architecture. Both NUMA 0 node 401 and NUMA n node 402 can include available memory and unavailable memory. Kernel mode reflects the state of the operating system's core operation; kernel mode can execute any instruction and access any hardware resource. User mode can receive memory request requests from applications and obtain memory resources from memory nodes in the NUMA architecture through kernel mode. User mode cannot directly access memory nodes in the NUMA architecture. It is understood that the number of NUMA nodes in the NUMA architecture is unlimited; NUMA 0 and NUMA n are used as examples here.

[0084] In some embodiments, the memory segment can be divided into a page table area (PDTABLE) 403, an available page number area (APS) 404, and a general memory area (GENPAGES) 405 according to the memory segment size, and a management instance can be constructed. The page table area 403 and the available page number area 404 serve as management metadata areas and do not provide available memory externally. The general memory area 405 serves as allocable memory. For specific division details, refer to [reference needed]. Figure 4Page table area 403 is used to store the PFN mapping relationship between logical page numbers and corresponding physical pages. Page number area 404 can be used as a mapping during memory allocation to store the logical page number corresponding to the general memory area 405, ensuring the separation of responsibilities of different modules to optimize management efficiency.

[0085] The kernel-mode page table area 403, the available page number area 404, and the general-purpose memory area 405 can be mapped to user mode via the memory mapping (MemoryMap, mmap) system function. Based on the multiple page table areas 403 mapped to user mode, the page table node array (mem_PD[NUMA]) 406 can be obtained, and based on the multiple available page number areas 404 mapped to user mode, the page number node array (mem_APS[NUMA]) 407 can be obtained.

[0086] According to embodiments of the present invention, by dividing memory allocation information and reserved memory information based on the available memory information of a node, a management instance is obtained. This not only ensures that user programs do not occupy the memory reserved for the operating system, but also accurately counts and determines the allocation and release of each type of memory, thereby achieving refined management of memory resources and improving the processing efficiency of memory resources.

[0087] In some embodiments, memory allocation information may include at least one physical address. In this case, the memory resource processing method of this embodiment may include the following operations: at system startup, constructing a mapping relationship between logical page numbers and physical page numbers using a hash table based on the physical address; and obtaining the node available page numbers for each of the multiple nodes based on the status bit information in the mapping relationship that indicates the reference status of the physical page number.

[0088] In some embodiments, a mapping table between logical page numbers and physical page frame numbers (PFNs) can be established as core metadata. Based on the initialized logical page number space, the mapping table is created and stored in the page table area memory. An array or hash table structure is used to record the mapping relationship between each logical page number and the actual physical page frame number (PFN), as well as the status information of the referenced state (e.g., page reference count status). This table is dynamically generated based on the physical address of the physical memory segment at system startup and supports updates during runtime. The mapping table ensures efficient translation from logical page numbers to physical addresses, reduces memory access latency, and serves as the underlying support for APS memory allocation.

[0089] According to embodiments of the present invention, a global and fast memory index is established by constructing a mapping relationship between logical page numbers and physical page numbers using a hash table based on physical addresses at system startup. By obtaining the available page numbers of multiple nodes based on the status bit information indicating the reference status of physical page numbers in the mapping relationship, accurate and dynamic statistics of available resources can be achieved, enabling fine-grained management of memory resources and improving the processing efficiency of memory resources.

[0090] In some embodiments, continue to refer to Figure 4 In the user-mode mapping stage, the available page number area can be mapped as a one-dimensional array, and the array content can be initialized to store the corresponding logical page numbers. Specifically, in kernel mode, node arrays for storing logical page numbers can be constructed for multiple memory nodes, such as page table node arrays and page number node arrays, for user access.

[0091] In some embodiments, an independent one-dimensional array of APS can be maintained for each NUMA node. Based on the system configuration, a dedicated one-dimensional array structure of the free page pool (APS) is created for each individual node in the NUMA environment. This array serves as a user-space accessible data structure, with the index position corresponding to the lower 29 bits of the logical page number and storing the complete 32-bit logical page number value, including the higher 3 bits of the node identifier (ID), ensuring the isolation of the array between nodes and preventing data conflicts.

[0092] According to embodiments of the present invention, by constructing node arrays for storing logical page numbers for multiple memory nodes in kernel mode, memory resource isolation and management can be achieved, preventing memory allocation requests on one node from affecting other nodes. Moreover, during use, the kernel can operate on the array of a single node without traversing a global, potentially very large data structure, thus improving the efficiency of memory management operations.

[0093] In some embodiments, the mapping relationship can be maintained through a page table. Specifically, the process of converting physical memory information corresponding to a physical page number into user virtual address information based on the mapping relationship between logical page numbers and physical page numbers and the available page numbers of each of the multiple memory nodes may include the following operations: determining the target logical page number corresponding to the target physical page number from the page table, and combining it with the initial virtual address information corresponding to the resource request, mapping the target logical page number to the initial virtual address information through a mapping function to obtain the virtual address information, and then deleting the target logical page number from the device page table.

[0094] In some embodiments, the application layer can map available page number regions through the mmap system call. Specifically, the user program calls the mmap system function provided by the operating system at runtime to directly map the reserved available page number region memory into an operable one-dimensional array. The mapping process converts the physical memory region into a user-mode virtual address space, through which the application obtains direct access and can manipulate the array contents without kernel intervention.

[0095] In some embodiments, the array contents can be traversed and initialized to fill logical page number values. Specifically, after the array mapping is complete, an initialization operation can be performed, traversing the array elements one by one according to the logical page numbers, and assigning each position a corresponding complete 32-bit logical page number (consisting of the high 3 bits of the node ID and the low 29 bits of the index). This assignment process ensures that the array contents are consistent with the logical page numbers in the reserved memory, so as to enable efficient access in user space.

[0096] According to embodiments of the present invention, by mapping the target logical page number to the initial virtual address information based on the target logical page number corresponding to the target physical page number, the initial virtual address information corresponding to the resource request, and the mapping function, and deleting the target logical page number from the device page table, resource management can be simplified, unnecessary resource overhead can be avoided, and the speed of memory allocation and the overall efficiency of the system can be improved.

[0097] In some embodiments, the memory resource processing method of this invention may further include a process of being aware of NUMA memory allocation operations. Specifically, when an application requests memory, if no NUMA node is specified, memory will be allocated from the corresponding NUMA instance.

[0098] In some embodiments, a target node corresponding to a resource request may be determined. This target node may be the target node in operation S240, so that the user can access the memory resources of the target node through the target node identifier in the virtual address information.

[0099] In some embodiments, the NUMA node affiliation of the requesting thread can be identified. Specifically, when an application issues a memory allocation request, the NUMA node to which the requesting thread belongs is determined using APIs provided by the operating system (such as the `numa_get_thread_node` function). This identification process ensures that subsequent operations are bound to the local node, avoiding the introduction of cross-node latency.

[0100] In some embodiments, logical page numbers can be allocated from the local node's APS array. Specifically, after determining the NUMA node where the thread resides, one or more logical page numbers are retrieved and allocated from the one-dimensional array of the corresponding node's free page pool (APS). The specific allocation mechanism involves finding an available location in the array, extracting its stored 32-bit logical page number value, setting the value at that location to zero, marking it as allocated, thereby completing the memory page occupancy.

[0101] In some embodiments, logical page number to physical address translation can be performed during memory access operations. Specifically, after allocation, when the application performs actual memory access, an address translation process is required. This process includes passing the acquired logical page number to kernel mode, the system performing the translation using a mapping table (PDTABLE), confirming the required physical page frame, and mapping multiple physical pages to a contiguous virtual address space. This ensures that the application can directly operate in user mode, while the kernel layer efficiently handles mapping details, reducing context switching latency.

[0102] According to embodiments of the present invention, by directing memory allocation requests to the most suitable target NUMA memory node (e.g., a local node) and ensuring that subsequent memory accesses can be accurately located to that node, not only can the memory resource consumption caused by remote memory access be avoided and the latency of memory access be reduced, but also user-mode access is simplified and memory access efficiency is improved.

[0103] In some embodiments, the memory resource processing method of this invention may further include a NUMA-aware memory release operation. Specifically, when releasing memory, the corresponding logical page number is determined, and the logical page number is parsed to release the memory and return to the corresponding NUMA node.

[0104] In some embodiments, based on NUMA-aware memory release operations, the memory resource processing method of this embodiment can also, in response to detecting the completion of memory resource access of the target node, restore the target logical page number corresponding to the memory resource to the page table for subsequent resource allocation.

[0105] In some embodiments, the logical page number can be parsed to determine the target NUMA node. Specifically, when the application releases memory, the provided 32-bit logical page number is first parsed, and the high 3 bits of the node identifier (ID) are extracted to determine the original NUMA node to which the memory should be returned. The parsing operation is based on preset encoding rules to ensure that the node ownership is correct.

[0106] In some embodiments, the target node's APS array can be reclaimed and the page number value restored. Specifically, after identifying the target node, the released logical page number can be reclaimed into the node's one-dimensional array of the free page pool (APS). The reclamation process involves resetting the array to the complete 32-bit logical page number value (i.e., the original storage value) at the corresponding index position based on the lower 29 bits of the logical page number, indicating that the memory page has been returned to the free pool for subsequent allocation.

[0107] Before and after a reclamation operation, index validity can be verified to check whether the target index location is in an operable state (e.g., not incorrectly marked as allocated), preventing data inconsistency caused by erroneous operations. For example, the lower 29 bits can be extracted from the 32-bit logical page number to be released to obtain the index value. The calculated index value can then be checked to see if it is within the predetermined valid range. If it is, the index is valid and the reclamation operation can proceed.

[0108] According to embodiments of the present invention, by performing index validity verification before and after the reclamation operation, once the verification is successful, the system ensures efficient reuse of memory pages, maintains resource integrity through kernel-level reference count updates, and promotes sustainable resource management.

[0109] According to an embodiment of the present invention, in response to the detection that the memory resource access of the target node has been completed, the target logical page number corresponding to the memory resource is restored to the page table for subsequent resource allocation. This not only ensures that the released memory can be quickly and safely re-entered into the resource pool, realizing the immediate reclamation and reuse of memory resources, but also improves the efficiency of the memory allocator, thereby improving memory utilization and overall system performance.

[0110] Figure 5 A flowchart of a memory resource processing method according to another embodiment of the present invention is shown.

[0111] like Figure 5 As shown, another embodiment of the memory resource processing method may include operations S510 to S550.

[0112] When operating the S510, NUMA memory is segmented and reserved.

[0113] When operating S520, create multiple management instances and construct logical page number space encoding logical page numbers.

[0114] In operation S530, establish the mapping between logical page numbers and physical pages.

[0115] When operating S540, the user-mode logical page number management array is constructed.

[0116] When operating the S550, memory allocation and deallocation are handled.

[0117] According to embodiments of the present invention, by dynamically dividing NUMA segment memory according to a specified memory size and isolating memory from the operating system's memory management through reservation operations, the NUMA topology agnostic problem is avoided through a localized allocation mechanism, eliminating cross-node access latency; a 32-bit encoding structure is used to implement unified addressing of the logical page number space and NUMA awareness is achieved through multi-instance management, supporting a maximum of 2T memory per node and an 8-node expansion capability; a one-dimensional array memory allocation design shared by the user space and the kernel driver layer, combined with the mmap mechanism, enables user space access to specified physical pages. User space achieves memory allocation / release without kernel switching by directly reading and writing the APS array, and the allocated physical page PFN is aware according to the logical page number. Through memory remapping, memory mapping is only required during access, which can improve the efficiency of user space memory operations.

[0118] Figure 6 An architecture diagram of a memory resource processing method according to an embodiment of the present invention is shown.

[0119] like Figure 6 As shown, the architecture may include a user-mode memory management module 601, a NUMA segmentation logic calculation module 602, a memory reservation execution module 603, a driver loading module 604, and a kernel driver 605.

[0120] The application can send memory requirement information to the user-mode memory management module 601, which may include a specified memory size. The user-mode memory management module 601 can send the specified memory size to the NUMA segmentation logic calculation module 602, determine memory allocation information according to operations S210-S220, and call the memory reservation execution module 603 to complete the memory reservation operation that meets the requirements and NUMA architecture. The segmentation logic calculation module 602 can pass loading parameters (obtainable from the memory requirement information, such as the kernel driver identifier, runtime dependencies, resource requirements, and other key information) to the driver loading module 604. The memory reservation execution module 603 can send the starting address of the reserved memory block in the physical address space and the length of the reserved memory block to the driver loading model so that the driver loading module 604 can accurately load the memory. After receiving the parameters, the driver loading module 604 performs the loading operation, loading the specified kernel from the kernel driver 605 into the system kernel space. After completing the kernel driver loading, the driver loading module 604 establishes a mapping interaction relationship with the user-mode memory management module 601. The two parties exchange information required for memory mapping. For example, the user-mode memory management module 601 provides the physical address information of the reserved memory, and the driver loading module 604 transmits the kernel driver's access requirements for memory. Finally, the mapping configuration between the kernel driver and the reserved memory is completed, ensuring that the driver can access the target memory normally.

[0121] Based on the above-described memory resource allocation method, this invention also provides a memory resource processing device. The following will be combined with... Figure 7 The device is described in detail.

[0122] Figure 7 A structural block diagram of a memory resource processing apparatus according to an embodiment of the present invention is shown.

[0123] like Figure 7 As shown, the memory resource processing device 700 of this embodiment includes a first allocation module 710, a second allocation module 720, a creation module 730, and a conversion module 740.

[0124] The first allocation module 710 is used to obtain the initial allocation information of multiple memory nodes according to the memory demand information from the user and according to the preset allocation rules. The preset allocation rules include either a preset allocation ratio or a weight-based allocation rule.

[0125] The second allocation module 720 is used to obtain the memory allocation information of each of the multiple memory nodes based on the memory requirements of the initial allocation information and the reserved memory information.

[0126] Module 730 is used to create a corresponding management instance based on memory allocation information, and to obtain the available page number information of each memory node by encoding the identifier of multiple memory nodes and the logical page number of multiple memory nodes in the management instance.

[0127] The conversion module 740 is used to convert the physical memory information corresponding to the physical page number into the user's virtual address information based on the mapping relationship between logical page numbers and physical page numbers and the available page numbers of each of the multiple memory nodes. The user obtains the memory resources of the target node through the virtual address information, where the target node is the node corresponding to the user among the multiple memory nodes.

[0128] In some embodiments, the first allocation module 710 may include a determining unit and an updating unit.

[0129] The "Determine Individual" function is used to determine the node allocation information for each of the multiple memory nodes based on the memory requirement information and the allocation ratio corresponding to the memory requirement information for each of the multiple memory nodes.

[0130] The update unit is used to update the initial allocation information based on the allocation weights of multiple memory nodes when the node allocation information indicates that the available resources of the node are greater than a preset threshold, until the available resources of the node are less than or equal to the preset threshold, thus obtaining the initial allocation information.

[0131] In some embodiments, the creation module 730 may include partitioning units.

[0132] The partitioning unit is used to partition the memory allocation information and reserved memory information of a single node among multiple memory nodes, respectively, to obtain a management instance indicating the partitioning results of the memory allocation information and reserved memory information.

[0133] In some embodiments, the memory resource processing apparatus 700 may further include a first building module and an instruction module.

[0134] The first building module is used to construct a mapping relationship between logical page numbers and physical page numbers based on physical addresses using a hash table when the system starts up.

[0135] The indicator module is used to obtain the available page numbers of multiple nodes based on the status bit information indicating the reference status of physical page numbers in the mapping relationship.

[0136] In some embodiments, the creation module 730 may further include a determining unit.

[0137] The determination unit is used to determine the identifiers of multiple memory nodes as the high-order encoding information in the encoding scheme, determine the logical page number in the management instance as the low-order encoding information in the encoding scheme, and combine the high-order encoding information and the low-order encoding information to obtain the available page number information.

[0138] In some embodiments, the memory resource processing apparatus may further include a second building module.

[0139] The second building module is used to construct node arrays for storing logical page numbers for multiple memory nodes in kernel mode, so that users can access them.

[0140] In some embodiments, the conversion module 740 may include a mapping unit.

[0141] The mapping unit is used to determine the target logical page number corresponding to the target physical page number from the page table, and combine it with the initial virtual address information corresponding to the resource request. Through the mapping function, the target logical page number is mapped to the initial virtual address information to obtain the virtual address information, and the target logical page number is deleted from the device page table.

[0142] In some embodiments, the memory resource processing apparatus 700 may further include a recovery module.

[0143] The recovery module is used to restore the target logical page number corresponding to the memory resource to the page table in response to the detection that the memory resource access of the target node has been completed, so that it can be used for subsequent resource allocation.

[0144] In some embodiments, the memory resource processing apparatus 700 may further include a determination module.

[0145] The determination module is used to determine the target node corresponding to the resource request, so that the user can access the memory resources of the target node through the target node identifier in the virtual address information.

[0146] According to embodiments of the present invention, any plurality of modules among the first allocation module 710, the second allocation module 720, the creation module 730, and the conversion module 740 may be combined into one module, or any one of these modules may be split into multiple modules. Alternatively, at least a portion of the functionality of one or more of these modules may be combined with at least a portion of the functionality of other modules and implemented in one module. According to embodiments of the present invention, at least one of the first allocation module 710, the second allocation module 720, the creation module 730, and the conversion module 740 may be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging circuitry, or implemented in software, hardware, or firmware, or in any one of the three implementation methods, or in a suitable combination of any of them. Alternatively, at least one of the first allocation module 710, the second allocation module 720, the creation module 730, and the conversion module 740 may be implemented at least partially as a computer program module, which can perform corresponding functions when the computer program module is run.

[0147] Figure 8 A block diagram of an electronic device suitable for implementing a memory resource processing method according to an embodiment of the present invention is shown.

[0148] like Figure 8 As shown, an electronic device 800 according to an embodiment of the present invention includes a processor 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage portion 808 into a random access memory (RAM) 803. The processor 801 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor, and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 801 may also include onboard memory for caching purposes. The processor 801 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0149] RAM 803 stores various programs and data required for the operation of electronic device 800. Processor 801, ROM 802, and RAM 803 are interconnected via bus 804. Processor 801 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 802 and / or RAM 803. It should be noted that the programs may also be stored in one or more memories other than ROM 802 and RAM 803. Processor 801 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0150] According to an embodiment of the present invention, the electronic device 800 may further include an input / output (I / O) interface 805, which is also connected to a bus 804. The electronic device 800 may also include one or more of the following components connected to the input / output (I / O) interface 805: an input section 806 including a keyboard, mouse, etc.; an output section 807 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN card, modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the input / output (I / O) interface 805 as needed. A removable medium 811, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 810 as needed so that computer programs read from it can be installed into the storage section 808 as needed.

[0151] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0152] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of the present invention, a computer-readable storage medium may include ROM 802 and / or RAM 803 and / or one or more memories other than ROM 802 and RAM 803 described above.

[0153] Embodiments of the present invention also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the methods provided in the embodiments of the present invention.

[0154] When the computer program is executed by the processor 801, it performs the functions defined in the system / apparatus of this invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0155] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 809, and / or installed from a removable medium 811. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0156] In such an embodiment, the computer program can be downloaded and installed from a network via communication section 809, and / or installed from removable medium 811. When the computer program is executed by processor 801, it performs the functions defined in the system of this embodiment of the invention. According to embodiments of the invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0157] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0158] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0159] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0160] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for processing memory resources, characterized in that, The method includes: Based on the memory requirement information from the user, the initial allocation information of each of the multiple memory nodes is obtained according to the preset allocation rules, wherein the preset allocation rules include either a preset allocation ratio or a weight-based allocation rule; Based on the memory requirements of the initial allocation information and the reserved memory information, the memory allocation information of each of the multiple memory nodes is obtained; For the memory allocation information, a corresponding management instance is created, and by encoding the identifiers of the multiple memory nodes and their logical page numbers within the management instance, the available page number information for each of the multiple memory nodes is obtained, including: The identifiers of the multiple memory nodes are determined as the high-order encoding information in the encoding scheme, and the logical page number in the management instance is determined as the low-order encoding information in the encoding scheme. The high-order encoding information and the low-order encoding information are combined to obtain the available page number information. Based on the mapping relationship between the logical page number and the physical page number, and the available page number of each of the multiple memory nodes, the physical memory information corresponding to the physical page number is converted into the user's virtual address information, including: The target logical page number corresponding to the target physical page number is determined from the page table used to maintain the mapping relationship. Combined with the initial virtual address information corresponding to the resource request, the target logical page number is mapped to the initial virtual address information through a mapping function to obtain the virtual address information. The target logical page number is then deleted from the device page table. The user obtains the memory resources of the target node through the virtual address information, and the target node is the node corresponding to the user among the plurality of memory nodes.

2. The method according to claim 1, characterized in that, Based on the user's memory requirement information, the initial allocation information for multiple memory nodes is obtained according to preset allocation rules, including: Based on the memory requirement information and the allocation ratio of the multiple memory nodes for the memory requirement information, determine the node allocation information for each of the multiple memory nodes; When the node allocation information indicates that the available resources of a node are greater than a preset threshold, the initial allocation information is updated based on the allocation weights of the multiple memory nodes until the available resources of the node are less than or equal to the preset threshold, thus obtaining the initial allocation information.

3. The method according to claim 1, characterized in that, The initial allocation information includes multiple physical addresses corresponding to the memory resources; For the memory allocation information, create a corresponding management instance, including: For the available memory information of a single node among the multiple memory nodes, the memory allocation information and reserved memory information of the single node are divided to obtain a management instance that indicates the division results of the memory allocation information and the reserved memory information.

4. The method according to claim 3, characterized in that, The memory allocation information includes at least one physical address; The method further includes: When the system starts up, a mapping relationship between the logical page number and the physical page number is constructed using a hash table based on the physical address; Based on the status bit information in the mapping relationship that indicates the reference status of the physical page number, the available page numbers of each of the multiple nodes are obtained.

5. The method according to claim 1, characterized in that, The method further includes: In kernel mode, node arrays are constructed for each of the multiple memory nodes to store the logical page numbers, so that the user can access them.

6. The method according to claim 1, characterized in that, The method further includes: In response to the detection that the memory resource access of the target node has been completed, the target logical page number corresponding to the memory resource is restored to the page table for subsequent resource allocation.

7. The method according to claim 1, characterized in that, The method further includes: The target node corresponding to the resource request is determined so that the user can access the memory resources of the target node through the target node identifier in the virtual address information.

8. An electronic device, comprising: One or more processors; Memory, used to store one or more computer programs. The characteristic feature is that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 7.

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