A flash memory error correction method and system based on adaptive learning

Abstract

The application discloses a flash memory error correction method and system based on adaptive learning, relates to the technical field of data storage, and comprises the following steps: collecting flash memory voltage distribution and error code positions in real time, combining with environmental parameters to generate a dynamic feature vector; constructing a hypergraph neural network based on the dynamic feature vector, obtaining error propagation risk scores of each storage area, and generating a priority list; based on the priority list, adjusting the check connectivity of a low-density parity-check matrix by matrix reconstruction to form a sparse check matrix; generating initialization parameters and a solution vector based on a decoder ready state signal, performing sampling iteration and threshold decision, and outputting a decoding result; when decoding fails, performing multi-device parameter update by aggregation optimization, and re-decoding to output final correction data. The application solves the limitation of single-device decoding, optimizes global error correction performance, and enhances fault tolerance by multi-device parameter aggregation optimization collaborative error correction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, and particularly relates to a flash memory error correction method and system based on adaptive learning. BACKGROUND

[0002] Flash memory storage is now one of the important components of non-volatile storage technology, and is mainly applied in the fields of consumer electronics, data centers and embedded systems. Traditional flash memory error correction methods mostly rely on low-density parity-check codes, BCH codes and other error correction coding technologies for error correction, and use fixed check matrices and static decoding strategies to ensure data reliability. Most of the existing technologies currently use offline training and preset threshold methods to optimize error correction performance, such as using threshold adjustment based on statistical voltage distribution and configuring decoding parameters through historical error rates. In addition, some technologies involve using environmental parameters to assist error correction decision-making to improve error correction robustness under complex working conditions.

[0003] However, the existing methods still have deficiencies: for example, the existing error correction technologies mostly use fixed-connection-degree check matrices, which are difficult to adapt to the changes in nonlinear error distribution caused by process fluctuations or aging of flash memory units; and the existing decoding processes mostly rely on local information of a single device, lack a cross-device collaborative optimization mechanism, and when local error correction fails, cannot effectively use global features for error correction enhancement. SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides a flash memory error correction method based on adaptive learning, which solves the problem of insufficient flash memory data reliability under complex working conditions.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a flash memory error correction method based on adaptive learning, which includes: collecting flash memory voltage distribution and error code position in real time, and generating a dynamic feature vector in combination with environmental parameters;

[0008] Constructing a hypergraph neural network based on the dynamic feature vector, and obtaining error propagation risk scores of each storage area to generate a priority list;

[0009] Based on the priority list, adjusting the check connection degree of the low-density parity-check matrix by matrix reconstruction to form a sparse check matrix;

[0010] Dividing the sparse check matrix by partial reconfiguration, adjusting ADC quantization and interference cancellation to generate a signal-to-noise ratio, inputting the decoder in a hardware binding mode and outputting a ready state signal;

[0011] Generate initialization parameters and devector based on decoder ready state signal, perform sampling iteration and threshold decision, and output decoding result;

[0012] When decoding fails, use aggregation optimization to update multi-device parameters, and re-decode to output final correction data.

[0013] As a preferred scheme of the flash memory error correction method based on adaptive learning, the real-time flash memory voltage distribution and error code position are collected, and a dynamic feature vector is generated combined with environmental parameters, and the specific steps are as follows,

[0014] Using voltage scanning, the on-current of the unit is measured by applying scanning voltage step by step, the threshold voltage distribution is recorded, and real-time voltage offset and distribution characteristic data are generated;

[0015] Using bit comparison, the error code position is compared and marked, and the temperature, erase count and voltage fluctuation are collected synchronously, and the error code position distribution map and environmental parameter data set are output;

[0016] Combine real-time voltage offset, distribution characteristic data, error code position distribution map and environmental parameter data set, synthesize and generate dynamic feature vector.

[0017] As a preferred scheme of the flash memory error correction method based on adaptive learning, the real-time flash memory voltage distribution and error code position are collected, and a dynamic feature vector is generated combined with environmental parameters, and the specific steps are as follows,

[0018] Map the dynamic feature vector to a hypergraph node, use K-neighbor method to establish hyperedge connection, and construct a weighted hypergraph combined with hyperedge weight;

[0019] Based on the weighted hypergraph, use double-layer convolution to learn error propagation mode, use attention to strengthen the path, get error propagation risk score and normalize, and generate error propagation risk matrix;

[0020] According to the error propagation risk matrix, use dynamic weighting, top K screening and anomaly detection to form a priority list.

[0021] As a preferred scheme of the flash memory error correction method based on adaptive learning, the real-time flash memory voltage distribution and error code position are collected, and a dynamic feature vector is generated combined with environmental parameters, and the specific steps are as follows,

[0022] Use statistical distribution to divide the storage area and fuse the priority list to the initialized low-density parity check matrix, output the initial check matrix and region marker matrix;

[0023] Based on the initial check matrix, a third-order tensor containing the initial check matrix and the region label is constructed using tensor decomposition to generate a core tensor;

[0024] The initial check matrix is reconstructed according to the core tensor and differential sparse adjustment is implemented to form a sparse check matrix.

[0025] As a preferred scheme of the flash memory error correction method based on adaptive learning, the sparse check matrix is divided by partial reconfiguration, the ADC quantization and interference cancellation are adjusted to generate a signal-to-noise ratio, and the decoder is input in a hardware binding manner and an ready state signal is output.

[0026] The sparse check matrix is divided according to the error propagation risk matrix by partial reconfiguration to generate a sparse check matrix block;

[0027] Based on the sparse check matrix block, the non-uniform comparison level of the ADC is dynamically adjusted in combination with real-time voltage distribution, and the adjacent cell interference cancellation method is used to remove coupled noise to generate a signal-to-noise ratio.

[0028] The sparse check matrix block and the corresponding signal-to-noise ratio are packaged as a data packet, and the engine is directly connected and double-buffered for transmission to output a decoder ready state signal.

[0029] As a preferred scheme of the flash memory error correction method based on adaptive learning, the initialization parameters and the solution vector are generated based on the decoder ready state signal, the sampling iteration and threshold decision are performed, and the decoding result is output.

[0030] An initial solution is randomly generated using a random number generator, a signal-to-noise ratio weight table and a solution vector are output.

[0031] Based on the signal-to-noise ratio weight table and the solution vector, the MH sampling method is used for sampling iteration to form a final sampling solution.

[0032] According to the final sampling solution, the probabilities of each bit are obtained using probability statistics, and threshold decision is implemented to output the decoding result.

[0033] As a preferred scheme of the flash memory error correction method based on adaptive learning, when decoding fails, multi-device parameter updating is performed using aggregation optimization, and the final corrected data is output by re-decoding.

[0034] When decoding fails, based on the current sparse check matrix and real-time flash data, the error distribution characteristics are analyzed, the environment parameters are extracted, and the devices are matched to output a matching device list and environment characteristic parameters.

[0035] Based on matching the device list with the environmental characteristic parameters, a global optimization check matrix and an optimized signal-to-noise ratio are generated by weighted fusion of each device sparse check matrix, and calibration of the signal-to-noise ratio.

[0036] According to the global optimization check matrix and the optimized signal-to-noise ratio, decoding parameters are dynamically configured, enhanced decoding is executed, and data recovery is triggered to form final correction data.

[0037] In a second aspect, the present application provides a flash memory error correction system based on adaptive learning, comprising a data acquisition module, a risk assessment module, a matrix reconstruction module, a hardware configuration module, an iterative decoding module, and an aggregation optimization module,

[0038] The data acquisition module is configured to acquire flash memory voltage distribution and error code positions in real time, and generate a dynamic feature vector in combination with environmental parameters.

[0039] The risk assessment module is configured to construct a hypergraph neural network based on the dynamic feature vector, and obtain error propagation risk scores of each storage area to generate a priority list.

[0040] The matrix reconstruction module is configured to adjust the check connectivity of a low-density parity check matrix based on the priority list to form a sparse check matrix by using matrix reconstruction.

[0041] The hardware configuration module is configured to divide the sparse check matrix by partial reconfiguration, adjust the signal-to-noise ratio generated by ADC quantization and interference cancellation, input the decoder in a hardware binding manner, and output a ready state signal.

[0042] The iterative decoding module is configured to generate initialization parameters and a solution vector based on the decoder ready state signal, perform sampling iteration and threshold decision, and output a decoding result.

[0043] The aggregation optimization module is configured to perform multi-device parameter updating by using aggregation optimization when decoding fails, and output final correction data by re-decoding.

[0044] In a third aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, any step of the flash memory error correction method based on adaptive learning according to the first aspect of the present application is implemented.

[0045] In a fourth aspect, the present application provides a computer readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, any step of the flash memory error correction method based on adaptive learning according to the first aspect of the present application is implemented.

[0046] The application has the beneficial effects that: the application solves the problem of insufficient adaptability of a fixed check matrix, improves the accuracy of error detection, and enhances the adaptability to process fluctuations and aging effects by dynamically constructing a hypergraph neural network to analyze the error propagation characteristics of a flash memory unit in real time; the application solves the limitation of single-device decoding, optimizes global error correction performance, and enhances fault tolerance by optimizing collaborative error correction through multi-device parameter aggregation. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0048] Fig. 1 Flowchart of the flash memory error correction method based on adaptive learning.

[0049] Fig. 2 Schematic diagram of the flash memory error correction system based on adaptive learning.

[0050] Fig. 3 Flowchart of the sparse check matrix generation method.

[0051] Fig. 4 Flowchart of the multi-device aggregation optimization method. DETAILED DESCRIPTION

[0052] In order to make the above-mentioned purposes, features and advantages of the present application more apparent and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0053] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the scope of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0054] Secondly, the "one embodiment" or "embodiment" referred to herein means that the specific features, structures or characteristics can be included in at least one implementation of the present application. "In one embodiment" appearing in different places in the specification does not mean the same embodiment, nor is it an independent or alternative embodiment that excludes other embodiments.

[0055] REFERENCE Figs. 1-4 For one embodiment of the present application, the embodiment provides a flash memory error correction method based on adaptive learning, comprising the following steps:

[0056] S1, real-time collection of flash voltage distribution and error code position, and generation of dynamic feature vector combined with environmental parameters.

[0057] Further, voltage scanning is adopted to measure the conduction current of the unit by applying scanning voltage step by step, record threshold voltage distribution, and generate real-time voltage offset and distribution feature data.

[0058] Specifically, a high-precision digital-to-analog converter is used to generate a scanning voltage sequence, a row decoder is used to select a storage unit, and the scanning voltage is applied to the correct word line to ensure that the scanning voltage is applied to the correct word line. Starting from the initial voltage, it is increased step by step until the termination voltage is reached. After each voltage is stable, a sensitive amplifier is triggered to detect the conduction state of the storage unit to generate voltage-current correspondence data, and the conduction current value of the storage unit corresponding to each scanning voltage point is recorded to form a discrete voltage-current data sequence. Based on the voltage-current data sequence, a transimpedance amplifier is used to collect the conduction current value of the storage unit after each scanning voltage is stable, convert the conduction current value of the storage unit into a measurable voltage signal, and quantize it through a 16-bit analog-to-digital converter. For the same voltage point, multiple measurements are performed, random noise interference is eliminated using a moving average filtering algorithm, the conduction current value corresponding to each voltage point is recorded, and a voltage-current curve is formed.

[0059] Based on the voltage-current curve, the derivative of the voltage-current curve is obtained using the first derivative method, the peak value of the derivative corresponds to the threshold voltage of the storage unit, and the threshold voltage distribution of all storage units is counted to generate a threshold voltage distribution histogram. Based on the threshold voltage distribution histogram, the current threshold voltage distribution is compared with the baseline distribution at the time of factory shipment to obtain the voltage offset of each voltage interval, and the mean, standard deviation, skewness and kurtosis of the threshold voltage distribution are obtained. The moving standard deviation is combined with the slope to analyze the voltage drift, wherein the moving standard deviation captures local concentration drift, reflects the consistency degradation between units, the slope analyzes the global trend drift, reflects the intrinsic property change of the storage material, and the moving standard deviation and the slope are combined to output distribution feature data.

[0060] Bit comparison is used to compare read and write data to mark error code positions and simultaneously collect temperature, erase-write times and voltage fluctuations to output error code position distribution map and environmental parameter data set.

[0061] Specifically, a hardware-level data verification circuit is used to store a copy of the initial data in the controller's cache register group when read and write data is written into the flash unit. After reading the read and write data from the flash unit, it is immediately compared bit by bit with the initial data copy in the cache register group. When the read value and the written value are inconsistent, it is marked as an error code, and the physical address is recorded, and an error code position record table is generated. The current temperature value is read through the digital interface of the temperature sensor, the erase-write times are obtained, and the peak-to-peak fluctuation amplitude of the power supply voltage is sampled to generate an environmental parameter data set.

[0062] Based on the error code position record table, the physical address of the error code is spatially mapped, the physical address is converted into two-dimensional coordinates by linear mapping, and the error code density is obtained by dividing the grid and counting the number of error codes in each grid. The area with error code density exceeding the error code threshold (for example, 5%) is marked as an error code hotspot, and the error code density data is converted into a color gradient by a heat map to output an error code position distribution map.

[0063] It should be noted that the initial data copy refers to the initial data mirror temporarily saved in the controller when writing to the flash memory unit; the color gradient can be set, for example, red represents high density, and blue represents low density.

[0064] The real-time voltage offset, distribution characteristic data, error code position distribution map, and environmental parameter data set are combined, synthesized, and a dynamic feature vector is generated.

[0065] Specifically, based on the real-time voltage offset, distribution characteristic data, error code position distribution map, and environmental parameter data set, a timestamp is added to all data, the median filtering process is performed on the abnormal value, a unified data index is established, and feature extraction is performed.

[0066] Feature extraction includes voltage feature extraction, error code feature extraction, and environmental correlation analysis. The voltage feature extraction is based on real-time voltage offset to analyze the rate of change of voltage offset over time, obtain the global voltage offset trend, fit the voltage distribution curve based on the distribution characteristic data to obtain the peak value, half-width, and tailing characteristics of the distribution curve, and identify abnormal conditions such as multi-peak distribution. The error code feature extraction is spatial distribution analysis and error type statistics. Spatial distribution analysis divides the chip into a grid, obtains the error code density of each grid, and constructs an error code spatial distribution heat map. Error type statistics distinguish error types, spatial correlation of error types, and identify word line and bit line coupling errors. Environmental correlation analysis is based on the number of erase-write times and error rate to draw a curve and identify the durability inflection point for durability analysis.

[0067] Based on feature fusion and optimization, a weight allocation strategy can be set, such as a base weight of 40% for voltage, 35% for error code, and 25% for environment, and dynamic adjustment can be performed. The dynamic adjustment rule can be set, for example, when the temperature is greater than 85°C, the environmental weight is +5%, when the number of erase-write times is greater than 100,000 times, the error code weight is +3%, and when the voltage is abnormal, the voltage weight is +10%. Principal component analysis is used for feature dimension reduction processing, such as retaining 95% of the initial information amount, compressing the features to 10 dimensions, and outputting a dynamic feature vector.

[0068] S2, based on the dynamic feature vector, a hypergraph neural network is constructed, and the error propagation risk score of each storage area is obtained to generate a priority list.

[0069] Further, the dynamic feature vector is mapped to a hypergraph node, a K- nearest neighbor method is used to establish a hyperedge connection, and a weighted hypergraph is constructed by combining the hyperedge weight.

[0070] Specifically, the dynamic feature vector is standardized to eliminate the influence of different dimensions, so that all standardized feature values fall within the interval [0, 1], each storage unit is assigned a unique node, the node attribute is the normalized feature vector, the hypergraph node set is output, and each node corresponds to the standardized feature data of a storage unit; the cosine similarity is used to measure the correlation strength between nodes, reflecting the correlation of storage units in voltage, error code and environment, etc., a distance decay factor is introduced for the physical structure of three-dimensional flash memory to reduce the connection weight of non-adjacent units, a K- nearest neighbor method is used, and each node selects the n neighbors with the highest similarity to form a hyperedge, if the similarity of two nodes exceeds the similarity threshold (for example, 0.7), they are classified into the same hyperedge, and the hyperedge set is output.

[0071] The average similarity of all node pairs in the hyperedge set is obtained as the reference weight of the hyperedge, and is corrected according to the real-time environment, for example, the weight is reduced by 5% at a high temperature of more than 85℃, the Softmax function is used to normalize all hyperedge weights, ensuring that the weight sum is 1, the hypergraph node set, the hyperedge set and the weight are packaged into a unified data structure and a weighted hypergraph is output.

[0072] Based on the weighted hypergraph, a double-layer convolution is used to learn the error propagation pattern, the attention is strengthened on the path, the error propagation risk score is normalized to generate an error propagation risk matrix.

[0073] Specifically, based on the weighted hypergraph, a double-layer convolution is used to learn the error propagation pattern, the first layer convolution is local error feature extraction, the neighbor feature aggregation is used to collect the neighbor node features in all hyperedges of each node, the weighted sum is calculated according to the hyperedge weight to highlight the influence of strongly correlated neighbors, and the aggregation result is processed using the ReLU activation function to extract local error patterns such as voltage drift and adjacent interference, and output the first layer node embedding; based on the first layer node embedding, the indirect neighbor features are aggregated again, a distance decay factor (for example, 0.8) is added to reduce the influence of remote nodes, and complex propagation paths such as word line or bit line coupling are captured to identify potential error propagation chains, and output the second layer node embedding.

[0074] The first layer node embedding and the second layer node embedding are respectively linearly projected into an attention space, and a query vector and a key vector are obtained, a dot product similarity of the query vector and the key vector is extracted, and the dot product similarity is normalized by using Softmax to obtain an attention weight; the attention weight and the second layer node embedding are combined to perform weighted summation to strengthen a path, and an error propagation risk score is output; the first layer node embedding is scaled by Min-Max to a [0, 1] interval, and the error propagation risk score is arranged according to a physical address of a storage unit to generate an error propagation risk matrix.

[0075] According to the error propagation risk matrix, a priority list is formed by using dynamic weighting, top-K screening, and anomaly detection.

[0076] Specifically, according to the error propagation risk matrix, a sum of a risk received by each unit (column summation) and a sum of a risk propagated by each unit (row summation) are obtained, for example, top 5% units with the highest risk received and top 3% units with the highest risk propagated are selected, the two types of units are combined to remove duplicates, and a combined unit set is output; anomaly feature detection, secondary verification, and list correction are performed on the combined unit set, wherein the anomaly feature detection can include voltage distribution analysis on the combined unit set, identification of units with voltage deviation exceeding a normal range such as 3 times, and marking of abnormal points with temperature significantly deviating from surrounding units, the secondary verification can be set to perform accurate voltage scanning on the combined unit set, scanning voltage steps such as 0.05 volts, and confirming real electrical characteristics, and the list correction can be to exclude misjudged normal units and supplement missed high-risk units, and a verified high-risk unit list is output.

[0077] Based on the verified high-risk unit list, a priority classification is performed using a three-level classification, for example, a first priority is set to units with both high risk received and high risk propagated, a second priority is set to units with only a single high-risk feature, and a third priority is set to units with only an environmental parameter anomaly, and a real-time monitoring of unit state changes in the high-risk unit list is performed, a priority order is adjusted according to real-time flash memory data, a ranking list is generated from the top-K screening, high-priority units are marked, and a priority list is output.

[0078] It should be noted that the abnormal points with temperature deviating from surrounding units are marked as follows: for example, taking a target unit as the center, an average temperature of 8 adjacent units in the same storage block is taken, and if the absolute temperature difference is greater than 5°C or the relative deviation is greater than 10%, the unit is marked as an abnormal point; the environmental parameter anomaly can be set to, for example, a unit temperature greater than 85°C, a unit temperature less than -40°C (industrial standard), an erase-write greater than 100,000 times, and a voltage fluctuation greater than 5%; the determination of the high-risk feature is as follows: for example, when the error propagation risk score is greater than or equal to 0.8, it is a high-risk feature, when the error propagation risk score is greater than or equal to 0.6 and less than or equal to 0.8, it is a medium-risk feature, and when the error propagation risk score is less than 0.6, it is a low-risk feature.

[0079] S3, based on the priority list, adjust the check connection degree of the low-density parity check matrix by matrix reconstruction, and form a sparse check matrix.

[0080] Further, the storage area is divided using a statistical distribution, and the priority list is fused into the initialized low-density parity check matrix, and an initial check matrix and a region marking matrix are output.

[0081] Specifically, based on three-level classification, the storage area is divided into first-level priority, second-level priority and third-level priority, a standard low-density parity check matrix is initialized, the check connection degree follows the Poisson distribution, and the connection weight is adjusted according to the priority list, for example, for the first-level priority unit, the check connection density is increased, for the second-level priority, the default connection is maintained, and for the third-level priority unit, the check connection density is reduced, and an initial check matrix is output.

[0082] Based on spatial coding and bitmap compression, the physical address is mapped to a two-dimensional coordinate and a raw bitmap is generated according to the risk classification label, the raw bitmap is compressed using run-length coding, and a check is appended to ensure data integrity, and a region marking matrix is output.

[0083] Based on the initial check matrix, a three-order tensor containing the initial check matrix and the region marking is constructed using tensor decomposition, and a core tensor is generated.

[0084] Specifically, the initial check matrix is received and stored in a compressed row format, the compressed marking data generated by the initial check matrix is received, and a three-dimensional tensor structure is constructed, the tensor structure is built in the first direction corresponding to the check node number, the second direction corresponding to the variable node number, and the third direction setting three feature channels, channel one is the initial value of the check matrix, channel two is the region priority label, and channel three is the density of the surrounding unit, which is obtained by acquiring the proportion of priority units within the range; based on the tensor structure, feature fusion calculation is performed, for each tensor position, the value of the corresponding position of the check matrix is taken, the priority label is read, and the proportion of high priority units in the 3x3 region centered on the target node is obtained, and an initial tensor is generated; according to the initial tensor, a three-order tensor decomposition method is used to decompose the initial tensor into a tensor and three direction feature matrices, and parameter setting is performed, including retaining the features of the check node direction, retaining the features of the variable node direction, and retaining all initial features in the feature channel direction, and multiple rounds of calculation are performed through the alternating direction optimization algorithm, and when the difference between the results of two consecutive calculations is less than, for example, one ten-thousandth, the iteration is stopped, the check node feature matrix, the variable node feature matrix and the feature channel matrix are retained, and the core tensor is output.

[0085] According to the core tensor, the initial check matrix is reconstructed and differential sparse adjustment is implemented, and a sparse check matrix is formed.

[0086] Specifically, the Tucker reconstruction algorithm is adopted, the check node feature matrix, the variable node feature matrix and the feature channel matrix are multiplied by the modal product, the tensor product operation is performed, the core tensor is mapped back to the original dimension from the low-dimensional feature space, the check node feature matrix, the variable node feature matrix and the feature channel matrix are weighted and summed, and the reconstructed full connection check matrix is generated; according to the reconstructed full connection check matrix, the dynamic threshold sparsification based on the priority list is used, the first priority area, the second priority area and the third priority area are located by combining the region marking matrix, for each check node, the structured pruning is performed according to the priority weight threshold, and the random discard can be used for sparsification verification to check whether the number of non-zero elements in each row meets the target, such as the deviation connection degree of ±1 connection degree, and the sparse check matrix is output.

[0087] For example, the first priority area can be set to retain the check connection degree greater than or equal to 6 and set the weight threshold to 0.8 (retaining 80% strong connection), the second priority area retains the connection degree greater than or equal to 4 and sets the weight threshold to 0.6, and the third priority area retains the connection degree less than or equal to 2 and sets the weight threshold to 0.3.

[0088] It should be noted that the weight threshold is set by fitting historical bit error rate data to determine the optimal connection degree under different risk levels, for example, when the connection degree of the first area is increased to 6, the error correction success rate is increased the most; the weak connection edge is the weight < weight threshold, wherein the weight is directly obtained from the full connection matrix after tensor reconstruction and is constrained to the [0, 1] interval through normalization, and is dynamically corrected by environmental parameters (temperature and number of erasing times, etc.).

[0089] S4, divide the sparse check matrix by partial reconfiguration, adjust the ADC quantization and interference cancellation to generate a signal-to-noise ratio, input the decoder in a hardware binding mode and output a ready state signal.

[0090] Further, the sparse check matrix is divided according to the error propagation risk matrix by using partial reconfiguration to generate a sparse check matrix block.

[0091] Specifically, the physical address of the error propagation risk matrix is aligned with the node number of the sparse check matrix using a space encoder, each non-zero element in the sparse check matrix is associated to the corresponding error propagation risk score according to the region marker matrix, the check nodes are sorted in descending order of the error propagation risk score to generate a sorting list, and the aligned risk check association table is output; using a greedy algorithm and hardware constraints, the sparse check matrix is divided into independently configurable blocks, such as preferentially assigning check nodes with an error propagation risk score ≥ 0.8 to the same block, reducing the block size (such as 4x4) under high load, and expanding the block size (such as 16x16) under low load, wherein the hardware constraints are to ensure that the number of check nodes in each block does not exceed the upper limit of the capacity of the storage controller configurable region, and the divided sparse check matrix block list is output.

[0092] It should be noted that the load state determination method is to capture the decoding queue depth, decoding delay and hardware resource occupation rate in real time by directly reading the performance monitoring register built-in the storage controller, and to classify by using the threshold method, wherein the high load satisfies any one, such as decoding queue depth ≥ 5 indicating too many backlog tasks, average decoding delay > 50μs exceeding the real-time requirement, and hardware resource occupation rate ≥ 80% approaching the upper limit of computing power; the low load needs to satisfy all, such as decoding queue depth ≤ 2, average decoding delay ≤ 20μs, and hardware resource occupation rate < 50%.

[0093] Based on the sparse check matrix block, in combination with the real-time voltage distribution, the non-uniform comparison level of the ADC is dynamically adjusted, and the adjacent cell interference cancellation method is used to remove the coupled noise to generate the signal-to-noise ratio.

[0094] Specifically, the real-time threshold voltage distribution data is obtained by voltage scanning, the voltage measurement values of the adjacent cells around the current read cell are read, the initial set values of the ADC such as 4 reference comparison levels are read through the controller register, and the adjacent cell interference compensation coefficients are obtained through the factory calibration data; the distribution of the current voltage measurement value is obtained through the threshold voltage distribution histogram, the voltage interval with the most concentrated cell quantity is identified, finer level division (narrower interval) is set in the dense interval, and the level interval is appropriately relaxed in the sparse interval, and it is ensured that the adjusted level value meets the minimum interval requirement of the hardware, and the updated 4 non-uniform comparison level values are output; the voltage measurement values of the adjacent cells such as 4 adjacent cells around the current target cell are obtained, the interference amount of each adjacent cell is obtained using the obtained adjacent cell interference compensation coefficients, and the interference components are deducted from the current read voltage to output the corrected voltage value after interference compensation; based on the corrected voltage value, the deviation of each cell corrected voltage from the ideal level is obtained, the signal-to-noise ratio is obtained according to the ratio of the average deviation value to the ideal level interval, and the signal-to-noise ratio is normalized to generate the signal-to-noise ratio representing the current signal quality.

[0095] It should be noted that the voltage distribution histogram is established when real-time voltage scanning data is acquired, wherein the dense interval is a continuous voltage range in the voltage distribution histogram, for example, a unit quantity more than 1.5 times the average density; the sparse interval is a continuous voltage range in the voltage distribution histogram, for example, a unit quantity less than 0.7 times the average density; and the ideal level refers to an optimal reference voltage value corresponding to each storage state in a theoretical working state of the flash memory unit, including a voltage demarcation point distinguishing different storage states, a reference judgment threshold ensuring reading reliability, and a theoretical optimal value in the case of no noise and interference.

[0096] The sparse check matrix block and the corresponding signal-to-noise ratio are packaged as a data packet, and an engine direct connection and double buffering are used for transmission, and a decoder ready state signal is output.

[0097] Specifically, bit field mapping is used for field division, data compression, and integrity protection, wherein the field division is, for example, bit 0-31 for sparse check matrix block data, bit 32-47 for signal-to-noise ratio value, and bit 48-63 for control field, including priority and time stamp; the data compression is run-length encoding compression for sparse check matrix data, and if the compression fails, a backup scheme is enabled, such as discarding the lowest 2-bit precision; and the integrity protection is to obtain a cyclic redundancy check code and add a time stamp, and output a standardized data packet.

[0098] According to the standardized data packet, a zero-wait transmission mechanism based on ping-pong buffering is used, when buffer A is transmitting, new data packets are written to buffer B, the transmission completion signal triggers the role exchange between buffer A and buffer B, timing control is performed, and a timeout mechanism is set, when a cyclic redundancy check error is detected, the previous valid data packet is resent, continuous errors trigger an interrupt request, and a transmission state signal is output; based on the transmission state signal, when the current data packet cyclic redundancy check passes, the decoder feedback signal is available, and the transmission state is complete, the ready condition monitoring is completed; when all conditions are met, the ready signal is pulled high, and the start address of the data packet is synchronously sent to the decoder for signal generation; when the ready signal is not responded after being sent, a timeout retry is triggered, and continuous timeouts enter an error mode, and a decoder ready state signal is output.

[0099] S5, based on the decoder ready state signal, initialization parameters and solution vectors are generated, sampling iteration and threshold decision are performed, and a decoding result is output.

[0100] Further, a random number generator is used to randomly generate an initial solution, and a signal-to-noise ratio weight table and a solution vector are output.

[0101] Specifically, a hybrid random number generation is adopted to generate a random number, and random noise of the flash memory cell itself is used as a true random number seed to enhance unpredictability; seed initialization is performed based on the true random number seed, a true random number is collected from a physical noise source (such as threshold voltage fluctuation) of the flash memory chip to generate a random seed, the random seed is input into a pseudo-random number generator to initialize an internal state, so that the random number has unpredictability; according to a code length of a current storage page, initial values of bit positions are generated one by one, the pseudo-random number generator is called to generate a random number, and a probability is dynamically adjusted in combination with a signal-to-noise ratio of a current bit position, which can be set to be initialized to a correct value if the signal-to-noise ratio of the bit position is high, or to be kept completely random if the signal-to-noise ratio of the bit position is low, and an output solution vector and a signal-to-noise ratio weight table are output.

[0102] It should be noted that the bit position signal-to-noise ratio determination is based on stability of a voltage comparison window during flash memory cell reading, and is directly determined by an ADC quantization result. When the bit position signal-to-noise ratio is high, for example, the voltage value stably falls in the same quantization interval during multiple readings, the ADC comparator output waveform is clean, the rising or falling edge jitter is < 5 ns, and the voltage difference between adjacent interference cells is > 200 mV. When the bit position signal-to-noise ratio is low, for example, the voltage value jumps between multiple quantization intervals, the ADC output has burr or ringing phenomenon, and the voltage difference between adjacent cells is < 50 mV, which is easily affected by coupling interference.

[0103] Based on the signal-to-noise ratio weight table and the solution vector, MH sampling method is used for sampling iteration to form a final sampling solution.

[0104] Specifically, based on the solution vector and the signal-to-noise ratio weight table, a bit position is randomly selected from a low signal-to-noise ratio area to flip the value to generate a new candidate solution; in combination with the new candidate solution and the sparse check matrix, a parity check sum of the candidate solution and the sparse check matrix is obtained and the error number is counted, and the smaller the value is, the better the solution is; if the candidate solution error number is less than or equal to the current solution error number, the candidate solution is directly accepted, and if the candidate solution error number is greater than the current solution error number, the candidate solution is accepted with a probability. When the low acceptance rate (such as < 20%) is low, the search range is expanded, and when the high acceptance rate (such as > 50%) is high, the search range is reduced to only flip the highest signal-to-noise ratio bit, and a termination condition is set. The termination condition can be set as success and timeout, wherein the success is to output the solution immediately when there is no error number, and the current optimal solution is output when the maximum iteration number is reached, to generate the final sampling solution.

[0105] It should be noted that the probability acceptance expression is:

[0106] :

[0107] Among them, represents the acceptance probability, , is the difference between the candidate solution error number and the current solution error number, , denotes a temperature parameter, which can be set as an initial value halved every 10 iterations, is a shorthand for the natural exponential function, denoting an exponential operation with base the natural constant.

[0108] According to the final sampling solution, the probability of each bit is obtained using probability statistics, and threshold decision is implemented to output the decoding result.

[0109] Specifically, according to the final sampling solution, the number of times each bit is 1 is counted, for example, by traversing all candidate solutions, and the probability value of the candidate solution being 1 is obtained, and a probability vector is output. The signal-to-noise ratio is set to determine the threshold value and dynamic compensation. Based on the decision threshold and the probability vector, the decision threshold and the probability vector are compared bit by bit. When the probability vector is greater than or equal to the decision threshold, it is determined to be successful, and when the probability vector is less than the decision threshold, it is determined to be failed, and the decoding result is output.

[0110] It should be noted that the signal-to-noise ratio is classified: for example, 0.7≤signal-to-noise ratio≤1.0 is a high-level signal-to-noise ratio, 0.4≤signal-to-noise ratio<0.7 is a medium-level signal-to-noise ratio, and 0≤signal-to-noise ratio<0.4 is a low-level signal-to-noise ratio; the decision threshold: for example, high-level signal-to-noise ratio 0.5, medium-level signal-to-noise ratio 0.6, and low-level signal-to-noise ratio 0.7; dynamic compensation: for example, temperature>85℃ all decision thresholds+0.05, erase>100,000 times all decision thresholds+0.03,

[0111] S6, when the decoding fails, multi-device parameter update is performed using aggregation optimization, and the final correction data is output by re-decoding.

[0112] Further, when the decoding fails, based on the current sparse check matrix and the real-time flash data, the error code distribution characteristics are analyzed, the environmental parameters are extracted, and the devices are matched, and the matching device list and the environmental characteristic parameters are output.

[0113] Specifically, when the decoding fails, spatial distribution detection and error type determination are performed, wherein the spatial distribution detection is to scan the physical location coordinates of the current error code points, identify whether there are clustered distribution of error code hot spot areas, and detect whether there is regular distribution in the row and column directions; the error type determination is to distinguish whether the error is random, identify the coupling interference characteristics between adjacent cells, and mark the error code mode with propagation risk, and the error code characteristic report is output in combination with the spatial distribution detection and the error type determination; the flash chip temperature reading is collected in real time, the erase times of the current storage block are read, and the power supply voltage fluctuation is read, and the degradation degree is evaluated, including evaluating the loss degree caused by the erase times and analyzing the noise interference brought by the voltage fluctuation, etc. Form an environmental state vector to generate environmental characteristic parameters.

[0114] According to the physical location, find the surrounding same type device, screen the candidate device with normal working state and perform similarity comparison, including comparing the similarity of error code distribution characteristics and comparing the matching situation of environmental parameters, and arranging the similarity from large to small, and outputting the matching device list.

[0115] Based on the matching device list and the environmental characteristic parameters, the sparse check matrix of each device is weighted and fused, and the signal-to-noise ratio is calibrated to generate a global optimization check matrix and an optimized signal-to-noise ratio.

[0116] Specifically, the devices in the matching device list (such as the first three devices) are obtained, the sparse check matrix corresponding to each device is read, and the historical error code rate recorded by each device is extracted. The reciprocal of the error code rate of each device is taken as the initial weight, the weight sum is obtained, and the weight is normalized. For each element position of the sparse check matrix, the sparse check matrix value of the corresponding position of each device is taken, the weighted average value is obtained, and the fusion is completed by traversing all sparse check matrix elements to generate a global optimization check matrix. The signal-to-noise ratio data of the matching device is obtained, and the current environmental temperature value is read. The three signal-to-noise ratio values are sorted, and the middle value is taken as the reference signal-to-noise ratio. The current temperature interval is determined, for example, when the current temperature is greater than 85℃, the signal-to-noise ratio decreases by 5%, when the current temperature is less than -40℃, the signal-to-noise ratio decreases by 10%, and when -40℃≤current temperature≤85℃, it remains unchanged, and an optimized signal-to-noise ratio is generated.

[0117] According to the global optimization check matrix and the optimized signal-to-noise ratio, the decoding parameters are dynamically configured, the enhanced decoding is executed, and the data recovery is triggered to form the final correction data.

[0118] Specifically, according to the global optimization check matrix, the optimized signal-to-noise ratio, and the working state of the current flash memory chip (such as temperature and erase times), the initial decoding iteration number is set according to the signal-to-noise ratio quality, and adjusted according to the temperature condition, for example, an additional 5 iterations are added in a high temperature environment greater than 85℃, and an additional 3 iterations are added in a low temperature environment less than -40℃. According to the complexity of the global optimization check matrix, the resource allocation is balanced, and a configuration parameter package containing iteration number, resource allocation and other information is generated.

[0119] Based on the configuration parameter package for decoding, the read value is directly used for high-level signal-to-noise ratio data bits, and special marks are made for low signal-to-noise ratio data bits and initial decoding probability distribution is established. The check node processing and variable node updating are performed according to the configured iteration number, and the decoding progress is dynamically monitored. When there is no improvement for a plurality of times in succession, the decoding is terminated in advance, and the maximum iteration number is forced to terminate, and the preliminary decoding data is generated. Based on the preliminary decoding data, the integrity of the decoding data is checked, the proportion of error data is counted, and the error distribution characteristics are analyzed. A small amount of error recovery and a large amount of error recovery recovery strategy are used. The small amount of error recovery is repaired using backup check bits and repaired by referring to adjacent data. The large amount of error recovery is recovered by calling a deep recovery algorithm, enabling a backup storage block, and outputting final correction data. The complexity of the global optimization check matrix is obtained by the connection degree distribution, short loop detection, and row-column weight ratio.

[0120] It should be noted that the initial decoding iteration number is set according to the signal-to-noise ratio quality. For example, a high-level signal-to-noise ratio is set to a small iteration number, such as 15-20 times, a medium-level signal-to-noise ratio is set to a medium iteration number, such as 20-25 times, and a low-level signal-to-noise ratio is set to a large iteration number, such as 25-30 times.

[0121] The embodiment also provides a flash memory error correction system based on adaptive learning, comprising: a data acquisition module for real-time acquisition of flash memory voltage distribution and error code position, and generation of a dynamic feature vector in combination with environmental parameters; a risk assessment module for constructing a hypergraph neural network based on the dynamic feature vector, and obtaining an error propagation risk score of each storage area to generate a priority list; a matrix reconstruction module for adjusting the check connection degree of the low-density parity check matrix based on the priority list to form a sparse check matrix; a signal adaptation module for dividing the sparse check matrix by partial reconfiguration, adjusting the ADC quantization and interference cancellation to generate a signal-to-noise ratio, and inputting the decoder in a hardware binding manner and outputting a ready state signal; an iterative decoding module for generating initialization parameters and a solution vector based on the decoder ready state signal, performing sampling iteration and threshold decision, and outputting a decoding result; and an aggregation optimization module for performing multi-device parameter updating using aggregation optimization when decoding fails, and re-decoding to output final correction data.

[0122] The embodiment also provides a computer device suitable for the flash memory error correction method based on adaptive learning, comprising: a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute the computer executable instructions to realize the flash memory error correction method based on adaptive learning as proposed in the above embodiment.

[0123] The computer device can be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected by a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is configured to perform wired or wireless communication with an external terminal. The wireless communication can be achieved by WIFI, an operator network, NFC (Near Field Communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0124] The embodiment also provides a storage medium having a computer program stored thereon, the program being executed by a processor to implement the flash memory error correction method based on adaptive learning proposed in the above embodiment. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic storage, a flash memory, a magnetic disk or an optical disk.

[0125] To sum up, the application dynamically constructs a hypergraph neural network, analyzes the error propagation characteristics of the flash memory unit in real time, solves the problem of insufficient adaptability of the fixed check matrix, improves the accuracy of error detection, and enhances the adaptability to process fluctuations and aging effects. Through multi-device parameter aggregation optimization collaborative error correction, the limitation of single device decoding is solved, the global error correction performance is optimized, and the fault tolerance is enhanced.

[0126] It should be noted that the above examples are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application is described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or equivalently replaced, without departing from the spirit and scope of the technical solutions of the present application, which should be covered in the scope of the claims of the present application.

Claims

1. A method for flash memory error correction based on adaptive learning, the method comprising: The application relates to a flash memory error correction method and device. Real-time flash voltage distribution and error code position are collected, and dynamic feature vectors are generated in combination with environmental parameters; A hypergraph neural network is constructed based on the dynamic feature vectors, and error propagation risk scores of each storage area are obtained to generate a priority list; The dynamic feature vectors are mapped to hypergraph nodes, a K-nearest neighbor method is used to establish hyperedge connections, and a weighted hypergraph is constructed in combination with hyperedge weights; Based on the weighted hypergraph, a double-layer convolution is used to learn error propagation patterns, attention is used to strengthen the path, error propagation risk scores are normalized, and an error propagation risk matrix is generated; According to the error propagation risk matrix, dynamic weighting, K-item screening and anomaly detection are used to form a priority list; Based on the priority list, the check connectivity of the low-density parity check matrix is adjusted by matrix reconstruction to form a sparse check matrix; The sparse check matrix is divided by partial reconfiguration, the signal-to-noise ratio is generated by adjusting ADC quantization and interference elimination, the decoder is input in a hardware binding mode, and a ready state signal is output; Based on the decoder ready state signal, initialization parameters and solution vectors are generated, sampling iteration and threshold decision are performed, and a decoding result is output; When decoding fails, multi-device parameter updating is performed by using aggregation optimization, and final correction data is output by re-decoding; When decoding fails, based on the current sparse check matrix and real-time flash data, error code distribution characteristics are analyzed, environmental parameters are extracted, and devices are matched, and a matching device list and environmental characteristic parameters are output; Based on the matching device list and environmental characteristic parameters, the sparse check matrices of the devices are weighted and fused, and the signal-to-noise ratio is calibrated to generate a global optimization check matrix and an optimized signal-to-noise ratio; According to the global optimization check matrix and the optimized signal-to-noise ratio, decoding parameters are dynamically configured, enhanced decoding is executed, and data recovery is triggered to form final correction data.

2. The adaptive learning based flash memory error correction method of claim 1, wherein: The real-time flash voltage distribution and error code position are collected, and dynamic feature vectors are generated in combination with environmental parameters, and the specific steps are as follows, Voltage scanning is adopted, the on-current of a unit is measured by applying a scanning voltage step by step, the threshold voltage distribution is recorded, and real-time voltage offset and distribution characteristic data are generated; Bit comparison is used to compare read and write data, mark error code positions, and simultaneously collect temperature, erasing times and voltage fluctuation, output error code position distribution map and environmental parameter data set; Real-time voltage offset, distribution characteristic data, error code position distribution map and environmental parameter data set are synthesized to generate dynamic feature vectors.

3. The adaptive learning based flash memory error correction method of claim 2, wherein: Based on the priority list, the check connectivity of the low-density parity check matrix is adjusted by matrix reconstruction to form a sparse check matrix, and the specific steps are as follows, Statistical distribution is used to divide the storage area and fuse the priority list to the initialized low-density parity check matrix, and an initial check matrix and a region marker matrix are output; Based on the initial check matrix, a three-order tensor is constructed by using tensor decomposition to generate a core tensor; The initial check matrix is reconstructed according to the core tensor and differential sparse adjustment is implemented to form a sparse check matrix.

4. The adaptive learning based flash memory error correction method of claim 3, wherein: The sparse check matrix is divided by partial reconfiguration, the signal-to-noise ratio is generated by adjusting ADC quantization and interference elimination, the decoder is input in a hardware binding mode, and a ready state signal is output, and the specific steps are as follows, The sparse check matrix is divided according to an error propagation risk matrix by using partial reconfiguration to generate a sparse check matrix block; Based on the sparse check matrix block, the non-uniform comparison level of the ADC is dynamically adjusted in combination with the real-time voltage distribution, and the adjacent cell interference cancellation method is used to remove the coupled noise to generate a signal-to-noise ratio; The sparse check matrix block and the corresponding signal-to-noise ratio are packaged as a data packet, and the engine is directly connected and double-buffered for transmission, and a decoder ready state signal is output.

5. The adaptive learning based flash memory error correction method of claim 4, wherein: The initialization parameters and the solution vector are generated based on the decoder ready state signal, the sampling iteration and the threshold decision are performed, and the decoding result is output, and the specific steps are as follows, An initial solution is randomly generated using a random number generator, and a signal-to-noise ratio weight table and a solution vector are output; Based on the signal-to-noise ratio weight table and the solution vector, the MH sampling method is used for sampling iteration to form a final sampling solution; According to the final sampling solution, the probability of each bit is obtained using probability statistics, and threshold decision is implemented to output the decoding result.

6. An adaptive learning based flash memory error correction system based on the adaptive learning based flash memory error correction method of any one of claims 1-5. It comprises a data acquisition module, a risk assessment module, a matrix reconstruction module, a hardware configuration module, an iterative decoding module, and an aggregation optimization module. The data acquisition module is used for real-time acquisition of flash memory voltage distribution and error code position, and a dynamic feature vector is generated in combination with environmental parameters; The risk assessment module is used for constructing a hypergraph neural network based on the dynamic feature vector, and obtaining the error propagation risk score of each storage area to generate a priority list; The matrix reconstruction module is used for adjusting the check connectivity of the low-density parity check matrix based on the priority list to form a sparse check matrix; The signal adaptation module is used for dividing the sparse check matrix by partial reconfiguration, adjusting the ADC quantization and interference cancellation to generate a signal-to-noise ratio, and inputting the decoder in a hardware binding manner and outputting a ready state signal; The iterative decoding module is used for generating initialization parameters and solution vectors based on the decoder ready state signal, performing sampling iteration and threshold decision, and outputting a decoding result; The aggregation optimization module is used for performing multi-device parameter update by aggregation optimization when decoding fails, and outputting the final corrected data by re-decoding. 7.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is characterized in that: The processor executes the computer program to realize the steps of the flash memory error correction method based on adaptive learning according to any one of claims 1-5.

8. A computer readable storage medium having stored thereon a computer program, characterized in that: The computer program is executed by the processor to realize the steps of the flash memory error correction method based on adaptive learning according to any one of claims 1-5.

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