A bus interconnection system, a signal processing method, a server

Abstract

The application provides a bus interconnection system, a signal processing method and a server, and relates to the technical field of computers. In the bus interconnection system, an interconnection topology is formed between a processor and peripheral devices and between the peripheral devices, and communication connections can be established between the processor and the peripheral devices and between the peripheral devices. On the premise, a channel aggregation module can be used to expand the ports of a bus switch, and the number of peripheral devices that can be accessed by the bus switch can be effectively expanded. In this way, multiple bus switches can be connected to each other to form the above interconnection topology, the interconnection topology can be simplified, the system complexity can be reduced, and the port utilization rate of the bus switch can be improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a bus interconnection system, a signal processing method, and a server. Background Technology

[0002] To facilitate flexible communication between the processor and peripheral devices, and between peripheral devices themselves, multiple bus switches can be used to form an interconnect topology, ensuring that communication connections can be established between the processor and peripheral devices, and between all peripheral devices.

[0003] In related technologies, in order to meet the access requirements of a large number of peripheral devices, multiple bus switches need to be interconnected to form the above-mentioned interconnection topology. However, this increases the complexity of the system on the one hand, and is not conducive to improving the port utilization of the bus switch on the other hand. Summary of the Invention

[0004] This invention provides a bus interconnection system, a signal processing method, and a server, which can use a channel aggregation module to expand the ports of a bus switch, thereby improving the utilization of bus switch ports and simplifying the interconnection topology.

[0005] To solve the above-mentioned technical problems, the present invention provides a bus interconnection system, including a first bus switch, a second bus switch, a first channel aggregation module, and a second channel aggregation module. The interconnection port of the first bus switch is connected to the interconnection port of the second bus switch, the first port of the first bus switch is connected to the first channel aggregation module, and the second port of the second bus switch is connected to the second channel aggregation module.

[0006] The third port of the first bus switch is connected to the first processor, the fourth port of the second bus switch is connected to the second processor, the fifth port of the first channel aggregation module is connected to the first peripheral device, the first channel aggregation module includes at least two fifth ports, and the sixth port of the second channel aggregation module is connected to the second peripheral device, the second channel aggregation module includes at least two sixth ports.

[0007] The first channel aggregation module is configured to map the first port to at least two fifth ports, decompose the data signal sent from the first port to the corresponding fifth ports, and aggregate the data signal sent from the fifth ports to the first port;

[0008] The second channel aggregation module is configured to map the second port to at least two sixth ports, decompose the data signals sent from the second port to the corresponding sixth ports, and aggregate the data signals sent from the sixth ports to the second port.

[0009] The present invention also provides a signal processing method applied to a bus interconnection system. The bus interconnection system includes a first bus switch, a second bus switch, a first channel aggregation module, and a second channel aggregation module. The interconnection port of the first bus switch is connected to the interconnection port of the second bus switch. The first port of the first bus switch is connected to the first channel aggregation module, and the second port of the second bus switch is connected to the second channel aggregation module.

[0010] The third port of the first bus switch is connected to the first processor, the fourth port of the second bus switch is connected to the second processor, the fifth port of the first channel aggregation module is connected to the first peripheral device, the first channel aggregation module includes at least two fifth ports, and the sixth port of the second channel aggregation module is connected to the second peripheral device, the second channel aggregation module includes at least two sixth ports.

[0011] The methods include:

[0012] The first channel aggregation module maps the first port to at least two fifth ports, decomposes the data signal sent from the first port to the corresponding fifth ports, and aggregates the data signal sent from the fifth ports to the first port;

[0013] The second channel aggregation module maps the second port to at least two sixth ports, decomposes the data signals sent from the second port to the corresponding sixth ports, and aggregates the data signals sent from the sixth ports to the second port.

[0014] The present invention also provides a server, comprising: a first processor, a second processor, a first peripheral device, a second peripheral device, and the aforementioned bus interconnection system, wherein the bus interconnection system is connected to the first processor, the second processor, the first peripheral device, and the second peripheral device.

[0015] The beneficial effects of this invention are as follows: The bus interconnection system provided by this invention may include a first bus switch, a second bus switch, a first channel aggregation module, and a second channel aggregation module. The interconnection port of the first bus switch is connected to the interconnection port of the second bus switch. The first port of the first bus switch is connected to the first channel aggregation module, and the second port of the second bus switch is connected to the second channel aggregation module. The third port of the first bus switch is connected to the first processor, the fourth port of the second bus switch is connected to the second processor, the fifth port of the first channel aggregation module is connected to the first peripheral device, and the first channel aggregation module includes at least two fifth ports. The sixth port of the second channel aggregation module is connected to the second peripheral device, and the second channel aggregation module includes at least two sixth ports. This ensures that an interconnection topology is formed between the processor and the peripheral devices, and between each peripheral device, ensuring that communication connections can be established between the processor and the peripheral devices, and between each peripheral device. More importantly, the first channel aggregation module can be configured to map the first port to at least two fifth ports, decompose the data signal sent from the first port to the corresponding fifth ports, and aggregate the data signal sent from the fifth ports to the first port; and the second channel aggregation module can be configured to map the second port to at least two sixth ports, decompose the data signal sent from the second port to the corresponding sixth ports, and aggregate the data signal sent from the sixth ports to the second port. That is, the first channel aggregation module can expand the first port of the first bus switch to at least two fifth ports, and the second channel aggregation module can expand the second port of the second bus switch to at least two sixth ports, effectively expanding the number of peripheral devices that the bus switch can connect to. This avoids interconnecting multiple bus switches to form the aforementioned interconnect topology, simplifies the interconnect topology, reduces system complexity, and improves the port utilization of the bus switch.

[0016] The present invention also provides a signal processing method and a server, which have the above-mentioned beneficial effects. Attached Figure Description

[0017] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the interconnection topology provided for related technologies;

[0019] Figure 2 This is a structural block diagram of a first type of bus interconnection system provided in an embodiment of the present invention;

[0020] Figure 3 This is a structural block diagram of a second bus interconnection system provided in an embodiment of the present invention;

[0021] Figure 4 This is a structural block diagram of a channel aggregation module provided in an embodiment of the present invention;

[0022] Figure 5 A structural block diagram of a processing module provided in an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of another channel aggregation module provided in an embodiment of the present invention;

[0024] Figure 7 A comparative schematic diagram of a channel aggregation module form provided in an embodiment of the present invention;

[0025] Figure 8 A comparative schematic diagram of another channel aggregation module form provided in an embodiment of the present invention;

[0026] Figure 9 A flowchart of a signal processing method provided in an embodiment of the present invention;

[0027] Figure 10 This is a schematic diagram of a single motherboard provided in an embodiment of the present invention;

[0028] Figure 11 This is a schematic diagram of motherboard interconnection provided in an embodiment of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0030] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0031] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] To facilitate flexible communication between the processor and peripheral devices, and between peripheral devices themselves, multiple bus switches can be used to form an interconnect topology, ensuring that communication connections can be established between the processor and peripheral devices, and between all peripheral devices.

[0033] In related technologies, to accommodate the access of a large number of peripheral devices, multiple bus switches need to be interconnected to form the aforementioned interconnect topology. Please refer to... Figure 1 , Figure 1 This diagram illustrates the interconnect topology provided for related technologies. In current 16-GPU models, four 144-pin bus switches (such as PCIe 5.0 switches) can be interconnected in pairs to form an interconnect topology. Any two bus switches are connected via a single bus channel (such as PCIe 5.0 x16). In this topology, each bus switch requires three bus ports (such as x16 ports) for interconnection. After deducting the uplink ports for interconnecting the processor and the downlink ports for expanding network cards, each bus switch has only four bus ports available for mounting peripheral devices (such as graphics cards). A total of 16 GPUs can be mounted on four bus switches.

[0034] Clearly, in the above interconnection topology, the interconnection paths are complex because bus switches need to be interconnected to meet interconnection requirements. Firmware and software layers require extensive path planning for data access, which is detrimental to efficient communication between the processor and peripheral devices, and between peripheral devices themselves. Furthermore, the port utilization of a single bus switch is low, and the number of peripheral devices that can be connected is also limited.

[0035] In view of this, in order to address the technical problem of how to simplify the interconnect topology and improve the utilization of bus switch ports, the present invention provides a bus interconnect system that can use a channel aggregation module to expand the ports of the bus switch, effectively expanding the number of peripheral devices that can be connected to the bus switch and simplifying the interconnect topology.

[0036] The bus interconnection system provided in this embodiment is described below. Please refer to... Figure 2 , Figure 2 This is a structural block diagram of a first bus interconnection system provided in an embodiment of the present invention. The bus interconnection system may include: a first bus switch 1, a second bus switch 2, a first channel aggregation module 3, and a second channel aggregation module 4. The interconnection port 9 (fabric port) of the first bus switch is connected to the interconnection port 9 of the second bus switch. The first port 11 of the first bus switch 1 is connected to the first channel aggregation module 3, and the second port 21 of the second bus switch 2 is connected to the second channel aggregation module 4.

[0037] In this configuration, the third port 12 of the first bus switch 1 is connected to the first processor 5, and the fourth port 22 of the second bus switch 2 is connected to the second processor 6. The fifth port 31 of the first channel aggregation module 3 is connected to the first peripheral device 7, and the first channel aggregation module 3 includes at least two fifth ports 31. The sixth port 41 of the second channel aggregation module 4 is connected to the second peripheral device 8, and the second channel aggregation module 4 includes at least two sixth ports 41.

[0038] It should be noted that, in the above description, the connections between the first bus switch 1, the second bus switch 2, the first channel aggregation module 3, the second channel aggregation module 4, the first processor 5, the second processor 6, the first peripheral device 7, and the second peripheral device 8 are implemented by a bus, such as a PCIe bus. This embodiment does not limit the bus protocol and the number of channels of the PCIe bus between the above devices; please refer to the description in the subsequent embodiments.

[0039] It should also be noted that this embodiment does not limit the specific types of the first peripheral device 7 and the second peripheral device 8. They can be set according to the actual application type. For example, they can be network card devices, graphics card devices, etc., which are connected to the processor via a bus.

[0040] The following describes the uses of the first channel aggregation module and the second channel aggregation module:

[0041] The first channel aggregation module 3 is configured to map the first port 11 to at least two fifth ports 31, decompose the data signal sent from the first port 11 to the corresponding fifth ports 31, and aggregate the data signal sent from the fifth ports 31 to the first port 11;

[0042] The second channel aggregation module 4 is configured to map the second port 21 to at least two sixth ports 41, decompose the data signals sent from the second port 21 to the corresponding sixth ports 41, and aggregate the data signals sent from the sixth ports 41 to the second port 21.

[0043] In this embodiment, the first channel aggregation module 3 and the second channel aggregation module 4 are used to expand the ports of the first bus switch 1 and the second bus switch 2, respectively, to ensure that the first bus switch 1 and the second bus switch 2 can connect to more peripheral devices. Taking the first channel aggregation module 3 as an example, it can map the first port 11 to at least two fifth ports 31, and can decompose the data signal sent by the first port 11 to the corresponding fifth ports 31, and aggregate the data signal sent by the fifth ports 31 to the first port 11. In this way, at least one more first peripheral device 7 can be connected to a single port of the first bus switch 1, and in bus communication, the first channel aggregation module 3 can be responsible for the decomposition and aggregation of signals, which can effectively increase the number of peripheral devices that can be connected to a single port of the bus switch, and thus effectively increase the number of peripheral devices that can be connected to a single bus switch. In this way, this embodiment can avoid interconnecting multiple bus switches to form the above-mentioned interconnection topology while ensuring the number of peripheral devices that can be connected, which can simplify the interconnection topology, reduce system complexity, and improve the port utilization of the bus switch.

[0044] In another implementation, please refer to Figure 3 , Figure 3 This is a structural block diagram of a second type of bus interconnection system provided in an embodiment of the present invention. The first port 11 includes at least two first sub-ports 111, and the second port 21 includes at least two second sub-ports 211. The first sub-ports 111 correspond to the fifth port 31, and the second sub-ports 211 correspond to the sixth port 41.

[0045] The first channel aggregation module 3 can also be configured to map the first sub-port 111 to the fifth port 31, decompose the data signal sent by the first sub-port 111 to the fifth port 31, and aggregate the data signal sent by the fifth port 31 to the first sub-port 111.

[0046] The second channel aggregation module 4 can also be configured to map the second sub-port 211 to the sixth port 41, decompose the data signal sent by the second sub-port 211 to the sixth port 41, and aggregate the data signal sent by the sixth port 41 to the second sub-port 211.

[0047] In this embodiment, taking the first channel aggregation module 3 as an example, it can expand the first port 11 by splitting the first port 11 into at least two first sub-ports 111 and mapping each first sub-port 111 to each fifth port 31. For example, when the first port 11 is a PCIe x16 port, the first channel aggregation module can split the PCIe x16 port into two PCIe x8 ports and map these two PCIe x8 ports to two fifth ports 31. The second channel aggregation module works similarly.

[0048] In another implementation, the number of channels in the first channel of the first sub-port 111 is less than the number of channels in the fifth channel of the fifth port 31, and the number of channels in the second channel of the second sub-port 211 is less than the number of channels in the sixth channel of the sixth port 41. The first, second, fifth, and sixth channels are not shown.

[0049] The first channel aggregation module 3 can also be configured to decompose the data signals sent by each first channel in the first sub-port 111 to each fifth channel in the fifth port 31, and to aggregate the data signals sent by each fifth channel in the fifth port 31 to each first channel in the first sub-port 111.

[0050] The second channel aggregation module 4 can also be configured to decompose the data signals sent by each second channel in the second sub-port 211 to each sixth channel in the sixth port 41, and to aggregate the data signals sent by each sixth channel in the sixth port 41 to each second channel in the second sub-port 211.

[0051] In this embodiment, the number of first channels in the first sub-port 111 can be less than the number of fifth channels in the fifth port 31, and the number of second channels in the second sub-port 211 can be less than the number of sixth channels in the sixth port 41. The first channel aggregation module 3 and the second channel aggregation module 4 are responsible for the decomposition and aggregation of channel signals between the ports. The purpose of this arrangement is to further match the number of channels of the split sub-ports with the number of channels of the peripheral device ports. For example, when the first port 11 is a PCIe x16 port (x16 means the number of channels is 16), and the device port of the first peripheral device 7 is also a PCIe x16, after the first channel aggregation module 3 splits the first port 11 into two PCIe x8 first sub-ports 111, it needs to map these two first sub-ports to the fifth port 31 of PCIe x16, and perform decomposition and aggregation of each channel data signal between the first sub-port 111 and the fifth port 31. Only in this way can it be ensured that the extended ports match the peripheral device ports and that the peripheral devices can communicate smoothly within the bus interconnection system.

[0052] In another implementation, the bandwidth of the first channel is greater than the bandwidth of the fifth channel, and the maximum total bandwidth of the first sub-port 111 is equal to the maximum total bandwidth of the fifth port 31.

[0053] The bandwidth of the second channel is greater than that of the sixth channel, and the maximum total bandwidth of the second sub-port 211 is equal to the maximum total bandwidth of the sixth port 41.

[0054] Furthermore, the first bus switch and the first channel aggregation module use the first version of the bus protocol, the second bus switch and the second channel aggregation module use the first version of the bus protocol, the first channel aggregation module and the first peripheral device use the second version of the bus protocol, and the second channel aggregation module and the second peripheral device use the second version of the bus protocol. The version number of the first version is greater than the version number of the second version.

[0055] Taking the first channel aggregation module 3 as an example, in addition to port expansion and channel expansion, it can also achieve bandwidth matching between the first sub-port 111 and the fifth port 31. For example, when the first port 11 is a PCIe 6.0 x16 port and the peripheral device port of the first peripheral device 7 is a PCIe 5.0 x16 port, since the bidirectional bandwidth of PCIe 6.0 x16 is approximately 256GB / s, the bidirectional bandwidth of PCIe 6.0 x8 is approximately 128GB / s, and the bidirectional bandwidth of PCIe 5.0 x16 is approximately 128GB / s, when the first port 11 is split into two first sub-ports 111 and mapped to the fifth port 31, it can be ensured that the maximum total bandwidth of the first sub-port 111 matches the maximum total bandwidth of the fifth port 31. At the same time, since the bandwidth of the first channel of the first sub-port 111 is greater than the bandwidth of the fifth channel of the fifth port 31, the first channel aggregation module 3 will be responsible for decomposing and aggregating data signals between the first channel and the fifth channel to ensure rate matching between each first channel and each fifth channel. This ensures that the port bandwidth of the bus switch and the port bandwidth of the peripheral devices are fully utilized, thereby guaranteeing the communication efficiency within the bus interconnect system.

[0056] In another implementation, to ensure high-speed communication between the processor and peripheral devices, and between peripheral devices themselves, the first bus switch 1 and the second bus switch 2 are connected via at least two sets of interconnect ports 9. It is worth noting that, since the number of peripheral devices that can be connected to both the first and second bus switches has increased, they can free up additional ports for interconnection while maintaining the same total number of peripheral devices, thereby ensuring the overall communication efficiency of the system.

[0057] In another implementation, the first bus switch 1 is connected to the first processor 5 through at least two third ports 12, and the second bus switch 2 is connected to the second processor 6 through at least two fourth ports 22, thereby ensuring the communication efficiency between the processor and each peripheral device.

[0058] In another implementation, the seventh port of the first bus switch 1 is connected to the third peripheral device, and the eighth port of the second bus switch 2 is connected to the fourth peripheral device, so as to ensure the communication efficiency of special peripheral devices (such as network card devices).

[0059] Based on the above embodiments, the bus interconnection system provided by the present invention may include a first bus switch, a second bus switch, a first channel aggregation module, and a second channel aggregation module. The interconnection port of the first bus switch is connected to the interconnection port of the second bus switch. The first port of the first bus switch is connected to the first channel aggregation module, and the second port of the second bus switch is connected to the second channel aggregation module. The third port of the first bus switch is connected to the first processor, the fourth port of the second bus switch is connected to the second processor, the fifth port of the first channel aggregation module is connected to the first peripheral device, and the first channel aggregation module includes at least two fifth ports. The sixth port of the second channel aggregation module is connected to the second peripheral device, and the second channel aggregation module includes at least two sixth ports. This ensures that an interconnection topology is formed between the processor and the peripheral device, and between each peripheral device, ensuring that communication connections can be established between the processor and the peripheral device, and between each peripheral device. More importantly, the first channel aggregation module can be configured to map the first port to at least two fifth ports, decompose the data signal sent from the first port to the corresponding fifth ports, and aggregate the data signal sent from the fifth ports to the first port; and the second channel aggregation module can be configured to map the second port to at least two sixth ports, decompose the data signal sent from the second port to the corresponding sixth ports, and aggregate the data signal sent from the sixth ports to the second port. That is, the first channel aggregation module can expand the first port of the first bus switch to at least two fifth ports, and the second channel aggregation module can expand the second port of the second bus switch to at least two sixth ports, effectively expanding the number of peripheral devices that the bus switch can connect to. This avoids interconnecting multiple bus switches to form the aforementioned interconnect topology, simplifies the interconnect topology, reduces system complexity, and improves the port utilization of the bus switch.

[0060] Based on the above embodiments, the following describes two implementation forms of the first channel aggregation module 3 and the second channel aggregation module 4.

[0061] In one possible scenario, both the first channel aggregation module and the second channel aggregation module may include:

[0062] A first serializer-deserializer, a processing module, and a second serializer-deserializer are connected together;

[0063] The first serializer-deserializer is connected to either the first sub-port 111 or the second sub-port 211, and the second serializer-deserializer is connected to either the fifth port 31 or the sixth port 41. The specific uses of the first serializer-deserializer, the processing module, and the second serializer-deserializer are as follows:

[0064] The first serializer-deserializer is configured to perform serial-deserialization processing on the data signals of each first channel in the first sub-port 111; or is configured to perform serial-deserialization processing on the data signals of each second channel in the second sub-port 211.

[0065] The processing module is configured to, according to a preset data mapping relationship between each first channel of the first sub-port 111 and each fifth channel of the fifth port 31, perform rate conversion and decompose the data signals transmitted by each first channel of the first sub-port 111 to each fifth channel of the fifth port 31, and perform rate conversion and aggregate the data signals transmitted by each fifth channel of the fifth port 31 to each first channel of the first sub-port 111; or is configured to, according to a preset data mapping relationship between each second channel of the second sub-port 211 and each sixth channel of the sixth port 41, perform rate conversion and decompose the data signals transmitted by each second channel of the second sub-port 211 to each sixth channel of the sixth port 41, and perform rate conversion and aggregate the data signals transmitted by each sixth channel of the sixth port 41 to each second channel of the second sub-port 211.

[0066] The second serializer-deserializer is configured to perform serial-deserial processing on the data signals of each fifth channel in the fifth port 31; or to perform serial-deserial processing on the data signals of each sixth channel in the sixth port 41.

[0067] Please refer to Figure 4 , Figure 4This is a structural block diagram of a channel aggregation module provided in an embodiment of the present invention. The following description uses a first channel aggregation module as an example. The first channel aggregation module 3 includes a first serializer-deserializer 32, a processing module 33, and a second serializer-deserializer 34. The first serializer-deserializer 32 is connected to the first sub-port 111 and is responsible for providing serial processing and deserialization processing of data signals for the first sub-port 111. The second serializer-deserializer 34 is connected to the fifth port 31 and is responsible for providing serial processing and deserialization processing of data signals for the fifth port 31. The processing module 33 is the core module of the first channel aggregation module 3. Based on a preset data mapping relationship between each first channel of the first sub-port 111 and each fifth channel of the fifth port 31, it performs rate conversion on the data signals transmitted by each first channel of the first sub-port 111 and decomposes them to each fifth channel of the fifth port 31, and performs rate conversion on the data signals transmitted by each fifth channel of the fifth port 31 and aggregates them to each first channel of the first sub-port 111. For example, when the first sub-port 111 is a PCIe 6.0 x8 port and the fifth port 31 is a PCIe 5.0 x16 port, the processing module 33 can not only decompose and aggregate data signals between the first sub-port 111 and the fifth port 31, but also perform rate conversion between each first channel of the first sub-port 111 and each fifth channel of the fifth port 31 to ensure the rate matching between channels.

[0068] Furthermore, the processing module can also be configured to negotiate a first bus rate with the first bus switch 1 or the second bus switch 2, and to negotiate a second bus rate with the first peripheral device 7 or the second peripheral device 8.

[0069] Taking the processing module 33 in the first channel aggregation module as an example, in order to ensure that the speed on the first bus switch 1 side and the speed on the first peripheral device 7 side can be fully utilized, during the speed negotiation phase, the processing module 33 will negotiate the first bus speed with the first bus switch 1 separately and negotiate the second bus speed with the first peripheral device 7 separately, rather than being only responsible for transmitting bus speed negotiation data between the first bus switch 1 and the first peripheral device 7. For example, when the first bus switch 1 supports PCIe 6.0, the first sub-port 111 is a PCIe 6.0 x8 port, the first peripheral device 7 supports PCIe 5.0, and the fifth port 31 is a PCIe 5.0 x16 port, the processing module 33 can negotiate the PCIe 6.0 x8 rate (i.e., 128GB / s) with the first bus switch 1 independently, and negotiate the PCIe 5.0 x16 rate (also 128GB / s) with the first peripheral device 7 independently, and can perform channel rate conversion between the two, thus ensuring that the rates of the first sub-port 111 and the fifth port 31 are matched. If the processing module 33 only transmits bus rate negotiation data between the first bus switch 1 and the first peripheral device 7, that is, the bus rate is actually negotiated between the first bus switch 1 and the first peripheral device 7, then due to the influence of the PCIe protocol, the first bus switch 1 and the first peripheral device 7 can only negotiate a PCIe 5.0 x8 rate (i.e., 64GB / s). At this time, the bandwidth of both the first bus switch 1 and the first peripheral device 7 cannot be fully utilized, which easily leads to the data transmission efficiency of the bus interconnect system.

[0070] The structure of the processing module is described below. In one specific implementation, the processing module includes a first core module and a second core module;

[0071] The first core module includes a first physical port, a first branch aggregation module, an interconnection network, a second branch aggregation module, a second physical port, and a bus interface. The first physical port is connected to the first branch aggregation module, the first branch aggregation module is connected to the interconnection network, the interconnection network is connected to the second branch aggregation module, the second branch aggregation module is connected to the second physical port, and the first physical port, the first branch aggregation module, the interconnection network, the second branch aggregation module, and the second physical port are connected to the bus interface.

[0072] The second core module includes a first processor subsystem and an on-chip interconnect bus. The first processor subsystem is connected to the on-chip interconnect bus, and the interconnect bus is connected to a bus interface.

[0073] The first physical port is connected to the first serializer-deserializer, and the second physical port is connected to the second serializer-deserializer.

[0074] The first branch aggregation module is configured to, when switching to the first mode, perform rate conversion and decompose the data signals sent by each first channel in the first sub-port to each fifth channel in the fifth port according to the preset data mapping relationship between each first channel in the first sub-port and each fifth channel in the fifth port, and send the processed data signals to the second branch aggregation module through the Internet; or is configured to, when switching to the first mode, perform rate conversion and decompose the data signals sent by each second channel in the second sub-port to each sixth channel in the sixth port according to the preset data mapping relationship between each second channel in the second sub-port and each sixth channel in the sixth port, and send the processed data signals to the second branch aggregation module through the Internet.

[0075] The second branch aggregation module is configured to, when switching to the first mode, perform rate conversion on the data signals transmitted by each fifth channel in the fifth port and aggregate them to each first channel in the first sub-port according to the preset data mapping relationship between each first channel in the first sub-port and each fifth channel in the fifth port, and send the processed data signals to the first branch aggregation module through the Internet; or is configured to, when switching to the first mode, perform rate conversion on the data signals transmitted by each sixth channel in the sixth port and aggregate them to each second channel in the second sub-port according to the preset data mapping relationship between each second channel in the second sub-port and each sixth channel in the sixth port, and send the processed data signals to the first branch aggregation module through the Internet.

[0076] The first processor subsystem is configured to configure the first physical port, the first branch aggregation module, the interconnection network, the second branch aggregation module, and the second physical port when switching to the first mode.

[0077] The following description will still use the processing module 33 of the first channel aggregation module 3 as an example. Please refer to... Figure 5 , Figure 5This is a structural block diagram of a processing module provided in an embodiment of the present invention. The processing module 33 may include a first core module 331 and a second core module 332, which are connected via a bus interface 3317. The first core module 331 may include a first physical port 3311, a first branch aggregation module 3312, an interconnection network, a second branch aggregation module 3315, a second physical port 3316, and the bus interface 3317. The first physical port 3311 is connected to a first serializer-deserializer 32, and the second physical port 3316 is connected to a second serializer-deserializer 34. The first physical port 3311 and the second physical port 3316 are responsible for receiving and sending data packets. The first branch aggregation module 3312 is connected to the first physical port 3311, and the second branch aggregation module 3315 is connected to the second physical port 3316. The first branch aggregation module 3312 is connected to the second branch aggregation module 3315 via the interconnection network. The first branch aggregation module 3312 and the second branch aggregation module 3315 are responsible for the decomposition, aggregation, and rate conversion of data signals.

[0078] In addition, the interconnection network is connected by multiple selection modules 3313, each selection module 3313 corresponding to a different number of channels, and each selection module 3313 is connected in pairs through interconnection channels 3314. The first branch aggregation module 3312 and the second branch aggregation module 3315 select interconnection channels that match the number of the first channel and the number of the fifth channel through the interconnection network for data transmission. For example, when the first sub-port is a PCIe x8 port and the fifth port is a PCIe x16 port, the first branch aggregation module 3312 and the second branch aggregation module 3315 transmit data through the interconnection channels between selection modules x8 and x16. In this way, the data aggregation / decomposition functions with different numbers of channels can be bound to different interconnection channels in the interconnection network to facilitate the hardware layout in the first branch aggregation module 3312 and the second branch aggregation module 3315.

[0079] The second core module 332 includes at least a first processor subsystem 3321 and an on-chip interconnect bus 3323. The first processor subsystem 3321 can be connected to the bus interface 3317 via the on-chip interconnect bus 3323. When the processing module 33 switches to the first mode, the first processor subsystem 3321 can configure the first physical port 3311, the first branch aggregation module 3312, the interconnect network, the second branch aggregation module 3315, and the second physical port 3316 to enable the first core module 331 to have the functions of decomposing, aggregating, and rate-converting data signals.

[0080] In addition, the second core module 332 may also include an on-chip storage module 3324, an on-chip storage module 3325, a general-purpose peripheral module 3326, and a control module 3327. The on-chip storage module 3324 (ROM + RAM) is used to store the initialization program and firmware calling program; the on-chip storage module 3325 is an on-chip data cache; the general-purpose peripheral interface 3326 includes QSPI, I2C, UART, etc.; the QSPI interface built into the CPU connects to external Flash memory, responsible for refreshing and saving the chip firmware.

[0081] In another specific implementation, the second core module may further include a second processor subsystem, which is connected to an on-chip interconnect bus;

[0082] The first branch aggregation module is also configured to transparently transmit data signals between the first sub-port and the fifth port when switching to the second mode; or to transparently transmit data signals between the second sub-port and the sixth port when switching to the second mode.

[0083] The second branch aggregation module is also configured to transparently transmit data signals between the first sub-port and the fifth port when switching to the second mode; or to transparently transmit data signals between the second sub-port and the sixth port when switching to the second mode.

[0084] The first processor subsystem is configured to configure the first physical port, the first branch aggregation module, the interconnection network, the second branch aggregation module, and the second physical port when switching to the second mode.

[0085] Taking the processing module 33 of the first channel aggregation module 3 as an example, the second core module 332 may also include a second processor subsystem 3322. The second processor subsystem 3322 can be connected to the bus interface 3317 via the on-chip interconnect bus 3323. When the processing module 33 switches to the second mode, the second processor subsystem 3322 can configure the first physical port 3311, the first branch aggregation module 3312, the interconnect network, the second branch aggregation module 3315, and the second physical port 3316 to enable the first core module 331 to transparently transmit data signals. As mentioned above, when the first bus switch 1 supports PCIe 6.0 and the first peripheral device 7 supports PCIe 5.0, the processing module 33 needs to perform rate conversion between the two, at which time the processing module 33 needs to switch to the first mode. When the first bus switch 1 supports PCIe 6.0 and the first peripheral device 7 supports PCIe 6.0, the bus protocol versions of the first bus switch 1 and the first peripheral device 7 are the same, and there is no need for the processing module 33 to perform rate conversion between the two. At this time, the processing module 33 can switch to the second mode to perform data pass-through between the first bus switch 1 and the first peripheral device 7.

[0086] Furthermore, both the first-channel aggregation module and the second-channel aggregation module include a microcontroller. Please refer to [link / reference needed]. Figure 6 , Figure 6 This is a schematic diagram of another channel aggregation module provided in an embodiment of the present invention. Taking the first channel aggregation module as an example, it further includes a microcontroller 35, which is connected to the processing module 33.

[0087] The microcontroller 35 is configured to switch the processing module 33 to either a first mode or a second mode.

[0088] In another embodiment, the microcontroller 35 is also configured to adjust the operating frequency of the processing module 33 in order to improve the efficiency of data signal decomposition, aggregation, and rate conversion.

[0089] Furthermore, both the first channel aggregation module and the second channel aggregation module include at least two sets of first serializer-deserializer, processing module and second serializer-deserializer. Each set of first serializer-deserializer, processing module and second serializer-deserializer corresponds to a peripheral device and is specifically responsible for the data signal processing of that peripheral device.

[0090] Of course, each set of first serializer-deserializer, processing module, and second serializer-deserializer can also be encapsulated as a separate sub-module, and multiple sub-modules can constitute a complete channel aggregation module. Please refer to [reference needed]. Figure 7 , Figure 7 This is a comparative schematic diagram of the form of a channel aggregation module provided in an embodiment of the present invention. The left side shows a channel aggregation module formed by multiple discrete sub-modules, while the right side shows a complete channel aggregation module formed by sub-modules. The two have the same function and differ only in hardware form.

[0091] The following describes another form of the channel aggregation module. In another possible scenario, both the first and second channel aggregation modules can be bus switches.

[0092] In one embodiment, both the first channel aggregation module and the second channel aggregation module include at least two sub-bus switches, with a first end of the sub-bus switch connected to a first sub-port or a second sub-port, and a second end of the sub-bus switch connected to a fifth port or a sixth port.

[0093] In another implementation, both the first channel aggregation module and the second channel aggregation module include at least two virtual sub-bus switches, which are mapped to the first sub-port and the fifth port, or to the second sub-port and the sixth port.

[0094] Please refer to Figure 8 , Figure 8This is a comparative schematic diagram of another channel aggregation module configuration provided in an embodiment of the present invention. A similar port expansion effect can also be achieved using an LLC PCIe 6.0 bus switch, the difference being that it easily leads to wasted bandwidth and ports on the bus switch (the upstream PCIe 6.0 x16 needs to be downgraded to PCIe 6.0 x8, and the downstream PCIe 6.0 x16 needs to be downgraded to PCIe 5.0 x16). LLC stands for Low Lane Count. For example... Figure 8 The diagram illustrates two schemes for expanding from Gen6 x8 to Gen5 x16 using LLCPCIe bus switches. The left side shows expansion using two identical 24-lane or 32-lane PCIe 6.0 bus switches, while the right side shows expansion using only one 48-lane PCIe 6.0 bus switch. ① and ② are functionally identical, differing only in their presentation.

[0095] The signal processing method provided in this embodiment is described below. Please refer to... Figure 9 , Figure 9 The flowchart illustrates a signal processing method provided in an embodiment of the present invention. This method is applied to a bus interconnection system, which includes a first bus switch, a second bus switch, a first channel aggregation module, and a second channel aggregation module. The interconnection port of the first bus switch is connected to the interconnection port of the second bus switch, the first port of the first bus switch is connected to the first channel aggregation module, and the second port of the second bus switch is connected to the second channel aggregation module.

[0096] The third port of the first bus switch is connected to the first processor, the fourth port of the second bus switch is connected to the second processor, the fifth port of the first channel aggregation module is connected to the first peripheral device, the first channel aggregation module includes at least two fifth ports, and the sixth port of the second channel aggregation module is connected to the second peripheral device, the second channel aggregation module includes at least two sixth ports.

[0097] This method may include:

[0098] S901, the first channel aggregation module maps the first port to at least two fifth ports, decomposes the data signal sent from the first port to the corresponding fifth ports, and aggregates the data signal sent from the fifth ports to the first port;

[0099] S902, the second channel aggregation module maps the second port to at least two sixth ports, decomposes the data signals sent from the second port to the corresponding sixth ports, and aggregates the data signals sent from the sixth ports to the second port.

[0100] Based on the above embodiments, the bus interconnection system provided by the present invention may include a first bus switch, a second bus switch, a first channel aggregation module, and a second channel aggregation module. The interconnection port of the first bus switch is connected to the interconnection port of the second bus switch. The first port of the first bus switch is connected to the first channel aggregation module, and the second port of the second bus switch is connected to the second channel aggregation module. The third port of the first bus switch is connected to the first processor, the fourth port of the second bus switch is connected to the second processor, the fifth port of the first channel aggregation module is connected to the first peripheral device, and the first channel aggregation module includes at least two fifth ports. The sixth port of the second channel aggregation module is connected to the second peripheral device, and the second channel aggregation module includes at least two sixth ports. This ensures that an interconnection topology is formed between the processor and the peripheral device, and between each peripheral device, ensuring that communication connections can be established between the processor and the peripheral device, and between each peripheral device. More importantly, the first channel aggregation module can be configured to map the first port to at least two fifth ports, decompose the data signal sent from the first port to the corresponding fifth ports, and aggregate the data signal sent from the fifth ports to the first port; and the second channel aggregation module can be configured to map the second port to at least two sixth ports, decompose the data signal sent from the second port to the corresponding sixth ports, and aggregate the data signal sent from the sixth ports to the second port. That is, the first channel aggregation module can expand the first port of the first bus switch to at least two fifth ports, and the second channel aggregation module can expand the second port of the second bus switch to at least two sixth ports, effectively expanding the number of peripheral devices that the bus switch can connect to. This avoids interconnecting multiple bus switches to form the aforementioned interconnect topology, simplifies the interconnect topology, reduces system complexity, and improves the port utilization of the bus switch.

[0101] Optionally, the first bus switch and the second bus switch are connected via at least two sets of interconnect ports.

[0102] Optionally, the first bus switch is connected to the first processor via at least two third ports, and the second bus switch is connected to the first processor via at least two fourth ports.

[0103] Optionally, the seventh port of the first bus switch is connected to the third peripheral device, and the eighth port of the second bus switch is connected to the fourth peripheral device.

[0104] Optionally, the first port includes at least two first sub-ports, the second port includes at least two second sub-ports, the first sub-ports correspond to the fifth port, and the second sub-ports correspond to the sixth port;

[0105] This method may also include:

[0106] The first channel aggregation module maps the first sub-port to the fifth port, decomposes the data signal sent from the first sub-port to the fifth port, and aggregates the data signal sent from the fifth port to the first sub-port;

[0107] The second channel aggregation module maps the second sub-port to the sixth port, decomposes the data signal sent from the second sub-port to the sixth port, and aggregates the data signal sent from the sixth port to the second sub-port.

[0108] Optionally, the number of channels in the first channel of the first sub-port is less than the number of channels in the fifth channel of the fifth port, and the number of channels in the second channel of the second sub-port is less than the number of channels in the sixth channel of the sixth port.

[0109] This method may also include:

[0110] The first channel aggregation module decomposes the data signals sent by each first channel in the first sub-port to each fifth channel in the fifth port, and aggregates the data signals sent by each fifth channel in the fifth port to each first channel in the first sub-port;

[0111] The second channel aggregation module decomposes the data signals transmitted by each second channel in the second sub-port to each sixth channel in the sixth port, and aggregates the data signals transmitted by each sixth channel in the sixth port to each second channel in the second sub-port.

[0112] Optionally, the bandwidth of the first channel is greater than the bandwidth of the fifth channel, and the maximum total bandwidth of the first sub-port is equal to the maximum total bandwidth of the fifth port;

[0113] The bandwidth of the second channel is greater than that of the sixth channel, and the maximum total bandwidth of the second sub-port is equal to the maximum total bandwidth of the sixth port.

[0114] Optionally, the first bus switch and the first channel aggregation module use a first version of the bus protocol, the second bus switch and the second channel aggregation module use a first version of the bus protocol, the first channel aggregation module and the first peripheral device use a second version of the bus protocol, and the second channel aggregation module and the second peripheral device use a second version of the bus protocol, wherein the version number of the first version is greater than the version number of the second version.

[0115] Optionally, both the first channel aggregation module and the second channel aggregation module include:

[0116] A first serializer-deserializer, a processing module, and a second serializer-deserializer are connected together;

[0117] The first serializer-deserializer is connected to the first sub-port or the second sub-port, and the second serializer-deserializer is connected to the fifth port or the sixth port.

[0118] This method may also include:

[0119] The first serializer-deserializer performs serial-deserialization processing on the data signals of each first channel in the first sub-port; or is configured to perform serial-deserialization processing on the data signals of each second channel in the second sub-port;

[0120] The processing module performs rate conversion and decomposes the data signals transmitted by each first channel in the first sub-port to each fifth channel in the fifth port according to the preset data mapping relationship between each first channel in the first sub-port and each fifth channel in the fifth port; and performs rate conversion and aggregates the data signals transmitted by each fifth channel in the fifth port to each first channel in the first sub-port; or it is configured to perform rate conversion and decompose the data signals transmitted by each second channel in the second sub-port to each sixth channel in the sixth port according to the preset data mapping relationship between each second channel in the second sub-port and each sixth channel in the sixth port; and performs rate conversion and aggregates the data signals transmitted by each sixth channel in the sixth port to each second channel in the second sub-port.

[0121] The second serializer-deserializer performs serial-deserialization processing on the data signals of each of the fifth channels in the fifth port; it is configured to perform serial-deserialization processing on the data signals of each of the sixth channels in the sixth port.

[0122] Optionally, this method may also include:

[0123] The processing module negotiates a first bus rate with the first bus switch or the second bus switch, and negotiates a second bus rate with the first peripheral device or the second peripheral device.

[0124] Optionally, the processing module includes a first core module and a second core module;

[0125] The first core module includes a first physical port, a first branch aggregation module, an interconnection network, a second branch aggregation module, a second physical port, and a bus interface. The first physical port is connected to the first branch aggregation module, the first branch aggregation module is connected to the interconnection network, the interconnection network is connected to the second branch aggregation module, the second branch aggregation module is connected to the second physical port, and the first physical port, the first branch aggregation module, the interconnection network, the second branch aggregation module, and the second physical port are connected to the bus interface.

[0126] The second core module includes a first processor subsystem and an on-chip interconnect bus. The first processor subsystem is connected to the on-chip interconnect bus, and the interconnect bus is connected to a bus interface.

[0127] The first physical port is connected to the first serializer-deserializer, and the second physical port is connected to the second serializer-deserializer.

[0128] This method may also include:

[0129] When the first branch aggregation module switches to the first mode, it performs rate conversion and decomposes the data signals sent by each first channel in the first sub-port to each fifth channel in the fifth port according to the preset data mapping relationship between each first channel in the first sub-port and each fifth channel in the fifth port, and sends the processed data signals to the second branch aggregation module through the Internet; or it is configured to perform rate conversion and decompose the data signals sent by each second channel in the second sub-port to each sixth channel in the sixth port according to the preset data mapping relationship between each second channel in the second sub-port and each sixth channel in the sixth port, and send the processed data signals to the second branch aggregation module through the Internet.

[0130] When the second branch aggregation module switches to the first mode, it performs rate conversion on the data signals sent by each fifth channel in the fifth port and aggregates them to each first channel in the first sub-port according to the preset data mapping relationship between each first channel in the first sub-port and each fifth channel in the fifth port, and sends the processed data signals to the first branch aggregation module through the Internet; or it is configured to perform rate conversion on the data signals sent by each sixth channel in the sixth port and aggregate them to each second channel in the second sub-port according to the preset data mapping relationship between each second channel in the second sub-port and each sixth channel in the sixth port when switching to the first mode, and send the processed data signals to the first branch aggregation module through the Internet.

[0131] When the first processor subsystem switches to the first mode, it configures the first physical port, the first branch aggregation module, the interconnection network, the second branch aggregation module, and the second physical port.

[0132] Optionally, the second core module includes a second processor subsystem, which is connected to an on-chip interconnect bus;

[0133] This method may also include:

[0134] When the first branch aggregation module switches to the second mode, it transparently transmits the data signal between the first sub-port and the fifth port; or it is configured to transparently transmit the data signal between the second sub-port and the sixth port when switching to the second mode.

[0135] When the second branch aggregation module switches to the second mode, it transparently transmits the data signal between the first sub-port and the fifth port; or it is configured to transparently transmit the data signal between the second sub-port and the sixth port when switching to the second mode.

[0136] When the first processor subsystem switches to the second mode, it configures the first physical port, the first branch aggregation module, the interconnection network, the second branch aggregation module, and the second physical port.

[0137] Optionally, both the first channel aggregation module and the second channel aggregation module include a microcontroller, which is connected to the processing module;

[0138] This method may also include:

[0139] The microcontroller processing module switches to either the first or second mode.

[0140] Optionally, this method may also include:

[0141] The microcontroller is used to adjust the operating frequency of the processing module.

[0142] Optionally, both the first channel aggregation module and the second channel aggregation module include at least two sets of first serializer-deserializer, processing module and second serializer-deserializer.

[0143] This invention also provides a server, including: a first processor, a second processor, a first peripheral device, a second peripheral device, and a bus interconnection system as described above, wherein the bus interconnection system is connected to the first processor, the second processor, the first peripheral device, and the second peripheral device.

[0144] Please refer to Figure 10 , Figure 11 , Figure 10 This is a schematic diagram of a single motherboard provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of motherboard interconnection provided in an embodiment of the present invention. Peripheral devices can be connected to the motherboard through slots, and motherboards can be interconnected through interconnect ports (Fabric connectors) to achieve interconnection.

[0145] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0146] The above provides a detailed description of the bus interconnection system, signal processing method, and server provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A bus interconnection system, characterized in that, It includes a first bus switch, a second bus switch, a first channel aggregation module, and a second channel aggregation module. The interconnect port of the first bus switch is connected to the interconnect port of the second bus switch. The first port of the first bus switch is connected to the first channel aggregation module, and the second port of the second bus switch is connected to the second channel aggregation module. Wherein, the third port of the first bus switch is connected to the first processor, the fourth port of the second bus switch is connected to the second processor, the fifth port of the first channel aggregation module is connected to the first peripheral device, the first channel aggregation module includes at least two fifth ports, the sixth port of the second channel aggregation module is connected to the second peripheral device, and the second channel aggregation module includes at least two sixth ports; The first channel aggregation module is configured to map the first port to at least two of the fifth ports, decompose the data signal sent by the first port to the corresponding fifth ports, and aggregate the data signal sent by the fifth ports to the first port; The second channel aggregation module is configured to map the second port to at least two of the sixth ports, decompose the data signals sent by the second port to the corresponding sixth ports, and aggregate the data signals sent by the sixth ports to the second port.

2. The bus interconnection system according to claim 1, characterized in that, The first bus switch and the second bus switch are connected through at least two sets of interconnect ports.

3. The bus interconnection system according to claim 1, characterized in that, The first bus switch is connected to the first processor through at least two third ports, and the second bus switch is connected to the second processor through at least two fourth ports.

4. The bus interconnection system according to claim 1, characterized in that, The seventh port of the first bus switch is connected to the third peripheral device, and the eighth port of the second bus switch is connected to the fourth peripheral device.

5. The bus interconnection system according to claim 1, characterized in that, The first port includes at least two first sub-ports, the second port includes at least two second sub-ports, the first sub-ports correspond to the fifth port, and the second sub-ports correspond to the sixth port; The first channel aggregation module is configured to map the first sub-port to the fifth port, decompose the data signal sent by the first sub-port to the fifth port, and aggregate the data signal sent by the fifth port to the first sub-port; The second channel aggregation module is configured to map the second sub-port to the sixth port, decompose the data signal sent by the second sub-port to the sixth port, and aggregate the data signal sent by the sixth port to the second sub-port.

6. The bus interconnection system according to claim 5, characterized in that, The number of channels in the first channel of the first sub-port is less than the number of channels in the fifth channel of the fifth port, and the number of channels in the second channel of the second sub-port is less than the number of channels in the sixth channel of the sixth port. The first channel aggregation module is configured to decompose the data signals sent by each first channel in the first sub-port to each fifth channel of the fifth port, and to aggregate the data signals sent by each fifth channel in the fifth port to each first channel of the first sub-port. The second channel aggregation module is configured to decompose the data signals transmitted by each second channel in the second sub-port to each sixth channel of the sixth port, and to aggregate the data signals transmitted by each sixth channel in the sixth port to each second channel of the second sub-port.

7. The bus interconnection system according to claim 6, characterized in that, The bandwidth of the first channel is greater than the bandwidth of the fifth channel, and the maximum total bandwidth of the first sub-port is equal to the maximum total bandwidth of the fifth port; The bandwidth of the second channel is greater than that of the sixth channel, and the maximum total bandwidth of the second sub-port is equal to the maximum total bandwidth of the sixth port.

8. The bus interconnection system according to claim 7, characterized in that, The first bus switch and the first channel aggregation module use a first version of the bus protocol, the second bus switch and the second channel aggregation module use a first version of the bus protocol, the first channel aggregation module and the first peripheral device use a second version of the bus protocol, and the second channel aggregation module and the second peripheral device use a second version of the bus protocol. The version number of the first version is greater than the version number of the second version.

9. The bus interconnection system according to claim 7, characterized in that, Both the first channel aggregation module and the second channel aggregation module include: A first serializer-deserializer, a processing module, and a second serializer-deserializer, wherein the processing module is connected to the first serializer-deserializer and the second serializer-deserializer; Wherein, the first serializer-deserializer is connected to the first sub-port or the second sub-port, and the second serializer-deserializer is connected to the fifth port or the sixth port; The first serializer-deserializer is configured to perform serial-deserialization processing on the data signals of each first channel in the first sub-port; or is configured to perform serial-deserialization processing on the data signals of each second channel in the second sub-port. The processing module is configured to, according to a preset data mapping relationship between each first channel of the first sub-port and each fifth channel of the fifth port, perform rate conversion and decompose the data signals transmitted by each first channel of the first sub-port to each fifth channel of the fifth port, and perform rate conversion and aggregate the data signals transmitted by each fifth channel of the fifth port to each first channel of the first sub-port; or is configured to, according to a preset data mapping relationship between each second channel of the second sub-port and each sixth channel of the sixth port, perform rate conversion and decompose the data signals transmitted by each second channel of the second sub-port to each sixth channel of the sixth port, and perform rate conversion and aggregate the data signals transmitted by each sixth channel of the sixth port to each second channel of the second sub-port; The second serializer-deserializer is configured to perform serial-deserialization processing on the data signals of each fifth channel in the fifth port; or to perform serial-deserialization processing on the data signals of each sixth channel in the sixth port.

10. The bus interconnection system according to claim 9, characterized in that, The processing module is further configured to negotiate a first bus rate with the first bus switch or the second bus switch, and to negotiate a second bus rate with the first peripheral device or the second peripheral device.

11. The bus interconnection system according to claim 9, characterized in that, The processing module includes a first core module and a second core module; The first core module includes a first physical port, a first branch aggregation module, an interconnection network, a second branch aggregation module, a second physical port, and a bus interface. The first physical port is connected to the first branch aggregation module, the first branch aggregation module is connected to the interconnection network, the interconnection network is connected to the second branch aggregation module, the second branch aggregation module is connected to the second physical port, and the first physical port, the first branch aggregation module, the interconnection network, the second branch aggregation module, and the second physical port are connected to the bus interface. The second core module includes a first processor subsystem and an on-chip interconnect bus. The first processor subsystem is connected to the on-chip interconnect bus, and the on-chip interconnect bus is connected to the bus interface. Wherein, the first physical port is connected to the first serializer-deserializer, and the second physical port is connected to the second serializer-deserializer; The first branch aggregation module is configured to, when switching to the first mode, perform rate conversion and decompose the data signals sent by each first channel in the first sub-port to each fifth channel of the fifth port according to the preset data mapping relationship between each first channel of the first sub-port and each fifth channel of the fifth port, and send the processed data signals to the second branch aggregation module through the interconnection network; or is configured to, when switching to the first mode, perform rate conversion and decompose the data signals sent by each second channel in the second sub-port to each sixth channel of the sixth port according to the preset data mapping relationship between each second channel of the second sub-port and each sixth channel of the sixth port, and send the processed data signals to the second branch aggregation module through the interconnection network. The second branch aggregation module is configured to, when switching to the first mode, perform rate conversion on the data signals sent by each fifth channel in the fifth port and aggregate them to each first channel of the first sub-port according to the preset data mapping relationship between each first channel of the first sub-port and each fifth channel of the fifth port, and send the processed data signals to the first branch aggregation module through the interconnection network; or is configured to, when switching to the first mode, perform rate conversion on the data signals sent by each sixth channel in the sixth port and aggregate them to each second channel of the second sub-port according to the preset data mapping relationship between each second channel of the second sub-port and each sixth channel of the sixth port, and send the processed data signals to the first branch aggregation module through the interconnection network. The first processor subsystem is configured to configure the first physical port, the first branch aggregation module, the interconnection network, the second branch aggregation module, and the second physical port when switching to the first mode.

12. The bus interconnection system according to claim 11, characterized in that, The second core module includes a second processor subsystem, which is connected to the on-chip interconnect bus; The first branch aggregation module is further configured to transparently transmit the data signal between the first sub-port and the fifth port when switching to the second mode; or to transparently transmit the data signal between the second sub-port and the sixth port when switching to the second mode. The second branch aggregation module is further configured to transparently transmit the data signal between the first sub-port and the fifth port when switching to the second mode; or to transparently transmit the data signal between the second sub-port and the sixth port when switching to the second mode. The first processor subsystem is configured to configure the first physical port, the first branch aggregation module, the interconnection network, the second branch aggregation module, and the second physical port when switching to the second mode.

13. The bus interconnection system according to claim 12, characterized in that, Both the first channel aggregation module and the second channel aggregation module include a microcontroller, and the microcontroller is connected to the processing module; The microcontroller is configured to switch the processing module to either the first mode or the second mode.

14. The bus interconnection system according to claim 13, characterized in that, The microcontroller is also configured to adjust the operating frequency of the processing module.

15. The bus interconnection system according to claim 9, characterized in that, Both the first channel aggregation module and the second channel aggregation module include at least two sets of the first serializer-deserializer, the processing module, and the second serializer-deserializer.

16. The bus interconnection system according to claim 6, characterized in that, Both the first channel aggregation module and the second channel aggregation module are bus switches.

17. The bus interconnection system according to claim 16, characterized in that, Both the first channel aggregation module and the second channel aggregation module include at least two sub-bus switches. The first end of each sub-bus switch is connected to the first sub-port or the second sub-port, and the second end of each sub-bus switch is connected to the fifth port or the sixth port.

18. The bus interconnection system according to claim 16, characterized in that, Both the first channel aggregation module and the second channel aggregation module include at least two virtual sub-bus switches, which are mapped to the first sub-port and the fifth port, or to the second sub-port and the sixth port.

19. A signal processing method, characterized in that, The system is applied to a bus interconnection system, which includes a first bus switch, a second bus switch, a first channel aggregation module, and a second channel aggregation module. The interconnection port of the first bus switch is connected to the interconnection port of the second bus switch, the first port of the first bus switch is connected to the first channel aggregation module, and the second port of the second bus switch is connected to the second channel aggregation module. Wherein, the third port of the first bus switch is connected to the first processor, the fourth port of the second bus switch is connected to the second processor, the fifth port of the first channel aggregation module is connected to the first peripheral device, the first channel aggregation module includes at least two fifth ports, the sixth port of the second channel aggregation module is connected to the second peripheral device, and the second channel aggregation module includes at least two sixth ports; The method includes: The first channel aggregation module maps the first port to at least two fifth ports, decomposes the data signal sent by the first port to the corresponding fifth ports, and aggregates the data signal sent by the fifth ports to the first port; The second channel aggregation module maps the second port to at least two of the sixth ports, decomposes the data signals sent by the second port to the corresponding sixth ports, and aggregates the data signals sent by the sixth ports to the second port.

20. A server, characterized in that, include: A first processor, a second processor, a first peripheral device, a second peripheral device, and a bus interconnect system as described in any one of claims 1 to 18, wherein the bus interconnect system is connected to the first processor, the second processor, the first peripheral device, and the second peripheral device.

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