Path analysis method and system of integrated circuit, storage medium and computer program product
By constructing a shortest path forest on the GPU and utilizing implicit path representation methods, combined with explicit CPU reconstruction, the problem of low efficiency in timing path analysis in integrated circuit design is solved, achieving efficient and accurate path analysis.
Patent Information
- Application Number
- CN202410689927.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-30
- Publication Date
- 2025-12-02
AI Technical Summary
The timing path analysis in existing integrated circuit designs is inefficient, especially in large-scale designs where the PBA method is too time-consuming, while the GBA method is not accurate enough.
We construct a shortest path forest on the GPU, and use the GPU-accelerated kernel to perform path analysis through hierarchical allocation and implicit path representation methods. We then combine this with the CPU to explicitly reconstruct candidate paths, thus optimizing the path analysis process.
It significantly improves the efficiency of time-series path analysis, reduces computation time, and enhances the accuracy and quality of analysis results.
Smart Images
Figure CN121052182A_ABST
Abstract
Description
[Technical Field]
[0001] This invention relates to the field of integrated circuit design, and in particular to a path analysis method, system, storage medium, and computer program product for integrated circuits. [Background Technology]
[0002] Timing analysis in computer-aided circuit design employs two main methods: PBA (Path Based Analysis) and GBA (Graph Based Analysis). PBA is a path-based analysis method that evaluates the timing performance of a circuit by traversing and analyzing various timing paths. PBA first identifies candidate paths—those with the greatest impact on circuit timing—and performs detailed timing analysis on these paths to determine delays and check for compliance with timing constraints. PBA primarily focuses on the delays of timing paths and the satisfaction of timing constraints, enabling rapid identification and resolution of path-based timing problems. GBA, on the other hand, is a graph-based analysis method that analyzes and optimizes timing performance by modeling the circuit as a graph structure. GBA represents the components in the circuit (such as logic gates and clock networks) as nodes in a graph, using edges to represent the relationships between them. By analyzing the graph, candidate paths can be identified, timing constraints checked, and timing performance optimized. GBA primarily focuses on the graphical representation of the circuit structure and the application of graph algorithms, allowing for comprehensive analysis and optimization of the timing performance of complex circuits.
[0003] The PBA method primarily focuses on the analysis and optimization of individual time-series paths. It requires traversing and analyzing each path, performing detailed analysis of candidate paths. Therefore, PBA may need to handle larger datasets for designs containing a large number of time-series paths.
[0004] If using the GBA analysis mode, the tool only considers the most pessimistic case for each unit, thus selecting the most pessimistic timing path. However, if using the PBA analysis mode, the tool uses the actual path when calculating slope propagation. While PBA is more accurate and realistic, its computational complexity is enormous, leading to a significant increase in runtime. PBA is extremely time-consuming, typically 10-1000 times slower than GBA, and the performance improvement gained by current STAR engines using multi-core CPUs is very limited. Therefore, when our design scale reaches millions of gates, using PBA would require the tool to spend a very long time finding the true slope propagation. Thus, generally, we use the GBA mode for timing analysis, but this results in less accurate inspection results. [Summary of the Invention]
[0005] To address the problem of low efficiency in timing path analysis within integrated circuits in current integrated circuit design, this invention provides a path analysis method for integrated circuits, comprising the following steps:
[0006] On the GPU, the shortest path forest is obtained based on the timing analysis graph of the input integrated circuit.
[0007] Candidate paths in the shortest path forest are defined as suffix edges, and candidate paths in the STA graph other than those in the shortest path forest are defined as deviation edges. The number of deviation edges is represented as the deviation level. Candidate paths with the same deviation level are stored in an array and assigned to a thread on the GPU.
[0008] Traverse each candidate path in the same deviation level and find deviation edges along the candidate path. Use these deviation edges as sub-edges of the candidate path to supplement it, and obtain the expanded candidate path for the next level. Iterate along the deviation level to obtain the final path report.
[0009] The path report data is input into the CPU. Based on the deviation edges and corresponding suffix edges of the candidate paths in the path report, the explicit candidate paths are reconstructed, thus completing the path analysis of the integrated circuit.
[0010] Preferably, the clock net of the integrated circuit is represented as a timing analysis diagram. After the timing analysis diagram is stored in a compressed sparse row format, the timing analysis diagram data is transmitted to the GPU, and the timing analysis diagram of the integrated circuit is obtained on the GPU.
[0011] Preferably, after obtaining candidate paths in a level, the CPU deletes the remaining paths in that level other than the candidate paths.
[0012] Preferably, the shortest path tree of the nodes in the time series analysis graph is obtained, any node is selected from the nodes that are close to each other in the shortest path tree, and only the candidate path with the shortest distance to that node is explored. The remaining candidate paths in the shortest path tree are deleted, and the shortest path trees are merged to obtain the shortest path forest.
[0013] Preferably, candidate paths with the same deviation level are assigned to a thread on the GPU for execution. In the thread, the sub-offset of the last constituent unit of the candidate path in the current level is calculated, and the sub-offset is used as the total number of candidate paths to be explored in the next level.
[0014] Preferably, starting from the level with a deviation level of zero, each candidate path in the current level is traversed, and deviation edges are found along the candidate path. These deviation edges are then used as sub-edges of the candidate path to supplement it, thus obtaining the candidate path for the next level.
[0015] Preferably, the maximum level of the deviation level is obtained through the level counter. After obtaining the candidate path of the current level, it is determined whether the maximum level has been reached. If the current level is less than the maximum level, the next level is processed.
[0016] To address the aforementioned technical problems, this invention also provides a path analysis system for integrated circuits, comprising:
[0017] The shortest path forest construction module is used to input the timing analysis diagram of the integrated circuit into the GPU, obtain the shortest path tree of the nodes in the timing analysis diagram, and merge the shortest path trees to obtain the shortest path forest.
[0018] The forward-looking hierarchy allocation module is used to define candidate paths in the shortest path forest as suffix edges, and candidate paths in the time series analysis graph other than those in the shortest path forest as deviation edges. The number of deviation edges is represented by the deviation level. Candidate paths with the same deviation level are stored in an array and allocated to a thread of the GP U for execution.
[0019] The inter-layer expansion module is used to traverse each candidate path in the current layer, find deviation edges along the candidate path, and supplement these deviation edges as sub-edges of the candidate path to obtain the candidate path of the next layer. The module iteratively expands along the deviation layers to obtain the final path report.
[0020] The path recovery module is used to input the data from the path report into the CPU, and to restore the explicit candidate path based on the deviation edge and the corresponding suffix edge of the candidate path in the path report, thereby completing the path analysis of the integrated circuit.
[0021] To solve the above-mentioned technical problems, the present invention also provides a storage medium, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements a path analysis method for integrated circuits.
[0022] To address the aforementioned technical problems, this invention also provides a computer program product, comprising a computer program / instructions that are executed by a processor to implement the steps of a path analysis method for integrated circuits.
[0023] Compared with existing technologies, the present invention provides a path analysis method, system, storage medium, and computer program product for integrated circuits. These advantages include:
[0024] 1. The integrated circuit path analysis method of this invention constructs a shortest path forest on the GPUI, making the structure of the paths enumerated on the GPUI more compact and correspondingly reducing the space occupied on the GPUI. Then, candidate paths in the shortest path forest are hierarchically allocated. Candidate paths with the same deviation level are stored in an array and assigned to a thread on the GPUI for execution. This schedules the role of each thread before timing analysis of the candidate paths, avoiding thread contention and deadlocks, effectively improving the efficiency of timing analysis of candidate paths. Furthermore, by expanding the hierarchy to supplement the sub-edges of the candidate paths, the next layer of candidate paths is obtained. Threads are assigned to different memory locations, thus eliminating the need for shared data synchronization. This implicit candidate path representation method improves memory efficiency.
[0025] Finally, explicit candidate paths are obtained by explicitly reconstructing the candidate paths in the CPU. Since the number of paths requested and the graph diameter required for the entire path recovery have linear complexity, path recovery can be completed more efficiently in the CPU. This invention decomposes candidate path generation into multiple GPUB accelerated cores and uses implicit path representation methods to design efficient data structures for the GPUB, enabling this method to significantly accelerate the timing analysis of integrated circuit paths.
[0026] 2. The integrated circuit path analysis method of the present invention, after obtaining candidate paths in a level, deletes the remaining paths in that level except for the candidate paths through the CPU, compresses the paths in each level to delete unnecessary paths and improve memory efficiency, and sorts the paths based on path priority in order to compress them before they can be used in the next expansion in the new level. Since the sorted array is not large, it is more efficient to use the CPU to compress each level.
[0027] 3. The present invention also provides a path analysis system for integrated circuits, which has the same beneficial effects as the path analysis method for integrated circuits described above, and will not be elaborated here.
[0028] 4. The present invention also provides a storage medium storing a computer program thereon. When the computer program is executed, it implements the path analysis method of the above-mentioned integrated circuit and has the same beneficial effects as the path analysis method of the above-mentioned integrated circuit, which will not be described in detail here.
[0029] 5. The present invention also provides a computer program product, including a computer program / instructions, which is executed by a processor to implement the steps of the path analysis method for integrated circuits, and has the same beneficial effects as the path analysis method for integrated circuits described above, which will not be elaborated here. [Attached Image Description]
[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a flowchart of the steps of a path analysis method for an integrated circuit provided in the first embodiment of the present invention.
[0032] Figure 2a This is an example diagram of STA provided in the first embodiment of the present invention.
[0033] Figure 2b This is an example diagram of the shortest path forest provided in the first embodiment of the present invention.
[0034] Figure 3 This is a schematic diagram of the structure of an integrated circuit path analysis system provided in the second embodiment of the present invention.
[0035] Figure 4 This is a schematic diagram of the structure of a storage medium provided in the third embodiment of the present invention.
[0036] Explanation of reference numerals in the attached diagram:
[0037] 1. Integrated circuit path analysis system; 2. Storage medium; 101. Shortest path forest construction module; 102. Forward-looking hierarchical allocation module; 103. Inter-layer expansion module; 104. Path recovery module; 201. Memory; 202. Processor; 203. Computer program.
Detailed Implementation Methods
[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0039] Path Based Analysis (PBA) is a path-based analysis method that evaluates the timing performance of a circuit by traversing and analyzing each timing path. PBA first identifies candidate paths—those with the greatest impact on circuit timing—and performs detailed timing analysis on these paths to determine delays and check for compliance with timing constraints. PBA primarily focuses on the delays and constraint fulfillment of timing paths, enabling rapid identification and resolution of path-based timing problems. However, PBA mainly focuses on the analysis and optimization of individual timing paths. It requires traversing and analyzing each path in detail, including detailed analysis of candidate paths. Therefore, PBA may require handling a larger amount of data for designs with a large number of timing paths.
[0040] To address the issue of low efficiency in timing path analysis within integrated circuits in current integrated circuit design, please refer to [link / reference]. Figure 1 The first embodiment of the present invention provides a path analysis method for integrated circuits, which includes the following steps:
[0041] S1: On the GPU, obtain the shortest path forest based on the timing analysis graph of the input integrated circuit.
[0042] S2: Define candidate paths in the shortest path forest as suffix edges, define candidate paths in the time series analysis graph other than those in the shortest path forest as deviation edges, and the number of deviation edges is represented as the deviation level. Store candidate paths with the same deviation level in an array and allocate them to a thread of the GPU.
[0043] S3: Starting from the level with a deviation level of zero, traverse each candidate path in the same deviation level and find deviation edges along the candidate path. Use these deviation edges as sub-edges of the candidate path to supplement them, and obtain the candidate path of the next level after expansion. Iterate along the deviation level to obtain the final path report.
[0044] S4: Input the data from the path report into the CPU, and reconstruct the explicit candidate path based on the deviation edge and the corresponding suffix edge of the candidate path in the path report, thus completing the path analysis of the integrated circuit.
[0045] The integrated circuit path analysis method in this invention constructs a shortest path forest on the GPU, making the structure of the enumerated paths on the GPU more compact and correspondingly occupying less space. Next, candidate paths in the shortest path forest are hierarchically assigned. Candidate paths with the same deviation level are stored in an array and assigned to a thread on the GPU for execution. This schedules the role of each thread before timing analysis of candidate paths, avoiding thread contention and deadlocks, effectively improving the efficiency of timing analysis. Furthermore, the sub-edges of the candidate paths are supplemented through hierarchical expansion to obtain the next level of candidate paths. Threads are assigned to different memory locations, thus eliminating the need for shared data synchronization. This implicit candidate path representation method improves memory efficiency.
[0046] Since the candidate paths in the obtained path report are implicit paths represented by biased edges, their trajectories differ from those of normal candidate paths. Therefore, explicit candidate paths need to be explicitly reconstructed in the CPU to obtain explicit candidate paths, which are represented as the completed path trajectories. Because the total number of requested paths and the graph diameter required for path recovery have linear complexity, path recovery can be performed more efficiently in the CPU. This invention decomposes candidate path generation into multiple GPU-accelerated cores and utilizes implicit path representation methods to design efficient GPU data structures, enabling this method to significantly accelerate the timing analysis of paths in integrated circuits.
[0047] It should be noted that the English name for timing analysis diagram is Static Timing Analysis, hence it is also called STA diagram, which represents static timing analysis. In the field of electronic design automation (EDA), timing analysis is a method used to check whether timing constraints such as signal delays and clock edge arrival times are met in digital circuits.
[0048] Time series analysis typically uses STA diagrams to represent and analyze time series relationships.
[0049] In timing path analysis, a STAR diagram is a graphical representation used to represent and analyze the logic paths of a circuit. Nodes and edges are two important concepts in an STAR diagram. Nodes represent specific timing elements in the circuit's logic path, typically logic gates, clock signals, and data signals. Each node represents a specific logic element or signal, which can be a register, flip-flop, logic gate, etc. Each node is associated with a specific clock domain and contains timing information such as arrival and output times. A node is represented as a point or vertex in a STAR diagram. Edges represent logical paths or timing relationships between nodes. They represent dependencies between nodes and signal propagation paths. Edges are usually weighted, representing delays in the circuit logic; the weight typically represents the time required for a signal to propagate along the path. An edge in a STAR diagram is represented as a directed edge connecting two nodes.
[0050] It's important to note that in a STAR diagram, the shortest path tree is a crucial tool for analyzing signal propagation delays in circuits. The shortest path tree finds the shortest paths from a given starting node to all other nodes, sorting and displaying them according to the propagation delay along the paths. This provides design engineers with valuable information when analyzing critical paths and timing issues in circuits. By constructing a shortest path tree, the shortest paths from the starting node to other nodes can be found, and the total propagation delay along the paths can be calculated.
[0051] A path refers to the signal propagation route from the start point to the end point of a circuit. It is a sequence of multiple circuit elements (such as logic gates, registers, and interconnects) representing the order in which signals propagate within the circuit. A candidate path, on the other hand, refers to a potential path that may be considered in path analysis. A candidate path can be any possible path from the start point to the end point or a path selected based on certain rules or constraints. In static timing analysis, a candidate path refers to a path that may affect timing when timing constraints are considered.
[0052] Please refer to the following: Figure 2a and Figure 2b Furthermore, step S1 also includes the following steps:
[0053] S11: Represent the clock net of the integrated circuit as a timing analysis diagram. The timing analysis diagram is stored in a compressed sparse row format. The stored timing analysis diagram is then transferred to the GPU, where the timing analysis diagram of the integrated circuit is obtained.
[0054] S12: Obtain the shortest path tree of the nodes in the time series analysis graph. Select any node among the nodes that are close to each other in the shortest path tree, and explore only the candidate path with the shortest distance to that node. Delete the remaining paths in the shortest path tree and merge the shortest path trees to obtain the shortest path forest.
[0055] This invention combines shortest path trees to form a shortest path forest, which is more compact and saves memory compared to building each independent shortest path tree.
[0056] It should be noted that the Compressed Sparse Row format is also called CSR (Compressed Sparse Row) format. CSR is a data storage format used to represent sparse matrices. In CSR format, the matrix is represented as three arrays: values, column indices, and row offsets.
[0057] Value array: Stores the values of the non-zero elements in the matrix.
[0058] The column index array stores the column index of each non-zero element.
[0059] Row offsets: Stores the position of the first non-zero element of each row in the value array and column index array.
[0060] The CSR format reduces storage space requirements by compressing and storing sparse matrices, thus avoiding the storage of a large number of zero elements in the sparse matrix.
[0061] It should be noted that PBA is a path-based analysis method used to evaluate and optimize the timing performance of circuits. PBA performs detailed timing analysis on the critical path, focusing on the delays and timing constraint satisfaction of the critical path in the STA diagram. PBA identifies the critical path based on the path information in the STA diagram and calculates the path delays to check if they meet timing constraints.
[0062] Therefore, the implementation of the PBA method requires the representation and information provided by the STA diagram. The STA diagram provides timing relationships and constraint information between circuit elements, enabling PBA to accurately identify critical paths and perform detailed timing analysis. The PBA method and the STA diagram work together to achieve comprehensive timing analysis, helping designers evaluate and optimize the timing performance of circuits and ensure that circuits meet design specifications and timing constraints.
[0063] Understandably, in order to load PBA onto the GPU, the STA graph needs to be efficiently represented on the GPU. This is achieved by collecting all fan-in edges or incoming edges of each vertex in the STA graph and representing this set as graph G. - Similarly, the set of all sectors or outward edges of each vertex is denoted as graph G+. We use Compacted Sparse Rows (CSR) format to represent G. -And G+. CSR is one of the most commonly used graphics formats in GPU applications. CSR requires three one-dimensional arrays to represent a weighted directed graph. The format includes a vertex array for row offsets, an edge array for column values, and a weight array for the weights of all edges. Therefore, CSR is highly memory efficient. For a graph with N vertices and M edges, the total size of CSR is only N+2M.
[0064] Understandably, candidate paths with the same bias level are assigned to a single thread on the GPU to run. The thread calculates the sub-offset of the last constituent unit of the candidate path in the current level, and the sub-offset is used as the total number of candidate paths to be explored in the next level.
[0065] It should be noted that in path analysis, the sub-offset of a component unit in the path refers to its offset relative to the path's starting point. It describes the offset of each component unit's position relative to the path's starting point, used to accurately determine the signal propagation delay along the path.
[0066] Understandably, the first embodiment of the present invention further includes the step of:
[0067] S31: After obtaining the candidate paths in a level, delete the remaining paths in that level except for the candidate paths through the CPU.
[0068] In step S31, the paths within each level are compressed to remove unnecessary paths and improve memory efficiency. In order to compress the new level before it can be used for the next expansion, the paths are sorted based on path priority. Since the sorted array is not large, it is more efficient to use the CPU to compress each level.
[0069] Understandably, this first embodiment also includes the following steps:
[0070] S32: Obtain the maximum level of the deviation level through the level counter, obtain the candidate path of the current level, and determine whether the maximum level has been reached. If the current level is less than the maximum level, continue to process the next level.
[0071] By maintaining a level counter to record the number of expansion levels, setting a threshold based on GPU capabilities, and stopping iteration when the level counter reaches the threshold, the final candidate path is derived from the implicitly expressed candidate paths on the GPU.
[0072] This first embodiment proposes a novel GPU-accelerated PBA method to overcome the operational bottleneck of CPU-based PBA. By decomposing candidate path generation into multiple GPU-accelerated kernels, the role of each thread is scheduled before timing analysis of candidate paths, avoiding thread contention and deadlocks, thus effectively improving the efficiency of candidate path timing analysis. Furthermore, an implicit path representation method is used to design a GPU-efficient data structure. Threads are assigned to different memory locations, thus eliminating the need for shared data synchronization, and this implicit candidate path representation method improves memory efficiency. Ultimately, this significantly improves the execution speed of PBA, enhances the quality of detection results, and reduces computation time.
[0073] Please see Figure 3 To solve the above-mentioned technical problems, the second embodiment of the present invention also provides an integrated circuit path analysis system 1, comprising:
[0074] The shortest path forest construction module 101 is used to input the timing analysis graph of the integrated circuit on the GPU, obtain the shortest path tree of the node in the timing analysis graph, and merge the shortest path trees to obtain the shortest path forest.
[0075] The forward-looking hierarchical allocation module 102 is used to define candidate paths in the shortest path forest as suffix edges, define candidate paths in the time series analysis graph other than the shortest path forest as deviation edges, the number of deviation edges is represented as the deviation level, and store candidate paths with the same deviation level in an array and allocate them to a thread of the GP U.
[0076] The inter-layer expansion module 103 is used to traverse each candidate path in the current layer, find deviation edges along the candidate path, supplement these deviation edges as sub-edges of the candidate path, obtain the candidate path of the next layer, and iteratively expand along the deviation layer to obtain the final path report.
[0077] The path recovery module 104 is used to input the path report data into the CPU, and restore the explicit candidate path based on the deviation edge and the corresponding suffix edge of the candidate path in the path report, thereby completing the path analysis of the integrated circuit.
[0078] The integrated circuit path analysis system 1 provided in this second embodiment has the same beneficial effects as the integrated circuit path analysis method described above, and will not be described in detail here.
[0079] Please see Figure 4To solve the above-mentioned technical problems, the third embodiment of the present invention also provides a storage medium 2, which includes a memory 201, a processor 202, and a computer program 203 stored on the memory 201 and executable on the processor 202. When the processor 202 executes the computer program 203, it implements the above-mentioned integrated circuit path analysis method and has the same beneficial effects as the above-mentioned integrated circuit path analysis method, which will not be described in detail here.
[0080] To solve the above-mentioned technical problems, the fourth embodiment of the present invention also provides a computer program product, including a computer program / instruction, which is executed by a processor to implement the steps of the path analysis method for integrated circuits, and has the same beneficial effects as the path analysis method for integrated circuits described above, which will not be elaborated here.
[0081] It is understood that, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), it performs the functions defined in the methods of this application. It should be noted that the computer-readable medium described in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. Computer-readable storage media include, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.
[0082] Computer program code for performing the operations of this application can be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, and C++, as well as conventional procedural programming languages such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0083] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.
[0084] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.
[0085] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0086] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0087] Compared with existing technologies, the present invention provides a path analysis method, system, storage medium, and computer program product for integrated circuits. These advantages include:
[0088] 1. The integrated circuit path analysis method of this invention constructs a shortest path forest on the GPU, making the structure of the enumerated paths on the GPU more compact and correspondingly occupying less space. Then, candidate paths in the shortest path forest are hierarchically allocated. Candidate paths with the same deviation level are stored in an array and assigned to a thread on the GPU for execution. This schedules the role of each thread before timing analysis of the candidate paths, avoiding thread contention and deadlocks, effectively improving the efficiency of timing analysis of candidate paths. Furthermore, the sub-edges of the candidate paths are supplemented through hierarchical expansion to obtain the next layer of candidate paths. Threads are assigned to different memory locations, thus eliminating the need for shared data synchronization. This implicit candidate path representation method improves memory efficiency.
[0089] Finally, explicit candidate paths are obtained by explicitly reconstructing the candidate paths in the CPU. Since the number of paths requested and the graph diameter required for the entire path recovery have linear complexity, path recovery can be completed more efficiently in the CPU. This invention decomposes candidate path generation into multiple GPU-accelerated cores and uses implicit path representation methods to design efficient data structures for the GPU, enabling this method to significantly accelerate the timing analysis of integrated circuit paths.
[0090] 2. The integrated circuit path analysis method of the present invention, after obtaining candidate paths in a level, deletes the remaining paths in that level except for the candidate paths by CPU, compresses the paths in each level to delete unnecessary paths and improve memory efficiency, and sorts the paths based on path priority in order to compress them before they can be used in the next expansion in the new level. Since the sorted array is not large, it is more efficient to use CPU to compress each level.
[0091] 3. The present invention also provides a path analysis system for integrated circuits, which has the same beneficial effects as the path analysis method for integrated circuits described above, and will not be elaborated here.
[0092] 4. The present invention also provides a storage medium storing a computer program thereon. When the computer program is executed, it implements the path analysis method of the above-mentioned integrated circuit and has the same beneficial effects as the path analysis method of the above-mentioned integrated circuit, which will not be described in detail here.
[0093] 5. The present invention also provides a computer program product, including a computer program / instructions, which is executed by a processor to implement the steps of the path analysis method for integrated circuits, and has the same beneficial effects as the path analysis method for integrated circuits described above, which will not be elaborated here.
[0094] The foregoing has provided a detailed description of a path analysis method, system, storage medium, and computer program product for an integrated circuit disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A path analysis method for integrated circuits, characterized in that, Includes the following steps: On the GPUI, the shortest path forest is obtained based on the timing analysis graph of the input integrated circuit; Candidate paths in the shortest path forest are defined as suffix edges, and candidate paths in the time series analysis graph other than those in the shortest path forest are defined as deviation edges. The number of deviation edges is represented as the deviation level. Candidate paths with the same deviation level are stored in an array and assigned to a thread of the GP U. Traverse each candidate path in the same deviation level and find deviation edges along the candidate path. Use these deviation edges as sub-edges of the candidate path to supplement it, and obtain the expanded candidate path of the next level. Iterate along the deviation level to obtain the final path report. The path report data is input into the CPU, and the explicit candidate path is obtained by reconstructing the candidate path based on the deviation edge and the corresponding suffix edge of the deviation edge in the path report, thus completing the path analysis of the integrated circuit.
2. The path analysis method for integrated circuits according to claim 1, characterized in that: The clock net of the integrated circuit is represented as a timing analysis diagram. After the timing analysis diagram is stored in a compressed sparse row format, the timing analysis diagram data is transmitted to the GPU, and the timing analysis diagram of the integrated circuit is obtained on the GPU.
3. The path analysis method for integrated circuits according to claim 2, characterized in that: Obtain the shortest path tree of the nodes in the time series analysis graph. Select any node among the nodes that are close to each other in the shortest path tree, and explore only the candidate path with the shortest distance to that node. Delete the other candidate paths in the shortest path tree, and merge the shortest path trees to obtain the shortest path forest.
4. The path analysis method for integrated circuits according to claim 3, characterized in that: After obtaining candidate paths in a level, the CPU deletes the remaining paths in that level that are not candidate paths.
5. The path analysis method for an integrated circuit according to claim 4, characterized in that: Candidate paths with the same deviation level are assigned to a thread in the GP U for execution. In the thread, the sub-offset of the last constituent unit of the candidate path in the current level is calculated. The sub-offset is used as the total number of candidate paths to be explored in the next level.
6. The path analysis method for an integrated circuit according to claim 5, characterized in that: Starting from the level with a deviation level of zero, traverse each candidate path in the current level and find deviation edges along the candidate path. Use these deviation edges as sub-edges of the candidate path to supplement it and obtain the candidate path for the next level.
7. The path analysis method for integrated circuits according to claim 6, characterized in that: The maximum level of the deviation level is obtained by using a level counter. After obtaining the candidate path of the current level, it is determined whether the maximum level has been reached. If the current level is less than the maximum level, the next level is processed.
8. A path analysis system for integrated circuits, characterized in that, include: The shortest path forest construction module is used to input the timing analysis diagram of the integrated circuit into the GPU, obtain the shortest path tree of the node in the timing analysis diagram, and merge the shortest path trees to obtain the shortest path forest; The forward-looking hierarchical allocation module is used to define candidate paths in the shortest path forest as suffix edges, and candidate paths in the time series analysis graph other than those in the shortest path forest as deviation edges. The number of deviation edges is represented by the deviation level. Candidate paths with the same deviation level are stored in an array and assigned to a thread of the GP U for execution. The inter-layer expansion module is used to traverse each candidate path in the current layer, find deviation edges along the candidate path, and supplement these deviation edges as sub-edges of the candidate path to obtain the candidate path of the next layer. The module iteratively expands along the deviation layers to obtain the final path report. The path recovery module is used to input the data from the path report into the CPU, and to restore the explicit candidate path based on the deviation edge and the corresponding suffix edge of the candidate path in the path report, thereby completing the path analysis of the integrated circuit.
9. A storage medium comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, it implements a path analysis method for an integrated circuit as described in any one of claims 1-7.
10. A computer program product comprising a computer program / instructions, characterized in that: The computer program / instructions are executed by the processor to implement the steps of the path analysis method for an integrated circuit as described in claims 1-7.