Core particle verification apparatus, method, medium and program product

Abstract

Embodiments of the present application disclose a kind of core particle verification device, method, medium and program product, comprising: first simulation core particle, second simulation core particle and interface connection module;The first simulation core particle and the second simulation core particle are used to simulate first core particle and second core particle respectively;The first simulation core particle is connected with the second simulation core particle by the interface connection module;The interface connection module is used to simulate the delay characteristic of the physical layer link between the first core particle and the second core particle;The first simulation core particle is used to send verification data;The interface connection module is used to send target verification data to the second simulation core particle;The target verification data is the verification data obtained by delaying the verification data through the interface connection module;The second simulation core particle is used to verify the first core particle and / or second core particle according to the target verification data received.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of chip technology, and in particular to a chip verification device, method, medium, and program product. Background Technology

[0002] With the development of semiconductor technology, chiplet or dielet technology has become a trend in integrated circuit design because it can break down large chips into smaller dieslet, which can then be combined into larger system-on-a-chip (SoC). The interconnect interfaces between dieslet involve complex physical layer communication mechanisms that include analog mixed-signal circuitry. Therefore, dieslet verification is required before tape-out to ensure the performance and yield of the interconnect characteristics between dieslet.

[0003] In related technologies, digital simulation platforms can usually be used to verify the chip system. However, since the physical layer of the chip interface contains analog mixed signal circuits, it is impossible to accurately model them in a digital simulation environment. This makes it difficult to verify the interface behavior and timing characteristics in advance, which in turn affects the verification accuracy and completeness of the chip interconnect characteristics. Summary of the Invention

[0004] In view of this, embodiments of this application provide at least one chip verification device, method, medium, and program product.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] On one hand, embodiments of this application provide a chip verification device, the device comprising: a first simulated chip, a second simulated chip, and an interface connection module;

[0007] The first simulation chip and the second simulation chip are used to simulate the first chip and the second chip, respectively; the first simulation chip communicates with the second simulation chip through the interface connection module; the interface connection module is used to simulate the latency characteristics of the physical layer link between the first chip and the second chip.

[0008] The first simulation chip is used to send verification data;

[0009] The interface connection module is used to send target verification data to the second simulation chip; the target verification data is the verification data obtained after time delay processing of the verification data through the interface connection module.

[0010] The second simulated core is used to verify the first core and / or the second core based on the received target verification data.

[0011] In some embodiments, the interface connection module includes a data channel and a control channel; wherein, the data channel is used to transmit the link training sequence in the verification data to send the target link training sequence after time delay characteristic simulation to the second simulation chip; the control channel is used to send the control signal in the verification data to the second simulation chip, so that the second simulation chip verifies the first chip and / or the second chip according to the control signal and the target link training sequence.

[0012] In some embodiments, the first simulation chip includes a first interface module, and the second simulation chip includes a second interface module, wherein the data channel is configured to: receive the link training sequence sent by the first interface module; simulate the delay characteristics of the physical layer link by simulating a delay circuit to obtain a target link training sequence after delay characteristic simulation; and send the target link training sequence after delay characteristic simulation to the second simulation chip.

[0013] In some embodiments, the simulated delay circuit is used to: perform delay processing on the link training sequence according to the acquired delay control parameters to obtain a target link training sequence after delay characteristic simulation; wherein, the delay control parameters are used to simulate the delay characteristics of the physical layer link.

[0014] In some embodiments, the delay control parameters include fixed offset parameters; the simulated delay circuit is used to: determine the fixed offset parameters of the link training sequence according to the preset delay parameters of the link and the clock frequency; the fixed offset parameters are used to simulate the delay characteristics of the physical layer link; and perform delay processing on the link training sequence according to the fixed offset parameters to obtain the target link training sequence.

[0015] In some embodiments, the delay control parameter includes a jitter intensity parameter; the simulated delay circuit is configured to: generate a corresponding random number at the rising edge of each clock cycle using a preset system function, wherein the random number is normally distributed; and for each clock cycle, perform an XOR operation on the link training sequence within the clock cycle using the random number corresponding to the clock cycle to obtain the target link training sequence after jitter processing within the clock cycle.

[0016] In some embodiments, the delay control parameters include a fixed offset parameter and a jitter intensity parameter; the simulated delay circuit is used to: determine the fixed offset parameter of the link training sequence according to the preset delay parameter of the link and the clock frequency; the fixed offset parameter is used to simulate the delay characteristics of the physical layer link; perform delay processing on the link training sequence according to the fixed offset parameter to obtain a candidate link training sequence; generate a corresponding random number at the rising edge of each clock cycle through a preset system function, wherein the multiple random numbers are normally distributed; for each clock cycle, use the random number corresponding to the clock cycle to perform an XOR operation on the candidate link training sequence within the clock cycle to obtain the target link training sequence after jitter processing within the clock cycle.

[0017] On the other hand, this application provides a chip verification method, which is applied to the interface connection module in the chip verification device provided in the above-described embodiment of this application; the method includes:

[0018] Receive verification data sent by the first simulation chip;

[0019] Target verification data is sent to the second simulation core, so that the second simulation core can verify the first core and / or the second core based on the received target verification data; wherein, the target verification data is the verification data obtained after delaying the verification data through the interface connection module.

[0020] In some embodiments, sending target verification data to the second simulation chip includes: simulating the delay characteristics of the physical layer link through the simulated delay circuit in the interface connection module to obtain a target link training sequence after delay processing; and sending the target link training sequence after delay characteristic simulation to the second simulation chip.

[0021] On the other hand, embodiments of this application provide a computer storage medium storing executable instructions. When the executable instructions are executed by a processor, the processor executes any of the chip verification methods provided in embodiments of this application.

[0022] In another aspect, embodiments of this application provide a computer program product, including a computer program or instructions, which, when executed by a processor, implement any of the chip verification methods provided in embodiments of this application.

[0023] This application provides a chip verification device, comprising: a first simulated chip, a second simulated chip, and an interface connection module; the first simulated chip and the second simulated chip are respectively used to simulate the first chip and the second chip; the first simulated chip communicates with the second simulated chip through the interface connection module; the interface connection module is used to simulate the latency characteristics of the physical layer link between the first chip and the second chip; the first simulated chip is used to send verification data; the interface connection module is used to send target verification data to the second simulated chip; the target verification data is verification data obtained after latency processing of the verification data through the interface connection module; the second simulated chip is used to verify the first chip and / or the second chip based on the received target verification data. In this way, by simulating the latency characteristics of the physical layer link through the interface connection module, simulated latency can be injected into the perfect data stream on the simulation platform. This makes the target verification data received by the second simulation chip no longer ideal perfect data, but data that is closer to the actual situation and has timing deviations. This can fill the gap between digital simulation and hybrid simulation in related technologies. Under digital simulation, the target verification data with injected simulated latency can be used to verify the interconnection protocol, controller logic and error handling mechanism between chips based on real timing. This can improve the accuracy and completeness of the interconnection verification between chips without sacrificing simulation speed.

[0024] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a chip verification device provided in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram illustrating the implementation process of a chip verification method provided in an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of a direct-connection verification architecture proposed in an embodiment of this application;

[0028] Figure 4 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application.

[0029] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0033] Before providing a further detailed description of the embodiments of this application, the nouns and terms used in the embodiments of this application are explained, and the nouns and terms used in the embodiments of this application shall be interpreted as follows:

[0034] 1) UCIe (Universal Chiplet Interconnect Express): A universal chiplet interface standard that supports multiple protocols such as CXL / PCIe and aims to build an open chiplet ecosystem for the same package.

[0035] 2) Chip: refers to a reusable integrated circuit module, which usually contains a fully functional subsystem and interconnects with other chips through standardized interfaces to form a larger-scale system chip.

[0036] 3) Simulated core: A virtual unit used to simulate the behavior of actual cores. It can run in a hardware-accelerated simulation platform to verify the interaction behavior between cores and their timing characteristics.

[0037] 4) Physical Layer Link: In a communication system, this layer is responsible for transmitting data between two nodes, including signal encoding, modulation, demodulation, and synchronization. In the UCIe architecture, the physical layer is mainly composed of analog circuits, making it difficult to accurately model in a digital simulation platform.

[0038] 5) Link Training Sequence: A set of data sequences used to establish and maintain communication links, typically used for operations such as initializing the communication process, calibrating channel parameters, and detecting connection status.

[0039] 6) Delay Characteristics: These describe the time delay characteristics experienced by a signal during transmission, including fixed offset and jitter. Fixed offset indicates that the signal arrives at the receiver after a fixed time delay; jitter is the uncertainty of the signal arrival time within a clock cycle, which usually conforms to a Gaussian distribution.

[0040] 7) Programmable Delay Module: A module that can be configured and adjusted on a hardware acceleration platform to simulate the latency characteristics of physical layer links. This module supports setting fixed offset and jitter intensity parameters, thereby more realistically reflecting the behavior of the actual physical layer.

[0041] 8) Link Training Loop: In a communication system, this refers to the process by which the transmitting and receiving ends exchange link training sequences to complete link initialization and parameter calibration. This process is a crucial step in ensuring communication stability and reliability.

[0042] 9) Pre-silicon Verification: This refers to the functional, performance, and timing verification performed before chip tape-out. Its purpose is to discover and fix design defects before chip manufacturing and improve tape-out success rate.

[0043] Currently, chiplets are a technology that breaks down large system-on-a-chip (SoC) into multiple small chip modules with specific functions, and then integrates them through packaging technology. Its working principle involves using interconnect technologies such as through-silicon vias (TSVs) and microbumps, as well as 2.5D and 3D packaging technologies, to achieve high-speed communication and collaborative operation between chips with different functions (such as computing, storage, and I / O) to form a complete chip system.

[0044] Since the advantage of Chiplet relies on reliable communication between chips, the interconnect characteristics between chips need to be verified. In related technologies, thorough simulation verification is typically performed before chip fabrication. This not only ensures chip performance and yield but also allows for timely modifications if problems are discovered, preventing issues from arising after fabrication and thus avoiding increased R&D costs.

[0045] Therefore, the interconnect characteristics between chips can be thoroughly simulated and verified using a digital simulation platform. Chips can be interconnected via interconnect interfaces, which are complex protocol stacks. The bottom layer is the Physical Layer (PHY), which is responsible for handling how raw 0 and 1 signals are transmitted over physical media (such as silicon interposers and redistribution layers). To achieve high-speed, low-power data transmission, the PHY layer extensively uses analog mixed-signal circuits. Digital simulation platforms typically employ event-driven or period-based simulation methods, primarily using four logic values: 0, 1, X (unknown), and Z (high impedance) to describe signals. However, the analog portion of analog mixed-signal circuits needs to consider continuous voltage and current changes, making accurate modeling impossible in a digital simulation environment. For example, the noise and distortion characteristics of analog signals are difficult to accurately represent in digital simulation.

[0046] Because analog mixed-signal circuits cannot be accurately modeled, the behavior and timing characteristics of the chip-to-chip interface are difficult to verify in advance. For example, timing issues such as delays and jitter in signal transmission between chips, as well as signal integrity issues under different operating conditions, cannot be accurately analyzed and verified on a digital simulation platform, thus affecting the accuracy and completeness of the verification of chip-to-chip interconnect characteristics.

[0047] To address the aforementioned issues, this application provides a chip verification device, method, medium, and program product. It can simulate the latency characteristics of physical layer links through an interface connection module, injecting simulated latency into a perfect data stream on a simulation platform. This ensures that the target verification data received by the second simulated chip is no longer ideally perfect data, but rather data closer to reality with timing deviations. This fills the gap between digital simulation and hybrid simulation in related technologies. In the case of digital simulation, it allows for the use of target verification data with injected simulated latency to perform real-time-based verification of interconnect protocols, controller logic, and error handling mechanisms between chips. This improves the accuracy and completeness of interconnect verification between chips without sacrificing simulation speed.

[0048] The chip verification apparatus provided in the embodiments of this application can be executed by electronic devices on a hardware acceleration simulation platform. These electronic devices can be virtual machines, hardware accelerators (such as Palladium), or chip design platforms integrating UCIe Adapter modules. That is, the chip verification methods in the embodiments of this application can be executed by running a simulation environment in a virtual machine, by performing real-time simulation using a hardware accelerator, or by deploying multiple UCIe Adapter modules on a hardware acceleration platform for system-level verification.

[0049] Figure 1 This is a schematic diagram of the structure of a chip verification device provided in an embodiment of this application, as shown below. Figure 1 As shown, the chip verification device 100 provided in this application embodiment may include the following components: a first simulated chip 101, a second simulated chip 102, and an interface connection module 103.

[0050] The first simulation chip 101 and the second simulation chip 102 are used to simulate the first chip and the second chip, respectively; the first simulation chip 101 communicates with the second simulation chip 102 through the interface connection module 103; the interface connection module 103 is used to simulate the delay characteristics of the physical layer link between the first chip and the second chip.

[0051] The simulated cores in this application embodiment are all used to simulate the behavior of actual cores. They can be virtual cores constructed through digital modeling, or software or hardware representations of real cores on a verification platform. The first simulated core 101 can be a master or initiator core; the second simulated core 102 can be a slave or target core.

[0052] For example, if the first core is a computing core (such as a GPGPU computing core) and the second core is a storage core (such as an HBM controller), then the first simulation core 101 needs to reproduce the logic of computing instruction generation and data transmission request; the second simulation core 102 needs to reproduce the logic of storage address resolution and data reception response; both contain physical layer signal encoding / decoding modules (such as NRZ encoding, 8b / 10b encoding) to simulate the signal transmission / reception behavior of the real core.

[0053] For example, if the first core is a computing core (such as a GPGPU computing core), and the second core can be an input / output core (such as an input / output connection core), then the first simulation core 101 needs to reproduce the parallel computing scheduling, data operation, and interaction control logic with the IO core of the GPGPU computing core, and the second simulation core 102 needs to reproduce the protocol parsing, data encoding and decoding, Ethernet frame forwarding, and bandwidth management logic of the IO connection core, in order to simulate an Ethernet switching scenario.

[0054] Since the physical layer links between chips (such as the silicon interposer in 2.5D packaging and the TSV in 3D packaging) limit the interconnect performance between chips, that is, the latency characteristics of the physical layer links between chips directly determine the timing convergence of chip communication (such as whether the setup time / hold time is satisfied), the interface connection module 103 in this embodiment can simulate the latency characteristics of the physical layer links between the first chip and the second chip to avoid verification failure caused by ignoring the actual link latency.

[0055] In this embodiment, the first simulation chip 101 can be used to send verification data.

[0056] Verification data refers to the data set used to test the communication behavior between the first and second core components. It typically includes link training sequences, protocol handshake signals, and functional test data. For example, during UCIe link initialization, verification data may include, but is not limited to, link training requests, status reports, and error injections to ensure that the Adapter module can correctly respond to communication behaviors in various scenarios.

[0057] The verification data transmitted by the first simulation chip 101 may include, but is not limited to, various types of data packets conforming to interconnection protocol standards such as UCIe, stress test data, error detection code data, and sideband signal simulation. Among them, data packets can be used to test the logical correctness of the protocol controller; stress test data can be used to push the link to its performance limits; error detection code data can be used to test whether the error detection and retransmission mechanism of the receiver is working properly; and sideband signal simulation can be used to simulate the behavior of sideband signals such as reset and power state switching, and test the stability of the link under abnormal conditions.

[0058] The first simulation chip 101 sends verification data to provide a controllable input for the entire chip verification device. When the verification data reaches the second simulation chip 102 through the interface connection module 103 that simulates physical layer distortion, it will become distorted data injected with simulated time delay. The second simulation chip 102 can then accurately quantify the impact of physical layer effects by comparing the sent data and the received distorted data.

[0059] For example, when the first simulation core 101 sends a link training sequence to the second simulation core 102, the second simulation core 102 and the interface connection module 103 can simulate the training process. The effectiveness of the link training algorithm can be verified by observing how the controller of the first simulation core 101 adjusts parameters (such as equalizer settings) to adapt to the channel simulated by the interface connection module 103.

[0060] In this embodiment, the interface connection module 103 can be used to send target verification data to the second simulation core 102.

[0061] The target verification data is obtained by delaying the verification data through the interface connection module 103. Delay processing involves superimposing the actual physical layer link delay onto the target verification data in the time dimension, ensuring that the transmission time of the verification data, the arrival time of the target verification data, and the signal edge timing are consistent with the effect of inter-chip transmission in the actual hardware. The target verification data not only retains the functional verification capability of the verification data but also adds timing verification capability.

[0062] Delay processing simulates the actual delay of the physical layer link between chips in real hardware. Delay can include, but is not limited to, basic propagation delay and signal jitter. Basic propagation delay refers to the fundamental time required for a signal to travel through a physical medium (such as traces on a silicon interposer), and this time can be a constant. Signal jitter refers to short-term variations in the time deviation of a signal edge from its ideal position, such as random jitter and deterministic jitter. Random jitter can be caused by random noise following a Gaussian distribution, while deterministic jitter can be caused by identifiable interference sources such as switching power supply noise and crosstalk.

[0063] Therefore, the interface connection module 103 can reconstruct the time attributes of the data in multiple dimensions based on the characteristics of the real physical layer link to ensure that the latency characteristics of the target verification data are consistent with those of the real link. For example, the interface connection module 103 can simulate the latency mentioned above using a programmable latency model to ensure that the latency characteristics of the target verification data are consistent with those of the real link.

[0064] In one possible implementation, the interface connection module 103 can pre-calculate the total latency value that the verification data should be superimposed during transmission based on preset real link parameters. The preset real link parameters can be parameters obtained by operators through testing with actual chips of the same packaging design. For example, real link parameters may include, but are not limited to, link length, dielectric constant, link spacing, temperature, and linewidth. In specific implementations, the interface connection module 103 can calculate the total latency based on the inherent latency of the preset real link parameters themselves. After calculating the total latency (e.g., 9ns), the interface connection module 103 will perform time offset processing on the verification data. For example, it can wait for the preset total latency time before sending the data to the second simulation chip 102.

[0065] It should be noted that the accuracy of the delay superposition must be consistent with the simulation step size. For example, if the simulation step size is 1ps, then the delay control accuracy must reach 1ps. This can avoid timing distortion due to insufficient accuracy. Also, if the first simulation chip 101 continuously sends multiple frames of data (e.g., one frame every 10ns), the interface connection module 103 needs to superimpose the same total delay (e.g., 9ns) on each frame of data to ensure that the inter-frame interval (10ns) remains unchanged. This can simulate the characteristic of consistent data transmission time for each frame in a real link.

[0066] In real-world data links, latency not only manifests as an overall time offset but also causes timing distortions at signal edges; for example, longer rise and fall times, and signal jitter. If signal edges are too slow, the signal may be unstable during sampling, leading to misjudgments.

[0067] Therefore, in another possible implementation, the delay processing of the interface connection module 103 also includes simulation of signal timing distortion. This timing distortion simulation may include, but is not limited to, edge delay distortion and signal jitter.

[0068] Due to crosstalk and reflection effects in the real physical link, the rise time of the original signal (e.g., 50 ps) will become longer (e.g., 60 ps) during the transmission of verification data. Therefore, the interface connection module 103 can adjust the signal edge of the target verification data to 60 ps through a preset edge reconstruction algorithm to simulate the edge degradation of the real link. The edge reconstruction algorithm can decompose the voltage-time curve of the ideal edge of the original signal into multiple time stages, and adjust the voltage change rate of each stage to ultimately achieve the target rise / fall time (e.g., 60 ps).

[0069] Moreover, when transmitting data signals in a real physical link, the latency of each data frame will fluctuate slightly (e.g., ±0.3ps). Therefore, the interface connection module 103 can add random jitter (e.g., 9ns ± 0.3ps) on the basis of the total latency (9ns) to make the arrival time of the target verification data fluctuate reasonably, and test the tolerance of the second simulation chip 102 to jitter.

[0070] It should be noted that after receiving the verification data, the interface connection module 103 does not passively forward the verification data, but actively performs time delay processing on the verification data and actively sends the target verification data obtained after time delay processing to the second simulation chip 102. This not only ensures the independence of time delay processing, but also guarantees the authenticity of the verification scenario and avoids the interface connection module 103 receiving logical interference from the first simulation chip 101 and the second simulation chip 102.

[0071] In this embodiment, the second simulated core 102 can be used to verify the first core and / or the second core based on the received target verification data.

[0072] The function of the first simulation chip 101 is to generate and send verification data that meets the design requirements. The second simulation chip 102 can verify that the sending capability of the first simulation chip 101 (corresponding to the real first chip) meets the indicators by analyzing the content integrity, protocol compliance, and transmission timing stability of the target verification data.

[0073] In one possible implementation, the second emulation core 102 can perform content correctness verification to determine that the data sent by the first emulation core 101 (corresponding to the first core) is error-free.

[0074] In some embodiments, the second simulation chip 102 extracts the core content (such as valid data and check code) from the target verification data and compares it with the expected value of the pre-synchronized original verification data to determine whether the first simulation chip 101 (corresponding to the first chip) has a transmission error.

[0075] Firstly, it allows for valid data comparison. Specifically, if the valid data in the original verification data is 0x12345678, while the valid data extracted from the target verification data is 0x12345679 (a bit error), it indicates that there is a defect in the data generation logic or transmission driver module of the first chip (such as encoding error or signal output error).

[0076] Secondly, checksum comparison can be performed. Specifically, if the CRC checksum of the target verification data is inconsistent with the expected CRC code calculated based on the valid data (excluding errors caused by link noise), it indicates that the checksum generation logic of the first core is incorrect (such as a CRC polynomial configuration error).

[0077] In this way, by performing simulation verification on a hardware simulation platform, the risk of errors in the data sent by the actual first chip can be exposed in advance (such as bit flipping in the protocol frame sent by the first chip after tape-out, which will cause the second chip to be unable to receive it normally).

[0078] In another possible implementation, the second emulation chip 102 can perform protocol compliance verification to confirm that the format sent by the first emulation chip 101 (corresponding to the first chip) conforms to the specification.

[0079] In some embodiments, since the interconnection of core particles needs to follow a fixed protocol (such as UCIe, PCIe), the verification data sent by the first emulated core particle 101 (corresponding to the first core particle) must meet the frame structure, field meaning, and interaction logic specified by the protocol. The second emulated core particle 102 can verify whether the protocol implementation of the first emulated core particle 101 (the first core particle) is compliant by parsing the protocol fields of the target verification data.

[0080] Firstly, frame structure verification can be performed. Taking the UCIe protocol as an example, the protocol requires the frame structure to be a synchronization header (8 bits) + frame type (4 bits) + data length (8 bits) + valid data (n bits) + CRC (16 bits). If the target verification data is missing a synchronization header or the frame type field is incorrect, it indicates that the protocol frame construction logic of the first core is in violation.

[0081] Secondly, it can perform interactive logic verification. For example, if the verification scenario is that the first core sends a link initialization request frame and needs to wait for the response frame from the second core before sending a data frame, if the second simulation core 102 does not return a response frame but receives the data frame sent by the first core, it indicates that the protocol interaction logic of the first core is in violation of the "request before data" time sequence.

[0082] This ensures that the protocol implementation of the true first chip conforms to industry standards, avoiding the inability to interconnect with other chips (such as third-party second chips) due to protocol violations.

[0083] In another possible implementation, the second simulation chip 102 can perform transmission timing stability verification to confirm that the transmission rhythm of the first chip meets the requirements.

[0084] In some embodiments, since the transmission timing of the first chip (such as frame interval, burst transmission frequency) needs to meet design constraints (such as transmitting one frame every 10ns, and burst transmission not exceeding 100 frames), the second simulation chip 102 can determine whether the transmission timing of the first chip is stable by recording the actual arrival time of the target verification data.

[0085] Firstly, frame interval verification can be performed. Specifically, if the expected frame interval is 10ns (original data is transmitted at T=10ns, 20ns, and 30ns), then the expected arrival times of the target data are 10.006ns, 20.006ns, and 30.006ns. If the actual arrival time intervals are 10ns, 9.5ns, and 10ns (a certain frame interval is shortened), it indicates that there are fluctuations in the transmission timing controller of the first chip (such as excessive clock jitter).

[0086] Secondly, burst transmission verification can be performed. For example, if the design requires the first core to continuously transmit a maximum of 100 frames of burst data, and the second simulated core 102 receives 101 frames of continuous data, it indicates that the burst length control logic of the first core is incorrect (the burst stop mechanism has not been triggered).

[0087] This avoids the second core from being overloaded due to unstable transmission timing caused by the first core (e.g., if the frame interval is too short, the receiver cannot process the data in time, resulting in data loss).

[0088] The function of the second simulation chip 102 is to correctly receive and process the target verification data. The second simulation chip 102 can verify whether its receiving capability meets the standard by the execution result of its own receiving logic.

[0089] In one possible implementation, the second simulation chip 102 can perform receive resolution capability verification to ensure that the second chip can process data correctly.

[0090] In some embodiments, the second emulation chip 102 can resolve target verification data with time delay distortion (such as edge degradation to 60ps and the presence of minor jitter) into a signal recognizable by digital logic. The success rate of this process can directly reflect the receiving and resolving capability of the second emulation chip 102.

[0091] Firstly, signal sampling verification can be performed. Specifically, edge degradation of the target verification data (such as a rise time of 60ps) will cause the signal to be unstable at the sampling time. If the second simulation chip 102 uses the rising edge of the clock for sampling and can accurately sample the correct logic level (0 / 1), it indicates that its sampling window design is reasonable (such as avoiding the unstable signal region at the sampling time).

[0092] Secondly, data decoding verification can be performed. Specifically, if the target verification data uses 8b / 10b encoding (such as UCIe physical layer), the second simulation chip 102 needs to decode the 10-bit encoded data into 8-bit raw data. If the decoding result is consistent with expectations, it indicates that its decoding logic is correct; if the decoding is incorrect (such as incorrectly decoding 1011000110 as 0x3A instead of 0x3B), it indicates that there is a defect in the decoding module.

[0093] This ensures that the real second core can correctly parse the data sent by the first core in real-world scenarios with link delay distortion, avoiding data loss due to reception and parsing errors.

[0094] In another possible implementation, the second simulation chip 102 can be used to verify timing tolerance capabilities to confirm that the second chip can adapt to link delay fluctuations.

[0095] In some embodiments, since the latency of the real link is not a fixed value (e.g., temperature changes cause latency fluctuations of ±0.3ps), the second simulation chip 102 needs to have timing tolerance capabilities so that it can receive the target verification data stably even if the arrival time of the target verification data fluctuates.

[0096] Firstly, setup time / hold time can be verified. Specifically, if the design requires the second chip to have a setup time Tsu = 0.5ns (data needs to be stable 0.5ns before the rising edge of the clock) and a hold time Th = 0.2ns (data needs to remain stable 0.2ns after the rising edge of the clock), but the target verification data fluctuates due to latency, resulting in an actual setup time of 0.4ns (less than 0.5ns), the second simulation chip 102 can still sample correctly, indicating that its timing margin design is sufficient (tolerating fluctuations of 0.1ns). If sampling errors occur, it indicates that the timing margin is insufficient, and the receiver clock design needs to be optimized.

[0097] Secondly, jitter tolerance verification can be performed. Specifically, if the target verification data has a jitter of ±0.3ps (the arrival time fluctuates between 10.0057ns and 10.0063ns), the second simulation chip 102 needs to maintain correct sampling within this fluctuation range. If the bit error rate increases (e.g., >1e-12), it indicates a design defect in its jitter suppression logic (e.g., the clock data recovery (CDR) module).

[0098] This ensures that the real second chip can still work stably under real-world conditions of link latency fluctuations, avoiding timing violations caused by environmental changes.

[0099] By adopting the above technical solution, the interface connection module 103 simulates the latency characteristics of the physical layer link, and can inject simulated latency into the perfect data stream on the simulation platform. This makes the target verification data received by the second simulation chip 102 no longer ideal perfect data, but data that is closer to the actual situation and has timing deviations. This can fill the gap between digital simulation and hybrid simulation in related technologies. In the case of digital simulation, the target verification data with injected simulated latency can be used to verify the interconnection protocol, controller logic and error handling mechanism between chips based on real timing. This can improve the accuracy and completeness of the interconnection verification between chips without sacrificing the simulation speed.

[0100] In some embodiments, considering that the first and second cores cannot directly transmit data at high speed after the real core system is powered on, interconnection parameter calibration must be completed through link training first to ensure the stability of subsequent data transmission. In order to reproduce the independent logic of training sequence transmission and training process control in simulation, the interface connection module 103 may include a data channel and a control channel.

[0101] The data channel is responsible for transmitting training data, while the control channel is responsible for controlling the training process.

[0102] In this embodiment, the data channel can be used to transmit the link training sequence in the verification data, so as to send the target link training sequence after the delay characteristics are simulated to the second simulation chip 102, so as to ensure that the target link training sequence received by the second simulation chip 102 is consistent with the real hardware scenario.

[0103] The link training sequence is a calibration signal generated by the first simulation core 101. Unlike ordinary data frames, it is used to enable the second simulation core 102 (corresponding to the second core) to perform parameter measurement and calibration.

[0104] During the link training phase, the interconnection between the first and second cores is still in an initial uncalibrated state, exhibiting significant latency fluctuations. Link training is required to reduce these latency fluctuations. However, burst transmissions of ordinary data frames may interrupt the training. Therefore, during this phase, the data channel can be controlled to transmit only the link training sequence and not other control signals, thus avoiding interference with the training process.

[0105] In this embodiment, the control channel can be used to send the control signal in the verification data to the second simulation chip 102, so that the second simulation chip 102 verifies the first chip and / or the second chip according to the control signal and the target link training sequence.

[0106] Control signals are instructions or status information used to manage the training process of the link. Since the value of control signals lies in their meaning rather than their timing, they need to be received accurately to verify the correctness of the logic. If the control signals themselves are corrupted due to latency and jitter, the entire training process cannot be synchronized, and it will be impossible to distinguish whether the problem is with the control logic or the physical layer.

[0107] During the link training process, the data channel and the control channel can work together in a timing-based manner to simulate the real link training process, so that the second simulation core 102 can verify the first core and / or the second core according to the control signal and the target link training sequence.

[0108] In this way, by setting up the interface connection module 103, including the data channel and the control channel, the architecture of separating control and data in the link training of real chip interconnect can be reproduced; and verification can be performed during the link training stage. If there are defects in the training stage (such as the first chip instruction error or the second chip calibration failure), all subsequent data transmissions will fail; and the dual-channel design can enable the second simulation chip 102 to expose these defects in advance, avoiding the failure of the chip to complete initialization after power-on after tape-out, which would ultimately lead to the paralysis of the entire system.

[0109] In some embodiments, the first simulation chip 101 includes a first interface module, and the second simulation chip 102 includes a second interface module.

[0110] In this embodiment, the data channel can be used to receive the link training sequence sent by the first interface module; then, the delay characteristics of the physical layer link are simulated by the simulated delay circuit to obtain the target link training sequence after the delay characteristics are simulated; and the target link training sequence after the delay characteristics are simulated is sent to the second interface module of the second simulation chip 102.

[0111] The interface module can be obtained by simulating the digital part of the SerDes (Serializer / Deserializer) interface module of the real chip in the relevant technology.

[0112] The SerDes interface module of a real chip includes digital and analog sections. The digital section is typically a digital adapter interface, and the analog section is typically a PHY (Physical Layer). Real chips can interconnect through the digital adapter interface and the PHY to achieve high-speed data transmission. However, since the PHY section usually includes a Physical Medium Adapter (PMA) layer and a Physical Medium Dependent Layer (PMD), and the PMA is a mixed-signal CML / CMOS circuit, the analog section cannot be simulated on a simulation verification platform.

[0113] In this embodiment, since the first and second cores are interconnected through the SerDes interface in a real physical environment, and the analog part of the SerDes interface cannot be simulated, when simulating the real first and second cores through the Palladium console, only the digital part of the SerDes interface can be simulated, while the analog part can be commented out and the analog part code can be left running.

[0114] Instead, a specially designed, configurable interface module 103 can be used to replace the original analog PHY function. This module can simulate the main timing characteristics of the real physical layer through behavioral-level modeling, including but not limited to signal propagation delay, random jitter, deterministic jitter, and channel loss.

[0115] Specifically, the digital signal (verification data) generated by the first simulation chip 101 no longer enters the unsimulated analog PHY circuit, but is instead imported into this interface connection module 103. This module applies corresponding timing perturbation processing to the ideal digital signal according to the preset physical model parameters, generates target verification data that approximates the real physical characteristics, and transmits it to the second simulation chip 102.

[0116] This approach avoids the efficiency issues associated with directly simulating analog circuits while providing a highly realistic physical layer timing environment for verifying the digital components, thus enabling comprehensive verification of the SerDes interface's functionality and performance. This method ensures thorough verification of the interconnect reliability before tape-out, significantly reducing development risks.

[0117] In some embodiments, the simulated delay circuit can be used to perform delay processing on the link training sequence according to the acquired delay control parameters, so as to obtain the target link training sequence after delay characteristic simulation.

[0118] The delay control parameters are used to simulate the latency characteristics of the physical layer link. They can be a set of quantitative metrics used to accurately describe the physical characteristics of a real physical layer link. Adjusting these parameters is equivalent to designing a specific physical link in the simulation platform.

[0119] Delay control parameters may include, but are not limited to, basic transmission parameters, parasitic load parameters, interference and loss parameters, and environmental and process parameters. Basic transmission parameters may be parameters used to control the propagation speed of signals in the medium, such as link length and dielectric constant; parasitic load parameters may be parameters used to reflect the RC and RLC load effects of the link, such as parasitic capacitance, parasitic resistance, and parasitic inductance; interference and loss parameters may be parameters used to reflect crosstalk (i.e., signal interference), such as spacing between adjacent signal lines and line width; environmental and process parameters may be parameters that can affect device performance, such as temperature and supply voltage.

[0120] In some embodiments, delay control parameters can be obtained in the following ways:

[0121] Method 1: After the chip / package design layout is completed, electromagnetic field simulation software (such as HFSS) can be used to directly calculate the link's time delay, impedance, and other characteristics.

[0122] Method 2: After making the test circuit board or chip, use instruments such as a network analyzer (VNA) and oscilloscope to directly measure the parameters of the actual link;

[0123] Method 3: You can pre-generate a lookup table (LUT) from the simulation or measurement results under different conditions (such as temperature and voltage), and then directly look up the table as needed to quickly obtain the parameters during simulation verification.

[0124] In this embodiment, the simulated delay circuit can obtain a set of delay control parameters from the verification platform or other control devices. The simulated delay circuit can convert the aforementioned delay control parameters into specific control signals for the underlying circuit through an internally configured parameter parsing device. For example, at a temperature of 85°C, this can be parsed as increasing the control voltage of the first variable resistor by 5 millivolts, since an increase in temperature is equivalent to an increase in resistance. Then, the internal structure of the simulated delay circuit can be adjusted according to the parsed control signals.

[0125] In one possible implementation, the analog delay circuit may include multiple switchable RC units or transmission segments. A control word derived from the delay control parameters can be used to control the switches, thereby connecting different numbers or values ​​of RC units. For example, a 4-bit control word can control the connection of 0 to 15 RC units, thereby achieving 16 different delay levels.

[0126] In another possible implementation, the simulated time delay circuit can be a high-precision model generated by an electromagnetic field simulation tool. The model itself contains mathematical descriptions of physical parameters such as length, dielectric constant, linewidth, and spacing. The delay control parameters are directly used as inputs, substituted into the model's formulas for calculation, thereby dynamically generating the corresponding time delay and waveform distortion.

[0127] When the delay control parameters include fixed offset parameters, the analog delay circuit can be used to determine the fixed offset parameters of the link training sequence based on the preset delay parameters and clock frequency of the link; then, the link training sequence is delayed according to the fixed offset parameters to obtain the target link training sequence.

[0128] The fixed offset parameter is used to simulate the latency characteristics of the physical layer link. It can be a fixed delay time set for the link training sequence, which can correspond to the basic transmission latency of the physical layer link.

[0129] First, we can obtain the basic physical data of the link. This data can come from the earlier design or simulation. For example, it is known that the link is a 1mm long silicon interposer, and the signal propagation speed in silicon is approximately 1.5 × 10⁻⁶. 8 Therefore, the basic delay of the link itself can be directly calculated as link length / signal propagation speed. Since the transmission of the link training sequence must be synchronized with the core clock, the fixed offset parameter must be an integer multiple or a reasonable fractional multiple of the clock period to avoid disrupting timing synchronization. For example, if the preset link delay parameter is 6.7 ps and the clock period is 1 ns (1000 ps), 6.7 ps is much smaller than the clock period and no adjustment is needed; simply set the fixed offset parameter to 6.7 ps. If the preset link delay parameter is 1.2 ns and the clock period is 1 ns, it can be fine-tuned to 1 ns (or 1.2 ns, as long as it does not exceed the tolerance range of clock synchronization) to ensure that the training sequence can still be accurately sampled by the clock of the second simulation core 102 after the delay. After calibrating the preset link delay parameter to a reasonable value that conforms to the clock frequency, the final fixed offset parameter can be obtained.

[0130] After obtaining the fixed offset parameters, the analog delay circuit can convert the fixed offset parameters into corresponding control words according to a preset correspondence. Different fixed offset parameters can correspond to different control words.

[0131] By employing the above technical solution and setting a fixed offset parameter, a fixed delay caused by differences in channel length in the physical layer link can be simulated. This method can effectively reproduce the delay differences caused by different cabling paths in a real environment, thereby improving the accuracy and practicality of the verification.

[0132] When the delay control parameters include jitter intensity parameters, the analog delay circuit can be used to generate corresponding random numbers at the rising edge of each clock cycle through a preset system function. The multiple random numbers are normally distributed. For each clock cycle, the random number corresponding to the clock cycle is used to perform an XOR operation on the link training sequence within the clock cycle to obtain the target link training sequence after jitter processing within the clock cycle.

[0133] First, a random jitter sequence can be generated. Specifically, based on the jitter intensity parameter, a pseudo-random number generator can generate a normally distributed random number sequence. The generation rate of this sequence is synchronized with the bit period of the link training sequence. Then, a jitter effect can be applied to the validation data. Specifically, the random number corresponding to each bit period is used as a decision variable. When the absolute value of this random number exceeds a preset threshold determined by the jitter intensity parameter, a sampling error caused by jitter is determined to have occurred in that bit period. Next, jitter injection is performed. Specifically, for the bit period where an error is determined to have occurred, a logical XOR operation (e.g., XOR with logical '1') is performed on the corresponding bit in the original link training sequence, thereby flipping the bit and generating the target link training sequence after jitter processing in that bit period.

[0134] By introducing jitter intensity parameters and a random number generation mechanism, the random jitter effects caused by factors such as clock instability in the physical layer link can be simulated. This approach can more realistically reproduce timing fluctuations in actual links, thereby improving the reliability of verification results.

[0135] By employing the above technical solution and adjusting latency processing through latency control parameters, the latency characteristics of different links can be flexibly configured to meet diverse verification needs. This approach not only improves the flexibility of verification but also enhances the coverage of test cases, thereby better simulating real-world application scenarios.

[0136] In some embodiments, the delay control parameters may include a fixed offset parameter and a jitter intensity parameter; the simulated delay circuit can determine the fixed offset parameter of the link training sequence according to the preset delay parameter of the link and the clock frequency; the fixed offset parameter is used to simulate the delay characteristics of the physical layer link; then the link training sequence is delayed according to the fixed offset parameter to obtain a candidate link training sequence; a corresponding random number is generated at the rising edge of each clock cycle through a preset system function, and the multiple random numbers are normally distributed; for each clock cycle, the candidate link training sequence within the clock cycle is XORed using the random number corresponding to the clock cycle to obtain the target link training sequence after jitter processing within the clock cycle.

[0137] In this embodiment, obtaining the candidate link training sequence can refer to the steps in the above embodiments where the delay control parameters include a fixed offset parameter to obtain the target link training sequence, and the specific details will not be repeated here. Obtaining the target link training sequence can refer to the steps in the above embodiments where the delay control parameters include a jitter intensity parameter to obtain the target link training sequence, and the specific details will not be repeated here.

[0138] By employing the above technical solution, combined with fixed offset and jitter processing, various latency characteristics in the physical layer link can be comprehensively simulated. This approach retains a fixed latency basis while incorporating dynamically changing jitter components, thus more closely resembling the real environment and improving the effectiveness of verification.

[0139] Based on the foregoing embodiments, this application provides a chip verification method. The method is applied to an interface connection module in a chip verification device, which includes an interface connection module, a first simulated chip, and a second simulated chip. Figure 2 As shown, the method may include the following steps S201 to S203.

[0140] Step S201: Receive the verification data sent by the first simulation chip.

[0141] Step S202: Send target verification data to the second simulation chip so that the second simulation chip can verify the first chip and / or the second chip according to the received target verification data; wherein, the target verification data is the verification data obtained after delaying the verification data through the interface connection module.

[0142] By adopting the above technical solution, the latency characteristics of the physical layer link can be simulated through the interface connection module. Simulated latency can be injected into the perfect data stream on the simulation platform, so that the target verification data received by the second simulation chip is no longer ideal perfect data, but data that is closer to the actual situation and has time deviation. This can fill the gap between digital simulation and hybrid simulation in related technologies. Under the condition of digital simulation, the target verification data with injected simulated latency can be used to verify the interconnection protocol, controller logic and error handling mechanism between chips based on real timing. The accuracy and completeness of the interconnection verification between chips can be improved without sacrificing the simulation speed.

[0143] In some embodiments, step S202 can be implemented by steps S2021 and S2022:

[0144] Step S2021: Simulate the delay characteristics of the physical layer link through the simulated delay circuit in the interface connection module to obtain the target link training sequence after delay processing.

[0145] Step S2022: Send the target link training sequence after time delay characteristic simulation to the second simulation chip.

[0146] By adopting the above technical solution, through the interface connection module including the data channel and the control channel, the control and data separation architecture of link training in real chip interconnect can be reproduced; and verification can be performed during the link training stage. If there are defects in the training stage (such as the first chip instruction error or the second chip calibration failure), all subsequent data transmissions will fail; and the dual-channel design can expose these defects in advance in the second simulation chip, avoiding the failure of the chip to complete initialization after power-on after tape-out, which would ultimately lead to the paralysis of the entire system.

[0147] In this application, specific implementation methods can be referred to the description of any of the foregoing chip verification devices. The descriptions of the above method embodiments are similar to those of the above device embodiments and have similar beneficial effects. For technical details not disclosed in the method embodiments of this application, please refer to the description of the device embodiments of this application for understanding.

[0148] The following describes the application of the chip verification device provided in the embodiments of this application in a real-world scenario, mainly involving a pre-silicon verification method for inter-chip UCIe Adapter interconnects.

[0149] In this embodiment, efficient and realistic interconnect verification can be achieved by skipping physical layer simulation on a simulation verification platform and programming a delay module. The delay module is used to accurately reproduce the physical layer transmission delay characteristics.

[0150] In related technologies, the core verification bottleneck faced by UCIe technology lies in the fact that its PHY layer contains a large number of analog mixed-signal circuits, making it difficult to perform high-precision modeling in digital simulation platforms (such as Palladium). This limitation leads to a series of verification challenges: First, the functional and performance verification of the adapter digital control module heavily relies on post-silicon verification after tape-out, greatly increasing project risks and debugging difficulty; second, the verification of multi-chip system-level interconnect scenarios is severely delayed, requiring comprehensive evaluation only after silicon integration, significantly impacting system integration and time-to-market; finally, the inability to fully conduct multi-chip chiplet collaborative testing in the early stages significantly extends the overall testing cycle.

[0151] The main reason for the above problems is that traditional digital verification schemes cannot effectively simulate key timing characteristics of the physical layer (such as signal jitter, transmission delay, and channel loss), resulting in a significant gap between the simulation environment and real physical behavior. Existing typical verification methods all have obvious defects: simulation using PHY behavior models often lacks timing accuracy, causing distortion of the verification scenario and making it difficult to reflect the real link condition; software simulation based on EDA dynamic verification (DV) tools is slow and cannot effectively cover large-scale system-level scenarios; while FPGA prototype verification schemes have inherent limitations such as long construction cycles, high iteration costs, and difficulty in accurately simulating circuit characteristics.

[0152] In order to solve the fundamental bottleneck that the UCIe PHY layer cannot be accurately modeled in the digital simulation platform, and the resulting serious blockage in the chip verification process, this application proposes an adapter interface direct connection verification architecture. Figure 3 This is a schematic diagram of a direct-connection verification architecture proposed in an embodiment of this application, as shown below. Figure 3 As shown, the first interface module in the first simulation chip and the second interface module in the second simulation chip are connected through an interface connection module, and the signal transmission delay of the real PHY layer is simulated through the delay simulation module in the interface connection module.

[0153] First, it completely eliminates the dependence on the physical layer model. By bypassing the PHY layer and modeling analog circuits, it directly builds interconnection paths between adapter modules in the digital domain, thus overcoming the timing simulation bottleneck in traditional verification. Second, while abandoning the physical layer, it still ensures the integrity of functional verification. With the help of interface connection modules that can accurately simulate the timing characteristics of the link, it realizes closed-loop interactive verification including link training, signal recovery, and adaptation. Finally, it fundamentally reconstructs the verification efficiency system. By deploying this architecture on hardware acceleration platforms such as Palladium, it significantly improves the coverage and execution speed of multi-chip system-level verification scenarios, thereby moving key verification tasks forward from the post-silicon stage, shortening the development cycle, and reducing tape-out risks.

[0154] This application's embodiments significantly advance key verification tasks that traditionally rely on the post-silicon stage, thereby systematically exposing and mitigating potential problems before tape-out. Specifically: First, with the help of flexibly configurable interface connection modules, this application can accurately simulate key timing characteristics such as latency and jitter in real physical links, thus comprehensively evaluating the actual bandwidth performance and signal integrity risks of high-speed interfaces during the pre-silicon stage; Second, this architecture supports true multi-chip system-level collaborative verification on hardware acceleration platforms, enabling early identification of performance bottlenecks, functional interaction conflicts, and protocol compatibility issues in system integration; Finally, through this deep and forward-looking verification strategy, the uncertainty in the later stages of the project is significantly reduced, fundamentally improving the success rate of the first chip tape-out, shortening the development cycle, and effectively controlling costs.

[0155] This application proposes a UCIe Adapter direct-connect pre-silicon verification method. Its core lies in building a verification environment within a hardware-accelerated simulation platform, bypassing the difficult-to-simulate analog mixed-signal portion of the UCIe PHY physical layer. Multiple UCIe Adapter digital control modules distributed across different chips are directly interconnected via a dedicated interface module. This interface module has a data channel and a sideband channel: the data channel is typically a parallel bus structure used to transmit data packets conforming to the UCIe protocol format; the sideband channel is responsible for transmitting critical control signals such as reset, link status management, power control, interrupts, and clock signals. Furthermore, a programmable delay module is integrated into the data channel. By injecting configurable transmission delays, signal jitter, or timing offsets, the delay characteristics of a real physical link are effectively simulated, thereby achieving comprehensive and efficient verification of UCIe protocol interaction, link training, and system-level collaborative functions in the pre-silicon stage.

[0156] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0157] Figure 4 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application, such as... Figure 4 As shown, the hardware entity of the computer device 400 includes a processor 401 and a memory 402, wherein the memory 402 stores a computer program that can run on the processor 401, and the processor 401 executes the program to implement the steps in the method of any of the above embodiments.

[0158] The memory 402 stores computer programs that can run on the processor. The memory 402 is configured to store instructions and applications that can be executed by the processor 401. It can also cache data to be processed or already processed by the processor 401 and various modules in the computer device 400 (e.g., image data, audio data, voice communication data and video communication data). It can be implemented by flash memory or random access memory (RAM).

[0159] The processor 401 executes the steps of the task execution method described above when executing the program. The processor 401 typically controls the overall operation of the computer device 400.

[0160] This application provides a computer storage medium that stores one or more programs, which can be executed by one or more processors to implement the steps of the task execution method described above.

[0161] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0162] The aforementioned processor can be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that other electronic devices can also implement the functions of the aforementioned processor, and this application does not specifically limit the specific implementation.

[0163] The aforementioned computer storage media / memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; or it can be various terminals that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0164] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0165] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0166] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0167] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0168] Furthermore, in the various embodiments of this application, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0169] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0170] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A chip verification device, characterized in that, The device includes: a first simulation core, a second simulation core, and an interface connection module; The first simulation chip and the second simulation chip are used to simulate the first chip and the second chip, respectively; the first simulation chip communicates with the second simulation chip through the interface connection module; the interface connection module is used to simulate the delay characteristics of the physical layer link between the first chip and the second chip, wherein the delay characteristics include basic propagation delay, signal jitter, and timing distortion, and the simulation of the delay characteristics is achieved by a programmable delay circuit based on delay control parameters; The first simulation chip is used to send verification data, which includes the link training sequence; The interface connection module is used to send target verification data to the second simulation chip; the target verification data is the verification data obtained by delaying the verification data through the programmable delay circuit via the interface connection module. The second simulated core is used to verify the first core and / or the second core based on the received target verification data.

2. The chip verification device according to claim 1, characterized in that, The interface connection module includes a data channel and a control channel; wherein... The data channel is used to transmit the link training sequence in the verification data, so as to send the target link training sequence after time delay characteristic simulation to the second simulation chip. The control channel is used to send the control signal in the verification data to the second simulation chip, so that the second simulation chip can verify the first chip and / or the second chip according to the control signal and the target link training sequence.

3. The chip verification device according to claim 2, characterized in that, The first simulation chip includes a first interface module, and the second simulation chip includes a second interface module, wherein the data channel is used for: Receive the link training sequence sent by the first interface module; The latency characteristics of the physical layer link are simulated by simulating a latency circuit to obtain the target link training sequence after latency characteristic simulation. The target link training sequence, after time delay characteristic simulation, is sent to the second simulation chip.

4. The chip verification device according to claim 3, characterized in that, The analog time delay circuit is used for: The link training sequence is subjected to delay processing based on the obtained delay control parameters to obtain the target link training sequence after delay characteristic simulation. The delay control parameters are used to simulate the delay characteristics of the physical layer link.

5. The chip verification device according to claim 4, characterized in that, The delay control parameters include a fixed offset parameter; the analog delay circuit is used for: Based on the preset delay parameters and clock frequency of the link, a fixed offset parameter is determined for the training sequence of the link; the fixed offset parameter is used to simulate the delay characteristics of the physical layer link. The target link training sequence is obtained by delaying the link training sequence according to the fixed offset parameter.

6. The chip verification device according to claim 4, characterized in that, The delay control parameters include jitter intensity parameters; the analog delay circuit is used for: A preset system function generates a corresponding random number at the rising edge of each clock cycle, and the multiple random numbers are normally distributed. For each clock cycle, the random number corresponding to the clock cycle is used to perform an XOR operation on the link training sequence within the clock cycle to obtain the target link training sequence after jitter processing within the clock cycle.

7. The chip verification device according to claim 4, characterized in that, The delay control parameters include a fixed offset parameter and a jitter intensity parameter; the analog delay circuit is used for: Based on the preset delay parameters and clock frequency of the link, a fixed offset parameter is determined for the training sequence of the link; the fixed offset parameter is used to simulate the delay characteristics of the physical layer link. The link training sequence is delayed according to the fixed offset parameter to obtain a candidate link training sequence. A preset system function generates a corresponding random number at the rising edge of each clock cycle, and the multiple random numbers are normally distributed. For each clock cycle, the candidate link training sequence within the clock cycle is XORed with the random number corresponding to the clock cycle to obtain the target link training sequence after jitter processing within the clock cycle.

8. A chip verification method, characterized in that, The method is applied to the interface connection module in the chip verification device according to claim 1; the method includes: Receive verification data sent by the first simulation chip, the verification data including the link training sequence; Target verification data is sent to the second simulation chip so that the second simulation chip can verify the first chip and / or the second chip based on the received target verification data; wherein, the target verification data is verification data obtained by delaying the verification data through the interface connection module using the programmable delay circuit.

9. The method according to claim 8, characterized in that, Sending target verification data to the second simulation core includes: The latency characteristics of the physical layer link are simulated by the simulation latency circuit in the interface connection module to obtain the target link training sequence after latency processing. The target link training sequence, after time delay characteristic simulation, is sent to the second simulation chip.

10. A computer storage medium, characterized in that, The processor stores executable instructions that, when executed by the processor, perform the method as described in claim 8 or 9.

11. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by the processor, they implement the method of claim 8 or 9.

Images