Super-junction charge-coupled based on-resistance optimization method and system

Abstract

The present application relates to the technical field of on-resistance optimization, and a on-resistance optimization method and system based on super-junction charge coupling, comprising: building a on-resistance optimization platform based on a semiconductor device, testing the on-resistance based on the on-resistance optimization platform to obtain an original on-resistance data set, performing gain conversion on the original on-resistance data set to obtain a on-resistance gain data set, training a neural network using the on-resistance gain data set to obtain a gain prediction model, simulating the on-resistance of a semiconductor device set according to the gain prediction model to obtain a target on-resistance set, performing deviation analysis on the target on-resistance set based on a standard on-resistance to obtain an optimal semiconductor device, and connecting the optimal semiconductor device to a device operating environment. The present application can improve the accuracy of on-resistance optimization, and improve the efficiency and environmental adaptability of on-resistance optimization.

Description

Technical Field

[0001] This invention relates to the field of on-resistance optimization technology, and in particular to an on-resistance optimization method and system based on superjunction charge coupling. Background Technology

[0002] In power electronic systems such as high-voltage frequency converters, electric vehicle drives, and industrial power modules, the on-resistance of superjunction semiconductor devices directly determines system efficiency, temperature rise, and power density. As bus voltage increases and switching frequency rises, even milliohm-level resistance increments can lead to significant conduction losses and heat dissipation pressure. Therefore, optimizing high-precision, low-deviation on-resistance for actual operating environments has become a key aspect of power device selection and breaking through the performance limits of the entire system.

[0003] Traditional methods often rely on datasheets to perform static tests at a single temperature and pressure point, and then extrapolate based on empirical formulas. While this can complete basic selection, it requires a lot of manual intervention, resulting in low efficiency. Furthermore, once there are fluctuations in ambient temperature or voltage, the actual accuracy of the device drops sharply. Summary of the Invention

[0004] This invention provides a method and system for optimizing on-resistance based on superjunction charge coupling. Its main purpose is to improve the accuracy, efficiency and environmental adaptability of on-resistance optimization.

[0005] To achieve the above objectives, this invention provides a method for optimizing on-resistance based on superjunction charge coupling, comprising:

[0006] Receive on-resistance optimization instructions, determine the device operating environment and semiconductor device set based on the on-resistance optimization instructions, wherein the semiconductor device set includes multiple semiconductor devices, and the semiconductor devices are superjunction semiconductor devices;

[0007] Semiconductor devices are extracted sequentially from the semiconductor device set, and a conduction resistance optimization platform is built based on the semiconductor devices. The conduction resistance optimization platform includes: semiconductor devices, driving circuits, precision resistors, limiters, and thermal resistors.

[0008] On resistance testing was performed based on the on resistance optimization platform to obtain the original on resistance data set. The original on resistance data set includes multiple original on resistance data, and the original on resistance data includes: original on resistance, original ambient voltage, original ambient temperature and device structural characteristics.

[0009] The original conduction data set is subjected to gain conversion based on the preset reference ambient temperature and preset reference ambient voltage to obtain the conduction gain data set.

[0010] The conduction gain data groups are merged to obtain a conduction gain dataset. The pre-constructed neural network is trained using the conduction gain dataset to obtain a gain prediction model.

[0011] Based on the device operating environment, the target ambient voltage and target ambient temperature are determined. The on-resistance of the semiconductor device set is simulated according to the gain prediction model, the target ambient voltage and target ambient temperature, and the target on-resistance set is obtained.

[0012] Based on the preset standard on-resistance, a deviation analysis is performed on the target on-resistance set to obtain the on-resistance deviation set. The optimal semiconductor device is then identified from the semiconductor device set based on the on-resistance deviation set.

[0013] Connect the optimal semiconductor device to the device operating environment to complete the on-resistance optimization based on superjunction charge coupling.

[0014] Optionally, the on-resistance test based on the on-resistance optimization platform to obtain the original on-resistance data set includes:

[0015] Obtain the device structure feature set of the semiconductor device, wherein the device structure feature set includes: P-type doping concentration, number of field confinement rings, length of field confinement rings, thickness of buffer layer and thickness of absorption layer;

[0016] Construct an ambient voltage range and an ambient temperature range. Based on the preset optimization accuracy, extract equal portions from the ambient voltage range and the ambient temperature range to obtain the original ambient voltage set and the original ambient temperature set.

[0017] The original ambient voltage is extracted sequentially from the original ambient voltage set, and the original ambient temperature is extracted sequentially from the original ambient temperature set.

[0018] Based on the original ambient temperature and voltage, the on-resistance optimization platform is set to obtain the target optimization platform. Resistance testing is then performed based on the target optimization platform to obtain the original on-resistance.

[0019] The original on-resistance, original ambient voltage, original ambient temperature, and the device structural feature group are combined to obtain the original on-resistance data;

[0020] The original conduction data corresponding to each original ambient voltage in the original ambient voltage set and each original ambient temperature in the original ambient temperature set are summarized to obtain the original conduction data group.

[0021] Optionally, the resistance test based on the target optimization platform to obtain the original on-resistance includes:

[0022] A low-frequency pulse signal is generated and sent to the semiconductor device in the target optimization platform to obtain a closed device. The semiconductor device was in an open state before the low-frequency pulse signal was sent.

[0023] The first generation time of the low-frequency pulse signal was identified;

[0024] Based on the first generation time, the closed device is measured using the precision resistor and limiter in the target optimization platform to obtain the original drain current and the original drain-source voltage.

[0025] The signal acquisition time is determined based on the preset acquisition interval and the first generation time;

[0026] The signal acquisition time is taken as the first generation time, and the steps of measuring the closed device using the precision resistor and limiter in the target optimization platform based on the first generation time are returned until the closed device is in an open state, and the closed device in the open state is recorded as the open device.

[0027] The drain current of the disconnected device is obtained by current detection.

[0028] If the disconnected drain current is not the preset zero value, return to the step of current detection of the disconnected device until the disconnected drain current is zero.

[0029] If the drain current is zero when disconnected, return to the step of generating the low-frequency pulse signal until a preset stop test signal is received;

[0030] By summing up the original drain current and the original drain-source voltage, we obtain the original drain current set and the original drain-source voltage set.

[0031] The original on-resistance is obtained by differential calculation based on the original drain current set and the original drain-source voltage set.

[0032] Optionally, the differential calculation based on the original drain current set and the original drain-source voltage set to obtain the original on-resistance includes:

[0033] The original on-resistance can be calculated using the following formula:

[0034]

[0035] Among them, R raw V represents the initial on-resistance, N represents the initial drain current concentration or the initial drain-source voltage concentration, and V represents the initial drain-source voltage concentration. i+1 and V i Let I represent the (i+1)th original drain-source voltage and Ii original drain-source voltage in the original drain-source voltage set, respectively. i+1 and Ii These represent the (i+1)th and ith original drain currents in the original drain current set, respectively.

[0036] Optionally, the step of performing gain conversion on the original conduction data group according to a preset reference ambient temperature and a preset reference ambient voltage to obtain a conduction gain data group includes:

[0037] Extract the original conduction data sequentially from the original conduction data group;

[0038] The reference resistance is obtained by performing a reference resistance test based on the reference ambient voltage, reference ambient temperature, and on-resistance optimization platform.

[0039] The original on-resistance in the original on-resistance data is converted based on the reference on-resistance to obtain the on-resistance gain, where the on-resistance gain is the ratio of the on-resistance in the original on-resistance data to the reference on-resistance.

[0040] The on-resistance gain is used to update the original on-state data to obtain the on-state gain data;

[0041] Summarize the conduction gain data to obtain the conduction gain data set.

[0042] Optionally, the step of simulating the on-resistance of the semiconductor device set based on the gain prediction model, the target ambient voltage, and the target ambient temperature to obtain the target on-resistance set includes:

[0043] A reference analog circuit is constructed based on the reference ambient voltage and reference ambient temperature.

[0044] The target semiconductor devices are extracted sequentially from the semiconductor device set, and then connected to the reference analog circuit to obtain the running analog circuit. Based on the running analog circuit, the parameters are simulated to obtain the simulated on-resistance.

[0045] Obtain the target structural feature set of the target semiconductor device;

[0046] The target structural feature set, target ambient voltage, and target ambient temperature are input into the gain prediction model to obtain the target resistance gain;

[0047] Calculate the target on-resistance based on the simulated on-resistance and the target resistance gain;

[0048] Summarize the target on-resistances to obtain the target on-resistance set.

[0049] Optionally, the step of performing parameter simulation based on the operating simulation circuit to obtain the simulated on-resistance includes:

[0050] Obtain the work function difference of the target semiconductor device;

[0051] The gate oxide layer and P-type doped region of the target semiconductor device are identified. The gate oxide layer is detected based on the running simulation circuit to obtain the oxide layer charge and oxide layer capacitance value, and the P-type doping concentration and P-type Fermi potential of the P-type doped region are obtained.

[0052] The resistance is predicted based on the work function difference, oxide charge, oxide capacitance, P-type doping concentration, and P-type Fermi potential, resulting in a simulated on-resistance.

[0053] Optionally, the step of predicting the resistance based on the work function difference, oxide layer charge, oxide layer capacitance, P-type doping concentration, and P-type Fermi potential to obtain the simulated on-resistance includes:

[0054] The device threshold voltage is calculated based on the work function difference, oxide charge, oxide capacitance, P-type doping concentration, and P-type Fermi potential. The device threshold voltage is expressed as:

[0055]

[0056] Among them, V TH q represents the device threshold voltage, ΔH represents the work function difference, and q represents the device threshold voltage. o V represents the charge of the oxide layer, C represents the capacitance of the oxide layer, and V represents the capacitance of the oxide layer. F ε represents the P-type Fermi potential, ε represents the preset semiconductor dielectric constant, and K represents the P-type doping concentration.

[0057] Voltage measurements of the target semiconductor device are performed using a simulation circuit to obtain the target drain-source voltage and the target gate voltage.

[0058] The simulated on-resistance is calculated based on the target drain-source voltage, target gate voltage, oxide layer capacitance, and preset carrier mobility.

[0059] Optionally, the deviation analysis of the target on-resistance set based on a preset standard on-resistance to obtain an on-resistance deviation set includes:

[0060] The target on-resistance is extracted sequentially from the target on-resistance set, and the difference between the standard on-resistance and the target on-resistance is calculated to obtain the on-resistance difference;

[0061] Summarize the conduction resistance differences to obtain the conduction resistance difference set. Identify the maximum and minimum resistance differences in the conduction resistance difference set. Normalize the conduction resistance difference set based on the maximum and minimum resistance differences to obtain the conduction resistance deviation set.

[0062] To achieve the above objectives, the present invention also provides a superjunction charge coupling-based on-resistance optimization system, comprising:

[0063] An optimization instruction receiving module is used to receive on-resistance optimization instructions, determine the device operating environment and semiconductor device set based on the on-resistance optimization instructions, wherein the semiconductor device set includes multiple semiconductor devices, and the semiconductor devices are superjunction semiconductor devices. Semiconductor devices are extracted sequentially from the semiconductor device set, and an on-resistance optimization platform is built based on the semiconductor devices. The on-resistance optimization platform includes: semiconductor devices, driving circuits, precision resistors, limiters and thermal resistors.

[0064] The on-resistance testing module is used to perform on-resistance testing based on the on-resistance optimization platform to obtain the original on-resistance data set. The original on-resistance data set includes multiple original on-resistance data, including: original on-resistance, original ambient voltage, original ambient temperature and device structural characteristics. The original on-resistance data set is then subjected to gain conversion based on the preset reference ambient temperature and preset reference ambient voltage to obtain the on-resistance gain data set.

[0065] The gain model construction module is used to merge the conduction gain data group to obtain the conduction gain dataset, train the pre-built neural network using the conduction gain dataset to obtain the gain prediction model, determine the target ambient voltage and target ambient temperature based on the device operating environment, and simulate the on-resistance of the semiconductor device set according to the gain prediction model, target ambient voltage and target ambient temperature to obtain the target on-resistance set.

[0066] The optimal device identification module is used to perform deviation analysis on the target on-resistance set based on the preset standard on-resistance to obtain the on-resistance deviation set. Based on the on-resistance deviation set, the optimal semiconductor device is identified in the semiconductor device set, and the optimal semiconductor device is connected to the device operating environment.

[0067] To address the above problems, the present invention also provides an electronic device, the electronic device comprising:

[0068] Memory, storing at least one instruction; and

[0069] The processor executes the instructions stored in the memory to implement the on-resistance optimization method based on superjunction charge coupling described above.

[0070] To address the aforementioned problems, the present invention also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor in an electronic device to implement the aforementioned on-resistance optimization method based on superjunction charge coupling.

[0071] To address the problems described in the background art, this invention first establishes a conduction resistance optimization platform based on semiconductor devices. This step utilizes a dedicated optimization platform including drive circuits, precision resistors, limiters, and thermal resistors to directly couple the actual operating conditions of the device (ambient temperature and voltage) with the device's structural features in the same test circuit. This overcomes the limitation of traditional static testing, which cannot simultaneously consider the influence of voltage and temperature on conduction resistance. Secondly, conduction resistance testing is performed based on the optimization platform to obtain the original conduction data set. This step incorporates the influence of switching transients on conduction resistance into a quantitative evaluation through low-frequency pulse dynamic testing and differential noise reduction algorithms, making the test results closer to the actual losses of superjunction devices in real-world conditions such as high-voltage inverters and electric vehicle drives. Next, this solution performs gain conversion on the original conduction data set based on reference ambient temperature and voltage to obtain a conduction gain data set. This step uniformly maps the original resistance at different temperatures and voltages to a dimensionless gain, greatly eliminating the interference of environmental variables on conduction resistance and making performance comparisons of devices across batches and operating conditions comparable. Furthermore, this solution utilizes... The conduction gain dataset is used to train a pre-built neural network to obtain a gain prediction model. This step trains the neural network with the normalized conduction gain dataset to establish a nonlinear mapping between structure, environment, and gain, replacing the traditional coarse-grained fitting based on empirical formulas. This greatly improves the prediction accuracy of conduction resistance under unknown operating conditions and significantly shortens the conduction resistance optimization cycle. Then, based on the gain prediction model, target ambient voltage, and target ambient temperature, conduction resistance simulation is performed on a set of semiconductor devices to obtain a target conduction resistance set. This step uses a two-level strategy of benchmark simulation and gain mapping to quickly obtain the conduction resistance under any target environment with only one benchmark circuit simulation, solving the computational bottleneck of traditional methods that require point-by-point experiments or full-condition simulation. While maintaining accuracy, the conduction resistance optimization process is optimized. Finally, deviation analysis is performed on the target conduction resistance set based on the standard conduction resistance to obtain a conduction resistance deviation set. The optimal semiconductor device is identified in the semiconductor device set based on the conduction resistance deviation set. This step uses the standard conduction resistance as an anchor point for deviation quantification, avoiding the inefficient decision-making process of repeatedly weighing the weights of various parameters manually. Therefore, the present invention can improve the accuracy of on-resistance optimization, and enhance the efficiency and environmental adaptability of on-resistance optimization. Attached Figure Description

[0072] Figure 1 This is a flowchart illustrating a method for optimizing on-resistance based on superjunction charge coupling according to an embodiment of the present invention.

[0073] Figure 2 A functional block diagram of a superjunction charge coupling-based on-resistance optimization system provided in an embodiment of the present invention;

[0074] Figure 3This is a schematic diagram of an electronic device that implements the superjunction charge coupling-based on-resistance optimization method according to an embodiment of the present invention.

[0075] Explanation of reference numerals in the attached figures:

[0076] 10. Electronic device; 11. Processor; 12. Memory; 13. Bus.

[0077] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0078] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0079] This application provides a method for optimizing on-resistance based on superjunction charge coupling. The execution entity of the superjunction charge coupling-based on-resistance optimization method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the superjunction charge coupling-based on-resistance optimization method can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0080] Reference Figure 1 The diagram shown is a flowchart illustrating a method for optimizing on-resistance based on superjunction charge coupling according to an embodiment of the present invention. In this embodiment, the method for optimizing on-resistance based on superjunction charge coupling includes:

[0081] S1. Receive the on-resistance optimization instruction, and determine the device operating environment and semiconductor device set based on the on-resistance optimization instruction. The semiconductor device set includes multiple semiconductor devices, and the semiconductor devices are superjunction semiconductor devices.

[0082] It is understood that the on-resistance optimization instruction refers to a manually initiated instruction to optimize semiconductor devices in a specific operating environment. The device operating environment refers to the specific operating environment indicated by the on-resistance optimization instruction, such as the operating environment of a high-voltage frequency converter, an electric vehicle drive system, or an industrial power module. The semiconductor device set refers to a collection of multiple semiconductor devices, where the semiconductor devices are candidate devices installed in the device operating environment. Since different semiconductor devices have different characteristics, it is necessary to select appropriate semiconductor devices according to different device operating environments. This semiconductor device is a superjunction semiconductor device, which refers to a power device (such as a Super Junction MOSFET) with an alternating arrangement of P-type and N-type pillar structures. Compared with other semiconductors, the superjunction semiconductor device has higher breakdown voltage and lower on-resistance.

[0083] S2. Extract semiconductor devices sequentially from the semiconductor device set, and build a conduction resistance optimization platform based on the semiconductor devices. The conduction resistance optimization platform includes: semiconductor devices, driving circuits, precision resistors, limiters, and thermal resistors.

[0084] It should be explained that the on-resistance optimization platform refers to a dedicated experimental circuit system for testing the on-resistance of semiconductor devices. The driving circuit refers to the gate driving circuit, whose function is to provide a precise gate control signal to switch the on / off state of the semiconductor device. The precision resistor refers to a high-precision, low-temperature-drift current-sensing resistor, such as a 0.1% accuracy, 5ppm / ℃ metal foil resistor, which detects the drain current of the semiconductor device. The limiter refers to a voltage clamping protection circuit, such as a limiting circuit composed of a Zener diode or a transient voltage suppressor (TVS), which measures the drain-source voltage of the semiconductor device. The thermal resistor refers to a programmable heating resistor, such as a PTC thermistor or a thin-film heater, which acts as an additional heat source to heat the semiconductor device, thereby controlling its temperature to simulate the ambient temperature in the actual operating environment. The semiconductor device, precision resistor, limiter, and thermal resistor are all connected to the driving circuit.

[0085] S3. Conduct on-resistance testing based on the on-resistance optimization platform to obtain the original on-resistance data set. The original on-resistance data set includes multiple original on-resistance data, including: original on-resistance, original ambient voltage, original ambient temperature, and device structural characteristics.

[0086] Understandably, the raw conduction data set refers to a combination of multiple raw conduction data sets, wherein the raw conduction data set refers to a combination of raw conduction voltage, raw ambient voltage, raw ambient temperature, and device structural feature set. The raw conduction resistance refers to the conduction resistance of the tested semiconductor device under raw ambient voltage and raw ambient temperature during conduction resistance testing. The raw ambient voltage refers to the bus voltage that the tested semiconductor device withstands during conduction resistance testing. The raw ambient temperature refers to the temperature of the circuit containing the tested semiconductor device during conduction resistance testing. The device structural feature set refers to a combination of multiple structural features of the tested semiconductor device during conduction resistance testing, wherein structural features include, for example, P-type doping concentration, number of field-limiting rings, and field-limiting ring length.

[0087] In detail, the on-resistance test based on the on-resistance optimization platform to obtain the original on-resistance data set includes:

[0088] Obtain the device structure feature set of the semiconductor device, wherein the device structure feature set includes: P-type doping concentration, number of field confinement rings, length of field confinement rings, thickness of buffer layer and thickness of absorption layer;

[0089] Construct an ambient voltage range and an ambient temperature range. Based on the preset optimization accuracy, extract equal portions from the ambient voltage range and the ambient temperature range to obtain the original ambient voltage set and the original ambient temperature set.

[0090] The original ambient voltage is extracted sequentially from the original ambient voltage set, and the original ambient temperature is extracted sequentially from the original ambient temperature set.

[0091] Based on the original ambient temperature and voltage, the on-resistance optimization platform is set to obtain the target optimization platform. Resistance testing is then performed based on the target optimization platform to obtain the original on-resistance.

[0092] The original on-resistance, original ambient voltage, original ambient temperature, and the device structural feature group are combined to obtain the original on-resistance data;

[0093] The original conduction data corresponding to each original ambient voltage in the original ambient voltage set and each original ambient temperature in the original ambient temperature set are summarized to obtain the original conduction data group.

[0094] Understandably, the P-type doping concentration refers to the concentration of acceptor atoms in the P-type semiconductor region; the number of field-limiting rings refers to the number of annular doped regions in the device termination structure used to improve the electric field distribution; the field-limiting ring length refers to the longitudinal dimension of a single field-limiting ring along the device edge; the buffer layer thickness refers to the thickness of the lightly doped layer located between the drift region and the substrate; and the absorption layer thickness refers to the thickness of the charge absorption layer used to suppress dynamic avalanche. The aforementioned device structure feature group also includes: trench depth, trench width, shielding layer thickness, and shielding layer resistivity, where trench depth refers to the vertical distance from the semiconductor surface to the bottom of the trench; trench width refers to the lateral dimension of the trench structure; shielding layer thickness refers to the thickness of the electric field shielding layer located at the bottom of the trench; and shielding layer resistivity refers to the resistivity of the shielding layer material.

[0095] It should be explained that the ambient voltage range refers to the range of the bus voltage of the semiconductor device during operation, which is set manually. The ambient temperature range refers to the range of the temperature of the circuit in which the semiconductor device operates, which is set manually. Both the ambient voltage range and the ambient temperature range can be set by relevant operators using historical data. The target optimization platform refers to the on-resistance optimization platform when the circuit temperature and the bus voltage are controlled at the original ambient temperature and the original ambient voltage. The merging of the original on-resistance, original ambient voltage, original ambient temperature, and the device structural feature group means: putting all device structural features in the original on-resistance, original ambient voltage, original ambient temperature, and device structural feature group into the same combination; the resulting combination is the original on-resistance data.

[0096] In detail, the resistance test based on the target optimization platform to obtain the original on-resistance includes:

[0097] A low-frequency pulse signal is generated and sent to the semiconductor device in the target optimization platform to obtain a closed device. The semiconductor device was in an open state before the low-frequency pulse signal was sent.

[0098] The first generation time of the low-frequency pulse signal was identified;

[0099] Based on the first generation time, the closed device is measured using the precision resistor and limiter in the target optimization platform to obtain the original drain current and the original drain-source voltage.

[0100] The signal acquisition time is determined based on the preset acquisition interval and the first generation time;

[0101] The signal acquisition time is taken as the first generation time, and the steps of measuring the closed device using the precision resistor and limiter in the target optimization platform based on the first generation time are returned until the closed device is in an open state, and the closed device in the open state is recorded as the open device.

[0102] The drain current of the disconnected device is obtained by current detection.

[0103] If the disconnected drain current is not the preset zero value, return to the step of current detection of the disconnected device until the disconnected drain current is zero.

[0104] If the drain current is zero when disconnected, return to the step of generating the low-frequency pulse signal until a preset stop test signal is received;

[0105] By summing up the original drain current and the original drain-source voltage, we obtain the original drain current set and the original drain-source voltage set.

[0106] The original on-resistance is obtained by differential calculation based on the original drain current set and the original drain-source voltage set.

[0107] It is understood that the low-frequency pulse signal refers to a square wave signal with a frequency of 10–100Hz and an adjustable duty cycle. When a semiconductor device receives this low-frequency pulse signal, it will switch from an off state to a closed state; that is, before receiving the low-frequency pulse signal, the semiconductor device is in an off state in its circuit. The closed device refers to a semiconductor device whose gate is activated and in a conducting state. The original drain current and original drain-source voltage refer to the drain current and drain-source voltage of the closed device, respectively. The acquisition interval refers to the time interval between two adjacent data acquisitions of the closed device, set manually. The signal acquisition time refers to the time of one acquisition interval after the first generation time. The disconnected drain current refers to the drain current of the disconnected device. The stop test signal refers to a manually initiated signal to stop the resistance test.

[0108] It needs to be explained that before generating the low-frequency pulse signal, the semiconductor device is in an open state. Upon receiving the low-frequency pulse signal, the semiconductor device changes from an open state to a closed state. At this time, the original drain current of the semiconductor device will continuously increase linearly. When the original drain current increases to a preset limit value, the semiconductor device will automatically disconnect from the original circuit, that is, change from a closed state to an open state. The drain current of the disconnected device continuously decreases until it reaches 0 (i.e., the preset zero value). When the drain current of the disconnected device is detected to be 0, a low-frequency pulse signal is generated, and the above steps are repeated. By continuously applying low-frequency pulse signals to the semiconductor device, the semiconductor device can repeatedly switch between closed and open states, thus allowing the semiconductor device to withstand a high voltage bias for most of the time. This test allows us to obtain the dynamic conduction characteristics of the semiconductor device during continuous open and closed actions, making the subsequently obtained original on-resistance closer to the true value under actual switching conditions.

[0109] In detail, the differential calculation based on the original drain current set and the original drain-source voltage set to obtain the original on-resistance includes:

[0110] The original on-resistance can be calculated using the following formula:

[0111]

[0112] Among them, R raw V represents the initial on-resistance, N represents the initial drain current concentration or the initial drain-source voltage concentration, and V represents the initial drain-source voltage concentration. i+1 and V i Let I represent the (i+1)th original drain-source voltage and Ii original drain-source voltage in the original drain-source voltage set, respectively. i+1 and I i These represent the (i+1)th and ith original drain currents in the original drain current set, respectively.

[0113] It should be explained that, in the actual measurement process of drain-source voltage and drain current, the measured original drain-source voltage and original drain current contain noise. To avoid the influence of this noise on the actual measurement results, this scheme introduces a differential calculation of the original on-resistance, through V... i+1 With V i The difference and I i+1 and I i The difference can, to some extent, eliminate the operation in the original drain-source voltage and the original drain current.

[0114] It should be noted that in the above original on-resistance calculation formula, since V i+1 With V i I i+1 with I i These are two original drain-source voltages and two original drain currents that are adjacent in acquisition time. Therefore, after acquiring the original drain current and original drain-source voltage, it is also necessary to record the acquisition time of the original drain current and original drain-source voltage respectively. In the subsequent steps of summarizing the original drain current and original drain-source voltage, the summaries are arranged in order of acquisition time from farthest to near. That is, the original drain current or original drain-source voltage acquired earlier is placed at the beginning of the original drain current set or the original drain-source voltage set.

[0115] S4. Perform gain conversion on the original conduction data group according to the preset reference ambient temperature and preset reference ambient voltage to obtain the conduction gain data group.

[0116] It is clear that the reference ambient temperature and reference ambient voltage refer to the ambient temperature and ambient voltage that are set by humans. They serve as reference data to normalize the original on-resistance collected under different original ambient temperatures and different original ambient voltages, thereby eliminating the influence of environmental variables on the on-resistance evaluation.

[0117] Furthermore, the conduction gain data group refers to a combination of multiple conduction gain data, and the conduction gain data in the conduction gain data group corresponds one-to-one with the original conduction data in the original conduction data group. The conduction gain data includes: original ambient temperature, original ambient voltage, conduction resistance gain and device structure feature group, that is, the conduction gain data replaces the original conduction resistance in the original conduction data with conduction resistance gain.

[0118] Specifically, the step of performing gain conversion on the original conduction data group according to a preset reference ambient temperature and a preset reference ambient voltage to obtain a conduction gain data group includes:

[0119] Extract the original conduction data sequentially from the original conduction data group;

[0120] The reference resistance is obtained by performing a reference resistance test based on the reference ambient voltage, reference ambient temperature, and on-resistance optimization platform.

[0121] The original on-resistance in the original on-resistance data is converted based on the reference on-resistance to obtain the on-resistance gain, where the on-resistance gain is the ratio of the on-resistance in the original on-resistance data to the reference on-resistance.

[0122] The on-resistance gain is used to update the original on-state data to obtain the on-state gain data;

[0123] Summarize the conduction gain data to obtain the conduction gain data set.

[0124] It should be explained that the reference on-resistance refers to the on-resistance of the semiconductor device under reference ambient voltage and temperature. The method for obtaining this reference on-resistance is the same as that for obtaining the original on-resistance, and will not be repeated here. The on-resistance gain is expressed as: Z = R raw / R base Where Z represents the on-resistance gain, and R base This represents the reference on-resistance. Updating the original conduction data using the on-resistance gain means replacing the original on-resistance in the original conduction data with the on-resistance gain; the replaced original conduction data is the conduction gain data.

[0125] S5. Merge the conduction gain data groups to obtain a conduction gain dataset. Use the conduction gain dataset to train the pre-built neural network to obtain a gain prediction model.

[0126] It is clear that merging the conduction gain data groups means placing all conduction gain data from each conduction gain data group into the same set, which becomes the conduction gain dataset. The neural network can be selected as a multilayer perceptron (MLP) or a convolutional neural network (CNN). The gain prediction model refers to the trained neural network, which can output a gain value based on the input ambient temperature, ambient voltage, and device structural features. This gain value corresponds to the on-resistance gain. The training process of the aforementioned neural network is existing technology and will not be described in detail here.

[0127] Furthermore, before training the neural network, the conduction gain dataset needs to be normalized. This step is an existing and common technique for neural network training, and will not be elaborated here.

[0128] S6. Determine the target ambient voltage and target ambient temperature based on the device operating environment. Simulate the on-resistance of the semiconductor device set according to the gain prediction model, target ambient voltage and target ambient temperature to obtain the target on-resistance set.

[0129] It is understood that the target ambient voltage and target ambient temperature refer to the ambient voltage and ambient temperature that need to be maintained under the operating environment of the device, respectively, and these target ambient voltage and target ambient temperature are specified by the relevant circuit operation standards. The target on-resistance set includes multiple target on-resistances, and the target on-resistances in the target on-resistance set correspond one-to-one with the semiconductor devices in the semiconductor device set. Here, the target on-resistance refers to the on-resistance of a certain semiconductor device under the target ambient voltage and target ambient temperature.

[0130] In detail, the step of simulating the on-resistance of the semiconductor device set based on the gain prediction model, the target ambient voltage, and the target ambient temperature to obtain the target on-resistance set includes:

[0131] A reference analog circuit is constructed based on the reference ambient voltage and reference ambient temperature.

[0132] The target semiconductor devices are extracted sequentially from the semiconductor device set, and then connected to the reference analog circuit to obtain the running analog circuit. Based on the running analog circuit, the parameters are simulated to obtain the simulated on-resistance.

[0133] Obtain the target structural feature set of the target semiconductor device;

[0134] The target structural feature set, target ambient voltage, and target ambient temperature are input into the gain prediction model to obtain the target resistance gain;

[0135] Calculate the target on-resistance based on the simulated on-resistance and the target resistance gain;

[0136] Summarize the target on-resistances to obtain the target on-resistance set.

[0137] It is understood that the reference simulation circuit refers to an equivalent test circuit built based on reference ambient voltage and temperature. This reference simulation circuit can be built using relevant simulation software, such as SPICE (e.g., LTspice) or TCAD tools. The reference simulation circuit is used to simulate the operation of semiconductor devices in a semiconductor device cluster under reference ambient voltage and temperature. The configuration of this reference simulation circuit is the same as that of the aforementioned on-resistance optimization platform.

[0138] Furthermore, the target semiconductor device refers to the semiconductor device in the semiconductor device cluster used for subsequent parameter simulation. The operating simulation circuit refers to the reference simulation circuit connected to the target semiconductor device. The simulated on-resistance refers to the on-resistance of the target semiconductor device at a reference ambient voltage and temperature. The target structural feature set refers to the device structural feature set of the target semiconductor device. The target resistance gain refers to the output value of the gain prediction model. The target on-resistance is the product of the target resistance gain and the simulated on-resistance.

[0139] It needs to be explained that the reason for constructing the reference simulation circuit based on the reference ambient voltage and reference ambient temperature is as follows: In practical applications, the target ambient temperature and target ambient voltage are often not fixed values, but are dynamically determined by operating conditions, load changes, or system scheduling strategies, exhibiting randomness and unpredictability. To address this uncertainty, this solution introduces reference ambient voltage and reference ambient temperature. The reference ambient voltage and reference ambient temperature are fixed reference points set by humans (such as 25℃ and 400V), and their data can be determined through historical operating logs or typical operating condition statistics, ensuring that the construction of the reference simulation circuit has reproducibility and universality. If the circuit is directly constructed for random target environments (i.e., different device operating environments), it is necessary to repeatedly simulate all possible combinations of ambient temperature and ambient voltage, resulting in extremely high computational costs. The reference environment circuit can generate reference data once and then quickly map it to any target environment through a gain model, balancing efficiency and accuracy.

[0140] Furthermore, the reason for performing parameter simulation based on the operating simulation circuit is that the differential calculation method (S3) relies on measured data, requires the physical construction of a test platform and point-by-point data acquisition, which is time-consuming and limited by hardware conditions (such as temperature control accuracy and pulse signal stability). In contrast, parameter simulation directly calculates the on-resistance through theoretical models and process parameters. Its advantages are that only the process parameters of the device (such as P-type doping concentration and oxide layer capacitance) are needed to quickly solve the problem through semiconductor physical equations (such as threshold voltage formula and linear region resistance formula), which is suitable for screening or virtual verification in the design stage. Moreover, when the target environment exceeds the capabilities of the test platform (such as -55℃ low temperature or 800V high voltage), parameter simulation can extrapolate the on-resistance based on the physical dependence of temperature and voltage (such as the Matthiessen model of mobility changing with temperature), while differential calculation cannot cover the unmeasured range.

[0141] In detail, the process of obtaining the simulated on-resistance based on parameter simulation of the operating analog circuit includes:

[0142] Obtain the work function difference of the target semiconductor device;

[0143] The gate oxide layer and P-type doped region of the target semiconductor device are identified. The gate oxide layer is detected based on the running simulation circuit to obtain the oxide layer charge and oxide layer capacitance value, and the P-type doping concentration and P-type Fermi potential of the P-type doped region are obtained.

[0144] The resistance is predicted based on the work function difference, oxide charge, oxide capacitance, P-type doping concentration, and P-type Fermi potential, resulting in a simulated on-resistance.

[0145] It is clear that the work function difference refers to the difference in work function between the gate metal and the semiconductor substrate material of the target semiconductor device. The gate oxide layer refers to the insulating dielectric layer (such as SiO2) between the gate and the channel. The oxide layer charge and oxide layer capacitance refer to the amount of charge accumulated in the gate oxide layer and the capacitance per unit area of ​​the gate oxide layer, respectively. The oxide layer charge is obtained by measuring the capacitance-voltage characteristic curve of the target semiconductor device to extract the oxide layer charge, or by referring to the device specifications provided by the manufacturer. Similarly, the oxide layer capacitance can also be obtained from the device specifications. The P-type doped region refers to the P-type semiconductor region constituting the MOSFET body region. The P-type doping concentration refers to the acceptor impurity concentration in the P-type doped region. The P-type Fermi potential refers to the difference between the P-type semiconductor Fermi level and the intrinsic Fermi level. The P-type doping concentration and P-type Fermi potential can be obtained from the device's technical specifications.

[0146] In detail, the method of predicting the simulated on-resistance based on the work function difference, oxide layer charge, oxide layer capacitance, P-type doping concentration, and P-type Fermi potential includes:

[0147] The device threshold voltage is calculated based on the work function difference, oxide charge, oxide capacitance, P-type doping concentration, and P-type Fermi potential. The device threshold voltage is expressed as:

[0148]

[0149] Among them, V TH q represents the device threshold voltage, ΔH represents the work function difference, and q represents the device threshold voltage. o V represents the charge of the oxide layer, C represents the capacitance of the oxide layer, and V represents the capacitance of the oxide layer. F ε represents the P-type Fermi potential, ε represents the preset semiconductor dielectric constant, and K represents the P-type doping concentration.

[0150] Voltage measurements of the target semiconductor device are performed using a simulation circuit to obtain the target drain-source voltage and the target gate voltage.

[0151] The simulated on-resistance is calculated based on the target drain-source voltage, target gate voltage, oxide layer capacitance, and preset carrier mobility.

[0152] It should be explained that the semiconductor node constant refers to the dielectric constant of the semiconductor material in the target semiconductor device. The target drain-source voltage and target gate voltage refer to the drain-source voltage and gate voltage of the target semiconductor in the operating analog circuit, respectively. The formula for calculating the analog on-resistance is:

[0153]

[0154] Among them, R moc V represents the analog on-resistance. DS V represents the drain-source voltage, L represents the preset device length, μ represents the carrier mobility, W represents the preset device width, and V represents the drain-source voltage. G This indicates the gate voltage.

[0155] S7. Based on the preset standard on-resistance, perform deviation analysis on the target on-resistance set to obtain the on-resistance deviation set, and identify the optimal semiconductor device in the semiconductor device set according to the on-resistance deviation set.

[0156] It should be explained that the standard on-resistance refers to the on-resistance that is artificially set and needs to be maintained in the device's operating environment, and this standard on-resistance is specified by relevant standards. The on-resistance deviation set refers to a collection of multiple on-resistance deviations, wherein the on-resistance deviation is a numerical value that quantifies the degree of difference between the target on-resistance and the standard on-resistance; the larger the on-resistance deviation, the greater the degree of difference between the target on-resistance and the standard on-resistance. Identifying the optimal semiconductor device in the semiconductor device set based on the on-resistance deviation set means: identifying the minimum on-resistance deviation in the on-resistance deviation set, and recording the target semiconductor device corresponding to the minimum on-resistance deviation as the optimal semiconductor device.

[0157] In detail, the deviation analysis of the target on-resistance set based on the preset standard on-resistance is used to obtain the on-resistance deviation set, including:

[0158] The target on-resistance is extracted sequentially from the target on-resistance set, and the difference between the standard on-resistance and the target on-resistance is calculated to obtain the on-resistance difference;

[0159] Summarize the conduction resistance differences to obtain the conduction resistance difference set. Identify the maximum and minimum resistance differences in the conduction resistance difference set. Normalize the conduction resistance difference set based on the maximum and minimum resistance differences to obtain the conduction resistance deviation set.

[0160] It is clear that the difference in on-resistance refers to the difference between the standard on-resistance and the target on-resistance. The above normalization refers to minimum-maximum normalization, which is existing technology and will not be elaborated further here.

[0161] S8. Connect the optimal semiconductor device to the device operating environment to complete the on-resistance optimization based on superjunction charge coupling.

[0162] It should be explained that the optimal semiconductor device is the target semiconductor device with the smallest deviation value in the on-resistance deviation concentration, and its on-resistance under the device operating environment is closest to the standard on-resistance value.

[0163] To address the problems described in the background art, this invention first establishes a conduction resistance optimization platform based on semiconductor devices. This step utilizes a dedicated optimization platform including drive circuits, precision resistors, limiters, and thermal resistors to directly couple the actual operating conditions of the device (ambient temperature and voltage) with the device's structural features in the same test circuit. This overcomes the limitation of traditional static testing, which cannot simultaneously consider the influence of voltage and temperature on conduction resistance. Secondly, conduction resistance testing is performed based on the optimization platform to obtain the original conduction data set. This step incorporates the influence of switching transients on conduction resistance into a quantitative evaluation through low-frequency pulse dynamic testing and differential noise reduction algorithms, making the test results closer to the actual losses of superjunction devices in real-world conditions such as high-voltage inverters and electric vehicle drives. Next, this solution performs gain conversion on the original conduction data set based on reference ambient temperature and voltage to obtain a conduction gain data set. This step uniformly maps the original resistance at different temperatures and voltages to a dimensionless gain, greatly eliminating the interference of environmental variables on conduction resistance and making performance comparisons of devices across batches and operating conditions comparable. Furthermore, this solution utilizes... The conduction gain dataset is used to train a pre-built neural network to obtain a gain prediction model. This step trains the neural network with the normalized conduction gain dataset to establish a nonlinear mapping between structure, environment, and gain, replacing the traditional coarse-grained fitting based on empirical formulas. This greatly improves the prediction accuracy of conduction resistance under unknown operating conditions and significantly shortens the conduction resistance optimization cycle. Then, based on the gain prediction model, target ambient voltage, and target ambient temperature, conduction resistance simulation is performed on a set of semiconductor devices to obtain a target conduction resistance set. This step uses a two-level strategy of benchmark simulation and gain mapping to quickly obtain the conduction resistance under any target environment with only one benchmark circuit simulation, solving the computational bottleneck of traditional methods that require point-by-point experiments or full-condition simulation. While maintaining accuracy, the conduction resistance optimization process is optimized. Finally, deviation analysis is performed on the target conduction resistance set based on the standard conduction resistance to obtain a conduction resistance deviation set. The optimal semiconductor device is identified in the semiconductor device set based on the conduction resistance deviation set. This step uses the standard conduction resistance as an anchor point for deviation quantification, avoiding the inefficient decision-making process of repeatedly weighing the weights of various parameters manually. Therefore, the present invention can improve the accuracy of on-resistance optimization, and enhance the efficiency and environmental adaptability of on-resistance optimization.

[0164] like Figure 2 The diagram shown is a functional block diagram of a superjunction charge coupling-based on-resistance optimization system provided in an embodiment of the present invention.

[0165] The superjunction charge coupling-based on-resistance optimization system 100 described in this invention can be installed in an electronic device. Depending on the functions implemented, the superjunction charge coupling-based on-resistance optimization system 100 may include an optimization instruction receiving module 101, an on-resistance testing module 102, a gain model construction module 103, and an optimal device identification module 104. The module described in this invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0166] The optimization instruction receiving module 101 is used to receive on-resistance optimization instructions, determine the device operating environment and semiconductor device set based on the on-resistance optimization instructions, wherein the semiconductor device set includes multiple semiconductor devices, and the semiconductor devices are superjunction semiconductor devices, the semiconductor devices are extracted sequentially from the semiconductor device set, and an on-resistance optimization platform is built based on the semiconductor devices, wherein the on-resistance optimization platform includes: semiconductor devices, driving circuits, precision resistors, limiters and thermal resistors;

[0167] The on-resistance testing module 102 is used to perform on-resistance testing based on the on-resistance optimization platform to obtain the original on-resistance data set. The original on-resistance data set includes multiple original on-resistance data, and the original on-resistance data includes: original on-resistance, original ambient voltage, original ambient temperature and device structure feature set. The original on-resistance data set is subjected to gain conversion according to the preset reference ambient temperature and preset reference ambient voltage to obtain the on-resistance gain data set.

[0168] The gain model construction module 103 is used to merge the conduction gain data group to obtain a conduction gain dataset, use the conduction gain dataset to train a pre-built neural network to obtain a gain prediction model, determine the target ambient voltage and target ambient temperature based on the device operating environment, and perform on-resistance simulation on the semiconductor device set according to the gain prediction model, target ambient voltage and target ambient temperature to obtain a target on-resistance set.

[0169] The optimal device identification module 104 is used to perform deviation analysis on the target on-resistance set based on the preset standard on-resistance to obtain the on-resistance deviation set, identify the optimal semiconductor device in the semiconductor device set according to the on-resistance deviation set, and connect the optimal semiconductor device to the device operating environment.

[0170] In detail, the modules in the superjunction charge coupling-based on-resistance optimization system 100 described in this embodiment of the invention employ the same methods as described above. Figure 1 The method used is the same as the superjunction charge coupling-based on-resistance optimization method described in the previous section, and can produce the same technical effect, so it will not be repeated here.

[0171] like Figure 3 The figure shown is a schematic diagram of an electronic device that implements a superjunction charge coupling-based on-resistance optimization method according to an embodiment of the present invention.

[0172] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a method program for optimizing on-resistance based on superjunction charge coupling.

[0173] The memory 11 includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device 1, such as a plug-in portable hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 11 includes both internal and external storage units of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as code for a method to optimize on-resistance based on superjunction charge coupling, but also to temporarily store data that has been output or will be output.

[0174] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., a method for optimizing on-resistance based on superjunction charge coupling) and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0175] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0176] Figure 3 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0177] For example, although not shown, the electronic device 1 may also include a power supply (such as a battery) to power various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management system, thereby enabling functions such as charging management, discharging management, and power consumption management through the power management system. The power supply may also include one or more DC or AC power supplies, recharging systems, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0178] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), which is typically used to establish communication connections between the electronic device 1 and other electronic devices.

[0179] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), or a standard wired or wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device 1 and to display a visual user interface.

[0180] The on-resistance optimization method program based on superjunction charge coupling stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When run in the processor 10, it can achieve the following:

[0181] Receive on-resistance optimization instructions, determine the device operating environment and semiconductor device set based on the on-resistance optimization instructions, wherein the semiconductor device set includes multiple semiconductor devices, and the semiconductor devices are superjunction semiconductor devices;

[0182] Semiconductor devices are extracted sequentially from the semiconductor device set, and a conduction resistance optimization platform is built based on the semiconductor devices. The conduction resistance optimization platform includes: semiconductor devices, driving circuits, precision resistors, limiters, and thermal resistors.

[0183] On resistance testing was performed based on the on resistance optimization platform to obtain the original on resistance data set. The original on resistance data set includes multiple original on resistance data, and the original on resistance data includes: original on resistance, original ambient voltage, original ambient temperature and device structural characteristics.

[0184] The original conduction data set is subjected to gain conversion based on the preset reference ambient temperature and preset reference ambient voltage to obtain the conduction gain data set.

[0185] The conduction gain data groups are merged to obtain a conduction gain dataset. The pre-constructed neural network is trained using the conduction gain dataset to obtain a gain prediction model.

[0186] Based on the device operating environment, the target ambient voltage and target ambient temperature are determined. The on-resistance of the semiconductor device set is simulated according to the gain prediction model, the target ambient voltage and target ambient temperature, and the target on-resistance set is obtained.

[0187] Based on the preset standard on-resistance, a deviation analysis is performed on the target on-resistance set to obtain the on-resistance deviation set. The optimal semiconductor device is then identified from the semiconductor device set based on the on-resistance deviation set.

[0188] Connect the optimal semiconductor device to the device operating environment to complete the on-resistance optimization based on superjunction charge coupling.

[0189] Specifically, the processor 10's implementation method for the above instructions can be found in [reference needed]. Figures 1 to 3 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0190] Furthermore, if the modules / units integrated in the electronic device 1 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or system capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0191] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following:

[0192] Receive on-resistance optimization instructions, determine the device operating environment and semiconductor device set based on the on-resistance optimization instructions, wherein the semiconductor device set includes multiple semiconductor devices, and the semiconductor devices are superjunction semiconductor devices;

[0193] Semiconductor devices are extracted sequentially from the semiconductor device set, and a conduction resistance optimization platform is built based on the semiconductor devices. The conduction resistance optimization platform includes: semiconductor devices, driving circuits, precision resistors, limiters, and thermal resistors.

[0194] On resistance testing was performed based on the on resistance optimization platform to obtain the original on resistance data set. The original on resistance data set includes multiple original on resistance data, and the original on resistance data includes: original on resistance, original ambient voltage, original ambient temperature and device structural characteristics.

[0195] The original conduction data set is subjected to gain conversion based on the preset reference ambient temperature and preset reference ambient voltage to obtain the conduction gain data set.

[0196] The conduction gain data groups are merged to obtain a conduction gain dataset. The pre-constructed neural network is trained using the conduction gain dataset to obtain a gain prediction model.

[0197] Based on the device operating environment, the target ambient voltage and target ambient temperature are determined. The on-resistance of the semiconductor device set is simulated according to the gain prediction model, the target ambient voltage and target ambient temperature, and the target on-resistance set is obtained.

[0198] Based on the preset standard on-resistance, a deviation analysis is performed on the target on-resistance set to obtain the on-resistance deviation set. The optimal semiconductor device is then identified from the semiconductor device set based on the on-resistance deviation set.

[0199] Connect the optimal semiconductor device to the device operating environment to complete the on-resistance optimization based on superjunction charge coupling.

[0200] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0201] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0202] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0203] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0204] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for optimizing on-state resistance based on super-junction charge coupling, comprising: The method comprises: ​ Receiving a conduction resistance optimization instruction, determining a device operating environment and a semiconductor device set based on the conduction resistance optimization instruction, wherein the semiconductor device set comprises a plurality of semiconductor devices, and the semiconductor device is a super-junction semiconductor device; Extracting the semiconductor devices in the semiconductor device set in turn, and building a conduction resistance optimization platform based on the semiconductor devices, wherein the conduction resistance optimization platform comprises: a semiconductor device, a driving circuit, a precision resistor, a limiter and a thermal resistor; Conducting a conduction resistance test based on the conduction resistance optimization platform to obtain an original conduction data set, wherein the original conduction data set comprises a plurality of original conduction data, and the original conduction data comprises: an original conduction resistance, an original environment voltage, an original environment temperature and a device structure feature set; According to the preset reference environment temperature and the preset reference environment voltage, the original conduction data set is gain-converted to obtain a conduction gain data set; According to the preset reference environment temperature and the preset reference environment voltage, the original conduction data set is gain-converted to obtain a conduction gain data set, comprising: Extracting the original conduction data in the original conduction data set in turn; According to the reference environment voltage, the reference environment temperature and the conduction resistance optimization platform, a reference resistance test is conducted to obtain a reference conduction resistance; Based on the reference conduction resistance, the original conduction resistance in the original conduction data is converted to obtain a conduction resistance gain, wherein the conduction resistance gain is the ratio of the conduction resistance in the original conduction data to the reference conduction resistance; The original conduction data is updated using the conduction resistance gain to obtain conduction gain data; The conduction gain data is summarized to obtain a conduction gain data set; The conduction gain data set is merged to obtain a conduction gain data set, and the pre-constructed neural network is trained using the conduction gain data set to obtain a gain prediction model; Based on the device operating environment, a target environment voltage and a target environment temperature are determined, and a conduction resistance simulation is performed on the semiconductor device set according to the gain prediction model, the target environment voltage and the target environment temperature to obtain a target conduction resistance set; Based on the preset standard conduction resistance, a deviation analysis is performed on the target conduction resistance set to obtain a conduction resistance deviation set, and the optimal semiconductor device is identified in the semiconductor device set according to the conduction resistance deviation set; The optimal semiconductor device is connected to the device operating environment to complete the conduction resistance optimization based on the super-junction charge coupling.

2. The super-junction charge-coupled based on-resistance optimization method of claim 1, wherein, The conduction resistance test based on the conduction resistance optimization platform obtains the original conduction data set, comprising: Obtaining the device structure feature set of the semiconductor device, wherein the device structure feature set comprises: P-type doping concentration, field limiting ring number, field limiting ring length, buffer layer thickness and absorption layer thickness; Building an environment voltage range and an environment temperature range, and extracting an equal number of samples in the environment voltage range and the environment temperature range according to a preset optimization accuracy to obtain an original environment voltage set and an original environment temperature set; Extracting the original environment voltage in the original environment voltage set in turn and extracting the original environment temperature in the original environment temperature set in turn; According to the original environment temperature and the original environment voltage, a conduction resistance optimization platform is set to obtain a target optimization platform, and resistance testing is performed based on the target optimization platform to obtain an original conduction resistance; The original conduction resistance, the original environment voltage, the original environment temperature and the device structure feature group are combined to obtain original conduction data; The original conduction data corresponding to each original environment voltage in the original environment voltage set and each original environment temperature in the original environment temperature set are summarized to obtain an original conduction data set.

3. The super-junction charge-coupled based on-resistance optimization method of claim 2, wherein, The resistance testing based on the target optimization platform to obtain the original conduction resistance comprises: A low-frequency pulse signal is generated, and the low-frequency pulse signal is sent to the semiconductor device in the target optimization platform to obtain a closed device, wherein the semiconductor device before the low-frequency pulse signal is sent is in an open state; A first generation time of the low-frequency pulse signal is determined; Based on the first generation time, the closed device is measured by using a precision resistor and a limiter in the target optimization platform to obtain an original drain current and an original drain-source voltage; A signal acquisition time is determined according to a preset acquisition interval and the first generation time; The signal acquisition time is taken as the first generation time, and the step of measuring the closed device by using the precision resistor and the limiter in the target optimization platform based on the first generation time is returned until the closed device is in an open state, and the closed device in the open state is recorded as an open device; The open device is subjected to current detection to obtain an open drain current; If the open drain current is not a preset zero value, the step of detecting the current of the open device is returned until the open drain current is zero; If the open drain current is zero, the step of generating the low-frequency pulse signal is returned until a preset stop testing signal is received; The original drain current and the original drain-source voltage are respectively summarized to obtain an original drain current set and an original drain-source voltage set; Differential calculation is performed based on the original drain current set and the original drain-source voltage set to obtain an original conduction resistance.

4. The super-junction charge-coupled based on-resistance optimization method of claim 3, wherein, The differential calculation based on the original drain current set and the original drain-source voltage set to obtain the original conduction resistance comprises: The original conduction resistance is calculated by using the following formula: in, Indicates the original on-resistance. This indicates the number of original drain currents or the number of original drain-source voltages in the initial drain current concentration. and These represent the first and second drain-source voltages in the original set. The original drain-source voltage and the first The original drain-source voltage, and These represent the first and second drain currents in the original drain current concentration. The initial drain current and the i-th initial drain current.

5. The super-junction charge-coupled based on-resistance optimization method of claim 4, wherein, The conduction resistance simulation of the semiconductor device set based on the gain prediction model, the target environment voltage and the target environment temperature to obtain a target conduction resistance set comprises: A reference simulation circuit is constructed according to a reference environment voltage and a reference environment temperature; A target semiconductor device is extracted from the semiconductor device set in sequence, and the target semiconductor device is connected to the reference simulation circuit to obtain a running simulation circuit, and parameter simulation is performed based on the running simulation circuit to obtain a simulated conduction resistance; A target structure feature group of the target semiconductor device is obtained; The target structure feature group, the target environment voltage and the target environment temperature are input into the gain prediction model to obtain a target resistance gain; The target conduction resistance is calculated according to the simulated conduction resistance and the target resistance gain; The target conduction resistance set is obtained by summarizing the target conduction resistance.

6. The super-junction charge-coupled based on-resistance optimization method of claim 5, wherein, The parameter simulation based on the running simulation circuit to obtain the simulated conduction resistance comprises: The work function difference of the target semiconductor device is obtained; Confirming a gate oxide layer and a P-type doped region of a target semiconductor device, detecting the gate oxide layer based on a running simulation circuit to obtain an oxide layer charge quantity and an oxide layer capacitance value, and obtaining a P-type doping concentration and a P-type Fermi potential of the P-type doped region; Resistance prediction is performed according to the work function difference, the oxide layer charge quantity, the oxide layer capacitance value, the P-type doping concentration and the P-type Fermi potential, to obtain a simulated on-resistance.

7. The super-junction charge-coupled based on-resistance optimization method of claim 6, wherein, The resistance prediction according to the work function difference, the oxide layer charge quantity, the oxide layer capacitance value, the P-type doping concentration and the P-type Fermi potential to obtain the simulated on-resistance comprises: A device threshold voltage is calculated according to the work function difference, the oxide layer charge quantity, the oxide layer capacitance value, the P-type doping concentration and the P-type Fermi potential, wherein the device threshold voltage is expressed as: wherein, represents a device threshold voltage, represents a work function difference, represents an oxide layer charge amount, represents an oxide layer capacitance value, represents a P-type Fermi potential, represents a predetermined semiconductor dielectric constant, represents a P-type doping concentration; Voltage measurement is performed on the target semiconductor device based on the running simulation circuit to obtain a target drain-source voltage and a target gate voltage; The simulated on-resistance is calculated according to the target drain-source voltage, the target gate voltage, the oxide layer capacitance value and a preset carrier mobility.

8. The super-junction charge-coupled based on-resistance optimization method of claim 7, wherein, The deviation analysis of the target on-resistance set based on the preset standard on-resistance comprises: A target on-resistance is extracted from the target on-resistance set in sequence, a difference value is calculated based on the standard on-resistance and the target on-resistance to obtain an on-resistance difference; The on-resistance differences are summarized to obtain an on-resistance difference set, the maximum on-resistance difference and the minimum on-resistance difference in the on-resistance difference set are identified, and the on-resistance difference set is normalized based on the maximum on-resistance difference and the minimum on-resistance difference to obtain an on-resistance deviation set.

9. A system using the super-junction charge-coupled based on-resistance optimization method according to any one of claims 1 to 8, characterized in that, The system comprises: An optimization instruction receiving module is configured to receive an on-resistance optimization instruction, determine a device running environment and a semiconductor device set based on the on-resistance optimization instruction, wherein the semiconductor device set comprises a plurality of semiconductor devices, the semiconductor devices are super-junction semiconductor devices, a semiconductor device is extracted from the semiconductor device set in sequence, and an on-resistance optimization platform is built based on the semiconductor device, wherein the on-resistance optimization platform comprises: the semiconductor device, a driving circuit, a precision resistor, a limiter and a thermal resistor; An on-resistance testing module is configured to perform on-resistance testing based on the on-resistance optimization platform to obtain an original on-resistance data group, wherein the original on-resistance data group comprises a plurality of original on-resistance data, and the original on-resistance data comprises: an original on-resistance, an original environment voltage, an original environment temperature and a device structure feature group; the original on-resistance data group is gain-converted according to a preset reference environment temperature and a preset reference environment voltage to obtain an on-resistance gain data group; A gain model construction module is configured to merge the on-resistance gain data group to obtain an on-resistance gain data set, train a pre-constructed neural network using the on-resistance gain data set to obtain a gain prediction model, determine a target environment voltage and a target environment temperature based on the device running environment, and perform on-resistance simulation on the semiconductor device set according to the gain prediction model, the target environment voltage and the target environment temperature to obtain a target on-resistance set. The optimal device identification module is configured to perform deviation analysis on the target on-resistance set based on a preset on-resistance criterion, obtain an on-resistance deviation set, identify an optimal semiconductor device from the semiconductor device set according to the on-resistance deviation set, and connect the optimal semiconductor device to a device running environment.

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