Cholesteric liquid crystal display device and its driving method

Abstract

This invention discloses a cholesteric liquid crystal display device and its driving method, belonging to the field of display technology. The device integrates a source switching module and an external driving module on a first substrate, respectively connected to the data leads of the driving chip, the external power supply, and the internal data lines. The driving method is executed by a timing control module. First, the external driving module is turned on to initialize the screen using an external high-voltage signal. Then, the system switches to the source switching module, using the low-voltage data signal from the driving chip and writing the image via time-division multiplexing. Finally, the display can be maintained by simultaneously turning off both modules to make the pixels float. This invention achieves safe switching of the driving source through structural innovation, effectively reducing the performance requirements of the driving chip, avoiding current backflow, and significantly reducing the number of chips used.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a cholesteric liquid crystal display device and its driving method. Background Technology

[0002] Cholesteric liquid crystal (ChLC) is an optically anisotropic material with a unique helical structure. Its core characteristic lies in its bistable effect: in the absence of an external electric field, cholesteric liquid crystals can stably exist in two microstructural states: a planar state (P-state) and a focal conic state (FC-state). The P-state, with its helical axes perpendicular to the substrate, exhibits Bragg reflection of specific wavelengths of light, thus displaying vibrant colors. The FC-state, with its multi-domain structure and randomly distributed helical axes, strongly scatters incident light, appearing milky white or opaque. Furthermore, when a sufficiently strong electric field is applied, the liquid crystal molecules can switch to a homeotropic state (H-state), and upon removal of the electric field, the H-state relaxes back to the P-state. This characteristic of maintaining display content without voltage makes cholesteric liquid crystals an ideal choice for applications such as electronic paper and low-power static signage.

[0003] Although cholesteric liquid crystals have the advantage of low power consumption, their driving technology faces serious challenges. Existing solutions mainly suffer from the following bottlenecks:

[0004] The transition of cholesteric liquid crystals from one steady state to another, especially from the P-state or FC-state to the H-state (or from the H-state to a rapid reset), typically requires a short pulse with a relatively high voltage (usually greater than 15V, and even reaching 20V-40V). However, mainstream display driver ICs are manufactured using large-scale integrated CMOS processes, and their design optimization focuses on high integration and low cost, resulting in their output voltage range typically limited to 0V to 10V, or even lower. This gap between "high demand" and "low capability" forces traditional designs to adopt the following complex and inefficient solutions:

[0005] Charge pump boost circuits add a DC-DC boost circuit inside or outside the driver chip to boost the chip's core voltage to achieve the required high driving voltage. This not only increases system complexity and PCB area, but the boost process also introduces additional power loss, generates electromagnetic interference, and contradicts the extremely low power consumption design of electronic paper.

[0006] Multi-level drive waveforms employ complex multi-step drive waveforms, ultimately achieving state switching through the cumulative effect of a series of medium- and low-voltage pulses. This method significantly reduces refresh rate, resulting in sluggish screen transitions and failing to meet the needs of dynamic display or rapid page turning.

[0007] To achieve full-color display, existing cholesteric liquid crystal display (CLCD) products generally employ multi-layer screen lamination technology. This involves fabricating three separate monochrome cholesteric liquid crystal panels for displaying red (R), green (G), and blue (B), and then precisely aligning and bonding them together. This means that a single color pixel is actually composed of sub-pixels belonging to three separate physical panels. The resulting problem is that each display layer requires an independent driving system, including complete row and column driver chips. Therefore, the total number of driver chips increases by 2 to 3 times compared to monochrome displays. This not only significantly increases material costs but also makes the display module thicker and heavier, and increases the complexity of the assembly process and the risk of yield loss.

[0008] To resolve the first contradiction, sometimes an attempt is made to introduce a separate external high-voltage source to directly drive the panel. However, in traditional display panel architectures, the output pins of the driver chip are directly connected to the source lines (data lines) of the panel. If an external high-voltage source is simply connected in parallel with the driver chip to the data lines, the high voltage can easily flow back through the data lines to the internal output stage circuitry of the driver chip at the instant the external high voltage is applied. The output transistors of the driver chip are designed for low voltage and cannot withstand such high voltage stress, which will instantly lead to overcurrent and thermal breakdown, causing permanent damage to the chip. This reliability issue severely restricts the practical application of high-voltage driving solutions.

[0009] In summary, existing cholesteric liquid crystal display devices face a triple dilemma in driving technology: insufficient high-voltage driving capability, excessively high system cost, and reliability risks associated with introducing high voltage. Those skilled in the art have long sought an innovative driving architecture and solution that can fundamentally solve these interrelated technical challenges, thereby promoting the application of cholesteric liquid crystal technology in a wider range of fields. Summary of the Invention

[0010] To address the technical problems existing in the background art, the present invention proposes a cholesteric liquid crystal display device and its driving method.

[0011] The cholesteric liquid crystal display device proposed in this invention includes a first substrate, a second substrate disposed opposite to the first substrate, a cholesteric liquid crystal layer disposed between the first substrate and the second substrate, a pixel electrode disposed on the first substrate, and a common electrode disposed on the first substrate or the second substrate, wherein the common electrode and the pixel electrode together sandwich the cholesteric liquid crystal layer. The device further includes:

[0012] Multiple data leads are used to receive data voltage signals from at least one driver chip;

[0013] Multiple internal data lines, each of which is electrically connected to a column of pixel electrodes;

[0014] The source switching module includes multiple source switching transistors. The source of each source switching transistor is connected to a data lead terminal, the drain of each source switching transistor is connected to an internal data line, and the gate of each source switching transistor is used to receive a source switching control signal.

[0015] An external drive module includes multiple external drive transistors. The drain of each external drive transistor is used to receive a first voltage signal, the source of each external drive transistor is connected to an internal data line, and the gate of each external drive transistor is used to receive an external drive control signal.

[0016] The source switching module establishes or disconnects the electrical connection between the data lead and the internal data line through the source switching control signal; the external drive module establishes or disconnects the electrical connection between the power supply used to provide the first voltage signal and the internal data line through the external drive control signal.

[0017] Preferably, the device further includes:

[0018] A timing control module is used to generate source switching control signals and external drive control signals. The output terminal of the timing control module outputs the source switching control signal to the gate of the source switching transistor and outputs the external drive control signal to the gate of the external drive transistor.

[0019] Preferably, the multiple data leads and the multiple internal data lines are all disposed on the first substrate.

[0020] Preferably, the source switching module establishes or disconnects the electrical connection between the data lead and the internal data line through a source switching control signal, specifically including:

[0021] When the source switching control signal is at an active level, the source switching transistor is turned on, establishing an electrical connection between the data lead and the internal data line; when the source switching control signal is at an inactive level, the source switching transistor is turned off, disconnecting the electrical connection.

[0022] Preferably, the external drive module establishes or disconnects the electrical connection between the power supply used to provide the first voltage signal and the internal data line through an external drive control signal, specifically including:

[0023] When the external drive control signal is at an active level, the external drive transistor is turned on, establishing an electrical connection between the power supply for providing the first voltage signal and the internal data line; when the external drive control signal is at an inactive level, the external drive transistor is turned off, disconnecting the electrical connection.

[0024] Preferably, the source switching module and the external driving module are integrated and disposed in the non-display area of ​​the first substrate.

[0025] The driving method for the cholesteric liquid crystal display device proposed in this invention includes the following steps:

[0026] High-voltage driving steps: The timing control module provides an effective level external driving control signal to the external driving module and an ineffective level source switching control signal to the source switching module, while providing an enable voltage to the scan lines of all pixel rows; A first voltage signal is applied to the internal data line through the activated external driving module to charge the pixel electrodes connected to the internal data line;

[0027] Stabilization steps: The timing control module maintains the on state of the external drive module and the off state of the source switching module, and grounds the power supply that provides the first voltage signal, so that the internal data lines and pixel electrodes are discharged.

[0028] Data writing steps: The timing control module provides an invalid level external drive control signal to the external drive module and turns on the scan line of the pixel row line by line; the timing control module provides an effective level source switching control signal to the selected source switching transistor in the source switching module in a time-division multiplexing manner; the data voltage signal from the driver chip is applied to the corresponding internal data line through the turned-on source switching module.

[0029] Preferably, in the high-voltage driving step, the cholesteric liquid crystal layer is switched to a vertical alignment state; in the stabilization step, the cholesteric liquid crystal layer relaxes to a planar state; and in the data writing step, the corresponding region of the cholesteric liquid crystal layer switches from a planar state to a focal conic state.

[0030] Preferably, in the data writing step, the timing control module provides effective source switching control signals to multiple source switching transistors connected to the same internal data line in a time-division manner, so that one data lead provides the data voltage signal to multiple pixel columns in a time-division manner.

[0031] Preferably, the method further includes:

[0032] Reset steps: The timing control module provides an invalid source switching control signal to the source switching module, and provides an effective external drive control signal to the external drive module and grounds the power supply that provides the first voltage signal. At the same time, it provides an enable voltage to the scan lines of all pixel rows to discharge all pixel electrodes.

[0033] This invention proposes a cholesteric liquid crystal display device and its driving method, which integrates a source switching module and an external driving module inside the display panel to construct an innovative driving architecture. This architecture, through precise coordination by a timing control module, achieves safe and efficient switching between external high-voltage driving and internal chip data writing modes. This not only significantly reduces the requirements for the output voltage and current capabilities of the driving chip, broadening the range of chip selection and reducing system costs, but its physical isolation mechanism also fundamentally eliminates the risk of high-voltage backflow damaging the driving chip, improving system reliability. Simultaneously, the signal time-division multiplexing technology implemented using the source switching module enables a single driving chip channel to serve multiple pixels, thereby significantly reducing the number of driving chips required to achieve the same resolution display. This cost-saving effect is particularly significant for color electronic paper requiring multi-layer lamination. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the distribution structure of an embodiment of the cholesteric liquid crystal display device proposed in this invention;

[0035] Figure 2 This is a schematic diagram of the circuit structure connection of one embodiment of the cholesteric liquid crystal display device proposed in this invention;

[0036] Figure 3 This is a timing diagram for the existing technology.

[0037] Figure 4 This is a driving timing diagram of one embodiment of the driving method for the cholesteric liquid crystal display device proposed in this invention;

[0038] Figure 5 This is a flowchart illustrating the driving method for the cholesteric liquid crystal display device proposed in this invention. Detailed Implementation

[0039] Reference Figures 1-5 The cholesteric liquid crystal display device proposed in this invention includes a first substrate, a second substrate disposed opposite to the first substrate, a cholesteric liquid crystal layer disposed between the first substrate and the second substrate, a pixel electrode disposed on the first substrate, and a common electrode disposed on the first substrate or the second substrate, wherein the common electrode and the pixel electrode together sandwich the cholesteric liquid crystal layer. The device further includes:

[0040] Multiple data leads are used to receive data voltage signals from at least one driver chip.

[0041] Multiple internal data lines, each of which is electrically connected to a column of pixel electrodes.

[0042] The source switching module includes multiple source switching transistors. The source of each source switching transistor is connected to a data lead terminal, the drain of each source switching transistor is connected to an internal data line, and the gate of each source switching transistor is used to receive a source switching control signal.

[0043] Specifically, the source switching module and the external drive module are integrated and set in the non-display area of ​​the first substrate.

[0044] An external drive module includes multiple external drive transistors. The drain of each external drive transistor is used to receive a first voltage signal, the source of each external drive transistor is connected to an internal data line, and the gate of each external drive transistor is used to receive an external drive control signal.

[0045] The source switching module establishes or disconnects the electrical connection between the data lead and the internal data line through the source switching control signal; the external drive module establishes or disconnects the electrical connection between the power supply used to provide the first voltage signal and the internal data line through the external drive control signal.

[0046] In this embodiment, the device further includes:

[0047] The timing control module is used to generate source switching control signals and external drive control signals. The output terminal of the timing control module outputs the source switching control signal to the gate of the source switching transistor and outputs the external drive control signal to the gate of the external drive transistor.

[0048] In this embodiment, multiple data leads and multiple internal data lines are disposed on the first substrate.

[0049] Specifically, the source switching module establishes or disconnects the electrical connection between the data lead and the internal data line through a source switching control signal, including:

[0050] When the source switching control signal is at an active level, the source switching transistor is turned on, establishing an electrical connection between the data lead and the internal data line; when the source switching control signal is at an inactive level, the source switching transistor is turned off, disconnecting the electrical connection.

[0051] Specifically, the external drive module establishes or disconnects the electrical connection between the power supply used to provide the first voltage signal and the internal data line through an external drive control signal, including:

[0052] When the external drive control signal is at an active level, the external drive transistor is turned on, establishing an electrical connection between the power supply for providing the first voltage signal and the internal data line; when the external drive control signal is at an inactive level, the external drive transistor is turned off, disconnecting the electrical connection.

[0053] Example 1:

[0054] In this embodiment, the source switching module includes three source switching transistors, and the external drive module includes three external drive transistors. For example... Figure 1 and Figure 2 As shown, the cholesteric liquid crystal display device of the present invention mainly includes a display panel and a printed circuit board (PCB) or flexible circuit board (FPC) control section connected thereto. The display panel includes a first substrate (such as a TFT array substrate) and a second substrate (such as a color filter substrate) disposed opposite to each other, and a cholesteric liquid crystal layer filled between the two. An integrated driving circuit is integrated into the edge region of the first substrate (i.e., above the gold fingers) using semiconductor technology. This integrated driving circuit consists of two parts:

[0055] The source switching module includes source switching transistors T1, T2, and T3. The source of each source switching transistor is connected to an independent data lead via a metal trace, which corresponds to a source output pin on the gold finger of the driver chip. The drains of all source switching transistors are connected to a common internal data line, i.e., the source line inside the panel, which ultimately connects to the pixel electrode of the pixel matrix.

[0056] An external drive module includes external drive transistors Tn1, Tn2, and Tn3. The drain of each external drive transistor is connected to an external high-voltage power supply to receive a first voltage signal. The sources of all external drive transistors are connected to the aforementioned internal data lines.

[0057] The gate pins of both the source switching transistor and the external drive transistor are connected to the timing control module on the printed circuit board (PCB) via bonding wires on the flexible circuit board.

[0058] The timing control module includes a field-programmable gate array (FPGA) and a level shifter. The FPGA is responsible for generating the original source switching control signals and external drive control signals according to a preset algorithm. The level shifter converts the low-voltage logic signals (such as 0V / 3.3V) output by the FPGA into high and low voltage signals (such as -5V / 25V) required to drive the thin-film transistor gate to turn on and off.

[0059] Reference Figures 1-5 The driving method for the cholesteric liquid crystal display device proposed in this invention includes the following steps:

[0060] High-voltage driving steps: The timing control module provides an effective level external driving control signal to the external driving module and an ineffective level source switching control signal to the source switching module, while providing an enable voltage to the scan lines of all pixel rows; A first voltage signal is applied to the internal data line through the activated external driving module to charge the pixel electrodes connected to the internal data line;

[0061] Stabilization steps: The timing control module maintains the on state of the external drive module and the off state of the source switching module, and grounds the power supply that provides the first voltage signal, so that the internal data lines and pixel electrodes are discharged.

[0062] Data writing steps: The timing control module provides an invalid level external drive control signal to the external drive module and turns on the scan line of the pixel row line by line; the timing control module provides an effective level source switching control signal to the selected source switching transistor in the source switching module in a time-division multiplexing manner; the data voltage signal from the driver chip is applied to the corresponding internal data line through the turned-on source switching module.

[0063] In this embodiment, during the high-voltage driving step, the cholesteric liquid crystal layer is switched to a vertical alignment state; during the stabilization step, the cholesteric liquid crystal layer relaxes to a planar state; and during the data writing step, the corresponding region of the cholesteric liquid crystal layer switches from a planar state to a focal conic state.

[0064] In this embodiment, during the data writing step, the timing control module provides effective source switching control signals to multiple source switching transistors connected to the same internal data line in a time-division manner, so that one data lead provides data voltage signals to multiple pixel columns in a time-division manner.

[0065] In this embodiment, the method further includes:

[0066] Reset steps: The timing control module provides an invalid source switching control signal to the source switching module, and provides an effective external drive control signal to the external drive module and grounds the power supply that provides the first voltage signal. At the same time, it provides an enable voltage to the scan lines of all pixel rows to discharge all pixel electrodes.

[0067] like Figure 4 As shown, the workflow of the driving method corresponding to Embodiment 1 specifically includes:

[0068] Phase 1: High-voltage drive phase (H-state writing)

[0069] The timing control module provides an invalid level control signal (e.g., low level) to the gates of all source switching transistors (T1~T3), turning them all off. This operation physically disconnects the driver chip from the internal data lines, forming isolation and effectively preventing subsequent high-voltage backflow from damaging the driver chip. Simultaneously, the timing control module provides an valid level control signal (e.g., high level) to the gates of all external driver transistors (Tn1~Tn3), turning them all on. Furthermore, all scan lines (G1, G2, … Gm) of all pixel rows are applied an on-state voltage, entering a global on state (Xon state). At this time, the external high-voltage power supply generates a first voltage signal with an absolute value greater than 15V (e.g., an AC pulse of +20V followed by -20V). This signal is directly applied to the internal data lines through the on external driver transistors, charging all pixel electrodes. Under the influence of the strong electric field, the cholesteric liquid crystal molecules align vertically, entering a vertical alignment state (H state).

[0070] Phase Two: Stable Phase (P-state Preparation)

[0071] The external driving transistors (Tn1~Tn3) are kept in the ON state, and the source switching transistors (T1~T3) are kept in the OFF state. The output of the external high-voltage power supply and the common electrode (AC common electrode) are switched to ground (0V). The internal data lines discharge to ground through the ON external driving transistors, and the pixel electrode voltage drops to 0V. After the electric field is removed, the cholesteric liquid crystal molecules rely on their own elastic relaxation to uniformly transition from the H state to the stable planar state (P state), providing a uniform initial optical background for subsequent image data writing.

[0072] Phases 3 and 4: Data Writing and Source-to-Source Reuse Phase (FC State Writing)

[0073] The timing control module sets the gate control signals of the external drive transistors (Tn1~Tn3) to an invalid level (low level), turning them all off and completely disconnecting the external high-voltage source to ensure the safety of the drive chip. Subsequently, the system begins the data writing process. When the timing control module activates the first scan line G1, it sequentially provides valid control signals (high level) to the gates of the source switching transistors T1, T2, and T3 in a time-division manner.

[0074] When T1 is turned on, the driver chip outputs a data voltage signal (e.g., +5V) through data lead 1, which is then written to pixel PS1 in the first row and first column via T1 and the internal data line.

[0075] Subsequently, T1 is turned off and T2 is turned on, and the driver chip writes the data voltage signal into the pixel PS2 in the first row and second column through data lead 2.

[0076] Similarly, when T3 is turned on, data is written to PS3.

[0077] This process achieves source channel multiplexing, meaning that the output channel of one driver chip sequentially controls three different pixel columns through time-division multiplexing. Pixels with applied data voltages switch their cholesteric liquid crystals from the P-state to the focal conic (FC) state. The FC state scatters light, creating a contrast with the surrounding reflective regions that remain in the P-state, thus forming an image. After completing row G1, G1 is turned off, G2 is turned on, and the time-division multiplexing process is repeated until the entire frame of image data is written.

[0078] Phase Five: Polarity Reversal Phase

[0079] This stage repeats the data writing and source multiplexing process of stages three and four, but the polarity of the data voltage signal output by the driver chip is reversed (for example, a pixel with +5V in a positive frame becomes -5V in a negative frame). This is intended to achieve frame inversion drive, which balances the DC component applied to the liquid crystal, prevents electrochemical degradation of the liquid crystal material, and ensures the long-term quality and lifespan of the display.

[0080] Phase Six: Reset Phase

[0081] After both positive and negative frames of data have been written, the timing control module sets the control signals of all source switching transistors (T1~T3) to an inactive level, ensuring they are all turned off and completely disconnecting the driver chip. Simultaneously, it sets the control signals of all external driver transistors (Tn1~Tn3) to an active level, turning them on, and grounds their source input terminals. Furthermore, it simultaneously turns on the scan lines (G1~Gm) of all pixel rows (Xon state). At this time, all pixel electrodes discharge to ground through the conducting external driver transistors and pixel transistors, quickly resetting to 0V potential, completing the display operation of one entire image, and the screen prepares to receive the drive signal for the next frame.

[0082] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A cholesteric liquid crystal display device, comprising a first substrate, a second substrate disposed opposite to the first substrate, a cholesteric liquid crystal layer disposed between the first substrate and the second substrate, a pixel electrode disposed on the first substrate, and a common electrode disposed on the first substrate or the second substrate, wherein the common electrode and the pixel electrode together sandwich the cholesteric liquid crystal layer, characterized in that, The device also includes: Multiple data leads are used to receive data voltage signals from at least one driver chip; Multiple internal data lines, each of which is electrically connected to a column of pixel electrodes; The source switching module includes multiple source switching transistors. The source of each source switching transistor is connected to a data lead terminal, the drain of each source switching transistor is connected to an internal data line, and the gate of each source switching transistor is used to receive a source switching control signal. An external drive module includes multiple external drive transistors. The drain of each external drive transistor is used to receive a first voltage signal, the source of each external drive transistor is connected to an internal data line, and the gate of each external drive transistor is used to receive an external drive control signal. The source switching module establishes or disconnects the electrical connection between the data lead and the internal data line through the source switching control signal; the external drive module establishes or disconnects the electrical connection between the power supply used to provide the first voltage signal and the internal data line through the external drive control signal.

2. The cholesteric liquid crystal display device according to claim 1, characterized in that, The device further includes: A timing control module is used to generate source switching control signals and external drive control signals. The output terminal of the timing control module outputs the source switching control signal to the gate of the source switching transistor and outputs the external drive control signal to the gate of the external drive transistor.

3. The cholesteric liquid crystal display device according to claim 1, characterized in that, The multiple data leads and multiple internal data lines are all disposed on the first substrate.

4. The cholesteric liquid crystal display device according to claim 1, characterized in that, The source switching module establishes or disconnects the electrical connection between the data lead and the internal data line through a source switching control signal, specifically including: When the source switching control signal is at an active level, the source switching transistor is turned on, establishing an electrical connection between the data lead and the internal data line; when the source switching control signal is at an inactive level, the source switching transistor is turned off, disconnecting the electrical connection.

5. The cholesteric liquid crystal display device according to claim 1, characterized in that, The external drive module establishes or disconnects the electrical connection between the power supply used to provide the first voltage signal and the internal data line through an external drive control signal, specifically including: When the external drive control signal is at an active level, the external drive transistor is turned on, establishing an electrical connection between the power supply for providing the first voltage signal and the internal data line; when the external drive control signal is at an inactive level, the external drive transistor is turned off, disconnecting the electrical connection.

6. The cholesteric liquid crystal display device according to claim 1, characterized in that, The source switching module and the external driving module are integrated and disposed in the non-display area of ​​the first substrate.

7. A driving method for a cholesteric liquid crystal display device, characterized in that, Includes the following steps: High-voltage driving steps: The timing control module provides an effective level external driving control signal to the external driving module and an ineffective level source switching control signal to the source switching module, while providing an enable voltage to the scan lines of all pixel rows; A first voltage signal is applied to the internal data line through the activated external driving module to charge the pixel electrodes connected to the internal data line; Stabilization steps: The timing control module maintains the on state of the external drive module and the off state of the source switching module, and grounds the power supply that provides the first voltage signal, so that the internal data lines and pixel electrodes are discharged. Data writing steps: The timing control module provides an invalid level external drive control signal to the external drive module and turns on the scan line of the pixel row line by line; the timing control module provides an effective level source switching control signal to the selected source switching transistor in the source switching module in a time-division multiplexing manner; the data voltage signal from the driver chip is applied to the corresponding internal data line through the turned-on source switching module.

8. The driving method for the cholesteric liquid crystal display device according to claim 7, characterized in that, In the high-voltage driving step, the cholesteric liquid crystal layer is switched to a vertical alignment state; in the stabilization step, the cholesteric liquid crystal layer relaxes to a planar state; in the data writing step, the corresponding region of the cholesteric liquid crystal layer switches from the planar state to the focal conic state.

9. The driving method for the cholesteric liquid crystal display device according to claim 7 or 8, characterized in that, In the data writing step, the timing control module provides effective source switching control signals to multiple source switching transistors connected to the same internal data line in a time-division manner, so that one data lead provides the data voltage signal to multiple pixel columns in a time-division manner.

10. The driving method for the cholesteric liquid crystal display device according to claim 7 or 8, characterized in that, The method further includes: Reset steps: The timing control module provides an invalid source switching control signal to the source switching module, and provides an effective external drive control signal to the external drive module and grounds the power supply that provides the first voltage signal. At the same time, it provides an enable voltage to the scan lines of all pixel rows to discharge all pixel electrodes.

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