Method of manufacturing a semiconductor structure
By forming a metal silicide layer on the surface of the protective layer to seal pinhole defects, the problem of etching solution penetration caused by insufficient thickness of amorphous silicon thin film is solved, thereby improving the performance and reliability of semiconductor structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SWAYSURE TECHNOLOGY CO LTD
- Filing Date
- 2025-11-05
- Publication Date
- 2026-05-22
AI Technical Summary
In existing technologies, amorphous silicon thin films with a thickness of less than 5 nm are prone to pinhole defects, which can cause wet etching solution to penetrate and damage the underlying protective layer, affecting the performance of the semiconductor structure.
A metal layer is formed on the surface of the protective layer and then heat-treated to allow the amorphous silicon and metal to react chemically to form a metal silicide layer, which seals pinhole defects and forms a dense metal silicide layer to prevent the etching solution from penetrating.
It effectively prevents etching solution penetration, protects the underlying protective layer, and improves the performance and reliability of the semiconductor structure.
Smart Images
Figure CN121054483B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for preparing a semiconductor structure. Background Technology
[0002] In some semiconductor structures (such as 3D memory), a thin amorphous silicon film needs to be formed on the layer to be protected as a protective layer to prevent the etching solution from penetrating into the layer to be protected during subsequent wet etching, which would damage the layer to be protected and thus affect the performance of the semiconductor structure.
[0003] However, the continuity of amorphous silicon thin films is highly dependent on their thickness. Only when the thickness of the amorphous silicon thin film is greater than 5nm can a continuous thin film without obvious pores be formed. Once the thickness of the amorphous silicon thin film is less than 5nm, the film will be discontinuous and form pinhole defects extending in the thickness direction. This makes it easy for the subsequent wet etching solution to contact the underlying layer to be protected through the pinhole defects, causing the underlying layer to be protected to suffer etching damage, and ultimately affecting the performance of the semiconductor structure.
[0004] Therefore, this application proposes a new method for fabricating semiconductor structures to at least partially solve the above-mentioned technical problems. Summary of the Invention
[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0006] To address the existing problems, embodiments of the present invention provide a method for fabricating a semiconductor structure, the method comprising:
[0007] Forming the initial semiconductor structure;
[0008] A protective layer is formed on the surface of the initial semiconductor structure;
[0009] A protective layer is formed on the surface of the layer to be protected. The protective layer contains pinhole defects extending along the thickness direction of the protective layer. The material of the protective layer is amorphous silicon.
[0010] A metal layer is formed on the surface of the protective layer, and then heat treatment is performed to cause the amorphous silicon in the protective layer to react chemically with the metal in the metal layer to form metal silicide, at least transforming the surface layer of the protective layer into a metal silicide layer; wherein, there are no pinhole defects penetrating the metal silicide layer along the thickness direction of the metal silicide layer.
[0011] In some embodiments of this application, the material of the metal layer includes at least one of Co, Ni, Ti, W and Pt, and the method of forming the metal layer includes physical vapor deposition.
[0012] In some embodiments of this application, the heat treatment includes rapid thermal annealing.
[0013] In some embodiments of this application, a portion of the metal layer undergoes a chemical reaction with the protective layer, and after heat treatment, a residual metal layer remains on the metal silicide layer.
[0014] In some embodiments of this application, the preparation method further includes:
[0015] The remaining metal layer was removed using a wet etching method.
[0016] In some embodiments of this application, a portion of the protective layer undergoes a chemical reaction with the metal layer, and after heat treatment, a residual protective layer remains between the layer to be protected and the metal silicide layer.
[0017] In some embodiments of this application, the initial semiconductor structure includes:
[0018] The substrate and a stacked layer above the substrate, and a bottom electrode layer between the stacked layer and the substrate, the stacked layer comprising a plurality of alternating stacked first material layers and a plurality of second material layers, and through-holes formed in the stacked layer, the bottom of the through-holes exposing the top of the bottom electrode layer;
[0019] The protective layer shall at least cover the bottom and sidewalls of the through hole, and the protective layer shall conform to the surface of the protective layer. The material of the protective layer shall be an insulating material.
[0020] In some embodiments of this application, the preparation method further includes:
[0021] A dry etching process is used to remove at least the metal silicide layer at the bottom of the via, so as to expose the protective layer at the bottom of the via.
[0022] A wet etching process is used to remove the protective layer located at the bottom of the via and exposed to expose the bottom electrode layer.
[0023] In some embodiments of this application, a portion of the metal layer reacts chemically with the protective layer, and after heat treatment, a residual metal layer remains on the metal silicide layer;
[0024] Before the step of removing the metal silicide layer located at the bottom of the via, the method further includes: removing the remaining metal layer by wet etching.
[0025] In some embodiments of this application, a portion of the protective layer undergoes a chemical reaction with the metal layer, and after heat treatment, a residual protective layer remains between the layer to be protected and the metal silicide layer.
[0026] After removing the metal silicide at the bottom of the via using a dry etching process, the process also includes continuing to use a dry etching process to remove the remaining protective layer at the bottom of the via, so as to expose the protective layer at the bottom of the via.
[0027] According to the semiconductor structure fabrication method provided by the present invention, by forming a metal layer on a protective layer, the amorphous silicon in the protective layer reacts chemically with the metal in the metal layer to form a metal silicide, at least the surface layer of the protective layer is transformed into a metal silicide layer. The metal silicide layer does not have pinhole defects that penetrate the metal silicide layer along the thickness direction, thereby physically sealing the original pinhole defects and providing a more reliable protective barrier for the underlying protective layer. This avoids damage to the protective layer caused by the penetration of the etching solution in subsequent wet etching, thereby improving the performance of the semiconductor structure. Attached Figure Description
[0028] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.
[0029] In the attached image:
[0030] Figures 1A to 1F A cross-sectional schematic diagram of the structure obtained by each step of a method for fabricating a three-dimensional memory in a related art is shown;
[0031] Figure 2 A schematic flowchart of a method for fabricating a semiconductor structure according to a specific embodiment of the present invention is shown;
[0032] Figures 3A to 3C The diagram shows a cross-sectional view of the structure obtained by each step of the semiconductor structure fabrication method according to a specific embodiment of the present invention.
[0033] Figures 4A to 4J A cross-sectional schematic diagram of the structure obtained by each step of the semiconductor structure fabrication method according to another specific embodiment of the present invention is shown. Detailed Implementation
[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.
[0035] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “ / the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0039] First, refer to Figures 1A to 1F This paper introduces a method for fabricating a semiconductor structure in related technologies. The method includes the following steps:
[0040] In step S1, as Figure 1A As shown, an initial semiconductor structure is provided, comprising: a substrate 101 and a stacked layer 105 located above the substrate 101, and a bottom electrode layer 102 located between the stacked layer 105 and the substrate 101. The stacked layer 105 includes a plurality of alternating stacked first material layers 104 and a plurality of second material layers 103. A via 106 is formed in the stacked layer 105, and the bottom of the via 106 exposes the top of the bottom electrode layer 102.
[0041] In step S2, as Figure 1B As shown, a protective layer 107, such as a silicon oxide sidewall dielectric layer, is formed on the bottom and sidewall of the through-hole 106.
[0042] In step S3, as Figure 1C As shown, an amorphous silicon thin film 108 is formed to conformally cover the surface of the protective layer 107, which serves as a protective layer. However, the continuity of the amorphous silicon thin film is highly dependent on its thickness. When the thickness of the amorphous silicon thin film is greater than 5 nm, a continuous film with no obvious pores on the surface can be formed. However, once the thickness of the amorphous silicon thin film is less than 5 nm, the film will be discontinuous and pinhole defects extending in the thickness direction will be formed.
[0043] In step S4, as Figure 1D As shown, a dry etching process is used to remove the amorphous silicon film 108 located at the bottom of the via 106. Since there are pinhole defects 1081 in the amorphous silicon film 108, the plasma of the dry etching process in this step may damage the amorphous silicon film 108, which may cause the size of the pinhole defects 1081 to increase, or even damage the protective layer 107 through the pinhole defects 1081.
[0044] In step S5, as Figure 1EAs shown, a wet etching process is used to remove the protective layer 107 exposed at the bottom of the via 106, thereby exposing the bottom electrode layer 102. Among these steps... Figure 1E The arrows in the diagram indicate the general flow direction of the etching solution in wet etching.
[0045] Because pinhole defects 1081 exist in the amorphous silicon thin film 108, the etching solution in this wet etching step can easily contact the underlying sidewall dielectric layer through the pinhole defects, causing etching damage to the underlying sidewall dielectric layer and forming, for example, in the sidewall dielectric layer. Figure 1F The fracture defects shown can lead to leakage current, affecting the performance of semiconductor structures such as three-dimensional memory.
[0046] Therefore, in view of the technical problems described above, embodiments of the present invention provide a method for fabricating a semiconductor structure, referring to... Figure 2 The preparation method mainly includes the following steps:
[0047] In step S210, an initial semiconductor structure is formed;
[0048] In step S220, a protective layer is formed on the surface of the initial semiconductor structure;
[0049] In step S230, a protective layer is formed on the surface of the layer to be protected. The protective layer contains pinhole defects extending along the thickness direction of the protective layer. The material of the protective layer is amorphous silicon.
[0050] In step S240, a metal layer is formed on the surface of the protective layer, and then heat treatment is performed to cause the amorphous silicon in the protective layer to react chemically with the metal in the metal layer to form a metal silicide, at least transforming the surface layer of the protective layer into a metal silicide layer; wherein, there are no pinhole defects penetrating the metal silicide layer along the thickness direction of the metal silicide layer.
[0051] In the above scheme, by forming a metal layer on the protective layer, the amorphous silicon in the protective layer reacts chemically with the metal in the metal layer to form metal silicide, at least the surface layer of the protective layer is transformed into a metal silicide layer. The metal silicide layer does not have pinhole defects that penetrate the metal silicide layer along the thickness direction, thereby physically sealing the original pinhole defects and providing a more reliable protective barrier for the underlying protective layer. This avoids damage to the protective layer caused by the penetration of the etching solution in subsequent wet etching, thereby improving the performance of the semiconductor structure.
[0052] Below, for reference Figures 3A to 3C and Figures 4A to 4J A method for fabricating a semiconductor structure according to one embodiment of this application is described in detail.
[0053] First, refer to Figure 3A , Figure 4A This forms the initial semiconductor structure.
[0054] The initial semiconductor structure may include a substrate 401 and transistors, capacitors, interconnect structures, etc. (not shown in the figure) formed on the substrate 401, the specific configuration of which depends on the type of device being fabricated. Alternatively, the initial semiconductor structure may consist only of the substrate 401, without any other structures formed on the substrate 401.
[0055] In a specific example, the semiconductor structure can be a three-dimensional memory, which can include DRAM (Dynamic Random Access Memory) or other types of three-dimensional memory.
[0056] like Figure 4A As shown, taking a three-dimensional memory semiconductor structure as an example, the initial semiconductor structure may include: a substrate 401 and a stacked layer 405 located above the substrate 401, and a bottom electrode layer 402 located between the stacked layer 405 and the substrate 401. The stacked layer 405 includes a plurality of alternately stacked first material layers 404 and a plurality of second material layers 403. A via 406 is formed in the stacked layer 405, and the bottom of the via 406 exposes the top of the bottom electrode layer 402. It can be understood that the via 406 exposing the top of the bottom electrode layer 402 includes the via 406 extending or not extending into a certain depth of the bottom electrode layer 402.
[0057] In some embodiments, the stacked layer 405 includes a plurality of alternately stacked first material layers 404 and a plurality of second material layers 403. The selection of the first material layers 404 and the second material layers 403 can be varied. In some embodiments, the first material layer 404 can be a dielectric layer; the second material layer 403 can be a horizontal conductor layer (which is substantially parallel to the surface of the substrate 401) or a sacrificial layer, and its specific material can be determined according to the fabrication process.
[0058] The function of the bottom electrode layer 402 disposed on the substrate 401 can be determined according to the specific type of the three-dimensional memory, as exemplarily described below. In some embodiments, the three-dimensional memory may include DRAM (Dynamic Random Access Memory), specifically 1TnC (one transistor corresponds to n capacitors in series, n≥1 and is an integer) DRAM, wherein the n capacitors in series are formed by n horizontal electrodes and vertical electrodes passing through these horizontal electrodes. It is understood that the capacitor also includes a capacitor dielectric layer located between the horizontal electrodes and the vertical electrodes. One transistor is used as a selection unit, which is used to select the vertical electrode. The selection unit may also be a selection circuit composed of multiple transistors or other selection circuits. This application does not make specific limitations, as long as the vertical electrode can be selected. For example, the selection unit is directly electrically connected to the vertical electrode, or the selection unit is electrically connected to the bottom electrode layer 402 and then electrically connected to the vertical electrode through the bottom electrode layer 402, thereby enabling the vertical electrode to be selected by the selection unit. In other embodiments, the three-dimensional memory may include other types of three-dimensional memory in which a sidewall dielectric layer with a bottom opening is formed in the via 406 through the stacked layer 405 without damaging the bottom electrode layer 402 exposed at the bottom of the via 406.
[0059] In one example, the capacitor dielectric layer comprises a ferroelectric material, making the three-dimensional memory a ferroelectric memory. However, this is not a limitation; in some embodiments, the capacitor dielectric layer can be made of other materials, as long as it can store data bits.
[0060] There are several ways to form the via 406 in the stacked layer 405. For example, refer to... Figure 4A Vias 406 are formed in the stacked layer 405 using processes such as, but not limited to, photolithography and dry etching. The etching process for forming the vias 406 stops at the upper surface of the bottom electrode layer 402 or extends partially into the bottom electrode layer 402, in which case the bottom of the via 406 exposes the top of the bottom electrode layer 402. The dimensions of the vias 406, such as the depth and diameter, can be adjusted according to actual needs. The shape of the vias 406, such as whether the horizontal cross-section of the via 406 is circular, elliptical, polygonal, or strip-shaped, whether the shapes of multiple horizontal cross-sections of the vias 406 are the same, and whether the shapes of different vias 406 are the same when there are multiple vias 406, can be adjusted according to actual needs. This application does not impose specific limitations on these aspects.
[0061] Next, refer to Figure 3A and Figure 4B A protective layer 407 is formed on the surface of the initial semiconductor structure.
[0062] The surface of the initial semiconductor structure can be the top surface of the initial semiconductor structure, which can be a generally flat surface, or it can be the bottom and sidewalls of the via 406, or it can be the bottom and sidewalls of the via 406 and the top surface of the stacked layer 405.
[0063] The material of the protective layer 407 can be an insulating material, which may include silicon nitride, silicon oxide, or other suitable insulating material layers. In this embodiment, the material of the protective layer 407 includes silicon oxide.
[0064] In a specific example, such as Figure 4B As shown, a protective layer 407 (sometimes referred to herein as a sidewall dielectric layer) is formed, which covers the bottom and sidewalls of the via 406, meaning the protective layer 407 at least covers the bottom and sidewalls of the via 406. In some embodiments, the thickness of the protective layer 407 is uniform, but this is not limited to it; the thickness distribution of the protective layer 407 can be controlled according to actual needs. The protective layer 407 can be formed using processes such as atomic layer deposition, thereby ensuring that the protective layer 407 uniformly covers the top of the stacked layer 405, the bottom and sidewalls of the via 406, but this is not limited to it; in some embodiments, the processes for forming the protective layer 407 include chemical vapor deposition or physical vapor deposition.
[0065] Next, refer to Figure 3A and Figure 4C A protective layer 408 is formed on the surface of the protective layer 407. A pinhole defect 4081 extending along the thickness direction of the protective layer 408 exists in the protective layer 408. The material of the protective layer 408 is amorphous silicon.
[0066] The protective layer 408 can be deposited using substrate methods including, but not limited to, physical vapor deposition and chemical vapor deposition. In a specific example, amorphous silicon can be deposited using low-pressure chemical vapor deposition.
[0067] In one example, such as Figure 4C As shown, the protective layer 407 at least covers the bottom and sidewalls of the through hole 406, and the protective layer 408 conformally covers the surface of the protective layer 407.
[0068] The protective layer 408 serves to protect the un-etched portion of the protective layer 407 during subsequent local etching, preventing etching damage to this portion. The thickness of the protective layer 408 is controlled within a relatively thin range, for example, less than 10 nanometers, preferably less than 5 nanometers, and more preferably 2 to 4 nanometers. This thickness range is chosen for considerations of overall device structure scale and compatibility with subsequent processes. However, this critical thickness parameter directly determines the morphology and defect characteristics of the protective layer 408 at this stage, resulting in pinhole defects 4081 extending along the thickness direction of the protective layer 408.
[0069] There can be multiple pinhole defects 4081, which are randomly distributed within the protective layer 408. They may penetrate the protective layer 408 in the thickness direction or not. These pinhole defects 4081 constitute weaknesses in subsequent wet etching processes. In subsequent processes, the etching solution can directly penetrate to the surface of the underlying protective layer 407 through these pinhole defects 4081, causing localized etching of the protective layer 407, forming etching damage, and ultimately severely affecting the electrical performance and reliability of the semiconductor structure.
[0070] Next, as Figures 3B-3C ,as well as Figures 4D to 4E As shown, a metal layer 409 is formed on the surface of the protective layer 408. Then, heat treatment causes the amorphous silicon in the protective layer 408 to react chemically with the metal in the metal layer 409 to form a metal silicide, at least transforming the surface layer of the protective layer 408 into a metal silicide layer 410. There are no pinhole defects 4081 in the metal silicide layer 410 that penetrate the metal silicide layer 410 along the thickness direction of the metal silicide layer 410.
[0071] The metal layer 409 is made of a metal that can react with silicon to form metal silicides, including but not limited to one or more of cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W) and platinum (Pt). Preferably, cobalt or nickel is selected because it can form low resistivity and high stability silicides (such as CoxSiy and NixSiy) with silicon at relatively low annealing temperatures.
[0072] The metal layer 409 can be formed by physical vapor deposition or other suitable methods, specifically sputtering. The thickness of the metal layer 409 can be designed according to the thickness of the target metal silicide layer 410, for example, in the range of 5 nanometers to 20 nanometers, or other suitable thicknesses.
[0073] like Figure 3B and Figure 4DAs shown, when there are pinhole defects 4081 in the protective layer 408 with openings facing the metal layer 409, the metal layer 409 can further fill these pinhole defects 4081.
[0074] After the metal layer 409 is formed, heat treatment is performed to allow a chemical reaction between the amorphous silicon and the metal. The heat treatment can be performed using rapid thermal annealing (RTA), furnace tube annealing, or other suitable annealing methods. Rapid thermal annealing is preferred.
[0075] In one example, during heat treatment, metal atoms in metal layer 409 cross the initial interface and react with amorphous silicon in protective layer 408. This reaction transforms at least the surface of protective layer 408 into metal silicide layer 410. This newly formed metal silicide layer 410 is continuous and dense. Because the silicide reaction involves interdiffusion of atoms, volume expansion, and atomic rearrangement, the original pinhole defects 4081 (e.g., pores and / or gaps) are eliminated in this process. Therefore, there are no pinhole defects 4081 penetrating along the thickness direction inside metal silicide layer 410.
[0076] Some of the metal layer 409 will react with the protective layer 408. Therefore, after heat treatment, there is a remaining, incompletely reacted metal layer 409 (i.e., the remaining metal layer 4091) on the surface of the metal silicide layer 410.
[0077] In this step, all of the protective layer 408 and the metal layer 409 may undergo a chemical reaction and be completely transformed into the metal silicide layer 410, or a portion of the protective layer 408 and the metal layer 409 may undergo a chemical reaction, and after heat treatment, there may be a remaining protective layer 4082 between the layer to be protected 407 and the metal silicide layer 410.
[0078] Through the deposition and heat treatment of the aforementioned metal layer 409, the porous, discontinuous amorphous silicon initial protective layer can be transformed in situ into a dense, complete, and chemically stable metal silicide layer 410. This metal silicide layer 410, acting as a subsequent protective layer, effectively blocks the penetration of subsequent wet etching solution, thus providing reliable protection for the underlying protective layer 407. This solves the problem that pinhole defects 4081 in the ultrathin protective layer easily lead to etching damage to the protective layer 407.
[0079] Next, as Figure 4F As shown, when the metal layer 409 has not fully reacted, the remaining metal layer 4091 is removed by wet etching.
[0080] Depending on the material of the metal layer 409, a suitable etching solution can be selected. For example, if the metal layer 409 includes Co, a mixed solution based on hydrochloric acid (HCl) and hydrogen peroxide (H2O2), or a standard SC-2 cleaning solution (HCl / H2O2 / H2O) can be used as the etching solution to etch the metal layer 409, while hardly causing any etching to the metal silicide layer 410.
[0081] Next, as Figure 4G As shown, a first dry etching process is used to remove at least the metal silicide layer 410 located at the bottom of the via 406, so as to expose the protective layer 407 located at the bottom of the via 406.
[0082] Before performing the first dry etching process, a patterned photoresist layer can be formed using photolithography. This patterned photoresist layer can expose only the metal silicide layer 410 at the bottom of the via 406. The subsequent first and second dry etching processes can both be performed using this patterned photoresist layer as a mask.
[0083] The first dry etching process can be reactive ion etching or other suitable etching methods. The first dry etching process can precisely etch vertically downwards to form an opening through the metal silicide layer 410, while causing almost no severe lateral etching to the surrounding sidewall material.
[0084] The appropriate etching gas can be selected based on the specific material of the metal silicide layer 410. For example, for cobalt silicides or nickel silicides, plasma chemical gases based on chlorine (such as Cl2) or bromine (such as HBr) can be used; for titanium silicides, fluorine-based gases (such as SF6, CF4) can be used.
[0085] When a residual protective layer 4082 exists between the protective layer 407 and the metal silicide layer 410, the first dry etching stops at the surface of the residual protective layer 4082. After removing the metal silicide layer 410 at the bottom of the via 406 using the first dry etching, a second dry etching process is used to remove the residual protective layer 4082 at the bottom of the via 406, exposing the protective layer 407 at the bottom of the via 406. This second dry etching is performed on amorphous silicon, for example, using an etching gas based on HBr and Cl2. The metal silicide layer 410 and the residual protective layer 4082 at the bottom of the via 406 are completely removed by the first and second dry etching processes, exposing the surface of the protective layer 407 at the bottom of the via 406, so that the protective layer 407 at the bottom of the via 406 can be removed by subsequent wet etching.
[0086] Next, as Figure 4HAs shown, a wet etching process is used to remove the protective layer 407 located at the bottom of the via 406 and exposed to expose the bottom electrode layer 402.
[0087] The protective layer 407 can be an insulating material, such as silicon nitride or silicon oxide. Wet etching can provide higher selectivity for the protective layer 407, ensuring that the protective layer 407 is completely removed without damaging the underlying bottom electrode layer 402.
[0088] Specifically, a suitable etching solution can be selected according to the material of the protective layer. For example, if the protective layer 407 is silicon nitride, hot phosphoric acid (H3PO4) can be used; if it is silicon oxide, diluted hydrofluoric acid (HF) or hydrofluoric acid vapor can be used. This wet etching exposes the bottom electrode layer 402, so as to facilitate the electrical lead-out of the bottom electrode layer 402.
[0089] In this wet etching process, the metal silicide layer 410 can effectively block the penetration of the etching solution, thereby providing reliable protection for the protective layer 407 on the sidewall. This solves the problem that the pinhole defect 4081 of the ultrathin protective layer can easily cause the protective layer 407 to suffer etching damage, ensuring the integrity of the device structure and the reliability of its electrical performance.
[0090] After removing the metal silicide at the bottom of the via 406 using a dry etching process, the remaining protective layer 4082 at the bottom of the via 406 is further removed using a dry etching process to expose the protective layer 407 at the bottom of the via 406.
[0091] like Figure 4I As shown, after exposing the bottom electrode layer 402, the metal silicide layer 410 and the remaining protective layer 4082 can be removed to expose the layer to be protected 407. Removing these layers can optimize the electrical performance of the device. For example, the metal silicide layer 410 and the remaining protective layer 4082 can be removed by wet etching with high selectivity. For example, wet etching has a higher etching selectivity for the metal silicide layer 410 and the remaining protective layer 4082 than for the layer to be protected 407 and the bottom electrode layer 402. Optionally, the etching selectivity is greater than 5:1.
[0092] Alternatively, the metal silicide layer 410 and the remaining protective layer 4082 can be left intact to simplify the process and reduce production costs.
[0093] In some embodiments, reference Figure 4J The preparation method may further include: forming a vertical conductor layer 411 electrically connected to the bottom electrode layer 402 in the remaining space of the through hole 406, thereby electrically connecting the vertical conductor layer 411 to the bottom electrode layer 402.
[0094] In some embodiments, the second material layer 403 includes a horizontal conductor layer and the first material layer 404 is a dielectric layer, such that adjacent horizontal conductor layers in the stacked layer 405 in the vertical direction are separated by the dielectric layer between them.
[0095] In other embodiments, the second material layer 403 includes a sacrificial layer that can be replaced with a horizontal conductor layer after the vertical conductor layer 411 is formed. Specific replacement methods may include: removing the sacrificial layer to form a horizontal groove between adjacent first material layers 404, and filling the horizontal groove to form a horizontal conductor layer.
[0096] A capacitor dielectric layer can be formed between the horizontal conductor layer and the vertical conductor layer 411. The storage cell of the three-dimensional memory can include a storage capacitor, which includes the horizontal conductor layer, the vertical conductor layer 411 and the capacitor dielectric layer between them.
[0097] In other embodiments, the vertical conductor layer 411 may include electrode pillars, which may be in direct contact with the layer to be protected 407, such as the sidewall dielectric layer or the bottom electrode layer 402. The electrode pillars and the horizontal conductor layer are isolated by the layer to be protected 407, thereby electrically isolating them. Optionally, the vertical conductor layer 411 includes electrode pillars and an electrode layer located between the electrode pillars and the stacked layer 405. That is, the vertical conductor layer 411 may be formed as a single layer or multiple layers. The electrode layer and the electrode pillars may be made of any conductor material, which is not specifically limited in this application. For example, during the formation of the vertical conductor layer 411, an electrode material layer can be formed first, covering the bottom of the via 406, the protective layer 407 (e.g., the sidewall dielectric layer), and the top of the stacked layer 405. Then, an electrode pillar material layer is filled, which fills the remaining space of the via 406 and covers the upper surface of the electrode material layer located at the bottom of the stacked layer 405. A planarization process such as chemical mechanical polishing is used to remove the electrode material layer and electrode pillar material layer located outside the via 406, so as to form an electrode layer and electrode pillars in the via 406. The electrode layer is located between the electrode pillars and the protective layer 407 and the bottom electrode layer 402 at the bottom of the via 406.
[0098] For example, the three-dimensional memory may further include a selection transistor (not shown in the figure), which, together with a storage capacitor, forms a storage cell of the three-dimensional memory. The selection transistor can be configured in various ways. For instance, the selection transistor may be formed on a substrate 401 and electrically connected to a bottom electrode layer 402, thereby enabling the selection transistor to conduct through the bottom electrode layer 402 to the vertical conductor layer 411. In other embodiments, the selection transistor may be formed on a stacked layer 405105 and electrically connected to the vertical conductor layer 411. In still other embodiments, the selection transistor may also be formed on a second substrate, and the second substrate is bonded to the first substrate, thereby achieving electrical connection of the selection transistor to the vertical conductor layer 411.
[0099] It should be noted that the aforementioned vertical conductor layer 411 is a conductor whose extension direction is perpendicular to the surface of the substrate 401. It can be any structure in a three-dimensional memory, such as, but not limited to, a cylindrical structure, a polygonal column structure, a conductive plate, or a conductive plug. Correspondingly, the through-hole 406 has a structure adapted to the vertical conductor layer 411. The aforementioned horizontal conductor layer is a conductor whose extension direction is parallel to the surface of the substrate 401. It can be any structure in a three-dimensional memory, such as, but not limited to, conductive lines or conductive plates. The vertical conductors can be distributed one-dimensionally or two-dimensionally on the horizontal plane, and this application does not make specific limitations.
[0100] Thus, the main steps of the semiconductor structure preparation method according to an embodiment of the present invention have been completed. It is understood that the preparation method of this embodiment includes not only the above steps, but may also include other necessary steps, all of which are included within the scope of the semiconductor structure preparation method of this embodiment.
[0101] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: An initial semiconductor structure is formed, the initial semiconductor structure comprising: a substrate and a stacked layer located above the substrate, and a bottom electrode layer located between the stacked layer and the substrate, wherein a via is formed in the stacked layer, the bottom of the via exposing the top of the bottom electrode layer; A protective layer is formed on the surface of the initial semiconductor structure, the protective layer at least covering the bottom and sidewalls of the via, and the material of the protective layer is an insulating material; A protective layer is formed on the surface of the layer to be protected. The protective layer conformally covers the surface of the layer to be protected. The protective layer contains pinhole defects extending along the thickness direction of the protective layer. The material of the protective layer is amorphous silicon. A metal layer is formed on the surface of the protective layer, followed by heat treatment to cause the amorphous silicon in the protective layer to chemically react with the metal in the metal layer to form a metal silicide, at least transforming the surface layer of the protective layer into a metal silicide layer; wherein the metal silicide layer physically seals the pinhole defects of the protective layer, so that there are no pinhole defects penetrating the metal silicide layer along the thickness direction of the metal silicide layer.
2. The preparation method according to claim 1, characterized in that, The metal layer is made of at least one of Co, Ni, Ti, W and Pt, and the method for forming the metal layer includes physical vapor deposition.
3. The preparation method according to claim 1, characterized in that, The heat treatment includes rapid thermal annealing.
4. The preparation method according to claim 1, characterized in that, A portion of the metal layer undergoes a chemical reaction with the protective layer, and after the heat treatment, a residual metal layer remains on the metal silicide layer.
5. The preparation method according to claim 4, characterized in that, The preparation method further includes: The remaining metal layer is removed by wet etching.
6. The preparation method according to claim 1, characterized in that, Part of the protective layer undergoes a chemical reaction with the metal layer, and after the heat treatment, there is still a residual protective layer between the layer to be protected and the metal silicide layer.
7. The preparation method according to claim 1, characterized in that, The stacked layer comprises multiple alternating layers of first material and multiple layers of second material.
8. The preparation method according to claim 7, characterized in that, The preparation method further includes: A dry etching process is used to remove at least the metal silicide layer at the bottom of the via, so as to expose the layer to be protected at the bottom of the via. A wet etching process is used to remove the protective layer located at the bottom of the via and exposed thereout, so as to expose the bottom electrode layer.
9. The preparation method according to claim 8, characterized in that, Part of the metal layer reacts chemically with the protective layer, and after the heat treatment, there is still a residual metal layer on the metal silicide layer; Before the step of removing the metal silicide layer located at the bottom of the via, the method further includes: removing the remaining metal layer by wet etching.
10. The preparation method according to claim 8, characterized in that, Part of the protective layer reacts chemically with the metal layer, and after the heat treatment, there is still a residual protective layer between the layer to be protected and the metal silicide layer; After removing the metal silicide layer at the bottom of the via using a dry etching process, the process further includes using a dry etching process to remove the remaining protective layer at the bottom of the via, thereby exposing the layer to be protected at the bottom of the via.