A semiconductor structure and a method of fabrication and corresponding chip, product

Abstract

The application discloses a semiconductor structure, a preparation method and a corresponding chip and product. The structure comprises a silicon-based integrated circuit and a bump structure arranged on the silicon-based integrated circuit. The bump structure comprises, in sequence, a UBM layer, a copper conductor layer, a nickel conductor layer and a gold conductor layer. A metal protective layer composed of palladium, palladium alloy, platinum or platinum alloy is coated on exposed sidewalls of the UBM layer, the copper conductor layer and the nickel conductor layer, and the protective layer does not cover the gold conductor layer. The preparation method forms stepped sidewalls through specific etching steps, and realizes selective self-growth of the protective layer on the titanium / copper / nickel sidewalls by using chemical plating based on the metal equilibrium potential difference, and the gold surface is not deposited. The application effectively solves the problems of poor welding and short circuit caused by oxidation of the copper-nickel-gold bump sidewall and oxides generated by copper diffusion, significantly improves long-term reliability, and is particularly suitable for high-end display fields such as liquid crystal drive chips.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and relates to a semiconductor structure, its fabrication method, and corresponding chips and products. More particularly, it relates to a low-cost semiconductor structure that effectively prevents copper and nickel oxidation and improves reliability, along with its selective sidewall protection method. This structure is especially suitable for cost-sensitive and high-reliability applications such as liquid crystal driver chips. Background Technology

[0002] In the semiconductor manufacturing field, bumping technology is one of the key technologies for achieving electrical interconnection between chips and external circuits. Especially in liquid crystal driver chips, flip-chip packaging with bumps enables reliable connection between the liquid crystal driver chip and flexible circuits, thereby achieving precise control of the screen display. Gold, due to its excellent physical properties, such as high oxidation resistance, good electrical and thermal conductivity, and strong resistance to electromigration, has long been widely used in bump manufacturing to form gold bump structures.

[0003] However, with the rising global gold price, the manufacturing cost of gold bumps has been increasing, severely restricting cost control of LCD driver chips and related terminal products. To address this issue, the industry has begun developing alternatives to gold bumps, among which the copper-nickel-gold (CNiG) stacked structure has become a research hotspot due to its cost advantages. The CNiG structure, by partially replacing gold with copper and nickel, can significantly reduce chip costs. For example, compared to a 9μm high gold bump, the copper height in the CNiG structure is 8μm, the nickel height is 0.25μm, and the gold height is only 1μm, resulting in a significant cost reduction.

[0004] Currently, mass production of liquid crystal driver chips using copper-nickel-gold bumps as a substitute for gold has been achieved. However, these products can only be used in the refurbishment and white-label markets, i.e., scenarios with low performance requirements, and cannot meet the high reliability demands of brand customers. Research has found that the core problem lies in the relatively reactive chemical properties of copper and nickel, which make them prone to oxidation. During long-term storage, oxides formed on the surfaces of copper and nickel may flow onto the gold surface before packaging, leading to poor subsequent soldering; or they may flow between circuits after packaging, causing short circuits and severely affecting the reliability and lifespan of the product.

[0005] Patent documents CN117594462A and CN120613316A primarily focus on the bump forming process itself, such as reducing electroplating penetration problems by improving the photoresist structure (CN117594462A), or improving the bump shape and electrical properties by improving the etching process of the bottom ball metal layer (UBM) (CN120613316A). However, these patent documents do not address or resolve the long-term reliability issues caused by the oxidation of the copper and nickel sidewalls in copper-nickel-gold bumps. From their structural descriptions, the copper and nickel sides are directly exposed without any protective measures, suggesting that reliability risks due to oxidation still exist.

[0006] Patent document CN101515573B discloses a conductive structure in which a layer of electroless gold plating (covering the conductor layer) is coated on the entire surface (including the top and all sides) of a basic bump structure (containing copper, nickel, and gold) to isolate it from air and prevent oxidation. While this solution addresses the surface oxidation problem to some extent, it has significant drawbacks: 1) Electroless gold plating on the gold bump surface wastes gold, contradicting the initial goal of cost reduction; 2) The electroplated gold surface may be contaminated, and stabilizers in the electroless gold plating solution may adsorb onto the gold surface, resulting in poor adhesion between the electroless gold plating layer and the underlying electroplated gold layer, posing a risk of peeling; 3) Gold has limited ability to block copper diffusion, and after long-term storage, copper may still diffuse to the outermost gold surface and be oxidized, failing to fundamentally solve the problem.

[0007] Therefore, there is an urgent need in this field for a new technical solution that can effectively solve the problem of copper-nickel sidewall oxidation while adopting a low-cost copper-nickel-gold bump structure, and avoid the problems of gold waste, poor adhesion and copper diffusion caused by existing protection technologies (such as full gold coating). It can balance cost control, structural stability and anti-oxidation effect, thereby meeting the market demand of brand customers for high performance and high reliability of products. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a semiconductor structure and its fabrication method. This structure can effectively prevent the oxidation of the copper and nickel sidewalls in copper-nickel-gold bumps, significantly improve the long-term reliability of the product, maintain a low-cost advantage, and has an ingenious and easy-to-implement fabrication process. The purpose of this invention is achieved through the following specific technical solutions.

[0009] A primary aspect of the present invention is to provide a semiconductor structure comprising:

[0010] A silicon-based integrated circuit having electrodes and a passivation layer disposed on its surface, the passivation layer having openings to expose the electrodes;

[0011] A bump structure is electrically connected to the electrode through the opening; the bump structure includes:

[0012] A UBM (Under Bump Metal) layer is disposed on the passivation layer and extends into the opening to connect with the electrode; the UBM layer includes an adhesion layer and a seed layer, wherein the adhesion layer is made of titanium or a titanium alloy, and the seed layer is made of copper.

[0013] The first conductor layer is disposed on the UBM layer and is made of copper.

[0014] The second conductor layer is disposed on the first conductor layer and is made of nickel.

[0015] The third conductor layer is disposed on the second conductor layer and is made of gold.

[0016] A metal protective layer covers the exposed sidewalls of the UBM layer, the first conductor layer, and the second conductor layer. The material of the metal protective layer is selected from one or more of palladium, palladium alloys, platinum, and platinum alloys. The metal protective layer does not cover the upper surface and sidewalls of the third conductor layer.

[0017] The semiconductor structure provided by this invention, by setting a noble metal protective layer (one or more of palladium, palladium alloy, platinum, and platinum alloy) on the sidewalls of easily oxidized copper, nickel, and UBM layers, effectively prevents the oxidation of copper and nickel and the diffusion of copper to the outer surface of the sidewalls. This solves the problems of poor soldering and short circuits caused by oxidation in the prior art, while avoiding the gold waste and adhesion problems between the electroplated gold layer and the electroless gold plating layer caused by full gold coating as in CN101515573B. Furthermore, since palladium or platinum is cheaper than gold, it also has a certain advantage in manufacturing cost compared to gold coating.

[0018] Preferably, the thickness of the metal protective layer is 10~1000nm. A suitable metal protective layer thickness strikes a balance between ensuring protective effect and controlling cost and size. If it is too thin (<10nm), it may not be possible to form a continuous and dense protective layer, resulting in poor effect; if it is too thick (>1000nm), the cost will increase.

[0019] Preferably, the sidewalls of the UBM layer, the first conductor layer, and the second conductor layer are aligned. By controlling the etching process, the sidewalls of the UBM layer, the first conductor layer, and the second conductor layer are aligned, thereby ensuring a consistent thickness of the metal protective layer formed by electroless plating.

[0020] Preferably, the material of the metal protective layer is selected from one or more of pure palladium, palladium-phosphorus alloy, palladium-nickel alloy, palladium-nickel-phosphorus alloy, palladium-cobalt alloy, palladium-cobalt-phosphorus alloy, pure platinum, and platinum-palladium alloy. These materials have good oxidation resistance and barrier properties and are easy to prepare by chemical plating.

[0021] Preferably, the width of the third conductor layer is greater than the widths of the UBM layer, the first conductor layer, and the second conductor layer.

[0022] Another aspect of the present invention is to provide a method for preparing the above-described semiconductor structure, comprising the following steps:

[0023] S1 provides a semiconductor substrate, the surface of which is provided with electrodes and a passivation layer, the passivation layer having openings to expose the electrodes;

[0024] S2 forms a UBM layer, which covers the passivation layer and extends into the opening to connect with the electrode; the UBM layer includes an adhesion layer and a seed layer, wherein the adhesion layer is made of titanium or a titanium alloy, and the seed layer is made of copper;

[0025] S3 forms a first conductor layer, a second conductor layer and a third conductor layer sequentially on the UBM layer by electroplating;

[0026] S4 performs the first etching step, etching the seed layer using a first etching solution;

[0027] S5 performs a second etching step, using a second etching solution to etch the adhesion layer so that the lateral dimension of the adhesion layer is smaller than that of the seed layer, forming a lateral groove that defines the width of the subsequent chemical plating.

[0028] S6 performs a third etching step, using a third etching solution to etch the seed layer, the first conductor layer, and the second conductor layer;

[0029] S7 Perform an acid activation step, using an acidic solution to remove the oxide layer on the sidewalls of the UBM layer, the first conductor layer, and the second conductor layer;

[0030] S8 performs chemical plating on the exposed sidewalls of the UBM layer, the first conductor layer, and the second conductor layer to form a metal protective layer.

[0031] The preparation method provided by this invention is ingenious. It forms a stepped structure through specific etching steps and utilizes the self-selectivity of electroless plating, taking advantage of the electrochemical potential differences of different metals to achieve selective deposition only on the sidewalls of specific metals (titanium, copper, and nickel), avoiding deposition on the gold surface. This is key to achieving localized coating. Simultaneously, a protective layer is formed only on the sidewalls requiring protection, solving the oxidation problem without significantly increasing the line width. First, gold has a higher equilibrium potential than palladium or platinum, so palladium or platinum ions will not precipitate on the gold surface. Furthermore, gold itself cannot catalyze the electroless plating of palladium or platinum, so electroless plating will not occur on the gold surface. In contrast, the equilibrium potential of titanium, copper, and nickel is lower than that of palladium, so a displacement reaction occurs first, and then palladium or platinum atoms form a metal protective layer through autocatalysis. Second, if the width of the titanium, copper, and nickel layer is not reduced through etching and the metal protective layer is directly electroless plated on the sidewalls of the titanium, copper, and nickel layer, the circuit width will increase, meaning the distance between lines will decrease, potentially leading to reliability issues. This invention uses etching to make the width of the titanium, copper, and nickel layer smaller than the width of the gold plating layer, and then electroless plating forms a protective layer at the etched locations, avoiding a significant increase in line width.

[0032] Preferably, the etching solution used in the first etching step and the third etching step is an acidic etching solution.

[0033] Preferably, the etching solution used in the second etching step is an alkaline etching solution.

[0034] Another aspect of the present invention is to provide a liquid crystal driver chip comprising the above-described semiconductor structure.

[0035] Another aspect of the present invention is to provide an electronic device, including a display screen driven by the aforementioned liquid crystal driver chip. The electronic device may be a smartphone, television, laptop computer, automotive display, tablet computer, wearable device, industrial equipment, or medical device.

[0036] Compared with the prior art, the present invention has the following beneficial technical effects.

[0037] (1) Highly targeted, effectively solving oxidation and diffusion problems: This invention creatively applies a protective layer of noble metals (palladium, platinum, and their alloys) only to the easily oxidized copper, nickel, and UBM layers (titanium / copper). Palladium and platinum are excellent antioxidants, and they also have a strong ability to block copper diffusion. This fundamentally eliminates the generation of sidewall oxides and the possibility of copper diffusing to the outer surface of the sidewall and being oxidized, thereby solving the risk of poor welding and short circuits after long-term placement.

[0038] (2) Significant cost advantage: Compared with the scheme in CN101515573B that fully covers a 1μm thick electroless gold plating layer, the present invention only deposits a protective layer with a thickness of nanometers (10nm-1000nm) in a local area of ​​the sidewall, which greatly reduces the amount of precious metal used and has an extremely obvious cost advantage. It achieves the goal of minimizing costs while ensuring reliability.

[0039] (3) Excellent adhesion and reliability: It avoids the adhesion problems that may arise from chemical gold plating on electroplated gold surfaces. The metal protective layer bonds directly to the clean surfaces of titanium, copper, and nickel, resulting in a strong bond. At the same time, the protective layer does not cover the gold layer, thus maintaining the original excellent welding performance of the gold layer.

[0040] (4) Ingenious process and structural design: Selective electroless plating: It fully utilizes the difference in equilibrium potential between gold and palladium / platinum (gold has a higher equilibrium potential) and the characteristic that gold cannot catalyze the electroless plating of palladium / platinum, so that the protective layer is selectively deposited only on the titanium, copper, and nickel sidewalls, while no deposition occurs on the gold surface. This is a self-selective and highly precise process. Controlling line width: By first etching the adhesion layer in the UBM layer to form a lateral groove, and then etching the copper-nickel layer to align with it, the sidewall area that needs to be protected is precisely defined. The protective layer formed by subsequent electroless plating fills this area without significantly increasing the overall lateral dimension of the bump (i.e., line width), thus avoiding the problem of reduced line spacing that may be caused by the introduction of the protective layer.

[0041] (5) Improved product quality and application scope: The long-term reliability of the copper-nickel-gold bump liquid crystal driver chip using the technology of this invention has been fundamentally improved, enabling this low-cost solution to meet the stringent requirements of brand customers for product quality and greatly expanding its application areas.

[0042] (6) Good process compatibility: The etching, cleaning, chemical plating and other processes involved are all mature processes in the semiconductor manufacturing field, which are easy to integrate into existing production lines and convenient to implement. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the semiconductor structure provided by the present invention.

[0044] Figure 2 This is a flowchart of the semiconductor structure fabrication method provided by the present invention.

[0045] Figure 3 This is a schematic diagram of the thickness of the semiconductor structure protective layer provided by the present invention, wherein a is a transverse groove formed after etching the adhesive layer, with a width of W; b is the protective layer space formed after simultaneously etching the copper seed layer / copper layer / nickel layer and aligning it with the side edge of the adhesive layer.

[0046] Reference numerals: 101-Silicon-based integrated circuit; 102-Electrode; 103-Passivation layer; 104-Adhesion layer; 105-Seed layer; 106-First conductor layer; 107-Second conductor layer; 108-Third conductor layer; 109-Metallic protective layer. Detailed Implementation

[0047] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention. Example 1

[0048] Semiconductor structures, such as Figure 1 As shown, the device includes a silicon-based integrated circuit 101, on which electrodes 102 (e.g., aluminum or copper electrodes) and a passivation layer 103 (e.g., silicon dioxide or silicon nitride) are formed on the surface. Openings are formed in the passivation layer 103 to expose the electrodes 102.

[0049] A bump structure is formed within the passivation layer 103 and the opening for flip-chip soldering to an external circuit. The bump structure includes:

[0050] The UBM layer consists of an adhesion layer 104 and a seed layer 105. The adhesion layer 104 is formed directly on the passivation layer 103 and the electrode 102, and is made of titanium (Ti) or a titanium alloy. Its main function is to provide good adhesion and prevent the diffusion of the underlying material. The seed layer 105 is formed on the adhesion layer 104 and is made of copper (Cu), providing conductive seeds for subsequent electroplating processes.

[0051] First conductor layer 106: formed on seed layer 105 by electroplating, the material is copper (Cu), and constitutes the main height of the bump, for example, about 8 μm.

[0052] The second conductor layer 107 is formed on the first conductor layer 106 by electroplating. The material is nickel (Ni) and it serves as a diffusion barrier layer, for example, about 0.25 μm.

[0053] The third conductor layer 108 is formed on the second conductor layer 107 by electroplating. The material is gold (Au), providing a solderable surface, for example, about 1 μm.

[0054] Metal protective layer 109: Covers the exposed sidewalls of the UBM layers (104 and 105), the first conductor layer 106, and the second conductor layer 107. The metal protective layer 109 is made of palladium (Pd), formed by chemical plating, and has a thickness of approximately 100 nm. Importantly, this metal protective layer 109 does not cover the upper surface and sidewalls of the third conductor layer 108. Example 2

[0055] The fabrication method and process of semiconductor structures are as follows: Figure 2 As shown. The key to this method lies in the specific sequence of etching steps, which is crucial for the accurate formation of the protective area.

[0056] Step S201: Provide a substrate and form a UBM layer and bump metal.

[0057] A silicon wafer is provided as a semiconductor substrate, on which electrodes (such as Al) and a passivation layer (such as SiN) have been fabricated. The passivation layer has openings to expose the electrodes. A titanium layer (adhesion layer, about 0.1-0.5 μm) and a copper layer (seed layer, about 0.3-1 μm) are deposited sequentially by sputtering or other methods to form a UBM layer.

[0058] Subsequently, using standard processes such as photolithography, electroplating, and resist removal, a first conductor layer of copper (approximately 8 μm), a second conductor layer of nickel (approximately 0.25 μm), and a third conductor layer of gold (approximately 1 μm) are sequentially electroplated on the UBM layer. At this point, the gold layer serves as the outermost layer, and its lateral dimensions define the top dimensions of the bump.

[0059] Step S202: First etching step (etching copper seed layer)

[0060] The first etching solution is used, which is an acidic etching solution, preferably a mixed aqueous solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), such as a mixture of 10 g / L H2SO4 and 30 ml / L H2O2, at a temperature of 30°C for 10 seconds. The purpose of this step is to etch away the copper seed layer that is not covered by the overlying conductor layer.

[0061] Step S203: Second etching step (etching the titanium adhesion layer to form a transverse groove)

[0062] A second etchant is used, which is an alkaline etchant, preferably a mixed aqueous solution of potassium hydroxide (KOH) and hydrogen peroxide (H2O2), such as a mixture of 10 g / L KOH and 50 ml / L H2O2, at a temperature of 35°C for 150 s. The purpose of this step is to selectively etch the exposed adhesion layer (titanium). Because the alkaline etchant is isotropic in its etching of titanium, it laterally etches the titanium layer beneath the copper seed layer and the copper / nickel / gold layer, thus forming a lateral undercut, such as... Figure 3 As shown in Figure a, the width W of this groove precisely defines the lateral extension width of the subsequent electroless metallization protective layer. During this step, the overlying copper / nickel / gold layer is relatively stable under alkaline conditions.

[0063] Step S204: Third etching step (etching the entire copper / nickel layer)

[0064] A third etching solution is used, which is an acidic etching solution, preferably a mixed aqueous solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), such as a mixture of 10 g / L H2SO4 and 30 ml / L H2O2, at a temperature of 30°C for 100 seconds. The purpose of this step is to simultaneously etch the copper seed layer, the first conductor layer (copper), and the second conductor layer (nickel), so that their sidewalls are substantially aligned with the sidewalls of the underlying adhesion layer (titanium) with which transverse grooves have already formed. Figure 3 As shown in b. After this three-step etching process, the sidewall areas of titanium, copper, and nickel that need to be protected are precisely exposed and defined.

[0065] Step S205: Remove oxide layer

[0066] In the acid etching step S204, hydrogen peroxide may form a thin oxide layer on the newly exposed sidewalls of titanium, copper, and nickel. A brief immersion in a mild acidic solution, such as 20 g / L H2SO4, using dilute sulfuric acid, removes this natural oxide film, exposing a clean metal surface in preparation for subsequent electroless plating.

[0067] Step S206: Chemical plating to form a metal protective layer

[0068] The wafers treated as described above were immersed in a palladium electroless plating solution, the composition of which was: 4 g / L palladium chloride, 15 ml / L ammonia (28% concentration), 30 mg / L sodium thiosulfate, and 15 g / L sodium hypophosphite. The pH was adjusted to 5.5 with ammonia, the solution temperature was controlled at 55°C, the electroless plating time was 40 minutes, and the thickness of the palladium layer was 0.5 μm.

[0069] Since the equilibrium potential of titanium, copper, and nickel is lower than that of palladium ions / palladium, palladium ions will first undergo a displacement reaction on the clean sidewall surfaces of these metals, depositing the initial palladium atoms.

[0070] The initially deposited palladium atoms act as autocatalytic centers, prompting the electroless plating reaction to continue, thereby forming a continuous protective metal layer (palladium) in the defined sidewall region.

[0071] Meanwhile, because the equilibrium potential of gold is higher than that of palladium ions / palladium, palladium ions cannot gain electrons on the gold surface to deposit. Furthermore, gold itself cannot catalyze the electroless palladium plating reaction. Therefore, the electroless palladium plating reaction will not occur on the surface and sidewalls of the third conductor layer (gold). Example 3

[0072] Variant implementation.

[0073] Protective layer material: The material of the metal protective layer 109 is not limited to pure palladium, but can also be palladium-phosphorus alloy (Pd-P), palladium-nickel alloy (Pd-Ni), palladium-nickel-phosphorus alloy (Pd-Ni-P), palladium-cobalt alloy (Pd-Co), palladium-cobalt-phosphorus alloy (Pd-Co-P), pure platinum (Pt), or platinum-palladium alloy (Pt-Pd), etc. These materials also possess excellent oxidation resistance and diffusion blocking capabilities. The chemical plating solution formulation needs to be adjusted accordingly.

[0074] Protective layer thickness: The thickness of the metal protective layer 109 can be adjusted between 10 nm and 1000 nm. The thickness is controlled by the electroless plating time and the concentration of metal ions in the plating bath.

[0075] Etching solution: For etching of the adhesion layer and conductor layer, other combinations of etching solutions with similar selectivity can be used, but the selectivity of the acidity and alkalinity must be guaranteed.

[0076] Structural dimensions: The width difference between the third conductor layer 108 (gold) and the underlying copper-nickel layer, as well as the width W of the transverse groove, can be adjusted according to actual design requirements. Example 4

[0077] LCD driver chips and electronic devices.

[0078] The bumps fabricated using the semiconductor structure and preparation method described above are applied to the manufacture of a liquid crystal driver chip. This liquid crystal driver chip is connected to a flexible circuit board via flip-chip bonding technology and is used to drive a display screen.

[0079] Electronic devices incorporating this liquid crystal driver chip, such as smartphones, televisions, laptops, automotive displays, tablets, smartwatches and other wearable devices, as well as industrial control display devices and medical display devices, all benefit from the high reliability and low cost advantages of this invention in their display driving components.

[0080] Although embodiments of the present invention have been shown and described above, it is understood that these embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and alterations to the above embodiments within the scope of the present invention without departing from its principles and spirit. The scope of protection of the present invention is defined by the claims and their equivalents.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: S1 providing a semiconductor substrate, the substrate surface being provided with an electrode and a passivation layer, the passivation layer having an opening to expose the electrode; S2 forming a UBM layer, covering the passivation layer and extending into the opening to connect with the electrode; the UBM layer comprising an adhesion layer and a seed layer, the adhesion layer being made of titanium or titanium alloy, and the seed layer being made of copper; S3 sequentially forming a first conductor layer, a second conductor layer and a third conductor layer on the UBM layer by electroplating; S4 performing a first etching step, using a first etching solution to etch the seed layer; S5 performing a second etching step, using a second etching solution to etch the adhesion layer, so that the lateral size of the adhesion layer is smaller than that of the seed layer, forming a lateral groove to define the width of subsequent electroless plating; S6 performing a third etching step, using a third etching solution to etch the seed layer, the first conductor layer and the second conductor layer; S7 performing an acidic activation step, using an acidic solution to remove the oxide layer on the sidewalls of the UBM layer, the first conductor layer and the second conductor layer; S8 performing electroless plating on the exposed sidewalls of the UBM layer, the first conductor layer and the second conductor layer to form a metal protective layer.

2. The production method according to claim 1, characterized by, The first etching step and the third etching step use an acidic etching solution.

3. The method of claim 1, wherein, The second etching step uses an alkaline etching solution.

4. A semiconductor structure, characterized by The semiconductor structure is prepared by the method of any one of claims 1-3, comprising: a silicon-based integrated circuit, the surface of which is provided with an electrode and a passivation layer, the passivation layer having an opening to expose the electrode; a bump structure electrically connected with the electrode through the opening; the bump structure comprising: a UBM layer provided on the passivation layer and extending into the opening to connect with the electrode; the UBM layer comprising an adhesion layer and a seed layer, the adhesion layer being made of titanium or titanium alloy, and the seed layer being made of copper; a first conductor layer provided on the UBM layer and made of copper; a second conductor layer provided on the first conductor layer and made of nickel; a third conductor layer provided on the second conductor layer and made of gold; a metal protective layer covering the exposed sidewalls of the UBM layer, the first conductor layer and the second conductor layer, the metal protective layer being made of one or more of palladium, palladium alloy, platinum and platinum alloy, and the metal protective layer not covering the upper surface and sidewalls of the third conductor layer.

5. The semiconductor structure of claim 4, wherein, The thickness of the metal protective layer is 10-1000 nm.

6. The semiconductor structure of claim 4, wherein, The sidewalls of the UBM layer, the first conductor layer and the second conductor layer are aligned.

7. The semiconductor structure of claim 4, wherein, The metal protective layer is made of one or more of pure palladium, palladium-phosphorus alloy, palladium-nickel alloy, palladium-nickel-phosphorus alloy, palladium-cobalt alloy, palladium-cobalt-phosphorus alloy, pure platinum and platinum-palladium alloy.

8. The semiconductor structure of claim 4, wherein, The width of the third conductor layer is greater than the width of the UBM layer, the first conductor layer and the second conductor layer.

9. A liquid crystal driving chip, characterized by comprising: The semiconductor structure comprises the semiconductor structure of any one of claims 4-8.

10. An electronic device comprising a display screen, characterized in that The display screen is driven by the liquid crystal driving chip of claim 9.

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