Single-inductor multi-output power converter

Abstract

The invention discloses a single-inductor multi-output power converter. The single-inductor multi-output power converter comprises an upper bridge switch, a lower bridge switch, a control circuit, a plurality of output switches and a signal duty ratio distribution circuit. A node between the first end of the lower bridge switch and the second end of the upper bridge switch is connected with the first end of the inductor. The first end of each output switch is connected with the second end of the inductor. The signal duty ratio distribution circuit sets a plurality of duty ratios of a plurality of waveforms of a plurality of switching signals according to a plurality of output voltages respectively received from the second ends of the plurality of output switches, and outputs the plurality of switching signals to the control ends of the plurality of output switches respectively.

Description

Technical Field

[0001] This invention relates to power converters, and more particularly to a single-inductor multi-output power converter. Background Technology

[0002] Power converters are indispensable for various electronic devices, used to regulate power and supply the regulated power to the devices. However, a power converter only has a single output / single channel, connecting to a single load, and supplying current from that single load through a single output. To supply power of different quantities to multiple loads, multiple power converters need to be configured to connect to each load. However, the number of power converters needs to increase with the number of loads, which in turn requires an increase in the number of circuit components. This large number of circuit components not only occupies space but also significantly increases costs. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a single-inductor multi-output power converter. The single-inductor multi-output power converter of this invention includes an upper bridge switch, a lower bridge switch, a control circuit, multiple output switches, and a signal duty cycle distribution circuit. A first terminal of the upper bridge switch is coupled to an input voltage. A first terminal of the lower bridge switch is connected to a second terminal of the upper bridge switch. The second terminal of the lower bridge switch is grounded. A node between the first terminal of the lower bridge switch and the second terminal of the upper bridge switch is connected to the first terminal of an inductor. The control circuit is connected to the control terminals of both the upper and lower bridge switches. The control circuit is configured to control the lower bridge switch. A first terminal of each output switch is connected to the second terminal of the inductor. The signal duty cycle distribution circuit is connected to the second terminal of each output switch and the control terminal. The signal duty cycle distribution circuit is configured to set multiple duty cycles of multiple waveforms of multiple switching signals based on multiple output voltages received from the second terminals of the multiple output switches, and output multiple switching signals to the control terminals of the multiple output switches respectively.

[0004] As described above, the present invention provides a single-inductor multi-output power converter. The single-inductor multi-output power converter of the present invention has multiple output terminals connected to multiple loads respectively, and these multiple output terminals share a single inductor and other circuit components. By appropriately distributing the duty cycle of the signals to the multiple switching components of the output switch through a signal duty cycle distribution circuit, the single-inductor multi-output power converter of the present invention effectively achieves the function of supplying power of different quantities to multiple loads without significantly increasing the number of circuit components.

[0005] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0006] Figure 1 This is a circuit diagram of a single-inductor multi-output power converter according to the first embodiment of the present invention.

[0007] Figure 2 This is a circuit diagram of the signal duty cycle distribution circuit of the single-inductor multi-output power converter according to the second embodiment of the present invention.

[0008] Figure 3 The waveform diagram is shown for the signal of the single-inductor multi-output power converter according to the second embodiment of the present invention.

[0009] Figure 4 This is a circuit diagram of a single-inductor multi-output power converter according to a third embodiment of the present invention.

[0010] Figure 5 This is a circuit diagram of the signal duty cycle distribution circuit of the single-inductor multi-output power converter according to the fourth embodiment of the present invention.

[0011] Figure 6 The waveform diagram is shown for the single-inductor multi-output power converter according to the fourth embodiment of the present invention.

[0012] Figure 7 The waveform diagrams are for the single-inductor multi-output power converters according to the third and fourth embodiments of the present invention.

[0013] Figure 8 The waveform diagrams are for the single-inductor multi-output power converters according to the third and fourth embodiments of the present invention. Detailed Implementation

[0014] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" as used herein may, depending on the actual situation, include any combination of any one or more of the associated listed items.

[0015] Please see Figure 1 This is a circuit diagram of a single-inductor multi-output power converter according to the first embodiment of the present invention.

[0016] The single-inductor multi-output power converter of the present invention includes, as follows Figure 1The diagram shows the upper bridge switch HS, the lower bridge switch LS, the control circuit CTR, and the signal duty cycle distribution circuit DUB1, and in particular, it also includes multiple output switches, such as, but not limited to, those shown. Figure 1 The first output switch SW1 and the second output switch SW2 are shown.

[0017] The first terminal of the upper bridge switch HS is coupled to an input voltage VIN. The first terminal of the lower bridge switch LS is connected to the second terminal of the upper bridge switch HS. The second terminal of the lower bridge switch LS is grounded. The node between the first terminal of the lower bridge switch LS and the second terminal of the upper bridge switch HS is connected to the first terminal of the inductor L.

[0018] The control circuit CTR is connected to the control terminal of the upper bridge switch HS and the control terminal of the lower bridge switch LS, and is configured to control the lower bridge switch LS.

[0019] If needed, the single-inductor multi-output power converter of the present invention may further include an upper bridge buffer BUH, a lower bridge buffer BUL, or a combination thereof.

[0020] The input terminals of the upper bridge buffer BUH and the lower bridge buffer BUL are connected to the output terminal of the control circuit CTR. The output terminal of the upper bridge buffer BUH is connected to the control terminal of the upper bridge switch HS. The output terminal of the lower bridge buffer BUL is connected to the control terminal of the lower bridge switch LS.

[0021] The first terminal of the first output switch SW1 and the first terminal of the second output switch SW2 are connected to the second terminal of the inductor L. The second terminal of the first output switch SW1 is connected to the first terminal of the output capacitor Cou1. The second terminal of the second output switch SW2 is connected to the first terminal of the output capacitor Cou2. The second terminals of the output capacitors Cou1 and Cou2 are grounded.

[0022] The second terminal of the first output switch SW1 or the first terminal of the output capacitor Cou1 serves as the first output terminal of the single-inductor multi-output power converter of the present invention, and is connected to the first load to supply the output voltage Vout1 to the first load. The second terminal of the second output switch SW2 or the first terminal of the output capacitor Cou2 serves as the second output terminal of the single-inductor multi-output power converter of the present invention, and is connected to the second load to supply the output voltage Vout2 to the second load.

[0023] It should be understood that, such as Figure 1 The first output switch SW and the second output switch SW2 shown are merely examples. In practice, the number of output switches can be increased according to actual needs such as the number of loads. The first terminals of multiple output switches are connected to the first terminal of a single inductor L, and the second terminals of multiple output switches are respectively connected to multiple loads as multiple output terminals of the single-inductor multi-output power converter of the present invention, so as to supply power of different quantities to multiple loads respectively.

[0024] The signal duty cycle distribution circuit DUB1 can be connected to the second terminal and control terminal of the first output switch SW1, and can also be connected to the second terminal and control terminal of the second output switch SW2.

[0025] It is worth noting that the signal duty cycle distribution circuit DUB1 sets multiple duty cycles of multiple waveforms of multiple switching signals DUTY1 and DUTY2 based on multiple output voltages received from the second terminal of the first output switch SW1 and the second terminal of the second output switch SW2, and outputs multiple switching signals DUTY1 and DUTY2 to the control terminals of the first output switch SW1 and the second output switch SW2, respectively.

[0026] If necessary, the single-inductor multi-output power converter of the present invention may further include a feedback circuit disposed between the second terminals of the multiple output switches and the signal duty cycle distribution circuit DUB1. This feedback circuit may include multiple voltage divider circuits (e.g., but not limited to...). Figure 1 The first voltage divider circuit DV1 and the second voltage divider circuit DV2 shown, the error amplifier circuit FEEB1, or a combination thereof.

[0027] The error amplifier circuit FEEB1 may include multiple error amplifiers, such as, but not limited to, those listed below. Figure 1 The first error amplifier ERR1 and the second error amplifier ERR2 are shown.

[0028] The first voltage divider circuit DV1 includes a first voltage divider resistor R11 and a second voltage divider resistor R12. The first terminal of the first voltage divider resistor R11 serves as the input terminal of the first voltage divider circuit DV1 and is connected to the node between the second terminal of the first output switch SW1 and the first terminal of the output capacitor Cou1 (i.e., the first output terminal of the single-inductor multi-output power converter of the present invention). The second terminal of the first voltage divider resistor R11 is connected to the first terminal of the second voltage divider resistor R12. The second terminal of the second voltage divider resistor R12 is grounded. A feedback node FB1 between the second terminal of the first voltage divider resistor R11 and the first terminal of the second voltage divider resistor R12 serves as the output terminal of the first voltage divider circuit DV1.

[0029] The first input terminal of the first error amplifier ERR1, for example, the inverting input terminal, is connected to a feedback node FB1. The second input terminal of the first error amplifier ERR1, for example, the non-inverting input terminal, is coupled to a reference voltage VREF1. The output terminal of the first error amplifier ERR1 is connected to the input terminal of the signal duty cycle distribution circuit DUB1.

[0030] The second voltage divider circuit DV2 includes a first voltage divider resistor R21 and a second voltage divider resistor R22. The first terminal of the first voltage divider resistor R21 serves as the input terminal of the second voltage divider circuit DV2, connected to the node between the second terminal of the second output switch SW2 and the first terminal of the output capacitor Cou2 (i.e., the second output terminal of the single-inductor multi-output power converter of the present invention). The second terminal of the first voltage divider resistor R21 is connected to the first terminal of the second voltage divider resistor R22. The second terminal of the second voltage divider resistor R22 is grounded. A feedback node FB2 between the second terminal of the first voltage divider resistor R21 and the first terminal of the second voltage divider resistor R22 serves as the output terminal of the second voltage divider circuit DV2.

[0031] The first input terminal of the second error amplifier ERR2, for example, the inverting input terminal, is connected to a feedback node FB2. The second input terminal of the second error amplifier ERR2, for example, the non-inverting input terminal, is coupled to a reference voltage VREF2. The output terminal of the second error amplifier ERR2 is connected to the input terminal of the signal duty cycle distribution circuit DUB1.

[0032] If needed, the single-inductor multi-output power converter of the present invention may further include multiple feedback resistors, for example... Figure 1 The first feedback resistor R1 and the second feedback resistor R2 shown, and multiple feedback capacitors (e.g., but not limited to) Figure 1 The first feedback capacitor C1 and the second feedback capacitor C2 are shown.

[0033] The first terminal of the first feedback resistor R1 is connected to the output terminal of the first error amplifier ERR1 and the output terminal of the signal duty cycle distribution circuit DUB1. The second terminal of the first feedback resistor R1 is connected to the first terminal of the first feedback capacitor C1. The second terminal of the first feedback capacitor C1 is grounded.

[0034] The first terminal of the second feedback resistor R2 is connected to the output terminal of the second error amplifier ERR2 and the output terminal of the signal duty cycle distribution circuit DUB1. The second terminal of the second feedback resistor R2 is connected to the first terminal of the second feedback capacitor C2. The second terminal of the second feedback capacitor C2 is grounded.

[0035] The first error amplifier ERR1 multiplies the difference between an output voltage Vout1 or its voltage divider (i.e., the voltage of a feedback node FB1) at the first output terminal of the single-inductor multi-output power converter of the present invention and the reference voltage VREF1 by a first gain to output an error amplification signal EAO1.

[0036] The second error amplifier ERR2 multiplies the difference between an output voltage Vout2 or its voltage divider (i.e., the voltage of a feedback node FB2) at the second output terminal of the single-inductor multi-output power converter of the present invention and the reference voltage VREF2 by a second gain to output an error amplification signal EAO2.

[0037] It is worth noting that the signal duty cycle allocation circuit DUB1 sets the duty cycle of the waveforms of multiple switching signals DUTY1 and DUTY2, which are respectively output to the control terminals of the first output switch SW1 and the second output switch SW2, based on multiple error amplification signals EAO1 and EAO2.

[0038] For example, the signal duty cycle allocation circuit DUB1 can calculate the ratio of the voltage of the error amplification signal EAO1 to the total voltage of the sum of the voltages of the error amplification signal EAO1 and the error amplification signal EAO2, so as to set the duty cycle of the waveform of a switching signal DUTY1.

[0039] The sum of the duty cycles of the waveforms of switching signal DUTY1 and switching signal DUTY2 can be 100%. The signal duty cycle allocation circuit DUB1 can subtract one duty cycle of a waveform of switching signal DUTY1 from 100% to obtain a ratio, which serves as the duty cycle of a waveform of switching signal DUTY2. Alternatively, the signal duty cycle allocation circuit DUB1 can calculate the ratio of the voltage of error amplification signal EAO2 to the total voltage of the sum of the voltages of error amplification signals EAO1 and EAO2, to set the duty cycle of the waveform of switching signal DUTY2.

[0040] It is worth noting that the duty cycle of the switching signal DUTY1 is different from that of the switching signal DUTY2, and the high-level time of switching signal DUTY1 does not overlap with the high-level time of switching signal DUTY2, so that the first output switch SW1 and the second output switch SW2 are turned on in different time intervals. Furthermore, the conduction time of the upper bridge switch HS and the lower bridge switch LS can be controlled to have different durations in different time intervals, so that the amount of current flowing to the inductor L is different in different time intervals. Thus, in different time intervals, power of different quantities is supplied to multiple loads through the turned-on first output switch SW1 and second output switch SW2 in turn. Therefore, a single single-inductor multi-output power converter of the present invention can supply power of different quantities to multiple loads.

[0041] If necessary, the single-inductor multi-output power converter of the present invention may further include one or more of the following: multiple buffers (e.g., but not limited to) Figure 1 The circuit includes a first buffer BU1 and a second buffer BU2, a current sensing circuit CUS, a sensing processor AD, and a comparator CMP.

[0042] The input terminal of the first buffer BU1 is connected to the output terminal of the signal duty cycle distribution circuit DUB1. The output terminal of the first buffer BU1 is connected to the control terminal of the first output switch SW1.

[0043] The input terminal of the second buffer BU2 is connected to the output terminal of the signal duty cycle distribution circuit DUB1. The output terminal of the second buffer BU2 is connected to the control terminal of the second output switch SW2.

[0044] The current sensing circuit CUS is connected to the first terminal of the upper bridge switch HS. The current sensing circuit CUS can sense the current of the upper bridge switch HS and convert the sensed current of the upper bridge switch HS into a voltage, and output a sensing signal ISEN based on this voltage.

[0045] The sensor processor AD is connected to the current sensing circuit CUS. The sensor processor AD can output a sensing processing signal based on the voltage of a sensing signal ISEN received from the current sensing circuit CUS and the voltage of a ramp signal SL received from an external ramp generator (not shown). For example, the sensor processor AD may include an adder or other circuit components with the function of adding voltages, configured to add the voltage of the sensing signal ISEN to the voltage of the ramp signal SL to obtain a total voltage, and output a sensing processing signal based on this total voltage.

[0046] The first input of comparator CMP, for example, the inverting input, is connected to the sensor processor AD to receive a sensing signal from the sensor processor AD. The second input of comparator CMP is connected to the signal duty cycle distribution circuit DUB1 to receive a total error voltage signal from the duty cycle distribution circuit DUB1. This total error voltage signal is the total error amplification voltage obtained by adding the voltages of error amplification signals EAO1 and EAO2. The output of comparator CMP is connected to the input of control circuit CTR. Control circuit CTR can control the upper bridge switch HS and the lower bridge switch LS based on the total error voltage signal received from duty cycle distribution circuit DUB1 and the comparison signal received from comparator CMP, thereby controlling the current flowing through inductor L to the load, including controlling the peak value of the current flowing through inductor L to the load in a peak current mode.

[0047] Please see Figure 2 and Figure 3 ,in Figure 2 This is a circuit diagram of the signal duty cycle distribution circuit of the single-inductor multi-output power converter according to the second embodiment of the present invention. Figure 3 The waveform diagram is shown for the signal of the single-inductor multi-output power converter according to the second embodiment of the present invention.

[0048] like Figure 1 The signal duty cycle distribution circuit DUB1 of the single-inductor multi-output power converter of the present invention shown may include multiple voltage-to-current conversion circuits (e.g., but not limited to) Figure 2 The first voltage-to-current conversion circuit VIC1 and the second voltage-to-current conversion circuit VIC2 shown are as follows. Figure 2 The duty cycle setting circuit DYST1 is shown.

[0049] The duty cycle setting circuit DYST1 may include a charging resistor Rdy, a charging capacitor Cdy, a first comparator CM1, a second comparator CM2, and a switching signal generation circuit LOG1. The switching signal generation circuit LOG1 may include... Figure 2 The first flip-flop DFF1 and clock circuit CLKL are shown. If needed, the duty cycle setting circuit DYST1 may further include multiple current mirror circuits (e.g., but not limited to...). Figure 2 The first current mirror circuit MR1 and the second current mirror circuit MR2 shown are as follows, and as shown in the figure. Figure 2 The reset switch SWRT is shown.

[0050] like Figure 2 The input terminal of the first voltage-to-current conversion circuit VIC1 shown is connected as follows: Figure 1 The output of the first error amplifier ERR1 shown is used to receive an error amplification signal EAO1 from the output of the first error amplifier ERR1. Figure 2 The input terminal of the second voltage-to-current conversion circuit VIC2 shown is connected as follows: Figure 1 The output of the second error amplifier ERR2 shown is used to receive an error amplification signal EAO2 from the output of the second error amplifier ERR2.

[0051] The first current mirror circuit MR1 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first terminal of the first transistor T1 is connected to the first terminals of the second transistor T2 and the third transistor T3. The second terminal and the control terminal of the first transistor T1 are connected to the output terminal of the first voltage-to-current conversion circuit VIC1, the control terminal of the second transistor T2, and the control terminal of the third transistor T3.

[0052] The second terminal of the second transistor T2 is connected to the first terminal of the charging resistor Rdy. The second terminal of the charging resistor Rdy is grounded. The second terminal of the third transistor T3 is connected to the first terminal of the charging capacitor Cdy. The second terminal of the charging capacitor Cdy is grounded.

[0053] The first voltage-to-current conversion circuit VIC1 converts an error amplification signal EAO1 into an error amplification current and outputs it to the second terminal of the first transistor T1. This error amplification current converted from the error amplification signal EAO1 is calculated by the following formula: I1 = VEAO1 / R, where I1 represents the error amplification current converted from the error amplification signal EAO1, VEAO1 represents the voltage value of the error amplification signal EAO1, and R represents the resistance value of the charging resistor Rdy.

[0054] The second current mirror circuit MR2 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The first terminal of the fourth transistor T4 is connected to the first terminals of both the fifth and sixth transistors T5. The second terminal and control terminal of the fourth transistor T4 are connected to the output terminal of the second voltage-to-current conversion circuit VIC2, the control terminal of the fourth transistor T4, and the control terminal of the sixth transistor T6. The second terminal of the fifth transistor T5 is connected to the first terminal of the charging resistor Rdy. The second terminal of the sixth transistor T6 is connected to the first terminal of the charging capacitor Cdy.

[0055] The second voltage-to-current conversion circuit VIC2 converts an error amplification signal EAO2 into an error amplification current and outputs it to the second terminal of the fourth transistor T4. This error amplification current converted from the error amplification signal EAO2 is calculated by the following formula: I2 = VEAO2 / R, where I2 represents the error amplification current converted from the error amplification signal EAO2, VEAO2 represents the voltage value of the error amplification signal EAO2, and R represents the resistance value of the charging resistor Rdy.

[0056] The first input terminal of the first comparator CM1, for example, the non-inverting input terminal, is connected to the first terminal of the charging capacitor Cdy. The second input terminal of the first comparator CM1, for example, the inverting input terminal, is connected to the output terminal of the first error amplifier ERR1, so as to receive an error amplification signal EAO1 from the output terminal of the first error amplifier ERR1.

[0057] The first input terminal of the second comparator CM2, for example, the non-inverting input terminal, is connected to the first terminal of the charging capacitor Cdy to receive a capacitor voltage RAMP at the first terminal of the charging capacitor Cdy. The second input terminal of the second comparator CM2, for example, the inverting input terminal, is connected to the first terminal of the charging resistor Rdy to receive the voltage at the first terminal of the charging resistor Rdy. The voltage at the first terminal of the charging resistor Rdy is calculated using the following formula: VEAOALL = VEAO11 + VEAO12, where VEAOALL represents the total error amplification voltage obtained by adding the voltages of the error amplification signals EAO1 and EAO2. The voltage at the first terminal of the charging resistor Rdy is equal to this total error amplification voltage VEAOALL, where VEAO1 represents the voltage value of the error amplification signal EAO1, and VEAO2 represents the voltage value of the error amplification signal EAO2.

[0058] The charging current of the charging capacitor Cdy is the sum of the error amplification current I1 converted from the error amplification signal EAO1 and the error amplification current I2 converted from the error amplification signal EAO2. The voltage received from the first terminal of the charging resistor Rdy at the second input terminal of the second comparator CM2, for example, the inverting input terminal, is calculated using the following formula:

[0059] Vdy = (I1 + I2) × Rdy,

[0060] Where Vdy represents the voltage at the first terminal of the charging resistor Rdy, I1 represents the current value of the error amplification current converted from the error amplification signal EAO1, I2 represents the current value of the error amplification current converted from the error amplification signal EAO2, and Rdy represents the resistance value of the charging resistor.

[0061] The charging time of the charging capacitor Cdy is calculated using the following formula:

[0062] T = Cdy × (I1 + I2) × Rdy / (I1 + I2) = Cdy × Rdy, where T represents the charging time of the charging capacitor Cdy, Cdy represents the capacitance value of the charging capacitor, I1 represents the current value of the error amplification current converted from the error amplification signal EAO1, I2 represents the current value of the error amplification current converted from the error amplification signal EAO2, and Rdy represents the resistance value of the charging resistor.

[0063] When the single-inductor multi-output power converter of the present invention operates in a peak current mode, a clock signal CLK with a fixed frequency is generated within a charging time T of the charging capacitor Cdy.

[0064] The first input terminal R of the first flip-flop DFF1 is connected to the output terminal of the first comparator CM1. For example... Figure 2 The output terminal Q of the first flip-flop DFF1 shown is connected as follows: Figure 1 The control terminal of the first switching component SW1 shown outputs a switching signal DUTY1 to the control terminal of the first switching component SW1. For example... Figure 2 The inverting output terminal QB of the first flip-flop DFF1 shown is connected as follows: Figure 1 The control terminal of the second switching component SW2 shown outputs a switching signal DUTY2 to the control terminal of the second switching component SW2.

[0065] The input of the clock circuit CLKL is connected to the output of the second comparator CM2. The first output of the clock circuit CLKL is connected to the second input S of the first flip-flop DFF1, so as to output a clock signal CLK to the second input of the first flip-flop DFF1. Figure 2 The first output terminal of the clock circuit CLKL shown can be connected to, for example... Figure 1 The control circuit CTR shown outputs a clock signal CLK to the control circuit CTR. The control circuit CTR can control the upper bridge switch HS and the lower bridge switch LS according to this clock signal CLK.

[0066] The control terminal of the reset switch SWRT is connected to the second output terminal of the clock circuit CLKL to receive a reset signal RESET from the second output terminal of the clock circuit CLKL. The first terminal of the reset switch SWRT is connected to the first terminal of the charging capacitor Cdy. The second terminal of the reset switch SWRT is grounded. When the second output terminal of the clock circuit CLKL outputs a (high-level) reset signal RESET to turn on the reset switch SWRT, the voltage at the first terminal of the charging capacitor Cdy discharges to ground through the turned-on reset switch SWRT, pulling the voltage at the first input terminal of the second comparator CM2, for example, the non-inverting input terminal, down to zero. Figure 3 The waveform shown in the upper half is the voltage waveform of the charging capacitor Cdy.

[0067] For example, such as Figure 3 As shown, at time point t2, the voltage value VEAO2 of the error amplification signal EAO2 is twice the voltage value VEAO1 of the error amplification signal EAO1, and the total error amplification voltage EAOALaa at the first terminal of the charging resistor Rdy at time point t2 is 1.5 times the total error amplification voltage EAOALa at the first terminal of the charging resistor Rdy at time point t1. Figure 2 The waveforms of the clock signal CLK, the switching signal DUTY1, and the switching signal DUTY2 shown are as follows: Figure 3 As shown above, the examples are merely illustrative and the invention is not limited thereto. The voltage value VEAO2 of the error amplification signal EAO2 at time point t1 can be as follows: Figure 3 The value obtained by subtracting the voltage of the error amplification signal EAO1 from the total error amplification voltage EAOALa at the first terminal of the charging resistor Rdy shown. The voltage value VEAO2 of the error amplification signal EAO2 at time point t2 can be expressed as follows: Figure 3 The value obtained by subtracting the voltage of the error amplification signal EAO1 from the total error amplification voltage EAOALaa at the first terminal of the charging resistor Rdy shown.

[0068] It is worth noting that, such as Figure 3As shown, the duty cycle of all switching signals DUTY1 output to the control terminal of the first switching component SW1 and the duty cycle of all switching signals DUTY2 output to the control terminal of the second switching component SW2 are summed to 100%, and the time intervals of switching signals DUTY1 and DUTY2 at high levels do not overlap. During the time interval of a high-level switching signal DUTY1, an output current flows sequentially through inductor L and the turned-on first switching component SW1 to a load. During the time interval of a high-level switching signal DUTY2, another output current flows sequentially through inductor L and the turned-on second switching component SW2 to another load. Therefore, in the case of a single-inductor multi-output power converter of the present invention having only a single inductor L, different powers can be supplied to multiple loads.

[0069] When the single-inductor multi-output power converter of the present invention operates in a peak current mode, the total error amplification voltage VEAOALL obtained by adding the voltages of the error amplification signal EAO1 and EAO2 is proportional to the magnitude of the current in inductor L. Therefore, within one cycle, the energy of the output voltage Vout1 of the single-inductor multi-output power converter of the present invention is proportional to the product of the total error amplification voltage VEAOALL and the duty cycle of a switching signal DUTY1, and the energy of the output voltage Vout2 of the single-inductor multi-output power converter of the present invention is proportional to the product of the total error amplification voltage VEAOALL and the duty cycle of a switching signal DUTY2.

[0070] exist Figure 3 As shown, within a time period with an upper limit at time point t1, VEAO1 = VEAO2, VEAOALL = 2 × VEAO1 = 2 × VEAO2, DTY1 = DTY2 = 50%, where VEAO1 represents the voltage of the error amplification signal EAO1, VEAO2 represents the voltage of the error amplification signal EAO2, VEAOALL represents the total error amplification voltage obtained by adding the voltages of error amplification signals EAO1 and EAO2, DTY1 represents the duty cycle of a switching signal DUTY1, and DTY2 represents the duty cycle of a switching signal DUTY2. At this time, the relationship between the voltage of the error amplification signal EAO1 and the total error amplification voltage VEAOALL is:

[0071] VEAOALL×50%=2×VEAO1×50%=VEAO1,

[0072] This makes the output voltages Vout1 and Vout2 of the single-inductor multi-output power converter of the present invention equal.

[0073] In such Figure 3 As shown, within a time period with an upper limit at time point t2, VEAO2 = 2 × VEAO1 => VEAOALL = 3 × VEAO1, DUTY1 = 33.3%. Therefore, the energy supplied to the output voltage Vout1 at time point t2 remains the same as at time point t1. At this time, the relationship between the voltage VEAO1 of the error amplification signal EAO1 and the total error amplification voltage VEAOALL is:

[0074] VEAOALL×DTY1=3×VEAO1×33.3%=VEAO1.

[0075] Because the voltage VEAO1 of the error amplification signal EAO1 remains unchanged, the output voltage Vout1 of the single-inductor multi-output power converter of the present invention remains unchanged, while the output voltage Vout2 of the single-inductor multi-output power converter of the present invention increases at time point t2. At time point t2, the relationship between the voltage VEAO1 of the error amplification signal EAO1 and the total error amplification voltage VEAOALL is as follows:

[0076] VEAOALL(t2)×Duty2(t2)=3×VEAO1×66.7%=2×VEAO1,

[0077] The energy at this point will be twice that provided to the output voltage Vout2 at time t1, and VEAO2(t2) will also be twice that of VEAO2(t1), which means that the output voltage Vout2 requires twice the energy.

[0078] Therefore, when one of the multiple loads connected to the multiple output terminals (the terminals respectively used to supply multiple output voltages Vout1 and Vout2) of the single-inductor multi-output power converter of the present invention changes, the single-inductor multi-output power converter of the present invention can provide the energy required by one of the loads in real time without affecting the output voltages Vout1 and Vout2 supplied to other loads.

[0079] The single-inductor multi-output power converter of the present invention only requires as follows Figure 2 By adding a first comparator CM1, the energy distribution function can be achieved (and the crosstalk during load changes can be reduced).

[0080] Please see Figure 4 , Figure 7 and Figure 8 ,in Figure 4 This is a circuit diagram of a single-inductor multi-output power converter according to the third embodiment of the present invention. Figure 7 and Figure 8The images show the signal waveforms of the single-inductor multi-output power converters according to the third and fourth embodiments of the present invention. The third embodiment of the present invention is similar to the first embodiment, and will not be repeated herein.

[0081] like Figure 1 The single-inductor multi-output power converter shown is similar to... Figure 4 The differences between the single-inductor multi-output power converters shown are as follows: Figure 1 The single-inductor multi-output power converter shown has two output terminals for supplying output voltages Vout1 and Vout2 respectively, and as... Figure 4 The single-inductor multi-output power converter shown has three output terminals for supplying three output voltages, Vout1, Vout2, and Vout3. For example, as... Figure 4 The output voltages Vout1, Vout2, and Vout3 shown can be the same as those shown below. Figure 7 The output voltages Vo1, Vo2, and Vo3 are shown. In practice, they can be adjusted according to actual needs, such as... Figure 4 The same or similar methods are used to increase the number of output terminals and the number of circuit components of the single-inductor multi-output power converter of the present invention, so as to supply more output voltage to more loads.

[0082] In order to enable the single-inductor multi-output power converter of the present invention as Figure 4 and Figure 8 As shown, in addition to supplying output voltages Vout1 and Vout2, output voltage Vout3 is also supplied, as follows: Figure 4 The single-inductor multi-output power converter of the present invention shown also includes a third output switch SW3, an output capacitor Cout3, a third voltage divider circuit DV3, a third error amplifier ERR3, a third feedback resistor R3, a third feedback capacitor C3, and a third buffer BU3.

[0083] The first terminal of the third output switch SW3 is connected to the second terminal of the inductor L. For example, as... Figure 4 The inductor voltage signal at the second terminal of the inductor L shown can be the same as that shown below. Figure 7 The diagram shows an inductor voltage signal LX2. For example, a voltage signal at the node between the first terminal of the lower bridge switch LS and the second terminal of the upper bridge switch HS can be the same as... Figure 7 The node voltage signal LX is shown.

[0084] The second terminal of the third output switch SW3 is connected to the first terminal of the output capacitor Cou3. The second terminal of the output capacitor Cou3 is grounded. The second terminal of the third output switch SW3 or the first terminal of the output capacitor Cou3 serves as the third output terminal of the single-inductor multi-output power converter of the present invention, and is connected to a third load to supply the output voltage Vout3 to the third load.

[0085] The third voltage divider circuit DV3 includes a first voltage divider resistor R31 and a second voltage divider resistor R32. The first terminal of the first voltage divider resistor R31 serves as the input terminal of the third voltage divider circuit DV3, connected to the node between the second terminal of the third output switch SW and the first terminal of the output capacitor Cou3. The second terminal of the first voltage divider resistor R31 is connected to the first terminal of the second voltage divider resistor R32. The second terminal of the second voltage divider resistor R32 is grounded. A feedback node FB3 between the second terminal of the first voltage divider resistor R31 and the first terminal of the second voltage divider resistor R32 serves as the output terminal of the third voltage divider circuit DV3.

[0086] The first input terminal of the third error amplifier ERR3, for example, the inverting input terminal, is connected to a feedback node FB3. The second input terminal of the third error amplifier ERR3, for example, the non-inverting input terminal, is coupled to a reference voltage VREF3. The output terminal of the third error amplifier ERR3 is connected to a signal duty cycle distribution circuit DUB1 to output an error amplified signal EAO3 to the signal duty cycle distribution circuit DUB1.

[0087] The first terminal of the third feedback resistor R3 is connected to the output terminal of the third error amplifier ERR3 and the input terminal of the signal duty cycle distribution circuit DUB1. The second terminal of the third feedback resistor R3 is connected to the first terminal of the third feedback capacitor C3. The second terminal of the third feedback capacitor C3 is grounded.

[0088] It is worth noting that the signal duty cycle allocation circuit DUB1 sets the duty cycle of multiple switching signals DUTY1, DUTY2, and DUTY3, which are respectively output to the control terminals of the first output switch SW1, the second output switch SW2, and the third output switch SW3, based on the multiple error amplification signals EAO1, EAO2, and EAO3 received from the output terminals of the first error amplifier ERR1, the second error amplifier ERR2, and the error amplification signal EAO3.

[0089] Please see Figures 5 to 8 ,in Figure 5 This is a circuit diagram of the signal duty cycle distribution circuit of the single-inductor multi-output power converter according to the fourth embodiment of the present invention. Figure 6 This is a waveform diagram of the signal of the single-inductor multi-output power converter according to the fourth embodiment of the present invention. Figure 7 and Figure 8 The waveform diagrams are for the single-inductor multi-output power converters according to the third and fourth embodiments of the present invention.

[0090] The fourth embodiment of the present invention is the same as the second embodiment, and will not be repeated herein.

[0091] like Figure 2 The single-inductor multi-output power converter shown is similar to... Figure 5The differences between the single-inductor multi-output power converters shown are as follows: Figure 5 The single-inductor multi-output power converter shown also includes a third voltage-to-current conversion circuit VIC3, such as... Figure 5 The duty cycle setting circuit DYST2 shown also includes a third current mirror circuit MR3, a third comparator CM3, and a switching signal generation circuit LOG2. For example... Figure 5 The switching signal generation circuit LOG2 shown includes a first flip-flop DFF1, a second flip-flop DFF2, a third flip-flop DFF3, and a clock circuit CLKL, which may be, for example but not limited to, an SR flip-flop.

[0092] The third current mirror circuit MR3 includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The first terminal of the seventh transistor T7 is connected to the first terminals of both the eighth and ninth transistors T8 and T9. The second terminal and control terminal of the seventh transistor T7 are connected to the output terminal of the third voltage-to-current conversion circuit VIC3, the control terminal of the eighth transistor T8, and the control terminal of the ninth transistor T9. The second terminal of the eighth transistor T8 is connected to the first terminal of the charging resistor Rdy. The second terminal of the ninth transistor T9 is connected to the first terminal of the charging capacitor Cdy.

[0093] The first input terminal of each comparator CM1 to CM3, for example, the non-inverting input terminal, is connected to the first terminal of the charging capacitor Cdy. The second input terminal of comparator CM1, for example, the inverting input terminal, is coupled to a total voltage EAO12, which is the sum of the voltage of an error amplified signal EAO1 output from the first error amplifier ERR1 and the voltage of an error amplified signal EAO2 output from the second error amplifier ERR2. The second input terminal of comparator CM2, for example, the inverting input terminal, is connected to the output terminal of the first error amplifier ERR1 to receive an error amplified signal EAO1 from the output terminal of the first error amplifier ERR1. The second input terminal of comparator CM3, for example, the inverting input terminal, is connected to the first terminal of the charging resistor Rdy.

[0094] The voltage at the first terminal of the charging resistor Rdy is the sum of the voltages of the error amplification signal EAO1 output by the first error amplifier ERR1, the error amplification signal EAO2 output by the second error amplifier ERR2, and the error amplification signal EAO3 output by the third error amplifier ERR3, resulting in a total error amplification voltage. For example, this total error amplification voltage is as follows: Figure 6 The voltage at time point t1 is the total error amplification voltage EAOALb, and at time point t2 it is the total error amplification voltage EAOALbb.

[0095] The second input terminal S of the first flip-flop DFF1 and the first input terminal R of the second flip-flop DFF2 are connected to the output terminal of the first comparator CM1. The second input terminal S of the first flip-flop DFF1 is connected to the output terminal Q of the first comparator CM1. The second input terminal S of the second flip-flop DFF2 is connected to the output terminal of the second comparator CM2. The first input terminal R of the third flip-flop DFF3 is connected to the output terminal of the second comparator CM2. The input terminal of the clock circuit CLKL is connected to the output terminal of the third comparator CM3. Figure 5 The first input terminal R of the first flip-flop DFF1 and the second input terminal S of the third flip-flop DFF3 are shown below. Figure 4 The control circuit CTR connection shown is as follows: Figure 5 The first output terminal of the clock circuit CLKL shown is used to receive a clock signal CLK from the first output terminal of the clock circuit CLKL.

[0096] like Figure 5 The output terminal Q of the third flip-flop DFF3 shown is connected as follows: Figure 4 The control terminal of the first switch assembly SW1 is shown. (As shown) Figure 5 The output terminal Q of the second flip-flop DFF2 shown is connected as follows: Figure 4 The control terminal of the second switch assembly SW2 is shown. (Example) Figure 5 The output terminal Q of the first flip-flop DFF1 shown is connected as follows: Figure 4 The control terminal of the third switch assembly SW3 shown.

[0097] The second output terminal of the clock circuit CLKL is connected to the control terminal of the reset switch SWRT to output a reset signal RESET to the control terminal of the reset switch SWRT. The first terminal of the reset switch SWRT is connected to the first terminal of the charging capacitor Cdy. The second terminal of the reset switch SWRT is grounded.

[0098] like Figure 6 As shown, the duty cycles of all switching signals DUTY1 output to the control terminal of the first switching component SW1, the duty cycles of all switching signals DUTY2 output to the control terminal of the second switching component SW2, and the duty cycles of all switching signals DUTY3 output to the control terminal of the third switching component SW3 sum to 100%, and the time intervals of switching signals DUTY1, DUTY2, and DUTY3 at high levels do not overlap. Thus, in the case of a single-inductor multi-output power converter of the present invention having only a single inductor L, it is possible to supply different powers to multiple loads.

[0099] In summary, this invention provides a single-inductor multi-output power converter. The single-inductor multi-output power converter of this invention has multiple output terminals connected to multiple loads, and these multiple output terminals share a single inductor and other circuit components. By appropriately distributing the duty cycle of the signals to the multiple switching components of the output switch through a signal duty cycle allocation circuit, the single-inductor multi-output power converter of this invention effectively achieves the function of supplying power of different quantities to multiple loads without significantly increasing the number of circuit components.

[0100] The above-disclosed content is only a preferred and feasible embodiment of the present invention and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included in the claims of the present invention.

Claims

1. A single-inductor multi-output power converter, characterized in that, Include: An upper bridge switch, wherein the first terminal of the upper bridge switch is coupled to an input voltage; A lower bridge switch, the first end of which is connected to the second end of the upper bridge switch, the second end of which is grounded, and the node between the first end of the lower bridge switch and the second end of the upper bridge switch is connected to the first end of an inductor; A control circuit is connected to the control terminal of the upper bridge switch and the control terminal of the lower bridge switch, and is configured to control the lower bridge switch and the lower bridge switch. Multiple output switches, each with its first terminal connected to the second terminal of the inductor; and A signal duty cycle distribution circuit is connected to the second terminal and the control terminal of each of the output switches. It is configured to set multiple duty cycles of multiple waveforms of multiple switching signals based on multiple output voltages received from the second terminals of the multiple output switches respectively, and output the multiple switching signals to the control terminals of the multiple output switches respectively.

2. The single-inductor multi-output power converter according to claim 1, characterized in that, The second terminals of the plurality of output switches are respectively connected to the first terminals of the plurality of output capacitors, and the second terminals of each of the output capacitors are grounded.

3. The single-inductor multi-output power converter according to claim 1, characterized in that, The single-inductor multi-output power converter also includes: Multiple error amplifiers are provided, with their first input terminals connected to the second terminals of multiple output switches, their second input terminals coupled to multiple reference voltages, and their output terminals connected to the signal duty cycle distribution circuit. The signal duty cycle allocation circuit therein sets the duty cycle of the multiple switching signals based on the multiple error amplification signals received from the output terminals of the multiple error amplifiers respectively.

4. The single-inductor multi-output power converter according to claim 3, characterized in that, The single-inductor multi-output power converter also includes: Multiple feedback resistors, the first ends of which are respectively connected to the output terminals of multiple error amplifiers and the output terminal of the signal duty cycle distribution circuit; Multiple feedback capacitors are provided, with the first terminals of each feedback capacitor connected to the second terminals of the multiple feedback resistors, and the second terminals of each feedback capacitor being grounded.

5. The single-inductor multi-output power converter according to claim 3, characterized in that, The single-inductor multi-output power converter also includes: Multiple voltage divider circuits are provided, with the input terminals of the multiple voltage divider circuits respectively connected to the second terminals of the multiple output switches, and the output terminals of the multiple voltage divider circuits respectively connected to the first input terminals of the multiple error amplifiers.

6. The single-inductor multi-output power converter according to claim 5, characterized in that, The voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor, and the first terminals of the multiple first voltage divider resistors of the multiple voltage divider circuits are respectively connected to the second terminals of the multiple output switches; In each of the voltage divider circuits, the second end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor, the second end of the second voltage divider resistor is grounded, and the first end of the second voltage divider resistor serves as a feedback node. The feedback nodes of the multiple voltage divider circuits are respectively connected to the first input terminals of the multiple error amplifiers.

7. The single-inductor multi-output power converter according to claim 5, characterized in that, The signal duty cycle allocation circuit includes: Multiple voltage-to-current conversion circuits are respectively connected to the output terminals of multiple error amplifiers and configured to convert the voltages of multiple error amplification signals into multiple error amplification currents respectively. as well as A duty cycle setting circuit is connected to multiple voltage-to-current conversion circuits and configured to set the duty cycle of multiple switching signals based on multiple error amplification currents.

8. The single-inductor multi-output power converter according to claim 7, characterized in that, The duty cycle setting circuit includes: A charging resistor, wherein the first end of the charging resistor is connected to multiple voltage-to-current conversion circuits, and the second end of the charging resistor is grounded; A charging capacitor, wherein the first terminal of the charging capacitor is connected to multiple voltage-to-current conversion circuits, and the second terminal of the charging capacitor is grounded; A first comparator, wherein the first input terminal of the first comparator is connected to the first terminal of the charging capacitor, and the second input terminal of the first comparator is connected to the output terminal of one of the plurality of error amplifiers; A second comparator, wherein the first input terminal of the second comparator is connected to the first terminal of the charging capacitor, and the second input terminal of the second comparator is connected to the first terminal of the charging resistor; as well as A switching signal generation circuit is configured to output a plurality of switching signals to the control terminals of a plurality of output switches based on a plurality of comparison signals received from the output terminal of the first comparator and the second comparator.

9. The single-inductor multi-output power converter according to claim 8, characterized in that, The switching signal generation circuit includes: A first flip-flop, wherein a first input terminal of the first flip-flop is connected to the output terminal of the first comparator, an output terminal of the first flip-flop is connected to the control terminal of one of the plurality of output switches, and an inverting output terminal of the first flip-flop is connected to the control terminal of the other of the plurality of output switches. A clock circuit, wherein the input terminal of the clock circuit is connected to the output terminal of the second comparator, and the first output terminal of the clock circuit is connected to the second input terminal of the first flip-flop; as well as A reset switch is provided, wherein the control terminal of the reset switch is connected to the second output terminal of the clock circuit, the first terminal of the reset switch is connected to the first terminal of the charging capacitor, and the second terminal of the reset switch is grounded.

10. The single-inductor multi-output power converter according to claim 8, characterized in that, The duty cycle setting circuit further includes: The first current mirror circuit includes a first transistor, a second transistor, and a third transistor. The first terminal of the first transistor is connected to the first terminal of the second transistor and the first terminal of the third transistor. The second terminal and the control terminal of the first transistor are connected to one of the multiple voltage-to-current conversion circuits, the control terminal of the second transistor, and the control terminal of the third transistor. The second terminal of the second transistor is connected to the first terminal of the charging resistor, and the second terminal of the third transistor is connected to the first terminal of the charging capacitor.

11. The single-inductor multi-output power converter according to claim 10, characterized in that, The duty cycle setting circuit further includes: The second current mirror circuit includes a fourth transistor, a fifth transistor, and a sixth transistor. The first terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the first terminal of the sixth transistor. The second terminal and the control terminal of the fourth transistor are connected to another of the plurality of voltage-current conversion circuits, the control terminal of the fifth transistor, and the control terminal of the sixth transistor. The second terminal of the fifth transistor is connected to the first terminal of the charging resistor, and the second terminal of the sixth transistor is connected to the first terminal of the charging capacitor.

12. The single-inductor multi-output power converter according to claim 7, characterized in that, The duty cycle setting circuit includes: A charging resistor, wherein the first end of the charging resistor is connected to multiple voltage-to-current conversion circuits, and the second end of the charging resistor is grounded; A charging capacitor, wherein the first terminal of the charging capacitor is connected to multiple voltage-to-current conversion circuits, and the second terminal of the charging capacitor is grounded; A first comparator, the first input terminal of the first comparator is connected to the first terminal of the charging capacitor, and the second input terminal of the first comparator is coupled to a total voltage of a plurality of the error amplification signals; A second comparator, the first input of which is connected to the first terminal of the charging capacitor, and the second input of which is connected to the output of one of the plurality of error amplifiers; A third comparator, wherein the first input terminal of the third comparator is connected to the first terminal of the charging capacitor, and the second input terminal of the third comparator is connected to the first terminal of the charging resistor; as well as A switching signal generation circuit is configured to output a plurality of switching signals based on a plurality of comparison signals received from the outputs of the plurality of comparators, respectively.

13. The single-inductor multi-output power converter according to claim 12, characterized in that, The plurality of output switches include a first output switch, a second output switch, and a third switch assembly, and the switching signal generation circuit includes: A first flip-flop, one output terminal of which is connected to the control terminal of the third switching assembly; The second flip-flop has its first input terminal connected to the output terminal of the first comparator, its second input terminal connected to the output terminal of the second comparator, and its output terminal connected to the control terminal of the second output switch. The third flip-flop has a first input terminal connected to the output terminal of the second comparator and an output terminal connected to the control terminal of the first output switch. A clock circuit, wherein the input terminal of the clock circuit is connected to the output terminal of the third comparator, the first output terminal of the clock circuit is connected to the first input terminal of the first flip-flop and the second input terminal of the third flip-flop, and the second input terminal of the first flip-flop is connected to the output terminal of the first comparator. as well as A reset switch is provided, wherein the control terminal of the reset switch is connected to the second output terminal of the clock circuit, the first terminal of the reset switch is connected to the first terminal of the charging capacitor, and the second terminal of the reset switch is grounded.

14. The single-inductor multi-output power converter according to claim 12, characterized in that, The duty cycle setting circuit further includes: The first current mirror circuit includes a first transistor, a second transistor, and a third transistor. The first terminal of the first transistor is connected to the first terminal of the second transistor and the first terminal of the third transistor. The second terminal and the control terminal of the first transistor are connected to one of the multiple voltage-to-current conversion circuits, the control terminal of the second transistor, and the control terminal of the third transistor. The second terminal of the second transistor is connected to the first terminal of the charging resistor, and the second terminal of the third transistor is connected to the first terminal of the charging capacitor.

15. The single-inductor multi-output power converter according to claim 14, characterized in that, The duty cycle setting circuit further includes: The second current mirror circuit includes a fourth transistor, a fifth transistor, and a sixth transistor. The first terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the first terminal of the sixth transistor. The second terminal and the control terminal of the fourth transistor are connected to another of the plurality of voltage-current conversion circuits, the control terminal of the fifth transistor, and the control terminal of the sixth transistor. The second terminal of the fifth transistor is connected to the first terminal of the charging resistor, and the second terminal of the sixth transistor is connected to the first terminal of the charging capacitor.

16. The single-inductor multi-output power converter according to claim 15, characterized in that, The duty cycle setting circuit further includes: The third current mirror circuit includes a seventh transistor, an eighth transistor, and a ninth transistor. The first terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the first terminal of the ninth transistor. The second terminal and the control terminal of the seventh transistor are connected to another of the multiple voltage-to-current conversion circuits, the control terminal of the eighth transistor, and the control terminal of the ninth transistor. The second terminal of the eighth transistor is connected to the first terminal of the charging resistor, and the second terminal of the ninth transistor is connected to the first terminal of the charging capacitor.

17. The single-inductor multi-output power converter according to claim 1, characterized in that, The single-inductor multi-output power converter also includes: Multiple buffers are provided, with their input terminals connected to the output terminal of the duty cycle allocation circuit, and their output terminals respectively connected to the control terminals of multiple output switches.

18. The single-inductor multi-output power converter according to claim 1, characterized in that, The single-inductor multi-output power converter also includes: A current sensing circuit is connected to the first terminal of the upper bridge switch, configured to sense the current of the upper bridge switch and convert the sensed current of the upper bridge switch into a voltage, and output a sensing signal based on the voltage. A sensor processor, connected to the current sensing circuit, is configured to output a current sensing processing signal based on the voltage of the sensing signal and the voltage of the ramp signal. as well as The comparator has its first input connected to the output of the sensor processor, its second input connected to the output of the signal duty cycle allocation circuit, and its output connected to the input of the control circuit.

Images