Transient analysis method for dual step-down power amplifier switch by characterizing distributed capacitance

Abstract

The invention provides a transient analysis method for a dual-step-down power amplifier switch by representing distributed capacitance, and belongs to the technical field of motor driving. The method comprises the following steps: step 1, influence of the position of a distributed capacitor on the transient characteristic of a dual-step-down symmetrical half-bridge power amplifier switch; 2, characterizing mathematical modeling of the distributed capacitance on the transient characteristics of the dual-step-down symmetrical half-bridge power amplifier switch; and step 3, influence of distributed capacitance value change on the switching process of the double-step-down symmetrical half-bridge power amplifier is determined. According to the method for analyzing the switching transient state of the dual-step-down power amplifier by representing the distributed capacitance, theoretical support and engineering basis are provided for layout design and electrical stress control of the dual-step-down symmetrical half-bridge power amplifier in high-precision application.

Description

Technical Field

[0001] This invention relates to a method for characterizing distributed capacitance in the switching transient analysis of a dual buck power amplifier, belonging to the field of motor drive technology. Background Technology

[0002] In ultra-precision motion control systems such as wafer positioning platforms, the output current of the power amplifier directly affects system performance. Traditional bridge power amplifiers require the introduction of dead time to avoid short-circuit risks; however, the nonlinear distortion caused by the dead time can induce undesirable pulsating torque in the generator.

[0003] To address this, a dual buck symmetrical half-bridge power amplifier (DBSHPA) based on GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) devices was proposed, such as... Figure 1 As shown, this structure effectively suppresses the midpoint potential shift of the bridge arms caused by the difference in thermal characteristics between the on-resistance and the forward voltage drop of the diode during the turn-on and turn-off transients through symmetrical conduction of the upper and lower bridge arms, thereby suppressing the nonlinear distortion of the output current. However, due to the extremely high dv / dt characteristics of GaN HEMTs, their switching process is more susceptible to interference from PCB (Printed Circuit Board) parasitic parameters, especially the distributed capacitance between the bridge arms. In high-frequency applications, this significantly affects the transient response during turn-on / turn-off, leading to phenomena such as current overshoot, voltage ringing, and even gate mis-turn-on, thereby reducing system stability and reliability. Summary of the Invention

[0004] The purpose of this invention is to solve the problems existing in the prior art and to provide a method for characterizing distributed capacitance for switching transient analysis of a dual buck power amplifier.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] The method for characterizing distributed capacitance in the switching transient analysis of a dual-buck power amplifier includes the following steps:

[0007] Step 1: The effect of distributed capacitance location on the switching transient characteristics of a dual buck symmetrical half-bridge power amplifier;

[0008] A transient analysis equivalent circuit model was adopted, and simulation comparison analysis was conducted by selecting different parasitic capacitance placement positions. The conduction current amplitude, turn-off voltage amplitude, and switching frequency of the device under different parasitic capacitance placement positions were compared with the transient analysis equivalent circuit model without distributed capacitance to determine the impact of capacitance position changes on the switching transient behavior of GaN HEMTs.

[0009] While keeping the total parasitic capacitance constant, the on-current amplitude, off-voltage amplitude, and switching frequency of the device remain almost unchanged for different parasitic capacitance placement locations, indicating that the location of the parasitic capacitance has little effect on the transient behavior of GaN HEMTs. Based on this, a simplified equivalent circuit model for transient analysis of parasitic capacitance is constructed.

[0010] Step 2: Mathematical modeling of the effect of distributed capacitance on the switching transient characteristics of a dual-buck symmetrical half-bridge power amplifier;

[0011] The study investigates the coupling relationship between the conduction and turn-off processes of GaN HEMTs switches S1, S2, S3, and S4 in the simplified transient analysis equivalent circuit model of parasitic capacitance in step one, and establishes a mathematical model. In this model, switches S2 and S3 are always in the conduction state, while switches S1 and S4 are simultaneously in the conduction and turn-off state.

[0012] Step 3: The effect of changes in distributed capacitance on the switching process of a dual buck symmetrical half-bridge power amplifier;

[0013] Based on the simplified transient analysis equivalent circuit model of parasitic capacitance in step one, and according to the mathematical model established in step two, the distributed capacitance value is changed to obtain the influence of the distributed capacitance value on the switching electrical stress of GaN HEMTs.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0015] This invention proposes a method for characterizing the effect of distributed capacitance on the switching transients of a dual-buck power amplifier. Based on the switching behavior of GaN HEMTs, this method systematically studies the influence mechanism of the location and size of the distributed capacitance between bridge arms on the device's on-state current and off-state voltage, and establishes its equivalent circuit model. First, by analyzing the influence of distributed capacitance at different locations on transient characteristics, the results show that the capacitance location has a relatively small impact on switching characteristics while keeping the total capacitance value constant. Second, a multi-modal mathematical model of the entire switching process is constructed to describe the transient evolution of voltage and current over time. Finally, by adjusting the distributed capacitance value, the influence of distributed capacitance on on-state overshoot and off-state ringing is revealed. Experimental results verify the effectiveness of the proposed analysis method, providing theoretical support and engineering basis for the layout design and electrical stress control of dual-buck symmetrical half-bridge power amplifiers in high-precision applications. Attached Figure Description

[0016] Figure 1 This is a topology diagram of a dual buck symmetrical half-bridge power amplifier.

[0017] Figure 2 This is a diagram of the parasitic capacitance between the bridge arms of the present invention.

[0018] Figure 3 The diagram shows the equivalent circuit model for transient analysis of gallium nitride (GaN) HEMTs switches considering parasitic parameters, as presented in this invention.

[0019] Figure 4 This is a diagram showing the turn-off voltage / turn-on current at different parasitic capacitance locations according to the present invention; wherein:

[0020] Figure 4 (a) is a current diagram of the parasitic capacitance positions from position 1 to position 3 of the present invention;

[0021] Figure 4 (b) is a current diagram of the parasitic capacitance positions from position 4 to position 6 of the present invention;

[0022] Figure 4 (c) is a diagram of the turn-off voltage at the parasitic capacitance positions 1 to 3 of the present invention;

[0023] Figure 4 (d) is a diagram of the turn-off voltage at the parasitic capacitance positions 4 to 6 of the present invention.

[0024] Figure 5 The diagram shows the equivalent circuit model for the simplified parasitic parameters of gallium nitride (GaN) HEMTs switching transient analysis according to the present invention.

[0025] Figure 6 This is a transient waveform diagram of the switching device of the present invention during conduction.

[0026] Figure 7 For the present invention Figure 6 The t0 to t1 stage is the equivalent circuit diagram of the S1 and S4 driving delay stages.

[0027] Figure 8 For the present invention Figure 6 The t1 to t2 stages are the equivalent circuit diagram for the S4 turn-on stage.

[0028] Figure 9 For the present invention Figure 6 The t2 to t3 stages are the equivalent circuit diagram of the S1 turn-on stage.

[0029] Figure 10 For the present invention Figure 6 The equivalent circuit diagram for the t3 to t4 stage is the drain-source voltage drop stage of S4.

[0030] Figure 11 For the present invention Figure 6 The equivalent circuit diagram for the t4 to t5 stage is the drain-source voltage drop stage of S1.

[0031] Figure 12 For the present invention Figure 6 The t5 to t7 stage is D 4、 Equivalent circuit diagram of diode D1 during the oscillation phase.

[0032] Figure 13 For the present invention Figure 6 During the t7 to t9 stage, switch S... 4、 Equivalent circuit diagram of S1 during the oscillation phase.

[0033] Figure 14 For switch S 4、 The equivalent circuit diagram of S1 turning on and oscillating.

[0034] Figure 15 This is a waveform diagram of the switching device of the present invention in the turn-off transient state.

[0035] Figure 16 For the present invention Figure 15 The t0 to t1 stage is S 1、 Equivalent circuit diagram of the S4 drive delay stage.

[0036] Figure 17 For the present invention Figure 15 The t1 to t2 stage is the equivalent circuit diagram of the drain-source voltage rise stage of S4.

[0037] Figure 18 For the present invention Figure 15 The t2 to t3 stage is the equivalent circuit diagram of the drain-source voltage rise stage of S1.

[0038] Figure 19 For the present invention Figure 15 This is one case in the t3 to t4 stage, which is the equivalent circuit diagram where the channel current ich reaches zero before the voltage across diodes D1 and D4 drops to 0.

[0039] Figure 20 For the present invention Figure 15 Another case is the channel current i during the t3 to t4 stage. ch The equivalent circuit diagram of the voltage across diodes D1 and D4 dropping to 0 before reaching 0.

[0040] Figure 21 For the present invention Figure 15 During the t4 to t5 stage, D 4、 Equivalent circuit diagram of diode D1 during the oscillation phase.

[0041] Figure 22 For the present invention Figure 15 During the t5 to t6 stage, switch S 1、 Equivalent circuit diagram of the S4 oscillation stage.

[0042] Figure 23 For switch S 4、 The equivalent circuit diagram of the oscillation completed by S1 being turned off.

[0043] Figure 24 This is a schematic diagram of the turn-on current and turn-off voltage of the present invention; wherein:

[0044] Figure 24 (a) is a schematic diagram of the turn-on current of the switch S1 of the present invention;

[0045] Figure 24 (b) is a schematic diagram of the turn-off voltage of the switch S1 of the present invention;

[0046] Figure 24 (c) is a schematic diagram of the turn-on current of the switch S4 of the present invention;

[0047] Figure 24 (d) is a schematic diagram of the turn-off voltage of the switch S4 of the present invention.

[0048] Figure 25 This is a schematic diagram of the turn-off current and rate of change of the present invention; wherein:

[0049] Figure 25 (a) is a schematic diagram of the turn-off current of the present invention;

[0050] Figure 25 (b) is a schematic diagram of the rate of change of the turn-off of the present invention.

[0051] Figure 26 This is a schematic diagram illustrating the turn-off voltage overshoot under different parasitic capacitances according to the present invention.

[0052] Figure 27 This is a schematic diagram of the experimental prototype of the dual buck symmetrical half-bridge power amplifier of the present invention.

[0053] Figure 28 The following are experimental waveforms of GaN HEMTs with different distributed capacitances according to the present invention; wherein:

[0054] Figure 28 (a) is an experimental waveform of the turn-on current of switch S1 in GaN HEMTs with different distributed capacitances.

[0055] Figure 28 (b) is an experimental waveform of the turn-off voltage of switch S1 for GaN HEMTs with different distributed capacitances.

[0056] Figure 28 (c) is an experimental waveform of the turn-on current of switch S4 for GaN HEMTs with different distributed capacitances.

[0057] Figure 28(d) is an experimental waveform of the turn-off voltage of switch S4 for GaN HEMTs with different distributed capacitances.

[0058] Figure 2 In the attached diagram, 1 represents the voltage node, 2 represents the top layer, 3 represents the copper foil, and 4 represents the bottom layer. Detailed Implementation

[0059] The present invention will be further described in detail below with reference to the accompanying drawings: This embodiment is implemented under the premise of the technical solution of the present invention, and detailed implementation methods are given, but the protection scope of the present invention is not limited to the following embodiments.

[0060] The method for characterizing the distributed capacitance to analyze the switching transient characteristics of a dual-step symmetrical half-bridge power amplifier involved in this embodiment includes:

[0061] (1) The effect of distributed capacitance location on the switching transient characteristics of a dual buck symmetrical half-bridge power amplifier.

[0062] In PCB traces, the distributed capacitance between bridge arms formed by the overlap of copper foils is unavoidable. For example... Figure 2 As shown, this illustrates the formation mechanism of parasitic capacitance between two PCB nodes, where the parasitic capacitance is introduced by adjacent copper.

[0063] To analyze the impact of parasitic capacitance at different positions between phase arms on the switching transient characteristics of GaN HEMTs devices, based on Figure 3 The transient analysis equivalent circuit model shown selects six typical parasitic capacitance placement positions (position 1 to position 6) and conducts simulation comparison analysis.

[0064] The equivalent circuit model for transient analysis includes: DC bus voltage U i1 U i2 Drive voltage V G1 ~V G4 The gate-source parasitic capacitance C of gallium nitride (GaN) HEMTs devices S1–S4 gs1 ~C gs4 Drain-source parasitic capacitance C ds1 ~C ds4 Gate-drain parasitic capacitance C gd1 ~C gd4 The junction capacitance C of diodes D1 to D4 D1 ~C D4 Distributed capacitance C introduced by PCB traces 1_1 ~C 3_3 Parasitic inductance L P1 L P2 Filter inductors L1 and L2, filter capacitor C f1 C f2Parasitic inductance L at the drain of GaN HEMTs D1 ~L D4 Parasitic inductance L at the source of GaN HEMTs S1 ~L S4 Drive circuit inductance L G1 ~L G4 The load inductance is L; R1 to R4 are parasitic line resistances; and the drive circuit resistance is R. G1 ~R G4 The load resistance is R. Since S2 and S3 are always in the conducting state, S2 and S3 are the on-resistance R. on2 R on3 Since the load branch is considered to be a constant current, its parasitic inductance can be ignored.

[0065] DC bus voltage U i1 The negative terminal and the DC bus voltage U i2 The positive terminal is connected to ground, and the DC bus voltage U i1 The positive terminal is connected to one end of the parasitic resistance R1, and the other end of the parasitic resistance R1 is connected to the parasitic inductance L. D1 One end is connected, parasitic inductance L D1 The other end is connected to the drain of the gallium nitride (GaN) HEMTs device S1, and the source of the gallium nitride (GaN) HEMTs device S1 is connected to the parasitic inductance L. S1 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S1 and the drive circuit inductor L. G1 One end is connected,

[0066] Gate-source parasitic capacitance C gs1 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S1, and the other end is connected to the source of the gallium nitride (GaN) HEMTs device S1. The drain-source parasitic capacitance C ds1 One end is connected to the drain of the gallium nitride (GaN) HEMTs device S1, and the other end is connected to the source of the gallium nitride (GaN) HEMTs device S1. The gate-drain parasitic capacitance C gd1 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S1, and the other end is connected to the drain of the gallium nitride (GaN) HEMTs device S1.

[0067] Drive circuit inductance L G1 The other end is connected to the driving voltage V G1 Positive terminal connection, driving voltage V G1 Negative terminal and drive circuit resistance R G1 One end is connected to the drive circuit resistor R. G1 The other end is connected to the source of the gallium nitride (GaN) HEMTs device S1, with parasitic inductance L. S1The other end is connected to the positive terminal of diode D1, and the negative terminal of diode D1 is connected to the parasitic inductance L. D2 One end is connected, and the junction capacitance C D1 It is connected in parallel across diode D1.

[0068] Parasitic inductance L D2 The other end is connected to the on-resistance R on2 One end is connected, with on-resistance R on2 The other end is connected to the parasitic inductance L S2 One end is connected, parasitic inductance L S2 The other end is connected to the negative terminal of diode D2, and the positive terminal of diode D2 is connected to one end of the line parasitic resistance R2. The junction capacitance C D2 The circuit parasitic resistance R2 is connected in parallel across the two ends of diode D2, and the other end of the circuit parasitic resistance R2 is connected to the DC bus voltage U. i2 The negative terminal connection,

[0069] Gate-source parasitic capacitance C gs2 One end is connected to the on-resistance R on2 One end is connected, and the gate-source parasitic capacitance C gs2 The other end is connected to the gate-drain parasitic capacitance C gd2 One end is connected, and the gate-drain parasitic capacitance C gd2 The other end is connected to the on-resistance R on2 The other end is connected to the drain-source parasitic capacitance C. ds2 Parallel to the on-resistance R on2 At both ends, the driving circuit resistance R G2 One end is connected to the gate-source parasitic capacitance C gs2 and gate-drain parasitic capacitance C gd2 The connection between them, the driving circuit resistance R G2 The other end is connected to the drive circuit inductor L G2 One end is connected to the drive circuit inductor L G2 The other end is connected to the driving voltage V G2 Positive terminal connection, driving voltage V G2 Negative terminal and on-resistance R on2 and parasitic inductance L S2 Connections between,

[0070] DC bus voltage U i1 The positive electrode and parasitic inductance L P1 One end is connected, parasitic inductance L P1 The other end is connected to one end of the parasitic resistance R3, and the other end of the parasitic resistance R3 is connected to the negative terminal of diode D3. The positive terminal of diode D3 is connected to the parasitic inductance L. D3 One end is connected, and the junction capacitance C D3 Parasitic inductance L is connected in parallel across diode D3. D3The other end is connected to the on-resistance R on3 One end is connected, with on-resistance R on3 The other end is connected to the parasitic inductance L S3 One end is connected,

[0071] Gate-source parasitic capacitance C gs3 One end is connected to the on-resistance R on3 One end is connected, and the gate-source parasitic capacitance C gs3 The other end is connected to the gate-drain parasitic capacitance C gd3 One end is connected, and the gate-drain parasitic capacitance C gd3 The other end is connected to the on-resistance R on3 The other end is connected to the drain-source parasitic capacitance C. ds3 Parallel to the on-resistance R on3 At both ends, the inductance L of the drive circuit G3 One end is connected to the gate-source parasitic capacitance C gs3 and gate-drain parasitic capacitance C gd3 The connection between them, the inductance of the drive circuit L G3 The other end is connected to the driving voltage V G3 Positive terminal connection, driving voltage V G3 Negative terminal and drive circuit resistance R G3 One end is connected to the drive circuit resistor R. G3 The other end is connected to the on-resistance R on3 and parasitic inductance L S3 Connections between,

[0072] Parasitic inductance L S3 The other end is connected to the positive terminal of diode D4, and the negative terminal of diode D4 is connected to the parasitic inductance L. D4 One end is connected, parasitic inductance L D4 The other end is connected to the drain of the gallium nitride (GaN) HEMTs device S4, and the source of the gallium nitride (GaN) HEMTs device S4 is connected to the parasitic inductance L. S4 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S4 and the drive circuit resistor R. G4 One end is connected,

[0073] Gate-source parasitic capacitance C gs4 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S4, and the other end is connected to the source of the gallium nitride (GaN) HEMTs device S4. The drain-source parasitic capacitance C ds4 One end is connected to the drain of the gallium nitride (GaN) HEMTs device S4, and the other end is connected to the source of the gallium nitride (GaN) HEMTs device S4. The gate-drain parasitic capacitance C gd4One end is connected to the gate of the gallium nitride (GaN) HEMTs device S4, and the other end is connected to the drain of the gallium nitride (GaN) HEMTs device S4.

[0074] Drive circuit resistance R G4 The other end is connected to the drive circuit inductor L G4 One end is connected to the drive circuit inductor L G4 The other end is connected to the driving voltage V G4 Positive terminal connection, driving voltage V G4 The negative electrode is connected to the source of the gallium nitride (GaN) HEMTs device S1, with parasitic inductance L. S4 The other end is connected to one end of the parasitic resistance R4, and the other end of the parasitic resistance R4 is connected to the parasitic inductance L. P2 One end is connected, parasitic inductance L P2 The other end is connected to the DC bus voltage U i2 The negative terminal connection,

[0075] Filter capacitor C f1 One end is connected to the parasitic inductance L P1 The filter capacitor C is connected between the line parasitic resistance R3 and the line. f1 The other end is connected to the filter capacitor C f2 One end is connected to the filter capacitor C. f2 The other end is connected to the line parasitic resistance R4 and parasitic inductance L. P2 The filter inductor L1 is connected to the diode D1 and the parasitic inductor L. D2 The two ends of the filter inductor L1 are connected to each other, and the other end of the filter capacitor C is connected to the filter capacitor C. f1 and C f2 The filter inductor L2 is connected to the parasitic inductor L. S3 The other end of the filter inductor L2 is connected to the filter capacitor C. f1 and C f2 The load inductor L is connected to the filter capacitor C. f1 and C f2 The two are connected together, with the other end of the load inductor L connected to one end of the load resistor R, and the other end of the load resistor R grounded.

[0076] like Figure 4 As shown, experimental data on the on-current and off-voltage waveforms of the device under different parasitic capacitance placements are presented. Simulation results show that, while keeping the total parasitic capacitance constant, the on-current amplitude, off-voltage amplitude, and switching frequency remain almost unchanged for different parasitic capacitance placements. The drain-source voltage and drain-source current overshoots are both less than 1%, indicating that changes in parasitic capacitance placement have minimal impact on the transient switching behavior of GaN HEMTs; the voltage / current waveforms of the device show no significant changes. Therefore, [the following is a continuation of the previous sentence, but the context is unclear]. Figure 3 The distributed parameter model is simplified to Figure 5 As shown.

[0077] (2) Mathematical modeling of the effect of distributed capacitance on the switching transient characteristics of a dual buck symmetrical half-bridge power amplifier

[0078] This specific implementation focuses on the mutual coupling of the switching on and off processes in the entire circuit. Switches S2 and S3 are always in the on state, while switches S1 and S4 are switched on and off simultaneously. Since it is difficult to make the parasitic parameters on the left and right sides completely consistent in the actual circuit, the following analysis assumes that the parasitic parameters of the II side branch are smaller based on the parasitic parameters extracted by Q3D.

[0079] The conduction transient waveform of gallium nitride (GaN) HEMTs is as follows: Figure 6 As shown, the equivalent circuit is as follows: Figures 7-14 As shown.

[0080] The specific process of establishing a mathematical model for the mutual coupling relationship between the turn-on and turn-off processes of GaN HEMTs switches S1, S2, S3, and S4 is as follows:

[0081] i g1 ~i g4 It is the driving current, R g1 ~R g4 It is the driving resistor, L G1 ~L G4 It is the gate parasitic inductance, V EE It is the driving negative voltage, DC bus voltage U i1 U i2 Drive voltage V G1 ~V G4 The gate-source parasitic capacitance C of gallium nitride (GaN) HEMTs devices S1–S4 gs Drain-source parasitic capacitance C ds Gate-drain parasitic capacitance C gd The junction capacitance C of diodes D1 to D4 D Parasitic capacitances C1, C2, and C3, and parasitic inductance L introduced by PCB traces P1 L P2 , filter capacitor C f The parasitic inductance L of the drain circuit D1 ~L D4 Parasitic inductance L of the source circuit S1 ~L S4 The load inductance is L. R1 to R4 are parasitic line resistances, and the load resistance is R. The drain-source current is i. D1 ~i D4 The channel current is i ch The filter inductor current is i L1 ~iL4 The parasitic resistance of the filter inductor is R. L The distributed capacitance voltage is u cp The distributed capacitance current is i cp The output voltage is u out The channel currents of switches S1 and S4 are i ch1 i ch4 ;

[0082] For the conduction phase of switches S1 and S4:

[0083] Mode I (t0~t1 stage, such as Figure 7 As shown): At time t0, the driving voltage V G1 V G4 The voltage changes from negative to positive, driving voltage V G1 and V G4 To the gate-source capacitance C respectively gs1 C gs4 and drain-source capacitance C ds1 C ds4 Charging, gate-source voltage u gs1 u gs4 It begins to rise; during this phase, the drain-source voltage u ds1 u ds4 It remains unchanged. Among them, the input capacitance C... iss =C gs +C gd Output capacitor C oss =C ds +C gd Reverse transfer capacitor C rss =C gd C gd It is the gate-drain capacitance. t1 and t0 are... Figure 6 The moment above.

[0084] (1)

[0085] The rise time of the drive is a = t1 - t0, and during this stage, the drive voltage is modeled as having a linear relationship with time. The voltage equations for the drive circuits of switches S1 and S4 are then obtained as follows:

[0086] (2)

[0087] Mode II (t1 to t2 stage, such as...) Figure 8 As shown): Due to the small driving resistance of the S4 circuit, S4 reaches the threshold voltage first, and the channel of switch S4 begins to conduct, with the channel current i ch4 From the gate-source voltage u gs4 Control. The junction capacitance C of diode D4. D4Discharge occurs, causing oscillation with the parasitic inductance in the right bridge arm, while S1 remains in the delay phase.

[0088] (3)

[0089] (4)

[0090] (5)

[0091] (6)

[0092] (7)

[0093] (8)

[0094] (9)

[0095] (10)

[0096] When the gate-source voltage u gs1 Rise to threshold voltage V th This mode ends at this point.

[0097] Mode III (t2 to t3 stage, such as...) Figure 9 As shown: At time t2, switch S1 reaches the threshold voltage, and the process is similar to that of switch S4. Due to the parasitic capacitance introduced by the PCB layout, the assumed value is C. p The two branches are connected by C. p Oscillation coupling occurs, further exacerbating the mutual influence between branches.

[0098] (11)

[0099] (12)

[0100] (13)

[0101] Modal IV (t3~t4 stage, such as Figure 10 As shown): Switch S4 reaches the Miller voltage, and the output capacitor C... OSS4 Discharge begins, drain-source voltage u ds4 The current begins to decrease, and during this stage, the switching device S1 is still in the current rising stage.

[0102] (14)

[0103] (15)

[0104] Mode V (t4~t5 stage, such as) Figure 11 As shown): Switch S1 reaches Miller voltage, drain-source voltage u ds1 It started to descend.

[0105] (16)

[0106] (17)

[0107] Modal VI (t5~t7 stage, such as) Figure 12 (As shown): Switch S4 enters the current overshoot stage. During the commutation process, the junction capacitance C of diodes D1 and D4... D1 C D4 Due to reverse bias, the stored charge is released when u D1 u D4 When the voltage drops to the forward threshold voltage, D1 and D4 switch from reverse recovery to forward conduction; when the drain-source current i D2 i D3 When the capacitance of the junction of diodes D2 and D3 drops to 0, C D2 C D3 They participate in resonance. Due to the different parasitic parameters of the two bridge arms, diodes D1 and D4 may conduct simultaneously or one may be on while the other is off. The choice of this process is related to the switching speed, circuit parameters, and load current.

[0108] (18)

[0109] (19)

[0110] (20)

[0111] (twenty one)

[0112] When the current i D1 and i D4 The phase ends when the value no longer becomes negative.

[0113] Mode VII (t7~t9 stage, such as Figure 13 (As shown): Switches S1 and S4 oscillate. At time t7, diodes D1 and D4 are fully turned on, and the parasitic inductance and capacitance on their respective bridge arms resonate. Simultaneously, due to the unavoidable distributed capacitance in the PCB layout, a path is provided for coupling between bridge arm I and bridge arm II, allowing resonant energy to be transferred interactively through this path. R loop High-frequency equivalent resistance

[0114] (twenty two)

[0115] (twenty three)

[0116] The process ends when the oscillation completely decays, and the S1 and S4 opening process ends, as follows: Figure 14 As shown.

[0117] The turn-off transient waveform of gallium nitride (GaN) HEMTs is as follows: Figure 15 As shown, the equivalent circuit is as follows: Figures 16-23 As shown.

[0118] For the turn-off phase of switches S1 and S4:

[0119] Mode I (t0~t1 stage, such as Figure 16 (As shown): Drive delay. At time t0, the drive voltage of switching devices S1 and S4 becomes -3V, and their input capacitor C... iss Discharge begins. In this operating mode, the inductor current i... L1 Through S1 freewheeling, the inductor current i L4 Continue streaming via S4.

[0120] (twenty four)

[0121] (25)

[0122] (26)

[0123] (27)

[0124] (28)

[0125] (29)

[0126] (30)

[0127] (31)

[0128] When the gate-source voltage satisfies u gs4 =v th4 +i L2max / g f At this time, the channel current is controlled by the drive voltage, and switch S4 begins to turn off, ending this mode. L2max For filter inductor i L2 Maximum value, g f For positive conduction transconductance.

[0129] Mode II (t1 to t2 stage, such as...) Figure 17 As shown): In this operating mode, the channel current i of switch S4 ch From the gate-source voltage ugs Control, with u gs Variation in channel current i ch In response to this change, switch S1 operates in the delay phase. Because i D4 The rate of change is limited by parasitic inductance, i D4 The change ratio of i ch Slow change, i D4 with i ch The current difference between them affects the output capacitor C. oss4 Charging, drain-source voltage u ds4 Start increasing. L1 and i D4 The current difference between them causes the parasitic capacitance C of the diode to... D3 Discharge, causing u D3 decline.

[0130] (32)

[0131] (33)

[0132] (34)

[0133] (35)

[0134] (36)

[0135] When the gate-source voltage satisfies u gs1 =v th1 +i L1max / g f At this time, the channel current is controlled by the driving voltage, and switch S1 begins to turn off, ending this mode. L1max For filter inductor i L1 Maximum value

[0136] Mode III (t2 to t3 stage, such as...) Figure 18 As shown): In this operating mode, the channel current i of switch S1 ch With u gs As it changes, switch S1 operates in mode I.

[0137] (37)

[0138] (38)

[0139] When the channel current i of switch S4 ch The mode ends when the voltage drops to zero or the voltage across the diode drops to 0. Which occurs first depends on the switching speed, circuit parameters, and load current. When the gate resistance is low, the channel current i... chThe rate of descent accelerates. However, when the parasitic inductance is large, i D3 The slower rate of descent causes the voltage u across the diode to decrease. D3 The decrease is slow. When the filter inductor current is small, the channel current i... ch It is easier to drop to zero.

[0140] Modal IV (t3~t4 stage): First case, such as Figure 19 As shown: the channel current i before the voltage across the diode drops to 0. ch First, it reaches zero. During this period, no current flows through the channel between switch S4 and switch S1, C iss and diode capacitor C D Continue discharging. Filter inductor current i L1 is i D1 and C D2 The sum of the discharge currents, and the filter inductor current i L4 is i D4 and C D3 The sum of the discharge currents.

[0141] (39)

[0142] (40)

[0143] This operating mode ends when the voltage across the diode drops to 0.

[0144] The second scenario, such as Figure 20 As shown: in the channel current i ch Before reaching 0, the voltage across the diode drops to 0. At this time, the channel current i ch Still determined by the gate-source voltage u gs Control. The filter inductor current freewheels through the diode.

[0145] When the channel current i ch When the value drops to 0, this working mode ends.

[0146] Mode V (t4~t5 stage, such as) Figure 21 As shown):

[0147] Because bridge arm I has larger parasitic parameters and greater high-frequency damping in the circuit, the current decay rate of bridge arm I is faster than that of bridge arm II. Therefore, diode D1 turns off first. Figure 21 As shown, S1 enters the drain-source voltage oscillation period. Capacitor C D1 With loop inductance L loop1 Capacitor C ds1 C ds2 There is an underdamped parasitic oscillation.

[0148] (41)

[0149] When diode D3 in bridge arm II is turned on and diode D4 is turned off, this mode ends.

[0150] Modal IV (t4 to t5 stage, such as...) Figure 22 As shown): Since diodes D1 and D4 are both in the off state, bridge arm I and bridge arm II are connected by inductors L1 and L2 and parasitic capacitance C. P C OSS1 C OSS4 When resonance occurs, the turn-off oscillation time of the drain-source voltage is longer.

[0151] (42)

[0152] When the oscillation completely decays, S1 and S4 are completely turned off, as follows: Figure 23 As shown, the shutdown process has ended.

[0153] (3) The effect of the change in distributed capacitance on the switching process of a dual buck symmetrical half-bridge power amplifier

[0154] To effectively study the impact of PCB distributed capacitance on the electrical stress of GaN HEMTs switches, based on the original equivalent circuit calculation model, we assume that C1, C2, and C3 have values ​​of C... P Change the distributed capacitance value C P Since C1, C2, and C3 are distributed capacitances at different locations, to simplify the following analysis, the values ​​of C1, C2, and C3 will be assumed to be C. P .

[0155] Figure 24 The influence of C2 on switch stress is given under operating conditions of 50V / 1.92A and 50V / -1.8A. (From...) Figure 24 (a) It can be seen that C2 has an effect on the turn-on current overshoot of GaN HEMTs, C P The larger the value, the greater the turn-on current overshoot. Under the conditions of this experiment, C P For every 20pF increase, the turn-on current overshoot increases by approximately 0.25A, meaning the current overshoot is related to C. P It changes in a direct proportion. This conclusion is consistent with the result of equation (1).

[0156] i D1 Current overshoot is:

[0157] (43)

[0158] Depend on Figure 24 (b) and Figure 24 (d) From this, we can obtain C P It also affects the turn-off voltage overshoot of GaN HEMTs, and varies with C. PThe increase of voltage overshoot leads to an increase in voltage overshoot.

[0159] (44)

[0160] Since the filter inductances are all constant values, C P The change in current can only cause changes in the rate of change of drain current and the rate of change of switching node voltage. The rate of change of current during the turn-off phase varies with C. P See the changes Figure 25 (a). By Figure 25 (b) It can be seen that, with C P As C increases, the turn-off current changes little and can be considered a constant. The second term in equation (44) changes with C. P It increases as it increases.

[0161] For quantitative analysis of C P The effect of turn-off voltage overshoot is analyzed by substituting the rate of change of turn-off current and the second-order rate of change of load voltage extracted from the equivalent circuit model calculation results into equation (44), and then comparing the results with the calculation results of the equivalent circuit model. Figure 26 As shown. The calculation results of the equivalent circuit model can be obtained from... Figure 25 Obtained from C. P When the voltage is taken as 0pF, 20pF, 40pF, and 60pF respectively, the first and second terms of the turn-off voltage overshoot calculated by equation (44) are 8V, 7.7V, 7.5V, 7.1V and 0V, 2.4V, 4.2V, 6.1V respectively. That is, the voltage overshoot caused by the second term basically follows C. P The voltage increases proportionally, while the voltage overshoot caused by the first term decays slowly, verifying the above conclusion that voltage overshoot is related to C. P It changes in direct proportion to the change.

[0162] To verify the impact of PCB distributed capacitance on the switching characteristics of GaN HEMTs, a DBSHPC prototype was fabricated, and a breakpoint was artificially preset between two branches, such as... Figure 27 As shown.

[0163] The distributed capacitance can be changed by adding capacitors of different sizes at the break point. For example... Figure 28 As shown, the switching waveform of the device is given when the distributed capacitance changes, with other conditions remaining unchanged.

[0164] The results show that distributed capacitance has little effect on steady-state operation, but is closely related to current overshoot and voltage overshoot in GaN HEMTs switching devices. Within a certain range, current and voltage overshoot increase approximately linearly with increasing distributed capacitance. For every 20 pF increase, drain-source current overshoot increases by about 10%, and drain-source voltage overshoot increases by about 6%. Comparatively, inter-branch current coupling caused by distributed capacitance is the key factor contributing to the large variation in drain-source current overshoot.

[0165] The above description is merely a preferred embodiment of the present invention. These specific embodiments are different implementations based on the overall concept of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for characterizing distributed capacitance to the switching transient analysis of a dual-buck power amplifier, characterized in that, Includes the following steps: Step 1: The effect of distributed capacitance location on the switching transient characteristics of a dual buck symmetrical half-bridge power amplifier; A transient analysis equivalent circuit model was adopted, and simulation comparison analysis was conducted by selecting different parasitic capacitance placement positions. The conduction current amplitude, turn-off voltage amplitude, and switching frequency of the device under different parasitic capacitance placement positions were compared with the transient analysis equivalent circuit model without distributed capacitance to determine the impact of capacitance position changes on the switching transient behavior of GaN HEMTs. While keeping the total parasitic capacitance constant, the on-current amplitude, off-voltage amplitude, and switching frequency of the device remain almost unchanged for different parasitic capacitance placement locations, indicating that the location of the parasitic capacitance has little effect on the transient behavior of GaN HEMTs. Based on this, a simplified equivalent circuit model for transient analysis of parasitic capacitance is constructed. Step 2: Mathematical modeling of the effect of distributed capacitance on the switching transient characteristics of a dual-buck symmetrical half-bridge power amplifier; The study investigates the coupling relationship between the conduction and turn-off processes of GaN HEMTs switches S1, S2, S3, and S4 in the simplified transient analysis equivalent circuit model of parasitic capacitance in step one, and establishes a mathematical model. In this model, switches S2 and S3 are always in the conduction state, while switches S1 and S4 are simultaneously in the conduction and turn-off state. Step 3: The effect of changes in distributed capacitance on the switching process of a dual buck symmetrical half-bridge power amplifier; Based on the simplified transient analysis equivalent circuit model of parasitic capacitance in step one, and according to the mathematical model established in step two, the distributed capacitance value is changed to obtain the influence of the distributed capacitance value on the switching electrical stress of GaN HEMTs.

2. The method for characterizing distributed capacitance for transient analysis of a dual-buck power amplifier switch according to claim 1, characterized in that, The transient analysis equivalent circuit model mentioned in step one includes: DC bus voltage U i1 U i2 Drive voltage V G1 ~V G4 The gate-source parasitic capacitance C of gallium nitride (GaN) HEMTs devices S1–S4 gs1 ~C gs4 Drain-source parasitic capacitance C ds1 ~C ds4 Gate-drain parasitic capacitance C gd1 ~C gd4 The junction capacitance C of diodes D1 to D4 D1 ~C D4 Distributed capacitance C introduced by PCB traces 1_1 ~C 3_3 Parasitic inductance L P1 L P2 Filter inductors L1 and L2, filter capacitor C f1 C f2 Parasitic inductance L at the drain of GaN HEMTs D1 ~L D4 Parasitic inductance L at the source of GaN HEMTs S1 ~L S4 Drive circuit inductance L G1 ~L G4 The load inductance is L; R1 to R4 are parasitic line resistances; and the drive circuit resistance is R. G1 ~R G4 The load resistance is R. Since S2 and S3 are always in the conducting state, S2 and S3 are the on-resistance R. on2 R on3 ; DC bus voltage U i1 The negative terminal and the DC bus voltage U i2 The positive terminal is connected to ground, and the DC bus voltage U i1 The positive terminal is connected to one end of the parasitic resistance R1, and the other end of the parasitic resistance R1 is connected to the parasitic inductance L. D1 One end is connected, parasitic inductance L D1 The other end is connected to the drain of the gallium nitride (GaN) HEMTs device S1, and the source of the gallium nitride (GaN) HEMTs device S1 is connected to the parasitic inductance L. S1 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S1 and the drive circuit inductor L. G1 One end is connected, Gate-source parasitic capacitance C gs1 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S1, and the other end is connected to the source of the gallium nitride (GaNHEMTs) device S1. The drain-source parasitic capacitance C ds1 One end is connected to the drain of the gallium nitride (GaN) HEMTs device S1, and the other end is connected to the source of the gallium nitride (GaN) HEMTs device S1. The gate-drain parasitic capacitance C gd1 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S1, and the other end is connected to the drain of the gallium nitride (GaN) HEMTs device S1. Drive circuit inductance L G1 The other end is connected to the driving voltage V G1 Positive terminal connection, driving voltage V G1 Negative terminal and drive circuit resistance R G1 One end is connected to the drive circuit resistor R. G1 The other end is connected to the source of the gallium nitride (GaN) HEMTs device S1, with parasitic inductance L. S1 The other end is connected to the positive terminal of diode D1, and the negative terminal of diode D1 is connected to the parasitic inductance L. D2 One end is connected, and the junction capacitance C D1 It is connected in parallel across diode D1. Parasitic inductance L D2 The other end is connected to the on-resistance R on2 One end is connected, with on-resistance R on2 The other end is connected to the parasitic inductance L S2 One end is connected, parasitic inductance L S2 The other end is connected to the negative terminal of diode D2, and the positive terminal of diode D2 is connected to one end of the line parasitic resistance R2. The junction capacitance C D2 The circuit parasitic resistance R2 is connected in parallel across the two ends of diode D2, and the other end of the circuit parasitic resistance R2 is connected to the DC bus voltage U. i2 The negative terminal connection, Gate-source parasitic capacitance C gs2 One end is connected to the on-resistance R on2 One end is connected, and the gate-source parasitic capacitance C gs2 The other end is connected to the gate-drain parasitic capacitance C gd2 One end is connected, and the gate-drain parasitic capacitance C gd2 The other end is connected to the on-resistance R on2 The other end is connected to the drain-source parasitic capacitance C. ds2 Parallel to the on-resistance R on2 At both ends, the driving circuit resistance R G2 One end is connected to the gate-source parasitic capacitance C gs2 and gate-drain parasitic capacitance C gd2 The connection between them, the driving circuit resistance R G2 The other end is connected to the drive circuit inductor L G2 One end is connected to the drive circuit inductor L G2 The other end is connected to the driving voltage V G2 Positive terminal connection, driving voltage V G2 Negative terminal and on-resistance R on2 and parasitic inductance L S2 Connections between, DC bus voltage U i1 The positive electrode and parasitic inductance L P1 One end is connected, parasitic inductance L P1 The other end is connected to one end of the parasitic resistance R3, and the other end of the parasitic resistance R3 is connected to the negative terminal of diode D3. The positive terminal of diode D3 is connected to the parasitic inductance L. D3 One end is connected, and the junction capacitance C D3 Parasitic inductance L is connected in parallel across diode D3. D3 The other end is connected to the on-resistance R on3 One end is connected, with on-resistance R on3 The other end is connected to the parasitic inductance L S3 One end is connected, Gate-source parasitic capacitance C gs3 One end is connected to the on-resistance R on3 One end is connected, and the gate-source parasitic capacitance C gs3 The other end is connected to the gate-drain parasitic capacitance C gd3 One end is connected, and the gate-drain parasitic capacitance C gd3 The other end is connected to the on-resistance R on3 The other end is connected to the drain-source parasitic capacitance C. ds3 Parallel to the on-resistance R on3 At both ends, the inductance L of the drive circuit G3 One end is connected to the gate-source parasitic capacitance C gs3 and gate-drain parasitic capacitance C gd3 The connection between them, the inductance of the drive circuit L G3 The other end is connected to the driving voltage V G3 Positive terminal connection, driving voltage V G3 Negative terminal and drive circuit resistance R G3 One end is connected to the drive circuit resistor R. G3 The other end is connected to the on-resistance R on3 and parasitic inductance L S3 Connections between, Parasitic inductance L S3 The other end is connected to the positive terminal of diode D4, and the negative terminal of diode D4 is connected to the parasitic inductance L. D4 One end is connected, parasitic inductance L D4 The other end is connected to the drain of the gallium nitride (GaN) HEMTs device S4, and the source of the gallium nitride (GaN) HEMTs device S4 is connected to the parasitic inductance L. S4 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S4 and the drive circuit resistor R. G4 One end is connected, Gate-source parasitic capacitance C gs4 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S4, and the other end is connected to the source of the gallium nitride (GaNHEMTs) device S4. The drain-source parasitic capacitance C ds4 One end is connected to the drain of the gallium nitride (GaN) HEMTs device S4, and the other end is connected to the source of the gallium nitride (GaN) HEMTs device S4. The gate-drain parasitic capacitance C gd4 One end is connected to the gate of the gallium nitride (GaN) HEMTs device S4, and the other end is connected to the drain of the gallium nitride (GaN) HEMTs device S4. Drive circuit resistance R G4 The other end is connected to the drive circuit inductor L G4 One end is connected to the drive circuit inductor L G4 The other end is connected to the driving voltage V G4 Positive terminal connection, driving voltage V G4 The negative electrode is connected to the source of the gallium nitride (GaN) HEMTs device S1, with parasitic inductance L. S4 The other end is connected to one end of the parasitic resistance R4, and the other end of the parasitic resistance R4 is connected to the parasitic inductance L. P2 One end is connected, parasitic inductance L P2 The other end is connected to the DC bus voltage U i2 The negative terminal connection, Filter capacitor C f1 One end is connected to the parasitic inductance L P1 The filter capacitor C is connected between the line parasitic resistance R3 and the line. f1 The other end is connected to the filter capacitor C f2 One end is connected to the filter capacitor C. f2 The other end is connected to the line parasitic resistance R4 and parasitic inductance L. P2 The filter inductor L1 is connected to the diode D1 and the parasitic inductor L. D2 The two ends of the filter inductor L1 are connected to each other, and the other end of the filter capacitor C is connected to the filter capacitor C. f1 and C f2 The filter inductor L2 is connected to the parasitic inductor L. S3 The other end of the filter inductor L2 is connected to the filter capacitor C. f1 and C f2 The load inductor L is connected to the filter capacitor C. f1 and C f2 The two are connected together, with the other end of the load inductor L connected to one end of the load resistor R, and the other end of the load resistor R grounded.

3. The method for characterizing distributed capacitance for transient analysis of a dual-buck power amplifier switching according to claim 2, characterized in that, The specific process of establishing a mathematical model for the mutual coupling relationship of the conduction and turn-off processes of GaN HEMTs switches S1, S2, S3, and S4 in step two is as follows: For the conduction phase of switches S1 and S4: Mode I, t0~t1 stage: At time t0, the driving voltage V G1 V G4 The voltage changes from negative to positive, driving voltage V G1 and V G4 To the gate-source capacitance C respectively gs1 C gs4 and drain-source capacitance C ds1 C ds4 Charging, gate-source voltage u gs1 u gs4 It begins to rise; during this phase, the drain-source voltage u ds1 u ds4 The input capacitance C remains unchanged; iss =C gs +C gd Output capacitor C oss =C ds +C gd Reverse transfer capacitor C rss =C gd C gd It is the gate-drain capacitance; (1) The rise time of the drive is a = t1 - t0. During this stage, the drive voltage and time are modeled as having a linear relationship; the voltage equations for the drive circuits of switches S1 and S4 are obtained as follows: (2) Mode II, t1~t2 stage: Due to the small driving resistance of the S4 circuit, S4 reaches the threshold voltage first, and the channel of switch S4 begins to conduct, with the channel current i ch4 From the gate-source voltage u gs4 Control; Junction capacitance C of diode D4 D4 Discharge occurs, causing oscillation with the parasitic inductance in the right bridge arm, and S1 remains in the delay phase; (3) (4) (5) (6) (7) (8) (9) (10) When the gate-source voltage u gs1 Rise to threshold voltage V th This mode ends at this point; Mode III, t2~t3 stage: At time t2, switch S1 reaches the threshold voltage, and the process is similar to that of switch S4; due to the parasitic capacitance introduced by the PCB layout, the assumed value is C. p The two branches are connected by C. p Oscillation coupling occurs, further exacerbating the mutual influence between branches; (11) (12) (13) Mode IV, t3~t4 stage: Switch S4 reaches Miller voltage, output capacitor C OSS4 Discharge begins, drain-source voltage u ds4 The current begins to decrease, and during this stage, the switching device S1 is still in the current-rising phase. (14) (15) Mode V, t4~t5 stage: Switch S1 reaches Miller voltage, drain-source voltage u ds1 It started to descend. (16) (17) Mode VI, t5~t7 stage: Switch S4 enters the current overshoot stage; during the commutation process, the junction capacitance C of diodes D1 and D4... D1 C D4 Due to reverse bias, the stored charge is released when u D1 u D4 When the voltage drops to the forward threshold voltage, D1 and D4 switch from reverse recovery to forward conduction; when the drain-source current i D2 i D3 When the capacitance of the junction of diodes D2 and D3 drops to 0, C D2 C D3 Participating in resonance; due to the different parasitic parameters of the two bridge arms, diodes D1 and D4 may be simultaneously turned on or one may be turned on while the other is turned off; the choice of this process is related to the switching speed, circuit parameters, and load current; (18) (19) (20) (21) When the current i D1 and i D4 This phase ends when the value no longer turns negative. Mode VII, t7~t9 stage: Switches S1 and S4 oscillate. At time t7, diodes D1 and D4 are fully turned on, and the parasitic inductance and capacitance on their respective bridge arms resonate. Simultaneously, due to the distributed capacitance in the PCB layout, a path is provided for coupling between bridge arm I and bridge arm II, allowing resonant energy to be transferred interactively through this path. R loop It is the high-frequency equivalent resistance; (22) (23) The process ends when the oscillation completely decays, and the opening process of S1 and S4 ends. For the turn-off phase of switches S1 and S4: Mode I, t0~t1 stage: drive delay; at time t0, the drive voltage of switching devices S1 and S4 becomes -3V, and their input capacitance C iss Discharge begins; in this operating mode, the inductor current i L1 Through S1 freewheeling, the inductor current i L4 Continuous streaming via S4; (24) (25) (26) (27) (28) (29) (30) (31) When the gate-source voltage satisfies u gs4 =v th4 +i L2max / g f At this time, the channel current is controlled by the drive voltage, switch S4 begins to turn off, and this mode ends; L2max For filter inductor i L2 Maximum value, g f For positive conduction transconductance; Mode II, t1~t2 stage: In this operating mode, the channel current i of switch S4 is... ch From the gate-source voltage u gs Control, with u gs Variation in channel current i ch In response to the change, switch S1 operates in the delay phase; due to i D4 The rate of change is limited by parasitic inductance, i D4 The change ratio of i ch Slow change, i D4 with i ch The current difference between them affects the output capacitor C. oss4 Charging, drain-source voltage u ds4 Start increasing; i L1 and i D4 The current difference between them causes the parasitic capacitance C of the diode to... D3 Discharge, causing u D3 decline; (32) (33) (34) (35) (36) When the gate-source voltage satisfies u gs1 =v th1 +i L1max / g f At this time, the channel current is controlled by the driving voltage, switch S1 begins to turn off, this mode ends, i L1max For filter inductor i L1 Maximum value; Mode III, t2~t3 stage: In this operating mode, the channel current i of switch S1 ch With u gs As it changes, switch S1 operates in mode I; (37) (38) When the channel current i of switch S4 ch The mode ends when the voltage drops to zero or the voltage across the diode drops to 0; which one is reached first depends on the switching speed, circuit parameters, and load current. When the gate resistance is small, the channel current i ch The rate of descent accelerates, and when the parasitic inductance is large, i D3 The slower rate of descent causes the voltage u across the diode to decrease. D3 The decrease is slow; when the filter inductor current is small, the channel current i ch It is easier to drop to zero; Mode IV, t3~t4 stage: First case: Before the voltage across the diode drops to 0, the channel current i ch First to zero; during this period, no current flows through the channel between switch S4 and switch S1, C iss and diode capacitor C D Continue discharging; filter inductor current i L1 is i D1 and C D2 The sum of the discharge currents, and the filter inductor current i L4 is i D4 and C D3 The sum of the discharge currents; (39) (40) This operating mode ends when the voltage across the diode drops to 0. The second scenario: when the channel current i ch Before reaching 0, the voltage across the diode drops to 0. At this time, the channel current i ch Still determined by the gate-source voltage u gs Controlled, the filter inductor current freewheels through the diode; When the channel current i ch When the value drops to 0, this working mode ends; Mode V, t4~t5 stage: Due to the larger parasitic parameters of bridge arm I and the greater high-frequency damping of the circuit, the current decay rate of bridge arm I is faster than that of bridge arm II. Therefore, diode D1 turns off first, and S1 enters the drain-source voltage oscillation period, capacitor C... D1 With loop inductance L loop1 Capacitor C ds1 C ds2 There is underdamped parasitic oscillation; (41) When diode D3 in bridge arm II is turned on and diode D4 is turned off, this mode ends; Mode IV, t4~t5 stage: Since diodes D1 and D4 are both in the off state, bridge arm I and bridge arm II are connected through inductors L1 and L2 and parasitic capacitance C. P C OSS1 C OSS4 When resonance occurs, the turn-off oscillation time of the drain-source voltage is longer; (42) Once the oscillation has completely decayed, S1 and S4 are completely turned off, and the turn-off process ends.

4. The method for characterizing distributed capacitance for transient analysis of a dual-buck power amplifier switching according to claim 3, characterized in that, The specific method for understanding the influence of distributed capacitance value on the electrical stress of GaN HEMTs switches in step three is as follows: Assume the distributed capacitances C1, C2, and C3 are C P Change the distributed capacitance value C P The distributed capacitance value C is obtained. P The effect of C on the electrical stress of GaN HEMTs switches p Impact of turn-on current overshoot on GaN HEMTs; i D1 Current overshoot is: (43) Among them, i D1 It is the drain-source current of switch S1, U ds2 It is the drain-source voltage of switch S2, R on2 It is the on-resistance of switch S2, C oss2 It is the switch drain-source parasitic output capacitance, V G1 It is the driving voltage of switch S1, v miller It is the Miller voltage of the switch, R g1 It is the driving resistor of switch S1, C gd1 It is the gate-drain capacitance of switch S1, V G4 It is the driving voltage of switch S4, R g4 It is the driving resistor of switch S4, C gd4 It is the gate-drain capacitance of switch S4; C P It also affects the turn-off voltage overshoot of GaN HEMTs, and varies with C. P The increase of voltage overshoot leads to an increase in voltage overshoot. (44) Among them, u ds1 The drain-source voltage of switch S1 is given, L1 and L2 are filter inductors, t is time, and u is the source-drain voltage. CP It is the voltage across the distributed capacitor; Since the filter inductances are all constant values, C P The change in C can only cause changes in the rate of change of drain current and the rate of change of switching node voltage; with C P As C increases, the change in the turn-off current is negligible, so it can be considered a constant. The second term in equation (44) changes with C. P It increases with the increase of; For quantitative analysis of C P The effect of turn-off voltage overshoot is to substitute the turn-off current change rate and the second-order change rate of the load voltage extracted from the equivalent circuit model calculation results into equation (44) to obtain the analytical result and compare it with the result of the equivalent circuit model calculation. In C P When the voltages are 0pF, 20pF, 40pF, and 60pF respectively, the first term of equation (44) is used to calculate the turn-off voltage overshoot. and item 2 The voltage overshoots are 8V, 7.7V, 7.5V, 7.1V and 0V, 2.4V, 4.2V, 6.1V respectively, meaning the voltage overshoot caused by the second term basically depends on C. P The voltage increases proportionally, while the voltage overshoot caused by the first term decays slowly, verifying the relationship between voltage overshoot and C. P The conclusion is that the change is directly proportional.

Images