Radio frequency power amplifier and electronic device

Abstract

The application relates to the field of electronic technology. The application provides a radio frequency power amplifier and an electronic device. The radio frequency power amplifier comprises a carrier amplification path, a carrier bias circuit connected with an input end of a carrier amplifier, and a first signal is first amplified; a peak value amplification path, a peak value bias circuit connected with an input end of a peak value amplifier, and a second signal is second amplified; a linearization circuit, an input end connected with the carrier amplification path, and an output end connected with the peak value bias circuit; when the power of the first signal is less than or equal to a power threshold value, the bias current of the peak value bias circuit flows through the linearization circuit, so that the gain of the peak value amplifier is not established; when the power of the first signal is greater than the power threshold value, the bias current of the peak value bias circuit flows through the input end of the peak value amplifier, so that the gain of the peak value amplifier is improved. Through the application, the linearity of the radio frequency power amplifier can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to a radio frequency power amplifier and an electronic device. BACKGROUND

[0002] In a mobile communication system, for example, in a 5G communication system, there is a very high requirement for the linearity of a radio frequency power amplifier (PA). How to improve the linearity of the radio frequency power amplifier has become a problem to be solved in the field of radio frequency power amplifiers. SUMMARY

[0003] Embodiments of the present application provide a radio frequency power amplifier and an electronic device to solve at least one technical problem in the related art. Through the present application, the linearity of the radio frequency power amplifier can be improved.

[0004] In a first aspect, the embodiments of the present application provide a radio frequency power amplifier, which comprises: a carrier amplification path comprising a carrier amplifier and a carrier bias circuit connected to an input end of the carrier amplifier, configured to perform first amplification on a received first signal; a peak amplification path comprising a peak amplifier and a peak bias circuit connected to an input end of the peak amplifier, configured to perform second amplification on a received second signal; a linearization circuit, an input end of which is connected to the carrier amplification path, and an output end of which is connected to the peak bias circuit; wherein when the power of the first signal is less than or equal to a power threshold, the bias current of the peak bias circuit flows through the linearization circuit, so that the gain of the peak amplifier is not established; and wherein when the power of the first signal is greater than the power threshold, the bias current of the peak bias circuit flows through the input end of the peak amplifier, so that the gain of the peak amplifier is improved.

[0005] In some embodiments, the linearization circuit comprises: a first resistor, a first end of which is connected to a first node, and a second end of which is connected to a power supply end; a first capacitor, a first end of which is connected to the first node, and a second end of which is connected to an input end of the linearization circuit; a first transistor, a first end of which is connected to a ground end, and a second end and a control end of which are connected to the first node; and a second transistor, a first end of which is connected to the ground end, a second end of which is connected to an output end of the linearization circuit, and a control end of which is connected to the first node; wherein when the power of the first signal is less than or equal to the power threshold, the second transistor is in a conductive state, and the bias current of the peak bias circuit flows through the second transistor, so that the gain of the peak amplifier is not established; and wherein when the power of the first signal is greater than the power threshold, the second transistor is in a non-conductive state, and the bias current of the peak bias circuit flows through the input end of the peak amplifier, so that the gain of the peak amplifier is improved.

[0006] In some embodiments, the linearization circuit further comprises: a second resistor, a first end of which is connected to the control end of the second transistor, and a second end of which is connected to the first node; and a second capacitor, a first end of which is connected to the first node, and a second end of which is connected to the power supply end.

[0007] In some embodiments, the peak biasing circuit comprises: a current source, a first end of which is connected to the ground end, and a second end of which is connected to the second node; a third transistor, a first end of which is connected to the ground end; a fourth transistor, a first end of which is connected to the second end and the control end of the third transistor, and a second end and the control end of which are connected to the second node; a fifth transistor, a second end of which is connected to the power supply end, and a control end of which is connected to the second node; a third resistor, a first end of which is connected to the output end of the peak biasing circuit, and a second end of which is connected to the first end of the fifth transistor; and a third capacitor, a first end of which is connected to the ground end, and a second end of which is connected to the second node.

[0008] In some embodiments, the output end of the linearization circuit is connected to the second node; wherein, when the power of the first signal is less than or equal to the power threshold, the second transistor is in the on state, the biasing current of the current source flows through the second transistor, and the fifth transistor is in the off state, so that the gain of the peak amplifier is not established; and wherein, when the power of the first signal is greater than the power threshold, the second transistor is in the off state, the biasing current of the current source flows through the control end of the fifth transistor, the fifth transistor is in the on state, and the biasing current at the output end of the peak biasing circuit flows through the input end of the peak amplifier, so that the gain of the peak amplifier is increased.

[0009] In some embodiments, the output end of the linearization circuit is connected to the output end of the peak biasing circuit; wherein, when the power of the first signal is less than or equal to the power threshold, the fifth transistor and the second transistor are in the on state, and the biasing current at the output end of the peak biasing circuit flows through the second transistor, so that the gain of the peak amplifier is not established; and wherein, when the power of the first signal is greater than the power threshold, the fifth transistor is in the on state, the second transistor is in the off state, and the biasing current at the output end of the peak biasing circuit flows through the input end of the peak amplifier, so that the gain of the peak amplifier is increased.

[0010] In some embodiments, the first transistor to the fifth transistor are NPN type bipolar transistors.

[0011] In some embodiments, the carrier amplifier comprises one or more stages of amplifiers, and the carrier biasing circuit comprises one or more corresponding output ends; the peak amplifier comprises one or more stages of amplifiers, and the peak biasing circuit comprises one or more corresponding output ends.

[0012] In some embodiments, the input end of the linearization circuit is connected to the input end of the carrier amplifier, or is connected to the output end of the carrier amplifier.

[0013] In some embodiments, the carrier amplification path further comprises a carrier driver; an input terminal of the carrier driver is connected to the input terminal of the carrier amplification path to receive the first signal, and an output terminal of the carrier driver is connected to an input terminal of the carrier amplifier; the peak amplification path further comprises a peak driver; an input terminal of the peak driver is connected to the input terminal of the peak amplification path to receive the second signal, and an output terminal of the peak driver is connected to an input terminal of the peak amplifier; wherein the input terminal of the linearization circuit is connected to the input terminal of the carrier driver, or connected to the output terminal of the carrier driver.

[0014] In some embodiments, the carrier amplification path further comprises a first carrier matching network; the first carrier matching network is located between the output terminal of the carrier driver and the input terminal of the carrier amplifier; wherein the input terminal of the linearization circuit is connected to an internal node of the first carrier matching network.

[0015] In some embodiments, the first carrier matching network comprises: a first inductor, a first terminal of which is connected to a ground terminal, and a second terminal of which is connected to a third node; a fourth capacitor, a first terminal of which is connected to the third node, and a second terminal of which is connected to the output terminal of the carrier driver; a fifth capacitor, a first terminal of which is connected to the third node, and a second terminal of which is connected to the input terminal of the carrier amplifier; wherein the input terminal of the linearization circuit is connected to the third node.

[0016] In some embodiments, the carrier amplification path further comprises a second carrier matching network; the second carrier matching network is located between the input terminal of the carrier amplification path and the input terminal of the carrier driver; wherein the input terminal of the linearization circuit is connected to the input terminal of the carrier amplification path.

[0017] In some embodiments, the second carrier matching network comprises: a second inductor, a first terminal of which is connected to a ground terminal, and a second terminal of which is connected to a fourth node; a sixth capacitor, a first terminal of which is connected to the fourth node, and a second terminal of which is connected to the input terminal of the carrier amplification path; a seventh capacitor, a first terminal of which is connected to the fourth node, and a second terminal of which is connected to the input terminal of the carrier driver; wherein the input terminal of the linearization circuit is connected to the second terminal of the sixth capacitor.

[0018] In some embodiments, the carrier amplification path further comprises a carrier suppression circuit; the carrier suppression circuit comprises: a third inductor, a first terminal of which is connected to a ground terminal; an eighth capacitor, a first terminal of which is connected to a second terminal of the third inductor, and a second terminal of which is connected to the output terminal of the carrier amplification path.

[0019] In some embodiments, the radio frequency power amplifier further comprises an input circuit and an output circuit: an input end of the input circuit receives an input signal, a first output end is connected with an input end of the carrier amplification path, and a second output end is connected with an input end of the peak amplification path; the input circuit is configured to divide the input signal into a first signal and a second signal; a first input end of the output circuit is connected with an output end of the carrier amplification path, a second input end is connected with an output end of the peak amplification path, and an output end outputs an amplified signal of the input signal; and the output circuit is configured to combine the outputs of the carrier amplification path and the peak amplification path to output the amplified signal of the input signal.

[0020] In a second aspect, the embodiments of the present application provide an electronic device, which comprises the radio frequency power amplifier of any one of the first aspect.

[0021] In the embodiments of the present application, a linearization circuit is arranged between the carrier amplification path and the peak biasing circuit of the peak amplification path, and the linearization circuit is configured to make the gain of the peak amplifier not established when the power of the first signal is less than or equal to the power threshold, and make the gain of the peak amplifier increased when the power of the first signal is greater than the power threshold. In this way, the linearization circuit makes the gain of the peak amplifier of the peak amplification path established more quickly, thereby improving the amplitude modulation-amplitude modulation (AM-AM) curve of the radio frequency power amplifier, and improving the linearity of the radio frequency power amplifier without sacrificing the power added efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 FIG. 1 is one of structural schematic diagrams of the radio frequency power amplifier of the embodiments of the present application;

[0023] Figure 2 FIG. 4 is one of circuit structural schematic diagrams of the linearization circuit of the embodiments of the present application;

[0024] Figure 3 FIG. 5 is another circuit structural schematic diagram of the linearization circuit of the embodiments of the present application;

[0025] Figure 4 FIG. 6 is a circuit structural schematic diagram of the peak biasing circuit of the embodiments of the present application;

[0026] Figure 5 FIG. 7 is one of circuit structural schematic diagrams of the connection between the linearization circuit and the peak biasing circuit of the embodiments of the present application;

[0027] Figure 6 FIG. 8 is another circuit structural schematic diagram of the connection between the linearization circuit and the peak biasing circuit of the embodiments of the present application;

[0028] Figure 7Fig. 1 is a schematic diagram of a circuit structure of a peak amplifier including a multi-stage amplifier and a peak bias circuit including multiple output terminals according to an embodiment of the present application;

[0029] Figure 8 Fig. 2 is a schematic diagram of a circuit structure of a connection between a linearization circuit and a carrier amplification path according to an embodiment of the present application;

[0030] Figure 9 Fig. 3 is a schematic diagram of a circuit structure of a connection between a linearization circuit and a carrier amplification path according to another embodiment of the present application;

[0031] Figure 10 Fig. 4 is a schematic diagram of a circuit structure of a connection between a linearization circuit and a carrier amplification path according to still another embodiment of the present application;

[0032] Figure 11 Fig. 5 is a schematic diagram of a circuit structure of a carrier driver according to an embodiment of the present application;

[0033] Figure 12 Fig. 6 is a schematic diagram of a circuit structure of a first carrier matching network according to an embodiment of the present application;

[0034] Figure 13 Fig. 7 is a schematic diagram of a circuit structure of a second carrier matching network according to an embodiment of the present application;

[0035] Figure 14 Fig. 8 is a schematic diagram of a circuit structure of a carrier suppression circuit according to an embodiment of the present application;

[0036] Figure 15 Fig. 9 is a schematic diagram of a circuit structure of a radio frequency power amplifier according to an embodiment of the present application;

[0037] Figure 16 Fig. 10 is a comparison diagram of linearity optimization effects of a radio frequency power amplifier including a linearization circuit and a radio frequency power amplifier not including a linearization circuit according to an embodiment of the present application;

[0038] Figure 17 Fig. 11 is a simulation diagram for verifying linearity optimization effects of a radio frequency power amplifier including a linearization circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The present application will be further described by the following embodiments in conjunction with the accompanying drawings. It should be understood that the following embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0040] 5G communication has very high requirements for the linearity of radio frequency power amplifiers. For example, a doherty amplifier has high efficiency but low linearity. Due to the influence of impedance modulation of the doherty amplifier itself, for example, when the carrier amplifier in the carrier amplification path is working, the load impedance of the carrier amplifier is 6 ohms, but after the peak amplifier in the peak amplification path is turned on, the load impedance of the carrier amplifier will decrease to 3 ohms. With the decrease of the load impedance, the gain of the carrier amplifier will decrease, thereby causing the amplitude modulation to amplitude modulation curve of the doherty amplifier to collapse seriously, and causing the linearity to be poor.

[0041] In some embodiments, in order to improve the linearity of the doherty amplifier, it is necessary to turn on the peak amplifier of the peak amplification path in advance to fill in the amplitude modulation to amplitude modulation curve. Turning on the peak amplifier of the peak amplification path in advance sacrifices the power added efficiency (PAE) of the doherty amplifier. It is necessary to improve the linearity of the radio frequency power amplifier while taking into account the power added efficiency.

[0042] Figure 1 FIG. 1 is a structural schematic diagram of a radio frequency power amplifier according to an embodiment of the present application.

[0043] In a first aspect, an embodiment of the present application provides a radio frequency power amplifier, which refers to Figure 1The radio frequency power amplifier 10 comprises: a carrier amplification path comprising a carrier amplifier 102 and a carrier bias circuit 104 connected to an input end of the carrier amplifier 102, configured to perform first amplification on the received first signal 12a; a peak amplification path comprising a peak amplifier 202 and a peak bias circuit 204 connected to an input end of the peak amplifier 202, configured to perform second amplification on the received second signal 14a; and a linearization circuit 302, an input end I_302 of which is connected to the carrier amplification path, and an output end O_302 of which is connected to the peak bias circuit 204; wherein when the power of the first signal 12a is less than or equal to a power threshold, the bias current of the peak bias circuit 204 flows through the linearization circuit 302, so that the gain of the peak amplifier is not established; and wherein when the power of the first signal 12a is greater than the power threshold, the bias current of the peak bias circuit 204 flows through the input end of the peak amplifier 202, so that the gain of the peak amplifier 202 is improved. In the embodiment of the present application, the linearization circuit is arranged between the carrier amplification path and the peak bias circuit of the peak amplification path, and is configured to, when the power of the first signal is less than or equal to the power threshold, make the gain of the peak amplifier not established, and when the power of the first signal is greater than the power threshold, make the gain of the peak amplifier improved. In this way, the gain of the peak amplifier of the peak amplification path is established more quickly through the linearization circuit, so that the amplitude modulation to amplitude modulation curve of the radio frequency power amplifier is improved, and the linearity of the radio frequency power amplifier can be improved without sacrificing power added efficiency.

[0044] In some embodiments, the output end of the carrier bias circuit 104 is connected to the input end of the carrier amplifier 102, configured to make the carrier amplifier 102 operate in different bias modes. Exemplarily, the different bias modes can include class A, class B, class AB, class C or any other bias mode.

[0045] In some embodiments, the output end of the peak bias circuit 204 is connected to the input end of the peak amplifier 202, configured to make the peak amplifier 202 operate in different bias modes. Exemplarily, the different bias modes can include class A, class B, class AB, class C or any other bias mode.

[0046] In some embodiments, the carrier amplifier 102 and the peak amplifier 202 can operate in different bias modes. Exemplarily, the carrier amplifier 102 can be configured to operate in an AB class mode, and the peak amplifier 202 can be configured to operate in a B class mode.

[0047] Figure 2 One of the circuit structure schematic diagrams of the linearization circuit in the embodiment of the present application.

[0048] Reference Figure 2In some embodiments, the linearization circuit 302 comprises: a first resistor R1, a first end of which is connected to a first node ND1, and a second end of which is connected to a power supply end V CC ; a first capacitor C1, a first end of which is connected to the first node ND1, and a second end of which is connected to an input end I_302 of the linearization circuit; a first transistor Q1, a first end of which is connected to a ground end GND, and a second end and a control end of which are connected to the first node ND1; a second transistor Q2, a first end of which is connected to the ground end GND, a second end of which is connected to an output end O_302 of the linearization circuit, and a control end of which is connected to the first node ND1; wherein when the power of the first signal is less than or equal to a power threshold, the second transistor Q2 is in a conducting state, a bias current of the peak bias circuit flows through the second transistor Q2, so that the gain of the peak amplifier is not established; and wherein when the power of the first signal is greater than the power threshold, the second transistor Q2 is in a non-conducting state, the bias current of the peak bias circuit flows through the input end of the peak amplifier, so that the gain of the peak amplifier is improved.

[0049] In some embodiments, the power supply end V CC supplies power for the linearization circuit 302. The term "power supply end V CC " in this document is used to indicate a power supply end for each circuit / device / terminal / node, and the voltage provided by the power supply end V CC may provide a corresponding power supply voltage according to the needs of the specific circuit / device / terminal / node.

[0050] In some embodiments, the first resistor R1 is an adjustable resistor, and / or the first capacitor C1 is an adjustable capacitor. In this way, the resistance value of the first resistor R1 and / or the capacitance value of the first capacitor C1 can be set according to the specific situation of the gain establishment of the peak amplifier, so as to establish the appropriate conducting or non-conducting state of the second transistor Q2.

[0051] In some embodiments, the first transistor Q1 and the second transistor Q2 are NPN type bipolar transistors. For example, the collector of the first transistor Q1 is connected to the ground end GND, and the emitter and the base thereof are connected to the first node ND1; and the collector of the second transistor Q2 is connected to the ground end GND, the emitter thereof is connected to the output end O_302 of the linearization circuit, and the base thereof is connected to the first node ND1.

[0052] Figure 3 FIG. 2 is a second circuit structure diagram of the linearization circuit according to an embodiment of the present application.

[0053] Reference is made to Figure 3In some embodiments, the linearization circuit 302 further comprises: a second resistor R2, a first end of which is connected to the control end of the second transistor Q2, and a second end of which is connected to the first node ND1; and a second capacitor C2, a first end of which is connected to the first node ND1, and a second end of which is connected to the power supply end V CC .

[0054] In some embodiments, the second resistor R2 is an adjustable resistor, and / or the second capacitor C2 is an adjustable capacitor. In this way, the resistance value of the first resistor R1 and the second resistor R2, and / or the capacitance value of the first capacitor C1 and the second capacitor C2 can be set according to the specific situation established by the gain of the peak value amplifier, so as to establish a suitable on or off state of the second transistor Q2.

[0055] Figure 4 A circuit structure schematic diagram of the peak value bias circuit of the embodiments of the present application.

[0056] Reference Figure 4 In some embodiments, the peak value bias circuit 204 comprises: a current source CS1, a first end of which is connected to the ground end GND, and a second end of which is connected to the second node ND2; a third transistor Q3, a first end of which is connected to the ground end GND; a fourth transistor Q4, a first end and a control end of which are connected to the second end of the third transistor Q3, and a second end and a control end of which are connected to the second node ND2; a fifth transistor Q5, a second end of which is connected to the power supply end V CC , and a control end of which is connected to the second node ND2; a third resistor R3, a first end of which is connected to the output end O_204 of the peak value bias circuit, and a second end of which is connected to the first end of the fifth transistor Q5; and a third capacitor C3, a first end of which is connected to the ground end GND, and a second end of which is connected to the second node ND2.

[0057] In some embodiments, the third resistor R3 is an adjustable resistor, and / or the third capacitor C3 is an adjustable capacitor. In this way, the resistance value of the third resistor R3 and / or the capacitance value of the third capacitor C3 can be set according to the specific situation established by the gain of the peak value amplifier, so as to establish a suitable on or off state of the fifth transistor Q5.

[0058] In some embodiments, the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 are NPN type bipolar transistors. Illustratively, the collector of the third transistor Q3 is connected to the ground end GND, and the emitter and the base thereof are connected to the collector of the fourth transistor Q4; the emitter and the base of the fourth transistor Q4 are connected to the second node ND2; the base of the fifth transistor Q5 is connected to the second node ND2, the collector thereof is connected to the second end of the third resistor R3, and the emitter thereof is connected to the power supply end V CC .

[0059] Figure 5This is one of the schematic diagrams of the circuit structure connecting the linearization circuit and the peak bias circuit in an embodiment of this application.

[0060] refer to Figure 5 In some embodiments, the output of the linearization circuit (reference) Figure 5 The second terminal of the second transistor Q2 is connected to the second node ND2. When the power of the first signal is less than or equal to the power threshold, the second transistor Q2 is in the on state, the bias current of the current source CS1 flows through the second transistor Q2, and the fifth transistor Q5 is in the off state, so that the gain of the peak amplifier is not established. When the power of the first signal is greater than the power threshold, the second transistor Q2 is in the off state, the bias current of the current source CS1 flows through the control terminal of the fifth transistor Q5, the fifth transistor Q5 is in the on state, the bias current of the output terminal of the peak bias circuit flows through the input terminal of the peak amplifier, so that the gain of the peak amplifier is increased.

[0061] For example, at low input power, such as when the power of the first signal is less than or equal to the power threshold, the second transistor Q2 is in the on state. The bias current of the current source CS1 flows through the second transistor Q2 but is not directed to the base of the fifth transistor Q5. This causes the gain of the bias current output from the output terminal O_204 of the peak bias circuit to the peak amplifier to not be established, thus preventing the peak amplifier from gaining. When the input power increases, such as when the power of the first signal is greater than the power threshold, the first capacitor C1 couples the power of the carrier amplification path to the linearization circuit through the input terminal I_302 of the linearization circuit. With the rectification effect of the first transistor Q1 and the first resistor R1, the base voltage of the second transistor Q2 decreases, causing the second transistor Q2 to be gradually turned off. This process directs the bias current to the base of the fifth transistor Q5. The base voltage of the fifth transistor Q5 rises rapidly, causing the gain of the bias current output from the output terminal O_204 of the peak bias circuit to the peak amplifier to be established, thereby improving the peak amplifier gain.

[0062] Figure 6 This is a second schematic diagram of the circuit structure connecting the linearization circuit and the peak bias circuit in an embodiment of this application.

[0063] refer to Figure 6 In some embodiments, the output of the linearization circuit (reference) Figure 6the second end of the second transistor Q2) is connected to the output end O_204 of the peak bias circuit; wherein when the power of the first signal is less than or equal to the power threshold, the fifth transistor Q5 and the second transistor Q2 are in the on state, the bias current of the output end of the peak bias circuit flows through the second transistor Q2, so that the gain of the peak amplifier is not established; wherein when the power of the first signal is greater than the power threshold, the fifth transistor Q5 is in the on state, the second transistor Q2 is in the off state, and the bias current of the output end of the peak bias circuit flows through the input end of the peak amplifier, so that the gain of the peak amplifier is improved.

[0064] Exemplarily, at low input power, for example, when the power of the first signal is less than or equal to the power threshold, the fifth transistor Q5 is in the on state, and the second transistor Q2 is in the on state, the bias current of the output end O_204 of the peak bias circuit flows through the second transistor Q2 and does not flow to the input end of the peak amplifier, so that the gain of the peak amplifier is not established; when the input power increases, for example, when the power of the first signal is greater than the power threshold, the fifth transistor Q5 is in the on state, and the first capacitor C1 couples the power of the carrier amplification path into the linearization circuit through the input end I_302 of the linearization circuit, with the rectification effect of the first transistor Q1 and the first resistor R1, the base voltage of the second transistor Q2 decreases, causing the second transistor Q2 to be gradually turned off, which directs the bias current to the input end of the peak amplifier, and the output end O_204 of the peak bias circuit outputs the bias current to the peak amplifier, so that the gain of the peak amplifier is established and the gain of the peak amplifier is improved.

[0065] In some embodiments, Figure 5 or Figure 6 The linearization circuit shown in Figure 3 The linearization circuit shown in

[0066] Figure 7 The circuit structure diagram of the peak amplifier including a multi-stage amplifier and the peak bias circuit including multiple output ends of the embodiments of the present application.

[0067] Referring to Figure 7 In some embodiments, the carrier amplifier includes one or more stages of amplifiers, and the carrier bias circuit includes one or more corresponding output ends; the peak amplifier includes one or more stages of amplifiers, and the peak bias circuit includes one or more corresponding output ends.

[0068] For example, the peak amplifier 202 includes one or more stages of amplifiers, the multi-stage amplifiers including a first stage amplifier Q6_0, ..., an Nth stage amplifier Q6_N-1, where N is a positive integer; the peak bias circuit 204 includes one or more output terminals corresponding to the multi-stage amplifiers of the peak amplifier 202, the multiple output terminals including a first output terminal O_204_0, ..., an Nth output terminal O_204_N-1, where N is a positive integer; in the direction toward the peak bias circuit 204, the first output terminal O_204_0, ..., the Nth output terminal O_204_N-1... 4_N-1 is connected to the collector of the fifth transistor Q5 through corresponding resistors R3_0, ..., R3_N-1; in the direction towards the peak amplifier 202, the first output terminal O_204_0, ..., the Nth output terminal O_204_N-1 are connected to the input terminals of the corresponding first-stage amplifier Q6_0, ..., the Nth-stage amplifier Q6_N-1; the collectors of the first-stage amplifier Q6_0, ..., the Nth-stage amplifier Q6_N-1 are connected to the ground terminal GND, and the emitters are connected to the output terminal of the peak amplifier 202. The first terminal of inductor L_202 is connected to the output terminal of the peak amplifier 202, and the second terminal is connected to the power supply terminal V. CC Power supply terminal V CC Used to power peak amplifier 202.

[0069] In this embodiment, the circuit structure of the carrier amplifier 102 can be understood with reference to the circuit structure of the peak amplifier 202, and the circuit structure of the carrier bias circuit 104 can be understood with reference to the circuit structure of the peak bias circuit 204. Furthermore, the case where the carrier amplifier 102 includes a multi-stage amplifier and the carrier bias circuit 104 includes one or more output terminals corresponding to one or more stages of the carrier amplifier 102 can be understood with reference to the case where the peak amplifier 202 includes one or more stages of amplifier and the peak bias circuit 204 includes one or more corresponding output terminals, and will not be described again here.

[0070] refer to Figure 1 In some embodiments, reference is made to Figure 1 In Figure (a), the input terminal I_302 of the linearization circuit 302 is connected to the input terminal of the carrier amplifier 102, or, refer to... Figure 1 In Figure (b), the input terminal I_302 of the linearization circuit 302 is connected to the output terminal of the carrier amplifier 102. In this embodiment, the selection of the input terminal I_302 of the linearization circuit 302 can be based on its ability to couple the power of the carrier amplification path to the linearization circuit 302. In this embodiment, the selection of the specific node connecting the input terminal I_302 of the linearization circuit 302 to the carrier amplification path can be further referenced... Figures 8 to 10 Related descriptions.

[0071] Figure 8 Fig. 1 is a schematic diagram of a circuit structure connected between a linearization circuit and a carrier amplification path according to an embodiment of the present application. Figure 9 Fig. 2 is a schematic diagram of a circuit structure connected between a linearization circuit and a carrier amplification path according to another embodiment of the present application. Figure 10 Fig. 3 is a schematic diagram of a circuit structure connected between a linearization circuit and a carrier amplification path according to another embodiment of the present application.

[0072] In combination with Figure 1 Fig. 1(a), reference is made to Figure 8 and Figure 9 In some embodiments, the carrier amplification path further comprises a carrier driver 106, an input terminal of the carrier driver 106 is connected to an input terminal of the carrier amplification path to receive the first signal 12a, and an output terminal of the carrier driver 106 is connected to an input terminal of the carrier amplifier 102; the peak amplification path further comprises a peak driver 206, an input terminal of the peak driver 206 is connected to an input terminal of the peak amplification path to receive the second signal 14a, and an output terminal of the peak driver 206 is connected to an input terminal of the peak amplifier; wherein the input terminal I_302 of the linearization circuit is connected to an input terminal of the carrier driver 106 (reference is made to Figure 9 ), or an output terminal of the carrier driver 106 (reference is made to Figure 8 ).

[0073] Figure 11 Fig. 4 is a schematic diagram of a circuit structure of a carrier driver according to an embodiment of the present application. Reference is made to Figure 8 and Figure 11 , or reference is made to Figure 9 and Figure 11 In some embodiments, the carrier driver 106 comprises an NPN bipolar transistor Q7 and an inductor L_106; a collector of the transistor Q7 is connected to a ground terminal GND, an emitter of the transistor Q7 is connected to an output terminal of the carrier driver 106, and a base of the transistor Q7 is connected to an input terminal of the carrier driver 106; a first terminal of the inductor L_106 is connected to the output terminal of the carrier driver 106, and a second terminal of the inductor L_106 is connected to a power supply terminal V CC ; the power supply terminal V CC may supply power to the carrier driver 106 through the inductor L_106. In some embodiments, the circuit structure of the peak driver 206 can be understood by reference to the circuit structure of the carrier driver 106, which will not be described herein again.

[0074] In some embodiments, the carrier amplification path further comprises a bias circuit 108 connected to the input terminal of the carrier driver 106, and the peak amplification path further comprises a bias circuit 208 connected to the input terminal of the peak driver 206. The circuit structure of the bias circuit 108 or the bias circuit 208 can be understood by reference to the circuit structure of the peak bias circuit 204 shown in Figure 4 , which will not be described herein again.

[0075] Reference is made to Figure 8 In some embodiments, the carrier amplification path further comprises a first carrier matching network 110; the first carrier matching network 110 is located between the output end of the carrier driver 106 and the input end of the carrier amplifier 102; wherein the input end I_302 of the linearization circuit is connected to an internal node of the first carrier matching network 110. In this way, the first carrier matching network 110 provides impedance matching between the carrier driver 106 and the carrier amplifier 102, and the power of the carrier amplification path can also be coupled to the linearization circuit 302 through the internal node of the first carrier matching network 110.

[0076] Figure 12 The circuit structure diagram of the first carrier matching network of the embodiments of the present application is shown in FIG. 2. Reference is made to Figure 8 and Figure 12 In some embodiments, the first carrier matching network 110 comprises: a first inductor L1, a first end of which is connected to a ground end GND, and a second end of which is connected to a third node ND3; a fourth capacitor C4, a first end of which is connected to the third node ND3, and a second end of which is connected to the output end of the carrier driver 106; a fifth capacitor C5, a first end of which is connected to the third node ND3, and a second end of which is connected to the input end of the carrier amplifier 102; wherein the input end I_302 of the linearization circuit is connected to the third node ND3. In this way, the third node ND3 can be used to couple the power of the carrier amplification path to the linearization circuit.

[0077] Reference is made to Figure 8 In some embodiments, the peak amplification path further comprises a first peak matching network 210; the first peak matching network 210 is located between the output end of the peak driver 206 and the input end of the peak amplifier 202. In some embodiments, the circuit structure of the first peak matching network 210 can be understood with reference to the circuit structure of the first carrier matching network 110 shown in FIG. 2, which will not be described herein again. Figure 12

[0078] Reference is made to Figure 9 In some embodiments, the carrier amplification path further comprises a second carrier matching network 112; the second carrier matching network 112 is located between the input end of the carrier amplification path and the input end of the carrier driver 106; wherein the input end I_302 of the linearization circuit is connected to the input end of the carrier amplification path. In this way, the second carrier matching network 112 provides impedance matching between the carrier amplification path and the carrier driver 106.

[0079] Figure 13 The circuit structure diagram of the second carrier matching network of the embodiments of the present application is shown in FIG. 3. Reference is made to Figure 9 and Figure 13 ​In some embodiments, the second carrier matching network 112 includes: a second inductor L2, with its first end connected to ground GND and its second end connected to the fourth node ND4; and a sixth capacitor C6, with its first end connected to the fourth node ND4 and its second end connected to the input of the carrier amplification path. Figure 13 The seventh node ND7 (shown) and the seventh capacitor C7 have their first end connected to the fourth node ND4 and their second end connected to the input of the carrier driver 106; the input I_302 of the linearization circuit is connected to the second end of the sixth capacitor C6. Thus, the seventh node ND7 can be used to couple the power of the carrier amplification path into the linearization circuit.

[0080] refer to Figure 9 In some embodiments, the peak amplification path further includes a second peak matching network 212; the second peak matching network 212 is located between the input of the peak amplification path and the output of the peak driver 206. In some embodiments, the circuit structure of the second peak matching network 212 can be referred to Figure 13 The circuit structure of the second carrier matching network 112 shown is explained here, and will not be repeated here.

[0081] Figure 14 This is a schematic diagram of the carrier suppression circuit according to an embodiment of this application. (Refer to the reference...) Figure 10 and Figure 13 In some embodiments, the carrier amplification path further includes a carrier suppression circuit 114; the carrier suppression circuit 114 includes: a third inductor L3, with its first end connected to the ground terminal GND; and an eighth capacitor C8, with its first end connected to the second end of the third inductor L3 and its second end connected to the output terminal of the carrier amplification path (e.g., ...). Figure 14 The fifth node ND5 is shown.

[0082] refer to Figure 10 In some embodiments, the peak amplification path further includes a peak suppression circuit 214; the peak suppression circuit 214 is connected to the output of the peak amplifier 202. In some embodiments, the circuit structure of the peak suppression circuit 214 can be referred to Figure 14 The circuit structure of the carrier suppression circuit 114 shown is explained here, and will not be repeated here.

[0083] Figure 15 This is a schematic diagram of the circuit structure of the radio frequency power amplifier according to an embodiment of this application.

[0084] refer to Figure 15In some embodiments, the radio frequency power amplifier further comprises an input circuit 402 and an output circuit 502: an input end of the input circuit 402 receives an input signal RFIN, a first output end is connected to an input end of the carrier amplification path, and a second output end is connected to an input end of the peak amplification path; the input circuit 402 is configured to divide the input signal RFIN into a first signal 12a and a second signal 14a; a first input end of the output circuit 502 is connected to an output end of the carrier amplification path, a second input end is connected to an output end of the peak amplification path, and an output end outputs an amplified signal RFOUT of the input signal; and the output circuit 502 is configured to combine the outputs of the carrier amplification path and the peak amplification path to output the amplified signal RFOUT of the input signal RFIN.

[0085] In some embodiments, the input circuit 402 comprises a first transformer 404, a pre-driver 406, a bias circuit 408, and a matching circuit 410. The matching circuit 410 is located between the input end of the input circuit and the input end of the driver 406, and is configured to provide impedance matching between the input end of the input circuit and the driver 406. The matching circuit 410 can be an LC matching circuit composed of inductance and capacitance. The input end of the pre-driver 406 is connected to the matching circuit 410, and the output end is connected to the input end of the first transformer 404, so that the input signal can be partially amplified by the pre-driver 406 before being divided into the first signal 12a and the second signal 14a. The circuit structure of the pre-driver 406 can be understood with reference to the circuit structure of the carrier driver 106 shown in Figure 11 The bias circuit 408 is connected to the input end of the pre-driver 406, and is configured to operate the pre-driver 406 in different bias modes. The different bias modes can include class A, class B, class AB, class C, or any other bias mode. The circuit structure of the bias circuit 408 can be understood with reference to the circuit structure of the peak bias circuit 204 shown in Figure 4 The first transformer 404 is connected to the output end of the pre-driver 406, the first output end is connected to the input end of the carrier amplification path, and the second output end is connected to the input end of the peak amplification path, so as to divide the input signal into the first signal 12a and the second signal 14a, and output them to the carrier amplification path and the peak amplification path, respectively.

[0086] In some embodiments, the output circuit 502 comprises a second transformer 504 and a matching circuit 506. The first input end of the second transformer 504 is connected to the output end of the carrier amplification path, the second input end is connected to the output end of the peak amplification path, and the output end is connected to the combining node ND6 for combining the amplified signal 12b of the first signal 12a output by the carrier amplification path and the amplified signal 14b of the second signal 14a output by the peak amplification path to the combining node ND6. The matching circuit 506 is located between the combining node ND6 and the output end of the output circuit, and is used to raise the impedance of the combining node ND6 to the transmission impedance, i.e., to convert to a 50-ohm output load. Exemplarily, the impedance of the load connected to the output end of the output circuit is 50 ohms. The matching circuit 506 can be an LC matching circuit composed of inductance and capacitance.

[0087] Reference Figure 5 , Figure 6 and Figure 15 In some embodiments, the input end I_302 of the linearization circuit is connected to the third node ND3, the seventh node ND7 or the fifth node ND5. In some embodiments, the output end O_302 of the linearization circuit (the second end of the second transistor Q2) Figure 5 , Figure 6 is connected to the second node ND2 inside the peak biasing circuit 204 or the output end O_204 of the peak biasing circuit 204.

[0088] Figure 16 The following is a comparison diagram of the linearity optimization effect of the radio frequency power amplifier comprising the linearization circuit and the radio frequency power amplifier not comprising the linearization circuit according to the embodiments of the present application. It should be noted that Figure 16 the linearization circuit and the peak biasing circuit shown in the diagram can be understood as Figure 5 the circuit structure shown in the diagram. Figure 16 The peak biasing circuit of the comparison radio frequency power amplifier not comprising the linearization circuit shown in the diagram. Figure 16 In the diagram, curve 1 schematically shows the base voltage-output power relationship curve of the fifth transistor of the peak biasing circuit of the comparison radio frequency power amplifier not comprising the linearization circuit; curve 1 serves as the reference curve of curve 2, and the peak biasing circuit of the comparison radio frequency power amplifier not comprising the linearization circuit corresponding to curve 1 can refer to Figure 4 the circuit structure shown in the diagram. Figure 16 In the diagram, curve 2 schematically shows the base voltage-output power relationship curve of the fifth transistor Q5 of the peak biasing circuit of the radio frequency power amplifier comprising the linearization circuit provided by the embodiments of the present application. Figure 16 In the diagram, curve 3 schematically shows the base voltage-output power relationship curve of the second transistor Q2 of the linearization circuit provided by the embodiments of the present application.

[0089] ReferenceFigure 16 At low input power, bias current I b flows into the second transistor Q2, at high input power, bias current I b flows into the base of the fifth transistor Q5 instead of the second transistor Q2. Referring to Figure 16 , the radio frequency power amplifier provided by the application embodiment includes a linearization circuit, which can make the gain of the peak amplifier of the peak amplification path be established more quickly through the linearization circuit, thereby improving the amplitude modulation to amplitude modulation curve of the radio frequency power amplifier, and improving the linearity of the radio frequency power amplifier without sacrificing power added efficiency.

[0090] Figure 17 The simulation schematic diagram is used to verify the linearity optimization effect of the radio frequency power amplifier provided by the application embodiment. Figure 17 Curve 1 in the middle of the figure shows the curve corresponding to the comparative radio frequency power amplifier without the linearization circuit. Figure 17 Curve 2 in the middle of the figure shows the curve corresponding to the radio frequency power amplifier provided by the application embodiment including the linearization circuit.

[0091] To verify the effectiveness of the linearity optimization effect of the simulation linearization circuit, two core indicators are used: one is the gain improvement effect of the peak amplifier under high input power, and the other is the 1 decibel compression point (P1dB) extrapolation result in the simulation environment. The verification data corresponding to the two core indicators are shown in Figure 17 (a) of the figure and Figure 17 (c) of the figure.

[0092] For the low frequency band shown in Figure 17 (a) of the figure, when the linearization circuit is not applied, the P1dB extrapolation value is 37.1 dBm, as shown by curve 1; after the linearization circuit is applied, the P1dB is significantly improved to 37.9 dBm, as shown by curve 2, and the linear working range is effectively expanded. For Figure 17 (b) of the figure is the power added efficiency-output power relationship curve corresponding to Figure 17 (a) of the figure, the power added efficiency shown by curve 1 and curve 2 is basically the same, and it can be seen that the radio frequency power amplifier provided by the application embodiment including the linearization circuit does not sacrifice the power added efficiency.

[0093] For the high frequency band shown in Figure 17 (c) of the figure, when the linearization circuit is not applied, the P1dB is 38.2 dBm, as shown by curve 1; after the linearization circuit is applied, the P1dB is further improved to 38.9 dBm, as shown by curve 2, and the linearity optimization effect is consistent with the low frequency band. For Figure 17 (d) of the figure is the power added efficiency-output power relationship curve corresponding toFigure 1 The power-added efficiency-output power curve corresponding to the (c) figure in the figure is shown in the figure, the power-added efficiency shown by the curve 1 and the curve 2 is basically equivalent, and it can be seen that the radio frequency power amplifier including the linearization circuit in the embodiment of the present application does not sacrifice the power-added efficiency.

[0094] In a second aspect, the embodiment of the present application provides an electronic device, which comprises the radio frequency power amplifier of any one of the first aspect.

[0095] Reference ​ The radio frequency power amplifier 10 comprises: a carrier amplification path including a carrier amplifier 102 and a carrier bias circuit 104 connected to the input end of the carrier amplifier 102, used for performing first amplification on the received first signal 12a; a peak amplification path including a peak amplifier 202 and a peak bias circuit 204 connected to the input end of the peak amplifier 202, used for performing second amplification on the received second signal 14a; a linearization circuit 302, the input end I_302 of which is connected to the carrier amplification path, and the output end O_302 of which is connected to the peak bias circuit 204; wherein when the power of the first signal 12a is less than or equal to the power threshold, the bias current of the peak bias circuit 204 flows through the linearization circuit 302, so that the gain of the peak amplifier is not established; wherein when the power of the first signal 12a is greater than the power threshold, the bias current of the peak bias circuit 204 flows through the input end of the peak amplifier 202, so that the gain of the peak amplifier 202 is improved.

[0096] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. The above described device embodiments are only schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, direct coupling or communication connection between the components can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0097] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units; they can be located in one place, or distributed on multiple network units; and some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0098] In addition, each of the functional units in the embodiments of the present application can be integrated in one processing unit, each unit can be separately implemented as a single unit, or two or more units can be integrated in one unit; the integrated unit can be implemented in the form of hardware, or in the form of hardware plus software function unit.

[0099] It should be understood that every technical feature mentioned in the specification refers to a specific feature of the embodiments and is included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that the size of the sequence number of each process in various embodiments of the present application does not mean the execution order, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The sequence number of the above embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0100] It should be noted that in this paper, the term "include", "contain" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the sentence "including a" does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0101] The above is only the implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A radio frequency power amplifier, characterized in that, include: The carrier amplification path includes a carrier amplifier and a carrier bias circuit connected to the input terminal of the carrier amplifier, for amplifying the received first signal. The peak amplification path includes a peak amplifier and a peak bias circuit connected to the input terminal of the peak amplifier, for amplifying the received second signal in a second way; The linearization circuit has its input terminal connected to the carrier amplification path and its output terminal connected to the peak bias circuit. Wherein, when the power of the first signal is less than or equal to the power threshold, the bias current of the peak bias circuit passes through the linearization circuit, causing the gain of the peak amplifier not to be established; Wherein, when the power of the first signal is greater than the power threshold, the bias current of the peak bias circuit flows through the input terminal of the peak amplifier, thereby increasing the gain of the peak amplifier; The linearization circuit includes: The first resistor has its first end connected to the first node and its second end connected to the power supply. A first capacitor, with its first end connected to the first node and its second end connected to the input of the linearization circuit; The first transistor has a first terminal connected to the ground terminal, and a second terminal and a control terminal connected to the first node; The second transistor has a first terminal connected to the ground terminal, a second terminal connected to the output terminal of the linearization circuit, and a control terminal connected to the first node. When the power of the first signal is less than or equal to the power threshold, the second transistor is in the on state, and the bias current of the peak bias circuit flows through the second transistor, so that the gain of the peak amplifier is not established. When the power of the first signal is greater than the power threshold, the second transistor is in the off state, and the bias current of the peak bias circuit flows through the input terminal of the peak amplifier, thereby increasing the gain of the peak amplifier.

2. The radio frequency power amplifier according to claim 1, characterized in that, The linearization circuit further includes: The second resistor has its first end connected to the control terminal of the second transistor and its second end connected to the first node. The second capacitor has its first end connected to the first node and its second end connected to the power supply.

3. The radio frequency power amplifier according to claim 1, characterized in that, The peak bias circuit includes: The current source has its first end connected to the ground terminal and its second end connected to the second node. The third transistor has its first terminal connected to the ground terminal; The fourth transistor has its first terminal connected to the second terminal and the control terminal of the third transistor, and the second terminal and the control terminal are connected to the second node; The fifth transistor has its second terminal connected to the power supply terminal and its control terminal connected to the second node. The third resistor has its first end connected to the output terminal of the peak bias circuit and its second end connected to the first terminal of the fifth transistor. The third capacitor has its first end connected to the ground terminal and its second end connected to the second node.

4. The radio frequency power amplifier according to claim 3, characterized in that, The output of the linearization circuit is connected to the second node; When the power of the first signal is less than or equal to the power threshold, the second transistor is in the on state, the bias current of the current source flows through the second transistor, and the fifth transistor is in the off state, so that the gain of the peak amplifier is not established. Specifically, when the power of the first signal is greater than the power threshold, the second transistor is in the off state, the bias current of the current source flows through the control terminal of the fifth transistor, the fifth transistor is in the on state, and the bias current at the output terminal of the peak bias circuit flows through the input terminal of the peak amplifier, thereby increasing the gain of the peak amplifier.

5. The radio frequency power amplifier according to claim 3, characterized in that, The output of the linearization circuit is connected to the output of the peak bias circuit. When the power of the first signal is less than or equal to the power threshold, the fifth transistor and the second transistor are in the on state, and the bias current at the output of the peak bias circuit flows through the second transistor, so that the gain of the peak amplifier is not established. Specifically, when the power of the first signal is greater than the power threshold, the fifth transistor is in the on state, the second transistor is in the off state, and the bias current at the output of the peak bias circuit flows through the input of the peak amplifier, thereby increasing the gain of the peak amplifier.

6. The radio frequency power amplifier according to claim 3, characterized in that, The first to the fifth transistors are NPN bipolar transistors.

7. The radio frequency power amplifier according to claim 1, characterized in that, The carrier amplifier includes one or more stages of amplifier, and the carrier bias circuit includes one or more corresponding output terminals; The peak amplifier includes one or more stages of amplifiers, and the peak bias circuit includes one or more corresponding output terminals.

8. The radio frequency power amplifier according to claim 1, characterized in that, The input terminal of the linearization circuit is connected to the input terminal of the carrier amplifier, or to the output terminal of the carrier amplifier.

9. The radio frequency power amplifier according to claim 8, characterized in that, The carrier amplification path further includes a carrier driver; the input terminal of the carrier driver is connected to the input terminal of the carrier amplification path to receive the first signal, and the output terminal is connected to the input terminal of the carrier amplifier. The peak amplification path further includes a peak driver; the input terminal of the peak driver is connected to the input terminal of the peak amplification path to receive the second signal, and the output terminal is connected to the input terminal of the peak amplifier. The input terminal of the linearization circuit is connected to the input terminal of the carrier driver, or to the output terminal of the carrier driver.

10. The radio frequency power amplifier according to claim 9, characterized in that, The carrier amplification path also includes a first carrier matching network; The first carrier matching network is located between the output of the carrier driver and the input of the carrier amplifier; The input of the linearization circuit is connected to an internal node of the first carrier matching network.

11. The radio frequency power amplifier according to claim 10, characterized in that, The first carrier matching network includes: The first inductor has its first end connected to the ground terminal and its second end connected to the third node. The fourth capacitor has its first end connected to the third node and its second end connected to the output of the carrier driver. The fifth capacitor has its first end connected to the third node and its second end connected to the input terminal of the carrier amplifier. The input terminal of the linearization circuit is connected to the third node.

12. The radio frequency power amplifier according to claim 9, characterized in that, The carrier amplification path also includes a second carrier matching network; The second carrier matching network is located between the input of the carrier amplification path and the input of the carrier driver; The input terminal of the linearization circuit is connected to the input terminal of the carrier amplification path.

13. The radio frequency power amplifier according to claim 12, characterized in that, The second carrier matching network includes: The second inductor has its first end connected to the ground terminal and its second end connected to the fourth node. The sixth capacitor has its first end connected to the fourth node and its second end connected to the input of the carrier amplification path. The seventh capacitor has its first end connected to the fourth node and its second end connected to the input terminal of the carrier driver. The input terminal of the linearization circuit is connected to the second terminal of the sixth capacitor.

14. The radio frequency power amplifier according to claim 9, characterized in that, The carrier amplification path also includes a carrier suppression circuit; The carrier suppression circuit includes: The third inductor has its first end connected to the ground terminal; The eighth capacitor has its first end connected to the second end of the third inductor, and its second end connected to the output of the carrier amplification path.

15. The radio frequency power amplifier according to claim 1, characterized in that, The radio frequency power amplifier also includes input circuitry and output circuitry: The input circuit receives an input signal at its input terminal, its first output terminal is connected to the input terminal of the carrier amplification path, and its second output terminal is connected to the input terminal of the peak amplification path; the input circuit is used to divide the input signal into a first signal and a second signal. The first input terminal of the output circuit is connected to the output terminal of the carrier amplification path, the second input terminal is connected to the output terminal of the peak amplification path, and the output terminal outputs the amplified signal of the input signal; the output circuit is used to combine the outputs of the carrier amplification path and the peak amplification path to output the amplified signal of the input signal.

16. An electronic device, characterized in that, The electronic device includes the radio frequency power amplifier according to any one of claims 1 to 15.

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