Low power timer circuit and chip

Abstract

The application belongs to the technical field of low-power consumption circuit, and particularly relates to a low-power consumption timer circuit and chip. The low-power consumption timer circuit comprises a preset value circuit, an asynchronous timer implementation circuit and an indication signal judgment circuit. The low-power consumption timer circuit realizes asynchronous control of the timer. When the second output end of the current stage count edge flip-flop occurs rising edge flip or falling edge flip, the corresponding next stage count edge flip-flop starts to work, so that the working power consumption is greatly reduced. The low-power consumption timer circuit adopts a simple preset value circuit, compared with the prior art, the use of n half adders is reduced, only a few simple gates are used to judge whether the indication signal temporary overvoltage is reached, the overall circuit is greatly reduced, and the cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of low-power circuit technology, specifically relating to a low-power timer circuit and chip. Background Technology

[0002] Timer circuits are widely used in chips such as MCUs and SOCs. Their main function is to set a fixed time interval through a program or hardware. This time interval is used to trigger or generate specific behavioral signals to complete a predetermined operation.

[0003] like Figure 1 The diagram shows a prior art synchronous design timer circuit with preset value function. In the synchronous design, the timing of all timing circuit modules is controlled by a unified overall clock. The combinational logic modules between the timing modules start working after the arrival of a valid clock edge and complete their work before the arrival of the next clock edge. During the operation, the clock of each register will jump, resulting in high power consumption. The use of 8 half-adders makes the entire circuit very complex and increases the cost. Summary of the Invention

[0004] The technical problem to be solved by this invention is that, on the one hand, the power consumption of the synchronous timer circuit is high, and on the other hand, the circuit for implementing the preset value function with 8 half-adders is very complex.

[0005] To address the aforementioned problems, this invention provides a low-power timer circuit, comprising a preset value circuit, an asynchronous timer implementation circuit, and an indicator signal judgment circuit. The preset value circuit is connected to the set and reset terminals of each counting edge flip-flop of the asynchronous timer implementation circuit, and the first output terminal of each counting edge flip-flop of the asynchronous timer implementation circuit is connected to the n input terminals of the indicator signal judgment circuit.

[0006] The preset value circuit sets each counting edge trigger according to the preset value;

[0007] The asynchronous timer implementation circuit enables each counting edge trigger to simultaneously output a high or low level signal, and the indicator signal judgment circuit outputs a timing indicator signal.

[0008] Optionally, the asynchronous timer implementation circuit includes a series structure of first counting edge triggers to nth counting edge triggers, wherein the first input terminals of the first counting edge triggers to nth counting edge triggers are connected to the second input terminal of the next counting edge trigger, the trigger signal terminal of the first counting edge trigger is the timer clock TCLK, and the second input terminals of the second counting edge triggers to nth counting edge triggers are connected to the second output terminal of the previous counting edge trigger. When the second output terminal of the previous stage counting edge trigger flips on a rising edge or a falling edge, the corresponding next stage counting edge trigger starts to work.

[0009] Optionally, the first counting edge trigger to the nth counting edge trigger are rising edge triggered D flip-flops, or the first counting edge trigger to the nth counting edge trigger are falling edge triggered D flip-flops.

[0010] Optionally, the preset value circuit includes RST_CNT first logic circuit to RST_CNT nth logic circuit, and CLR_CNT first logic circuit to CLR_CNT nth logic circuit, wherein the output terminals of RST_CNT first logic circuit to RST_CNT nth logic circuit are respectively connected to the set terminals of the first counting edge flip-flops to the nth counting edge flip-flops, and the output terminals of CLR_CNT first logic circuit to CLR_CNT nth logic circuit are respectively connected to the reset terminals of the first counting edge flip-flops to the nth counting edge flip-flops. The RST_CNT first logic circuit to RST_CNT nth logic circuit includes SEL first port to SEL nth port, TDATA first port to TDATA nth port, first AND gate to nth AND gate, and CLR_CNT first logic circuit to CLR_CNT nth logic circuit includes SEL first port to SEL nth port, TDATA first port to TDATA nth port, first AND gate to nth AND gate, and first NOT gate to nth NOT gate.

[0011] Optionally, the indicator signal determination circuit specifically includes: a first AND gate, a second AND gate, and a third AND gate, wherein the first AND gate is connected to the first output terminal of the first counting edge trigger to the n / 2th counting edge trigger, the second AND gate is connected to the first output terminal of the n / 2th counting edge trigger to the nth counting edge trigger, the input terminal of the third AND gate is connected to the output terminals of the first AND gate and the second AND gate, and the output terminal of the third AND gate is connected to the indicator signal output terminal.

[0012] Optional, including:

[0013] The clock of the first counting edge trigger of the asynchronous timer implementation circuit is the timer clock TCLK, and the clock of the second counting edge trigger to the nth counting edge trigger is the second output of the previous stage counting edge trigger. When the second output of the previous stage counting edge trigger flips on a rising edge or a falling edge, the corresponding next stage counting edge trigger starts to work.

[0014] Optional, including:

[0015] The preset value circuit is connected to the set and reset terminals of each counting edge trigger of the asynchronous timer implementation circuit. The high and low levels of the first set terminal to the nth set terminal are set according to the value of the TDATA port when SEL is the first preset value, and the nth set terminal is set when TDATA[n] is the second preset value. The high and low levels of the first clear terminal to the nth clear terminal are set according to the value of the TDATA port when SEL is the first preset value, and the nth clear terminal is cleared when TDATA[n] is the third preset value.

[0016] The present invention also provides a chip having the above-described low-power timer circuit.

[0017] In summary, the low-power timer circuit described in this application has the following advantages:

[0018] 1. The low-power timer circuit of the present invention realizes asynchronous control of the timer. When the second output terminal of the current stage counting edge flip-flop flips on a rising edge or a falling edge, the corresponding subsequent stage counting edge flip-flop starts to work, thereby greatly reducing the power consumption.

[0019] 2. The low-power timer circuit of the present invention adopts a simple preset value circuit, which reduces the use of n half-adders compared with the prior art. It only uses a few simple gates to determine whether the indicator signal has reached a temporary overvoltage, thus greatly reducing the overall circuit and lowering the cost.

[0020] 3. The low-power timer circuit described in this invention is implemented entirely using digital circuit design, and can be widely used in multiple fields such as integrated circuit design or system-on-a-chip. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1It is a synchronous timer circuit with preset value function in the existing technology;

[0023] Figure 2 This is a schematic diagram of an asynchronous low-power timer circuit without preset value function provided by an embodiment of the present invention;

[0024] Figure 3 This invention provides an indicator signal judgment circuit for an asynchronous low-power timer circuit without preset value function.

[0025] Figure 4 This is a diagram of the pulse signal at the first output terminal of the counting edge trigger within one counting cycle of a low-power timer circuit without preset value function provided by an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of a circuit structure for connecting a preset value circuit and a counting edge trigger according to an embodiment of the present invention;

[0027] Figure 6 This is a schematic diagram of an asynchronous low-power timer circuit with preset value function provided by an embodiment of the present invention;

[0028] Figure 7 This invention provides an asynchronous timer implementation circuit for a low-power timer circuit with preset value function, as provided in an embodiment of the invention.

[0029] Figure 8 This invention provides an indicator signal judgment circuit for an asynchronous low-power timer circuit with preset value function. Detailed Implementation

[0030] The asynchronous design and preset value method of the present invention will be further described in detail below with reference to two embodiments. The invention is not limited to these two embodiments.

[0031] First embodiment

[0032] like Figure 2 , Figure 3 The diagram shows a low-power timer circuit with asynchronous design and no preset value function. Specifically:

[0033] Includes an asynchronous timer implementation circuit 10 and an indicator signal judgment circuit 20.

[0034] The asynchronous timer implementation circuit 10 includes a first counting edge trigger I_FF1 to an eighth counting edge trigger I_FF8. The second input terminal of the first counting edge trigger I_FF1 is connected to the TCLK signal input terminal. The second input terminals of the second counting edge triggers I_FF2 to the eighth counting edge trigger I_FF8 are connected to the second output terminal of the previous counting edge trigger. The first input terminal of the first counting edge trigger I_FF1 to the eighth counting edge trigger I_FF8 is connected to the second output terminal. The clock of the first counting edge trigger I_FF1 is the timer clock TCLK. The clock of the second counting edge triggers I_FF2 to the eighth counting edge trigger I_FF8 is the second output terminal of the previous stage counting edge trigger. The counting edge triggers only work when the second output terminal of the previous stage counting edge trigger flips from 0 to 1. The clear terminal of the first counting edge triggers I_FF1 to the eighth counting edge trigger I_FF8 is connected to the signal RST. After the counting edge triggers work, RST is automatically cleared.

[0035] The indicator signal determination circuit 20 includes a first AND gate, a second AND gate, and a third AND gate. The first AND gate is connected to the first output terminals of the first counting edge triggers I_FF1 to the fourth counting edge triggers I_FF4. The second AND gate is connected to the first output terminals of the fifth counting edge triggers I_FF5 to the eighth counting edge triggers I_FF8. The input terminal of the third AND gate is connected to the output terminals of the first and second AND gates. The output terminal of the third AND gate is connected to the indicator signal TOV signal terminal. The indicator signal TOV can only be achieved when all of the first counting edge triggers I_FF1 to the eighth counting edge triggers I_FF8 are at a high level.

[0036] An asynchronous timer implementation method (Note: Because the first input D terminal of the first counting edge flip-flop I_FF1 to the eighth counting edge flip-flop I_FF8 is connected to the second output terminal, the signals of the two are the same), includes:

[0037] The asynchronous timer implementation circuit includes a first counting edge trigger I_FF1 to an eighth counting edge trigger I_FF8. The clock of the first counting edge trigger I_FF1 is the timer clock TCLK, and the clocks of the other counting edge triggers are the second output of the previous stage counting edge trigger. The counting edge triggers only work when the second output of the previous stage counting edge trigger flips from 0 to 1.

[0038] Specifically, its output pulse is as follows: Figure 4 As shown,

[0039] Step S1: The TCLK pulse input signal is input from the second input terminal of the first counting edge trigger I_FF1. When the signal reaches the first rising edge, the first output negative terminal / Q1 signal flips from 0 to 1, the first input terminal D1 signal flips from 0 to 1, the first output terminal Q1 signal flips from 0 to 1 synchronously with the first input terminal D1 signal, and at the same time the first counting edge trigger I_FF1 jumps from 00 to 01;

[0040] Step S2: The second output negative terminal / Q1 signal serves as the input pulse signal for the second counting edge trigger I_FF2. When the signal reaches the rising edge, the second output negative terminal / Q2 signal flips from 0 to 1, the second input terminal D2 signal flips from 0 to 1, the second output terminal Q2 signal flips from 0 to 1 synchronously with the second input terminal D2 signal, and at the same time, the second counting edge trigger I_FF2 jumps from 01 to 03;

[0041] Step S3: The second output negative terminal / Q2 signal serves as the input pulse signal for the third counting edge trigger I_FF3. When the signal reaches the rising edge, the third output negative terminal ( / Q3) flips from 0 to 1, the third input terminal D3 signal flips from 0 to 1, and the third output terminal Q3 signal flips from 0 to 1 synchronously with the third input terminal D3 signal. Simultaneously, the third counting edge trigger jumps from 03 to 07, and the output pulse signal is as follows: Figure 4 As shown;

[0042] Step S4: Similarly, the seventh output negative terminal / Q7 signal serves as the input pulse signal for the eighth counting edge trigger I_FF8. When the signal reaches the rising edge, the eighth input terminal D8 signal flips, and the eighth output terminal Q8 signal flips synchronously with the eighth input terminal D8 signal. At the same time, the eighth counting edge trigger I_FF8 jumps from 127 to 255.

[0043] Step S5: After the eighth output terminal Q8 signal is output, it enters the indicator signal judgment circuit 20 along with the first output terminal Q1 to the seventh output terminal Q7. When all eight signals are high at the same time, the indicator signal TOV is reached, and the timer completes one counting cycle. At the same time, after each counting edge trigger has finished working, RST will be automatically cleared. The asynchronous low-power timer without preset value function returns to the initial state and waits to enter the next counting cycle.

[0044] Second embodiment

[0045] like Figure 5 , Figure 6 , Figure 7 , Figure 8 The diagram shows an asynchronous, low-power timer circuit with preset value functionality. Specifically:

[0046] It includes an asynchronous timer implementation circuit 30, a preset value circuit 40, and an indicator signal judgment circuit 50.

[0047] The asynchronous timer implementation circuit 30 includes a first counting edge trigger I_FF1 to an eighth counting edge trigger I_FF8. The second input of the first counting edge trigger I_FF1 is connected to the TCLK signal input. The second inputs of the first counting edge trigger I_FF1 to the eighth counting edge trigger I_FF8 are connected to the second input of the preceding counting edge trigger. The first inputs of the first counting edge trigger I_FF1 to the eighth counting edge trigger I_FF8 are connected to their second outputs. The clock of the first counting edge trigger I_FF1 is the timer clock TCLK. The clocks of the second counting edge triggers I_FF2 to the eighth counting edge trigger I_FF8 are the second outputs of the preceding counting edge triggers. The counting edge triggers only operate when the second output of the preceding counting edge trigger flips from 0 to 1. The clear inputs of the first counting edge triggers I_FF1 to the eighth counting edge trigger I_FF8 are connected to the first clear input CLR_CNT. <1> ~Eighth Clear End CLR_CNT <8> After the counting edge trigger is activated, the first clear input CLR_CNT... <1> ~Eighth Clear End CLR_CNT <8> Automatically reset.

[0048] The preset value circuit 40 includes RST_CNT first logic circuit to RST_CNT eighth logic circuit, and CLR_CNT first logic circuit to CLR_CNT eighth logic circuit. The output terminals of RST_CNT first logic circuit to RST_CNT eighth logic circuit are respectively connected to the set terminals of the first counting edge flip-flops to the eighth counting edge flip-flops, and the output terminals of CLR_CNT first logic circuit to CLR_CNT eighth logic circuit are respectively connected to the reset terminals of the first counting edge flip-flops to the eighth counting edge flip-flops. The RST_CNT first logic circuit to RST_CNT eighth logic circuit includes SEL first port to SEL eighth port, TDATA first port to TDATA eighth port, and first AND gate to eighth AND gate. The CLR_CNT first logic circuit to CLR_CNT eighth logic circuit includes SEL first port to SEL eighth port, TDATA first port to TDATA eighth port, first AND gate to eighth AND gate, and first NOT gate to eighth NOT gate. The output levels of the first logic circuit to the eighth logic circuit of RST_CNT are set according to the value of TDATA[1:8] when SEL=1. When TDATA[1]=1, the first set terminal is high. The output levels of the first logic circuit to the eighth logic circuit of RST_CNT are set according to the value of TDATA[1:8] when SEL=1. When TDATA[1]=0, the first clear terminal is high.

[0049] The indicator signal judgment circuit 50 includes a first AND gate, a second AND gate, and a third AND gate. The first AND gate is connected to the first output terminals of the first counting edge triggers I_FF1 to I_FF4. The second AND gate is connected to the first output terminals of the fifth counting edge triggers I_FF5 to the eighth counting edge triggers I_FF8. The input terminal of the third AND gate is connected to the output terminals of the first and second AND gates. The output terminal of the third AND gate is connected to the indicator signal TOV signal terminal. The indicator signal TOV can only be achieved when all of the first counting edge triggers I_FF1 to the eighth counting edge triggers I_FF8 are at a high level.

[0050] Its asynchronous design with preset values ​​works as follows:

[0051] Step S1: SEL=1, the level of RST_CNT[1] is set according to the value of TDATA[1]. When TDATA[1]=1, RST_CNT[1] is high; when TDATA[1]=0, RST_CNT[1] is low. Similarly, the signals of RST_CNT[2:8] are determined by TDATA[2:8] when SEL=1.

[0052] Step S2: SEL=1, the high and low levels of CLR_CNT[1] are set according to the value of TDATA[1]. When TDATA[1]=0, CLR_CNT[1] is high; when TDATA[1]=1, CLR_CNT[1] is low. Similarly, the signals of CLR_CNT[2:8] are determined by TDATA[2:8] when SEL=1.

[0053] After the preset is completed, counting begins from the first rising edge of TCLK after SEL=0, and the counting period is T. TCLK *(256-TDATA).

[0054] Step S3: The asynchronous timer implementation method is the same as in Example 1;

[0055] Step S4: After the eighth output terminal Q8 signal is output, it enters the indicator signal judgment circuit 30 along with the first output terminal Q1 to the seventh output terminal Q7. After one counting cycle, if less than 8 signals are output, the next counting cycle will automatically begin. When all 8 output signals are high at the same time, the indicator signal TOV is reached, and the timer completes its work.

[0056] In summary, the low-power timer circuit described in this invention realizes asynchronous control of the timer, thereby greatly reducing operating power consumption. It adopts a simpler preset value circuit, reducing the use of 8 half-adders compared with the prior art. It only uses a few simple gates to determine the timing indicator signal TOV, greatly reducing the overall circuit size and lowering costs.

[0057] Finally, it should be noted that any modification or equivalent substitution of some or all of the technical features based on the device structure and the technical solutions of the embodiments of the present invention, without departing from the corresponding technical solutions of the present invention, shall fall within the patent scope of the device structure and the embodiments of the present invention.

Claims

1. A low-power timer circuit, characterized in that, It includes a preset value circuit, an asynchronous timer implementation circuit, and an indicator signal judgment circuit. The preset value circuit is connected to the set and reset terminals of each counting edge flip-flop of the asynchronous timer implementation circuit. The first output terminal of each counting edge flip-flop of the asynchronous timer implementation circuit is connected to the n input terminals of the indicator signal judgment circuit. The preset value circuit sets each counting edge flip-flop according to a preset value. The preset value circuit includes the first logic circuit RST_CNT to the nth logic circuit RST_CNT, the first logic circuit CLR_CNT to the nth logic circuit CLR_CNT, the output terminals of the first logic circuit RST_CNT to the nth logic circuit RST_CNT to the set terminals of the first counting edge flip-flops to the nth counting edge flip-flops respectively, and the output terminals of the first logic circuit CLR_CNT to the nth logic circuit CLR_CNT to the reset terminals of the first counting edge flip-flops to the nth counting edge flip-flops respectively. The output signal of each counting edge trigger of the asynchronous timer implementation circuit is simultaneously high or low. The indicator signal judgment circuit outputs a timing indicator signal. The asynchronous timer implementation circuit includes a series structure of first counting edge triggers to nth counting edge triggers. The first input of the first counting edge triggers to (n-1)th counting edge triggers is connected to the second input of the next counting edge trigger. The first input of the nth counting edge trigger is connected to the second output of the nth counting edge trigger. The trigger signal of the first counting edge trigger is the timer clock TCLK. The second input of the second counting edge triggers to nth counting edge triggers is connected to the second output of the previous counting edge trigger. When the second output of the previous counting edge trigger flips on a rising edge or a falling edge, the corresponding next counting edge trigger starts to work.

2. The low-power timer circuit as described in claim 1, characterized in that, The first counting edge trigger to the nth counting edge trigger are rising edge triggered D flip-flops, or the first counting edge trigger to the nth counting edge trigger are falling edge triggered D flip-flops.

3. The low-power timer circuit as described in claim 1, characterized in that, The RST_CNT first logic circuit to RST_CNT nth logic circuit includes SEL first port to SEL nth port, TDATA first port to TDATA nth port, and first AND gate to nth AND gate. The SEL first port to SEL nth port in the RST_CNT first logic circuit to RST_CNT nth logic circuit are respectively connected to the first input terminal of the first AND gate to the nth AND gate. The TDATA first port to TDATA nth port are respectively connected to the second input terminal of the first AND gate to the nth AND gate. The output terminal of the first AND gate to the nth AND gate is respectively connected to the set terminal of the first counting edge flip-flop to the nth counting edge flip-flop. The CLR_CNT first logic circuit to the CLR_CNT nth logic circuit includes SEL first port to SEL nth port, TDATA first port to TDATA nth port, first AND gate to nth AND gate, and first NOT gate to nth NOT gate. The SEL first port to SEL nth port of the CLR_CNT first logic circuit to the CLR_CNT nth logic circuit are respectively connected to the first input terminal of the first AND gate to the nth AND gate, the TDATA first port to TDATA nth port are respectively connected to the second input terminal of the first AND gate to the nth AND gate, and the output terminal of the first AND gate to the nth AND gate is respectively connected to the reset terminal of the first counting edge flip-flop to the nth counting edge flip-flop.

4. The low-power timer circuit as described in claim 1, characterized in that, The indicator signal judgment circuit specifically includes: a first AND gate, a second AND gate, and a third AND gate, wherein the first AND gate is connected to the first output terminal of the first counting edge trigger to the n / 2th counting edge trigger, the second AND gate is connected to the first output terminal of the n / 2th counting edge trigger to the nth counting edge trigger, the input terminal of the third AND gate is connected to the output terminals of the first AND gate and the second AND gate, and the output terminal of the third AND gate is connected to the indicator signal output terminal.

5. The low-power timer circuit as described in claim 1, characterized in that, include: The clock of the first counting edge trigger of the asynchronous timer implementation circuit is the timer clock TCLK, and the clock of the second counting edge trigger to the nth counting edge trigger is the second output of the previous stage counting edge trigger. When the second output of the previous stage counting edge trigger flips on a rising edge or a falling edge, the corresponding next stage counting edge trigger starts to work.

6. The low-power timer circuit as described in claim 1, characterized in that, include: The preset value circuit is connected to the set and reset terminals of each counting edge trigger of the asynchronous timer implementation circuit. The high and low levels of the first set terminal to the nth set terminal are set according to the value of the TDATA port when SEL is the first preset value, and the nth set terminal is set when TDATA[n] is the second preset value. The high and low levels of the first clear terminal to the nth clear terminal are set according to the value of the TDATA port when SEL is the first preset value, and the nth clear terminal is cleared when TDATA[n] is the third preset value.

7. A chip having a low-power timer circuit as described in any one of claims 1 to 6.

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