Semiconductor chip
By introducing dielectric mirrors and thin contact layers into semiconductor chips, the problems of uneven carrier injection and low light extraction efficiency are solved, achieving more uniform radiative emission and higher light extraction efficiency, and improving the thermal stability of the chip.
Patent Information
- Application Number
- CN202480029373.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-05-04
- Filing Date
- 2024-04-24
- Publication Date
- 2025-12-02
AI Technical Summary
Semiconductor chips suffer from problems such as non-uniform radiation emission due to uneven carrier injection and reduced light extraction efficiency due to the structure of the metal current diffuser.
The semiconductor chip structure employs a dielectric mirror, which consists of alternating sequences of low-refractive-index and high-reflectivity dielectric layers. Current injection is controlled through an opening configuration. Thin contact layers and graphene or metal contact layers are used to reduce lateral current diffusion. Radiation is reflected through a distributed Bragg reflector to improve light extraction efficiency.
This achieves uniformity in carrier injection and radiation output, improves light extraction efficiency, reduces absorption loss within the contact layer, and enhances the chip's thermal stability and optical coupling output.
Smart Images
Figure CN121058367A_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor chip. Background Technology
[0002] In semiconductor chips such as light-emitting diodes (LEDs), the relatively low lateral conductivity within the semiconductor layer can lead to uneven charge carrier injection, resulting in uneven radiative emission. Furthermore, the metallic current diffuser structure formed on the semiconductor chip can cause significant absorption of the emitted radiation, thereby further reducing light extraction efficiency. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a semiconductor chip that exhibits improved carrier injection efficiency and provides uniform radiation output.
[0004] The aforementioned technical problem is solved in particular by a semiconductor chip having the features of claim 1. Other extensions and configurations are the subject of the dependent claims.
[0005] Specifically, it describes a semiconductor chip, which includes the semiconductor body.
[0006] According to at least one embodiment of a semiconductor chip, the semiconductor body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type, and an active region configured for emitting radiation. For example, the first semiconductor layer is n-type and the second semiconductor layer is p-type, or the first semiconductor layer is p-type and the second semiconductor layer is n-type. The active region is disposed between the first semiconductor layer and the second semiconductor layer.
[0007] The first semiconductor layer and / or the second semiconductor layer and / or the active region may be a single layer, or may include multiple sublayers. For example, the active region is configured to emit radiation in the ultraviolet spectral range. Alternatively or additionally, the active region may be configured to emit radiation in the visible or infrared spectral range.
[0008] According to at least one embodiment of a semiconductor chip, a first semiconductor layer is electrically connected to a first contact structure, the first contact structure including at least one first contact finger. For example, the first contact structure includes a first contact pad configured for external electrical connection to the semiconductor chip.
[0009] According to at least one embodiment of a semiconductor chip, the at least one first contact refers to a contact layer. For example, the contact layer is disposed on a first semiconductor layer, particularly in direct contact with the first semiconductor layer. For example, the contact layer is the layer of the first contact structure disposed closest to the first semiconductor layer.
[0010] According to at least one embodiment of a semiconductor chip, the at least one first contact includes a current distribution layer. The current distribution layer may include one or more layers. For example, the current distribution layer is disposed at least in a region on the side of the contact layer facing away from the first semiconductor layer. In other words, the contact layer is disposed at least in the region between the current distribution layer and the first semiconductor layer. For example, at any location on the semiconductor chip, the current distribution layer is not directly adjacent to the first semiconductor layer.
[0011] According to at least one embodiment of a semiconductor chip, the semiconductor chip includes a dielectric mirror. For example, the dielectric mirror is formed as a distributed Bragg reflector (DBR), comprising alternating sequences of low-refractive-index dielectric layers and high-reflectivity dielectric layers. In particular, the dielectric mirror is configured to reflect radiation emitted by the active region during operation of the semiconductor chip. For example, the reflectivity is at least 80%, at least 90%, or at least 95% for the wavelength of maximum intensity of the radiation emitted by the active region.
[0012] According to at least one embodiment of a semiconductor chip, the dielectric mirror includes at least one opening. In particular, the at least one opening extends vertically and completely through the dielectric mirror.
[0013] In the context of this application, the vertical direction is the direction that extends vertically relative to the active region.
[0014] According to at least one embodiment of the semiconductor chip, a current distribution layer extends through the at least one opening and is directly adjacent to the contact layer. Therefore, the current distribution layer is directly adjacent to the contact layer within the at least one opening. A dielectric mirror is disposed at least in the region between the contact layer and the current distribution layer, lateral to the at least one opening. Therefore, current injection into the first semiconductor layer occurs primarily directly below the at least one opening.
[0015] In at least one embodiment of a semiconductor chip, the semiconductor chip includes a semiconductor body having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type, and an active region configured for emitting radiation, wherein the active region is disposed between the first and second semiconductor layers. The first semiconductor layer is electrically connected to a first contact structure, the first contact structure including at least one first contact finger. The at least one first contact finger includes a contact layer and a current distribution layer, wherein the contact layer is disposed on the first semiconductor layer. A dielectric mirror is disposed in the region between the contact layer and the current distribution layer. The dielectric mirror includes at least one opening, and the current distribution layer extends through the at least one opening and is directly adjacent to the contact layer.
[0016] During the fabrication of a semiconductor chip, current injection into the first semiconductor layer through the first contact structure can be controlled by proper configuration of at least one opening. In particular, current congestion along the edges of the first contact finger can be avoided or at least reduced. Therefore, more uniform emission from the semiconductor chip can be achieved.
[0017] Furthermore, the dielectric microscope can reflect radiation emitted toward the first contact structure with high efficiency, thereby further improving light extraction.
[0018] In this context, the term "light" is not limited to visible light, but also includes radiation in the ultraviolet and infrared spectral ranges.
[0019] According to at least one embodiment of the semiconductor chip, the contact layer has a thickness of up to 20 nm, up to 10 nm, or up to 5 nm.
[0020] Compared to a thicker contact layer, greater transparency can be achieved for radiation emitted from the active region. Therefore, absorption losses within the contact layer can be reduced. Radiation penetrating the contact layer can be reflected at the dielectric microscope.
[0021] Furthermore, the relatively low thickness of the contact layer intentionally reduces lateral current diffusion within it. Therefore, charge carrier injection into the first semiconductor layer occurs almost entirely or at least primarily directly below at least one opening. In other words, lateral current diffusion within the contact layer is negligible.
[0022] For example, the contact layer may include metals such as rhodium, palladium, nickel, chromium, titanium, gold, silver, or platinum. For example, a contact layer comprising or made of metal may have a thickness of at least 0.5 nm.
[0023] Alternatively, the contact layer may comprise graphene. For example, the contact layer may comprise a single monolayer of graphene or multiple stacked monolayers, such as up to 10 monolayers.
[0024] Using graphene, for example, in the UV-C spectral range, one can achieve exceptionally high transparency.
[0025] According to at least one embodiment of a semiconductor chip, in a top view of the semiconductor chip, a plurality of openings are arranged within at least one first contact finger. For example, at least one of these openings has a circular, elliptical, or polygonal shape, such as a rectangular or hexagonal shape. For example, the ratio between the longitudinal extension range and the lateral extension range of the at least one opening is between 1:1 and 20:1 (inclusive).
[0026] For example, two or more openings are arranged laterally side-by-side along the axis of the first contact finger. In a top view of the semiconductor chip, the axis of the first contact finger may be straight, for example, it may have one or more bends or bends, or it may be at least partially curved.
[0027] For example, the at least one opening is spaced apart from the edge of the first contact finger. Therefore, the current injection spaced apart from the edge of the first contact finger increases.
[0028] According to at least one embodiment of the semiconductor chip, two of the plurality of openings differ from each other by at least 50% in their lateral extension range perpendicular to the axis of at least one first contact finger. By using openings of different sizes, the local current injection under the at least one first contact finger can be altered, thereby obtaining more uniform light emission.
[0029] According to at least one embodiment of the semiconductor chip, the lateral extension of an opening perpendicular to the axis of at least one first contact finger decreases within the at least one first contact finger in at least one direction. For example, this at least one direction extends parallel to the axis of the first contact finger. For example, an opening having the maximum lateral extension perpendicular to the axis of the first contact finger is located at or near the center of the first contact finger, and the lateral extension of additional openings decreases from the center of the at least one first contact finger in two opposite directions.
[0030] Alternatively, the at least one direction extends perpendicular to the axis of the first contact finger. For example, an opening arranged closer to the axis of the first contact finger has a larger lateral extension than one or more openings arranged further away from the axis of the first contact finger. Therefore, current injection along the axis of the first contact finger increases compared to injection along the edge of the first contact finger.
[0031] According to at least one embodiment of the semiconductor chip, the longitudinal extension of at least one opening in a direction parallel to the axis of at least one first contact finger is at least 50% or at least 80% of the length of the at least one first contact finger. For example, the at least one opening is configured as a linear opening extending almost the entire length of the first contact finger.
[0032] According to at least one embodiment of a semiconductor chip, at least one opening includes a main region and at least one side region. For example, the main region extends along the axis of at least one first contact finger, while one or more side regions extend from the main region in a direction away from the axis. For example, the side regions are arranged on both sides of the main region. For example, the at least one opening has a caterpillar-like shape.
[0033] In this case, a single opening with the specific shape described herein ensures significant charge carrier injection along the axis of the first contact finger, thereby mitigating the current congestion effect along the edge of the first contact finger.
[0034] The semiconductor substrate, especially the active region, may include III-V compound semiconductor materials.
[0035] III-V compound semiconductor materials are suitable for use in ultraviolet (UV) ( ), through visible light (especially for blue to green radiation) Or particularly for yellow to red radiation. ), until infrared ( Radiation generation within the spectral range. The following applies in all cases: 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1, especially where x ≠ 1, y ≠ 1, x ≠ 0, and / or y ≠ 0. High internal quantum efficiency can be achieved using III-V compound semiconductor materials, particularly those in the aforementioned material systems.
[0036] According to at least one embodiment of a semiconductor chip, the active region is configured to emit radiation in the ultraviolet spectrum. For example, the wavelength of maximum intensity is at most 400 nm. For example, the active region or at least one layer thereof is based on a nitride compound semiconductor material.
[0037] In the current context, "nitride compound semiconductor material-based" means a semiconductor layer sequence or at least a portion thereof, such as at least the active region and / or the growth substrate, including nitride compound semiconductor materials, preferably including... Where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. This material does not necessarily have to have a composition that is mathematically exact according to the formula above. Instead, it may include, for example, one or more dopants as well as additional components. For simplicity, the formula above only includes the basic lattice components (Al, Ga, In, N), even though these components may be partially substituted and / or supplemented by small amounts of other substances.
[0038] According to at least one embodiment of a semiconductor chip, the material of the first semiconductor layer directly adjacent to the contact layer includes For example, the aluminum content x is at least 0.02, at least 0.05, at least 0.1, or at least 0.2. Compared to GaN, this material has higher transparency for radiation in the ultraviolet spectral range (wavelengths from 100 nm to 400 nm (inclusive)) and, for example, the UV-C spectral range (wavelengths from 100 nm to 280 nm (inclusive)).
[0039] Semiconductor chips that emit light in the ultraviolet spectrum can be used, for example, in surface disinfection or water purification applications. Radiation, for instance, can be used as a disinfectant.
[0040] According to at least one embodiment of a semiconductor chip, a second semiconductor layer is electrically connected to a second contact structure. For example, the second contact structure extends through at least one via of the semiconductor body, through the first semiconductor layer and the active region, into the second semiconductor layer.
[0041] According to at least one embodiment of a semiconductor chip, the semiconductor chip includes contact pads for external electrical contacts, wherein these contact pads are arranged on a side of the semiconductor body away from the radiation exit side of the semiconductor chip. Therefore, the radiation exit side of the semiconductor chip lacks the contact structures required for external electrical contacts.
[0042] According to at least one embodiment of a semiconductor chip, the semiconductor chip includes a substrate, wherein the substrate forms, in particular, a radiation exit side. For example, the substrate is a growth substrate for epitaxial deposition of a semiconductor layer for a semiconductor body. For example, the substrate includes sapphire or silicon carbide. Semiconductor chips having this type of contact configuration in terms of the substrate are also called flip chips.
[0043] Unless there is a contradiction, the features described above in connection with at least one embodiment of a semiconductor chip can be combined with other features described in connection with at least one embodiment of a semiconductor chip. Other features and extensions will become apparent from the following description of exemplary embodiments in conjunction with the accompanying drawings. Attached Figure Description
[0044] In the exemplary embodiments and drawings, components that function similarly or analogously are provided with the same reference numerals. Generally, only differences between aspects of the various embodiments are described. Unless otherwise specifically described, the description of a part or aspect of one embodiment also applies to corresponding parts or aspects of other embodiments.
[0045] In the attached diagram:
[0046] Figure 1A An exemplary embodiment of a semiconductor chip is shown in cross-sectional view;
[0047] Figure 1B An exemplary embodiment of a semiconductor chip is shown in top view;
[0048] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E Exemplary embodiments of the first contact finger are shown in top view; and
[0049] Figure 3 An exemplary embodiment of a semiconductor chip is shown in top view.
[0050] The accompanying drawings are illustrative. Therefore, the elements shown in the drawings and their dimensional relationships are not necessarily to scale. Instead, for better representation and / or for better understanding, individual elements or layer thicknesses may be shown at exaggerated dimensions. Detailed Implementation
[0051] exist Figure 1A In an exemplary embodiment, the semiconductor chip 1 includes a semiconductor body 2, which includes an active region 20 disposed between a first semiconductor layer 21 of a first conductivity type and a second semiconductor layer 22 of a second conductivity type. For example, the first semiconductor layer is p-type and the second layer 22 is n-type, or the first semiconductor layer is n-type and the second layer 22 is p-type.
[0052] The first semiconductor layer 21 is electrically connected to the first contact structure 3, which includes at least one first contact finger 31.
[0053] exist Figure 1B An exemplary embodiment of the arrangement of the first contact finger 31 and the second contact finger 51 of the second contact structure 5 is shown. The first contact fingers 31 of the first contact structure 3 are electrically connected to each other and can make electrical contact with the first contact fingers 31 of the first contact structure 3 from the outside via the first contact pad 32. Similarly, the second contact fingers 51 of the second contact structure 5 can make electrical contact with each other via the second contact pad 52.
[0054] The first contact pad 32 and the second contact pad 52 are disposed on the side of the semiconductor body 2 facing away from the radiation exit side 10 of the semiconductor chip 1. In the exemplary embodiment shown, the radiation exit side is formed by a substrate 29. For example, this substrate is a growth substrate for epitaxial growth of the semiconductor layer of the semiconductor body 2. Therefore, the semiconductor chip 1 represents a flip chip.
[0055] At least one first contact finger 31 includes a contact layer 35 and a current distribution layer 36. In the illustrated exemplary embodiment, the current distribution layer 36 includes a first layer 361 and a second layer 362. However, the current distribution layer may also include only one layer or more than two layers.
[0056] The contact layer 35 is disposed on and directly adjacent to the first semiconductor layer 21. For example, the contact layer 35 is a thin metal layer having a thickness of at most 20 nm, at most 10 nm, or at most 5 nm. Alternatively, the contact layer may comprise one or more monolayers of graphene or be composed of one or more monolayers of graphene.
[0057] A dielectric mirror 4 is disposed in the region between the contact layer 35 and the current distribution layer 36. The dielectric mirror 4 includes at least one opening 41 through which the current distribution layer 36 extends and is directly adjacent to the contact layer 35. Radiation generated in the active region 20 due to electron-hole pair recombination and emitted in a direction away from the radiation exit side 10 can pass through the relatively thin contact layer 35 and be reflected with high efficiency at the dielectric mirror 4. This contributes to improved light extraction efficiency.
[0058] For example, dielectric mirror 4 is configured as a distributed Bragg reflector, which includes, for example, [missing information]. , or Low refractive index layers and, for example, including Doped (YDH) or Alternating stacking of high refractive index layers.
[0059] For example, the dielectric mirror 4 has a reflectivity of at least 80%, at least 90%, or at least 95% for the radiation generated in the active region 20.
[0060] The contact layer 35 has relatively low conductivity in the lateral direction, i.e., in the direction extending parallel to the active region 20 of the semiconductor chip 1. Therefore, charge carrier injection into the first semiconductor layer 21 mainly occurs directly below at least one opening 41. Thus, a suitable choice of the configuration of the at least one opening 41 allows for control of charge carrier injection from the first contact finger 31 into the first semiconductor layer 21. In particular, the generation of radiation below the first contact finger 31 can be increased. In contrast, in conventional semiconductor chips using contact fingers, charge carrier recombination mainly occurs along the edges of the first contact finger 31 due to current crowding effects. Therefore, the semiconductor chip 1 fully utilizes the relatively high transmittance and relatively low lateral conductivity of the thin contact layer directly adjacent to the first semiconductor layer 21.
[0061] By eliminating the current congestion effect and introducing a uniform current distribution on all first contact fingers 31, less localized heating and better optical coupling output of the first contact fingers 31 can be achieved. This results in higher light extraction efficiency and better thermal stability of the semiconductor chip 1.
[0062] The described configuration of the semiconductor chip 1 can be used to generate radiation in the visible, ultraviolet, or infrared spectral range. For example, compared to semiconductor chips using a contact layer of a transparent conductive oxide such as ITO, radiation in the ultraviolet spectral range, such as the UV-C spectral range, can be generated with high efficiency because low light absorption of the contact layer 35 and high reflectivity due to the dielectric mirror 4 can be obtained.
[0063] For example, the material of the first semiconductor layer 21 can be formed of AlGaN, and in particular, it can be combined with the active region 20 based on a nitride compound semiconductor material. Compared with GaN used in conventional devices, AlGaN has a significantly lower absorption rate in the ultraviolet spectral range.
[0064] according to Figure 1A The semiconductor chip 1 also includes a first isolation layer 61 that electrically isolates the first semiconductor layer 21 and the active region 20 from the second contact structure 5. Specifically, the first isolation layer 61 covers the sidewalls of one or more vias 25 extending through the first semiconductor layer and the active region 20 into the second semiconductor layer 22. Electrical contact is made with the second semiconductor layer 22 vias 55 disposed in the vias 25.
[0065] The second isolation layer 62 electrically isolates the first contact structure 3 from the second contact structure 5. The first and / or second isolation layers may, for example, comprise oxides or nitrides.
[0066] The semiconductor chip 1 also includes a protective layer 45. This protective layer 45 can be used to protect the contact layer 35 during the manufacture of the semiconductor chip, and in particular, it can be used as an etch stop layer when at least one opening 41 is created through the dielectric mirror 4.
[0067] An adhesion enhancement layer 46 is disposed on the side of the dielectric mirror 4 facing away from the semiconductor body 2. This adhesion enhancement layer 46 can, for example, improve the adhesion of photoresist used in structuring processes during manufacturing.
[0068] Figures 2A to 2E Different exemplary embodiments of the configuration of at least one opening 41 within the first contact finger 31 are shown.
[0069] like Figure 2A As shown, the first contact finger 31 extends along axis 310. The first contact finger 31 has a longitudinal extension range 311 along the axis. In a direction extending perpendicular to the axis, the first contact finger 31 has a lateral extension range 312. For example, the ratio between the longitudinal extension range 311 and the lateral extension range 312 of the first contact finger 31 is in the range of 1:1 to 20:1 (inclusive).
[0070] In the illustrated exemplary embodiment, the axis 310 of the first contact finger 31 is straight. However, the axis 310 may also include bends or inflections, and / or be at least partially curved.
[0071] At least one opening 41 also has a longitudinal extension 411 along the axis 310 of the first contact finger 31 and a lateral extension 412 in a direction perpendicular to the axis 310.
[0072] exist Figure 2A In an exemplary embodiment, the opening 41 differs from each other in terms of its longitudinal extension 411 and its lateral extension 412. For example, the opening 41 has a circular shape, such that the longitudinal extension 411 is equal to the lateral extension 412. However, other shapes, such as elliptical or rectangular shapes, or similar shapes, may also be applied. Figure 2E The hexagonal shape shown.
[0073] For example, the ratio between the lateral extension range of the largest opening 41 within a first contact finger and the lateral extension range of the smallest opening 41 can be changed from 1:1 to 10:1 (inclusive).
[0074] Starting from the center of the first contact finger 31, the diameter of the opening 41 decreases as the distance from the center of the first contact finger 31 increases. For example, the opening 41 at the center of the first contact finger 31 has a diameter of 100 µm, while the smallest opening 41 located at the edge closest to the first contact finger 31 has a diameter of 20 µm.
[0075] exist Figure 2A and Figure 2E In an exemplary embodiment, the opening 41 is arranged along the axis 310 of the first contact finger 31. Therefore, the injection of charge carriers directly below the axis 310 of the first contact finger 31 is increased, thereby obtaining more uniform light generation.
[0076] exist Figure 2B In an exemplary embodiment, the first contact finger 31 includes an opening 41 extending along an axis 310 of the first contact finger 31 and another opening 41 spaced apart from the axis 310. The opening 41 further away from the axis has a smaller lateral extension 412 compared to the opening 41 overlapping the axis 310. This configuration also results in increased injection of charge carriers directly below the axis 310 of the first contact finger 31, leading to more uniform light generation in the active region 20.
[0077] exist Figure 2CIn an exemplary embodiment, the first contact finger 31 includes exactly one opening 41, wherein the opening 41 includes a main region 42 extending along an axis 310, and also includes a plurality of side regions 43 extending away from the main region 42 in a direction perpendicular to the axis 310. For example, the ratio of the longitudinal extension range of the side regions 43 to the longitudinal extension range of the main region 42 may be between 1:5 and 1:20 (inclusive). The ratio of the lateral extension range of the side regions 43 to the lateral extension range of the main region 42 may be between 1:1 and 1:10 (inclusive).
[0078] For example, the longitudinal extension range 411 of the main region 42 is at least 50% or at least 80% of the longitudinal extension range 311 of the first contact finger 31.
[0079] With the shown Figure 2C In different embodiments, a first contact finger 31 may be assigned to more than one opening 41, which have a main region 42 and at least one side region 43.
[0080] exist Figure 2D In an exemplary embodiment, the first contact finger 31 includes a plurality of linear openings 41. The longitudinal extension range 411 of these openings 41 is at least 50% or at least 80% of the longitudinal extension range 311 of the first contact finger 31. The openings overlapping the axis 310 of the first contact finger 31 have a larger lateral extension range than the openings 41 spaced apart from the axis 310 in the lateral direction. This configuration also increases light generation directly below the axis of the first contact finger 31, thereby resulting in better uniformity of light generation within the active region 20.
[0081] Figure 3 A further exemplary embodiment of the semiconductor chip is shown in top view, wherein a first contact finger 31 and a second contact finger 51 are shown. In this exemplary embodiment, the axis 310 of the contact fingers 31, 51 is not straight, but has a curved shape, such as a circular shape. Within such a first contact finger 31, at least one opening 41 may be, for example, as in combination Figures 2A to 2E It is configured relative to axis 310 as described.
[0082] This patent application claims priority to German Patent Application No. 10 2023 111 621.5, the disclosure of which is hereby incorporated herein by reference.
[0083] The invention described herein is not limited to the description given with reference to exemplary embodiments. Rather, the invention covers any novel features and any combination of features, particularly any combination of features in the claims, even if the feature or combination itself is not expressly specified in the claims or exemplary embodiments.
[0084] Figure Labels
[0085] 1 Semiconductor chip
[0086] 10 Radiation exit side
[0087] 2 Semiconductor Main Body
[0088] 20 active areas
[0089] 21 First semiconductor layer
[0090] 22 Second semiconductor layer
[0091] 25 through hole
[0092] 29 substrate
[0093] 3 First contact structure
[0094] 31 First contact points
[0095] 310 axis
[0096] 311 Vertical Extension Range
[0097] 312 lateral extension range
[0098] 32 First contact pad
[0099] 35 contact layer
[0100] 36 Current Distribution Layers
[0101] 361 First Layer
[0102] 362 Second Layer
[0103] 4 Dielectric microscopy
[0104] 41 opening
[0105] 411 Vertical Extension Range
[0106] 412 lateral extension range
[0107] 42 main areas
[0108] 43 Side Area
[0109] 45 protective layers
[0110] 46 Adhesion Reinforcement Layer
[0111] 5 Second contact structure
[0112] 51 Second contact finger
[0113] 52 contact pad
[0114] 55. Additional contact layers
[0115] 61 First Isolation Layer
[0116] 62 Second Isolation Layer
Claims
1. A semiconductor chip (1), the semiconductor chip comprising a semiconductor body (2), the semiconductor body having a first semiconductor layer (21) of a first conductivity type, a second semiconductor layer (22) of a second conductivity type different from the first conductivity type, and an active region (20) configured for emitting radiation, the active region (20) being disposed between the first semiconductor layer (21) and the second semiconductor layer (22), wherein, - The first semiconductor layer (21) is electrically connected to the first contact structure (3), and the first contact structure includes at least one first contact finger (31). - The at least one first contact finger (31) includes a contact layer (35) and a current distribution layer (36); - The contact layer (35) is disposed on the first semiconductor layer (21); - A dielectric mirror (4) is arranged in the region between the contact layer (35) and the current distribution layer (36); - The dielectric mirror (4) includes at least one opening (41); and - The current distribution layer (36) extends through the at least one opening (41) and is directly adjacent to the contact layer (35).
2. The semiconductor chip (1) according to claim 1. in, The contact layer (35) has a thickness of up to 5 nm.
3. The semiconductor chip (1) according to claim 1 or 2. in, In a top view of the semiconductor chip (1), a plurality of openings (41) are arranged within the at least one first contact finger (31).
4. The semiconductor chip (1) according to claim 3. in, Two of the plurality of openings (41) differ from each other by at least 50% in the lateral extension (412) of the axis (310) perpendicular to the at least one first contact finger (31).
5. The semiconductor chip (1) according to claim 3 or 4. in, The lateral extension range (412) of the opening perpendicular to the axis (310) of the at least one first contact finger (31) decreases in at least one direction within the at least one first contact finger (31).
6. The semiconductor chip (1) according to claim 5, wherein, The at least one direction extends parallel to the axis (310) of the at least one first contact finger (31).
7. The semiconductor chip (1) according to claim 5. in, The at least one direction extends perpendicularly to the axis (310) of the first contact finger (31).
8. The semiconductor chip (1) according to any one of the preceding claims. in, The longitudinal extension (411) of the at least one opening (41) in a direction parallel to the axis (310) of the at least one first contact finger (31) is at least 50% of the longitudinal extension (311) of the at least one first contact finger (31).
9. The semiconductor chip (1) according to any one of the preceding claims. in, The at least one opening (41) includes a main region (42) extending along the axis (310) of the at least one first contact finger (31), and wherein the at least one opening (41) includes a plurality of side regions (43) extending from the main region (42) in a direction away from the axis (310).
10. The semiconductor chip (1) according to any one of the preceding claims. in, The active region (20) is configured to emit radiation in the ultraviolet spectral range.
11. The semiconductor chip (1) according to any one of the preceding claims. in, The material of the first semiconductor layer (21) directly adjacent to the contact layer includes .
12. The semiconductor chip (1) according to any one of the preceding claims. in, The second semiconductor layer (22) is electrically connected to the second contact structure (5).
13. The semiconductor chip (1) according to any one of the preceding claims. in, The semiconductor chip (1) includes contact pads (32, 52) for external electrical contact of the semiconductor chip (1), the contact pads (32, 52) being arranged on the side of the semiconductor body (2) away from the radiation outlet side (10) of the semiconductor chip (1).
14. The semiconductor chip (1) according to claim 13. in, The semiconductor chip (1) includes a substrate (29) that forms the radiation outlet side (10).