Mask plate for plating seed layer by PVD (physical vapor deposition) of HJT (high junction transistor) battery and method for plating seed layer by PVD

Abstract

The invention relates to a PVD (Physical Vapor Deposition) process of an HJT (High Junction Transistor) battery, in particular to a mask plate for plating a seed layer through PVD of the HJT battery and a method for plating the seed layer through PVD, and aims to overcome the defects that in the prior art, when a metal transition layer is prepared by adopting the PVD process, a TCO (Transparent Conductive Oxide) is bombarded, a blue film is damaged, and the performance of the battery is influenced. The mask plate for the PVD plating seed layer of the HJT battery is made of a hard material; the mask plate is provided with a grid line area, the grid line area is composed of a plurality of hollow fine grids, and the grid line area corresponds to a film coating area of the HJT battery needing to be plated with a seed layer through PVD (Physical Vapor Deposition). Meanwhile, the invention also provides a method for plating a seed layer by PVD (Physical Vapor Deposition) by adopting the mask plate, and the surface of the battery is protected from being damaged by the PVD process through the method.

Description

Technical Field

[0001] This invention relates to the PVD process for HJT batteries, specifically to a mask plate and a method for PVD seed layer deposition in HJT batteries. Background Technology

[0002] Heterojunction (HJT) cells, with their higher bifaciality, open-circuit voltage, and efficiency, are considered the mainstream technology for next-generation batteries. Metal electrodes are a crucial step in their fabrication. However, the high cost and large consumption of low-temperature silver paste used in existing HJT cells significantly increase manufacturing costs, hindering their marketization. Currently, the metallization process for HJT cells typically employs a silver-free approach, including copper electroplating, silver-clad copper, base metal wire bonding, and copper-tin paste screen printing. Except for silver-clad copper, which can be directly screen-printed onto the cell, the other methods require a metal transition layer to connect the transparent conductive oxide (TCO) to the metal electrode, ensuring good adhesion and contact between the metal electrode and the TCO. This metal transition layer is often made of copper or its alloys, commonly referred to as a copper seed layer, and is fabricated using physical vapor deposition (PVD). However, PVD bombardment of the TCO during seed layer fabrication damages its blue film, affecting battery performance. Summary of the Invention

[0003] The purpose of this invention is to address the shortcomings of existing technologies where the PVD process for preparing a metal transition layer bombards the TCO, causing damage to the blue film and affecting battery performance. The invention provides a mask for PVD seed layer deposition in HJT batteries and a method for PVD seed layer deposition.

[0004] To achieve the above objectives, the technical solution provided by this invention is as follows:

[0005] A mask for PVD seed layer deposition in HJT batteries is characterized by the following features: it includes a mask template made of a rigid material; the mask template has a grid area composed of multiple perforated fine grids, and the grid area corresponds to the deposition area of ​​the HJT battery for which PVD seed layer deposition is required.

[0006] The hollowed-out design refers to the transparent setting on the mask template, which can be formed through various processes.

[0007] Furthermore, each of the aforementioned fine grids is composed of a continuous fine grid that is distributed in a continuous manner.

[0008] Furthermore, each of the aforementioned fine grids is composed of a discontinuous fine grid.

[0009] Furthermore, the width k of each of the fine grids satisfies the following condition: 0.1mm ≤ k ≤ 0.8mm;

[0010] The thickness of the mask plate is 0.01-0.2 mm.

[0011] Furthermore, the width k of the fine grid is 0.1 to 0.5 mm.

[0012] Furthermore, the mask plate is made of one or more of the following hard materials: stainless steel, aluminum, copper, and molybdenum.

[0013] Furthermore, the break length in the discontinuous fine grid is no greater than 0.5 mm.

[0014] Meanwhile, the present invention also provides a method for PVD seed layer deposition, which is characterized by including the following steps:

[0015] S1. Set the mask plate for PVD seed layer deposition of HJT battery on the blue film of HJT battery, so that its grid line area corresponds to the coating area of ​​HJT battery that needs to be PVD seed layer deposition, and cover the area that does not need to be seed layer deposition.

[0016] S2. A PVD coating process is used to coat the blue film on the HJT battery.

[0017] S3. After the coating is completed, remove the mask to complete the seed layer preparation and proceed with the subsequent metallization process.

[0018] Furthermore, in step S1, the grid line area is composed of multiple hollowed-out fine grids, and each fine grid is composed of a continuous fine grid that is continuously distributed.

[0019] In step S3, the metallization process employs an electroplating process.

[0020] Furthermore, in step S1, the grid line area is composed of multiple hollowed-out fine grids, and each fine grid is composed of a discontinuous fine grid.

[0021] In step S3, the metallization process is either wire welding or copper-containing paste screen printing.

[0022] The beneficial effects of this invention are:

[0023] 1. This invention addresses the problem of reduced battery efficiency caused by damage to the blue film during PVD seed layer deposition in HJT batteries. The mask is made of a rigid material with sufficient mechanical strength, is not easily deformed, and can be reused.

[0024] 2. In this invention, the mask plate adopts a specific thickness and fine grid width, which work together to improve the protection area of ​​the blue film while ensuring that subsequent processes can have good alignment accuracy and good mechanical strength.

[0025] 3. The PVD seed layer deposition method of the present invention uses a hard mask to cover the areas of the battery surface that do not require metallization, protecting the battery surface from damage during the PVD process. Using this method can reduce damage by more than 80%. After processing, the mask is removed, eliminating the need for additional processes to treat the battery surface and the mask, simplifying the production process and improving production efficiency.

[0026] 4. This invention is applicable to various silver-free metallization solutions such as electroplating, metal wire welding, and copper-containing paste screen printing, and has broad application prospects and practicality. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the continuous fine grid structure in Embodiment 1 of the present invention;

[0028] Figure 2 This is a schematic diagram of the structure of the discontinuous fine gate in Embodiment 2 of the present invention;

[0029] Explanation of reference numerals in the attached figures:

[0030] 1-Mask plate, 2-Continuous fine grid, 3-Discontinuous fine grid. Detailed Implementation

[0031] Example 1

[0032] The mask plate used for PVD deposition of seed layers in HJT batteries is made of a rigid material, which can be composed of one or more metals such as stainless steel, aluminum, copper, and molybdenum. The thickness of the mask plate 1 is 0.01-0.2 mm. If the thickness of the mask plate 1 is too small, it will affect its mechanical strength. If the thickness is too large, it will increase the difficulty of deposition near the edge of the mask plate 1 and cause a decrease in the flatness of the deposition edge. Therefore, the thickness of the mask plate 1 can be as small as possible while ensuring the mechanical strength of the mask plate 1.

[0033] The mask 1 has a graphically patterned grid area, which corresponds to the coating area of ​​the HJT battery. The grid area consists of multiple perforated fine grids, each composed of a continuously distributed series of fine grids 2. Figure 1 As shown.

[0034] The method of using mask 1 to deposit a seed layer for PVD can protect areas that do not need to be coated, thus avoiding damage to the blue film of TCO during the PVD process. Since the exposed area of ​​mask 1 is less than 20% of the total cell area, this method can reduce damage by more than 80%.

[0035] Before coating, the blue film is placed in a fixed position on the battery, and then a mask 1 is placed on top of it. The mask 1 is also fixed in a fixed area of ​​the coating tank to ensure the accurate position of the seed layer.

[0036] Currently, the grid lines of heterojunction solar cells include fine grids and main grids, with grid line widths all within 0.1 mm. The fine grid width k in the grid line area of ​​mask 1 needs to be greater than the grid line width of the heterojunction solar cell, therefore its minimum is 0.1 mm and does not exceed 0.8 mm. The fine grid width affects the alignment accuracy during subsequent welding and screen printing. The smaller the fine grid width, the higher the alignment accuracy requirement, but the larger the protection area for the battery's blue film. Therefore, after balancing the equipment alignment accuracy and reducing the degree of damage to the battery's blue film, the fine grid width is adjusted between 0.1 and 0.5 mm. The arrangement of the fine grids in the grid line area of ​​mask 1, as well as the length, spacing, and number of the fine grids, are all adjusted according to the grid lines required for the heterojunction solar cell metallization process.

[0037] The method of using the above-mentioned mask plate 1 to perform PVD deposition of seed layer for HJT battery in this invention is as follows: the above-mentioned mask plate 1 is set on the HJT battery to cover the area that does not need to be coated, and only the corresponding position of the grid line area is exposed, and PVD coating is performed in the grid line area.

[0038] In this embodiment, a stainless steel mask 1 with a thickness of 0.01 mm is used, and its gate line area is a continuous fine gate 2 with a width of 0.15 mm. PVD copper plating is performed using the mask 1 to obtain a copper layer thickness of 100 nm. After the plating is completed, the stainless steel mask 1 is removed and subsequent electroplating copper processes are performed.

[0039] Example 2

[0040] The difference between this embodiment and Embodiment 1 is that the fine gates in the gate line region are all composed of a discontinuous fine gate 3, such as... Figure 2 As shown, the discontinuous fine grid 3 can enhance the strength of the mask 1 and extend its service life. However, since the PVD seed layer is deposited before the grid line deposition in the electroplating process, the seed layer needs to be continuous to ensure current transmission. Therefore, the discontinuous fine grid 3 cannot be used in the electroplating process. The discontinuity length of the discontinuous fine grid 3 should not exceed 0.5 mm. If the discontinuity length is too large, the spacing between the resulting seed layers will be too large, affecting the collection of current from the battery surface by the seed layer.

[0041] In this embodiment, a copper mask 1 with a thickness of 0.2 mm is used, and its gate line area is a discontinuous fine gate 3 with a fine gate width of 0.5 mm and a break length of 0.4 mm. PVD copper plating is performed using the mask 1 to obtain a copper layer thickness of 200 nm. After the plating is completed, the copper mask 1 is removed, and copper-containing paste is screen printed to create copper-containing gate lines.

[0042] Example 3

[0043] The difference between this embodiment and Embodiment 1 is that a copper mask 1 with a thickness of 0.03 mm is used, and its gate line area is a continuous fine gate 2 with a fine gate width of 0.2 mm. The mask 1 is used to perform PVD copper-nickel alloy plating to obtain a coating thickness of 150 nm. After the coating is completed, the copper mask 1 is removed and metal wires are welded as gate lines.

Claims

1. A mask plate for PVD seed layer plating of HJT cells, characterized in that: it comprises a mask plate (1), the mask plate (1) is composed of hard material; and a grid line area is arranged on the mask plate (1), the grid line area is composed of a plurality of hollow fine grids, and the grid line area corresponds to the plating area of the HJT cell to which the PVD seed layer plating is performed.

2. The mask plate for PVD seed layer plating of HJT cells according to claim 1, characterized in that: each of the fine grids is composed of a continuous fine grid (2) in continuous distribution.

3. The mask plate for PVD seed layer plating of HJT cells according to claim 1, characterized in that: each of the fine grids is composed of a discontinuous fine grid (3) in discontinuous distribution.

4. The mask plate for PVD seed layer plating of HJT cells according to any one of claims 1-3, characterized in that: the width k of each of the fine grids satisfies the following condition: 0.1 mm≤k≤0.8 mm; and the thickness of the mask plate (1) is 0.01-0.2 mm.

5. The mask plate for PVD seed layer plating of HJT cells according to claim 4, characterized in that: the width k of the fine grid is 0.1-0.5 mm.

6. The mask plate for PVD seed layer plating of HJT cells according to claim 1, characterized in that: the mask plate (1) is composed of one or more of hard materials such as stainless steel, aluminum, copper, and molybdenum.

7. The mask plate for PVD seed layer plating of HJT cells according to claim 3, characterized in that: the disconnected length of the discontinuous fine grid (3) is not greater than 0.5 mm.

8. A method for PVD seed layer plating of HJT cells, characterized in that: it comprises the following steps: S1. arranging the mask plate for PVD seed layer plating of HJT cells according to claim 1 on a blue film piece of the HJT cell, so that the grid line area corresponds to the plating area of the HJT cell to which the PVD seed layer plating is performed, and covers the area to which the seed layer plating is not needed; S2. performing plating on the blue film piece of the HJT cell by using a PVD process; and S3. after the plating is completed, removing the mask plate (1), completing the preparation of the seed layer, and performing a subsequent metallization process.

9. The method for PVD seed layer plating according to claim 8, characterized in that: in step S1, the grid line area is composed of a plurality of fine grids, and each of the fine grids is composed of a continuous fine grid (2) in continuous distribution; and in step S3, the metallization process adopts an electroplating process.

10. The method for PVD seed layer plating according to claim 8, characterized in that: in step S1, the grid line area is composed of a plurality of fine grids, and each of the fine grids is composed of a discontinuous fine grid (3) in discontinuous distribution; and in step S3, the metallization process is metal wire welding or copper-containing paste screen printing. ​ ​ ​ ​ ​ ​ 8. A method of PVD seed layering, characterized in that, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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