Semiconductor device, preparation method and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method and electronic equipment, and the method comprises the steps: introducing a reactant containing a first element into a reaction chamber, introducing water or oxygen plasma into the reaction chamber, forming an oxide dielectric material, and enabling the surface of the oxide dielectric material to have hydroxyl. Bronsted acid or amino silane is introduced into the reaction chamber to react with hydroxyl groups on the surface of the oxide dielectric material, and after the reaction is completed, the concentration of the hydroxyl groups close to the bottom of the set structure is higher than that of the hydroxyl groups close to the top of the set structure so as to occupy growth sites where part of the hydroxyl groups are located; the deposition rate of the oxide dielectric material in the area close to the bottom of the set structure is high, the deposition rate of the oxide dielectric material in the area close to the top of the set structure is low, the oxide dielectric material gradually forms the similar V-shaped growth effect, seamless filling of the oxide dielectric material is achieved, the filling quality of the oxide dielectric material is improved, and the service life of the oxide dielectric material is prolonged. And the electrical performance of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor device, a preparation method and an electronic device. BACKGROUND

[0002] With the development of advanced semiconductor processes, the line width critical dimension of semiconductor devices has been reduced from microns to nanometers. When the technology node is further miniaturized, due to the limitation of process precision, it is usually necessary to connect the gate contact of the transistor to the position of the gate structure in the isolation region, otherwise it is easy to cause short circuit with the source or drain of the transistor, but such practice increases the unit area of the transistor. At present, in order to realize the further reduction of the transistor area, the active gate contact (COAG) process is introduced, which is a process mode of directly connecting the gate contact to the active gate of the transistor, thereby helping the transistor to save the unit area. In order to expand the process window, the COAG process needs to fill two different dielectric materials above the active gate and source / drain of the transistor. At present, the process of filling dielectric material usually produces gaps in the dielectric material film layer after filling, resulting in incomplete filling of the dielectric material film layer. Since the dielectric material film layer will be etched when etching other materials, if there are gaps in the dielectric material film layer, it is equivalent to accelerating the etching rate of the dielectric material film layer, which is easy to cause the etching to penetrate the dielectric material film layer, resulting in the exposure of the material below the dielectric material film layer, thereby causing etching damage to the material below the dielectric material film layer and affecting the electrical performance. SUMMARY

[0003] The present application provides a semiconductor device, a preparation method and an electronic device to improve the filling quality of the dielectric material film layer and improve the electrical performance of the device.

[0004] In a first aspect, the embodiments of the present application provide a preparation method of a semiconductor device. The semiconductor device includes a substrate, a first spacer dielectric layer and a set structure in the first spacer dielectric layer formed on the substrate. The set structure is a trench or a via. The method includes: placing the substrate with the first spacer dielectric layer in an atomic layer deposition (ALD) reaction chamber, and filling a second spacer dielectric layer in the set structure by using an ALD process. For the process of filling the second spacer dielectric layer in the set structure, the following process can be included: first, a reactant containing a first element is introduced into the reaction chamber, the reactant reacts with hydroxyl groups on the surface of the set structure material to perform monolayer adsorption containing the first element. Then, a purge gas is used to purge the reaction chamber to blow away the unreacted reactant or other impurity products in the reaction chamber. Then, water or oxygen plasma is introduced into the reaction chamber, the water or oxygen plasma reacts with the monolayer containing the first element to form an oxide dielectric material containing the first element, and the surface of the oxide dielectric material has hydroxyl groups. Then, a purge gas is used to purge the reaction chamber to blow away the unreacted water or oxygen plasma or other impurity products in the reaction chamber. Then, one or more times of the above steps can be performed to form an oxide dielectric material with a desired thickness. Then, a Bronsted acid or an aminosilane is introduced into the reaction chamber, the Bronsted acid or the aminosilane reacts with the hydroxyl groups on the surface of the oxide dielectric material, and after the reaction is completed, the concentration of the hydroxyl groups near the bottom of the set structure is higher than the concentration of the hydroxyl groups near the top of the set structure to occupy part of the growth sites where the hydroxyl groups are located. Then, when the oxide dielectric material is deposited, the deposition rate of the oxide dielectric material in the region near the bottom of the set structure is fast, and the deposition rate of the oxide dielectric material in the region near the top of the set structure is slow, so that the oxide dielectric material gradually forms a "V" shaped growth effect. Based on this, the above steps are performed until the second spacer dielectric layer is formed, so that the seamless filling of the oxide dielectric material is realized, thereby improving the filling quality of the oxide dielectric material and improving the electrical performance of the device.

[0005] Since the Bronsted acid can be an inorganic material and an organic material, the acidity of the inorganic material is generally higher than that of the organic material. In order to avoid the adverse effects of too strong acidity on the semiconductor device, in some embodiments, the Bronsted acid is set as an organic material to improve the safety of the device.

[0006] In some embodiments, the organic material can be one or more of acetic acid, acetylacetone, and ethanol.

[0007] Al2O3 is a common oxide medium material in the process, in some embodiments, the first element is aluminum element, and the oxide medium material is Al2O3. Based on this, in the process of filling Al2O3 in the set structure by using the ALD process, the reactant containing the aluminum element (i.e., the aluminum source) usually occupies the position of the hydroxyl group on the surface of the material. In the embodiments of the present application, a Bronsted acid or an amino silane can be used to occupy part of the position of the hydroxyl group on the surface of the material, thereby inhibiting the growth of Al2O3, so as to control the growth rate of Al2O3 in the ALD process, achieve fast deposition of Al2O3 in the bottom region close to the set structure, slow deposition of Al2O3 in the top region close to the set structure, realize seamless filling of Al2O3 in the COAG process, and thus improve the filling quality of Al2O3 and improve the electrical performance of the device.

[0008] In some embodiments, the oxide medium material containing the first element can also be set as other materials. For example, the first element is set as other metal elements, for example, the first element is hafnium element, and the oxide medium material is HfO2. Alternatively, the first element is set as non-metal elements, for example, the first element is silicon element, and the oxide medium material is SiO2.

[0009] In order to further realize the seamless filling of the oxide medium material, in some embodiments, in the direction from the bottom of the set structure to the top of the set structure, the concentration of the hydroxyl group can be distributed from high to low, so that the remaining hydroxyl group gradually transitions, so that the deposition rate of the oxide medium material gradually decreases in the direction from the bottom of the set structure to the top of the set structure, and the seamless filling of the oxide medium material is further realized.

[0010] In some embodiments, in the direction from the bottom of the set structure to the top of the set structure, the set structure includes a first region and a second region, and the first region is located between the second region and the substrate. In the direction from the bottom of the set structure to the top of the set structure, the region where the hydroxyl group is located in the first region is in a non-continuous distribution, so that the growth sites where the hydroxyl group is located in the first region are not completely occupied, so that the oxide medium material can be preferentially formed in the growth sites where the hydroxyl group is not occupied by the occupation compound in the first region, and the effect that the deposition rate of the oxide medium material is fast in the region close to the bottom of the set structure and the deposition rate of the oxide medium material is slow in the region close to the top of the set structure is further ensured.

[0011] In some embodiments, in the direction from the bottom of the set structure to the top of the set structure, the growth sites where the hydroxyl group is located in the second region can be completely occupied, further reducing the deposition rate of the oxide medium material in the region close to the top of the set structure.

[0012] In some embodiments, the second spacer dielectric layer can also not distinguish the first region and the second region, but in the direction from the bottom of the set structure to the top of the set structure, the region where the hydroxyl group is located is discontinuously distributed.

[0013] In some embodiments, the substance generated by the reaction of the Bronsted acid or the amino silane with the hydroxyl group can be removed by H2or O2plasma treatment to reduce the content of C or N impurities in the second spacer dielectric layer.

[0014] In some embodiments, after filling the second spacer dielectric layer in the set structure, the method further comprises: patterning the second spacer dielectric layer to form a contact hole in the second spacer dielectric layer; and filling a conductive material in the contact hole to form a conductive part to transmit a signal.

[0015] In a second aspect, the embodiments of the present application further provide a semiconductor device prepared by the preparation method in the first aspect, the semiconductor device comprising: a substrate, a first spacer dielectric layer and a second spacer dielectric layer, wherein the first spacer dielectric layer is arranged on the substrate, the first spacer dielectric layer has a set structure, and the set structure is a groove or a via. The second spacer dielectric layer is arranged in the set structure. Moreover, the second spacer dielectric layer formed based on the preparation method in the first aspect has no gap in a TEM image.

[0016] In the second aspect, the preparation process and the formed structure of each embodiment can refer to the related description of each embodiment in the first aspect, and specific details are not repeated here. Moreover, the technical effects of the corresponding solutions in the second aspect can refer to the technical effects of the corresponding solutions in the first aspect, and the details are not repeated here.

[0017] In a third aspect, the embodiments of the present application further provide an electronic device, which comprises a circuit board and the semiconductor device in the second aspect or any one of the embodiments of the second aspect, and the semiconductor device is arranged on the circuit board. Exemplarily, the electronic device includes, but is not limited to, a terminal device, a communication device, etc. The terminal device includes, but is not limited to, a mobile phone, a computer, a television, a television set-top box, a watch, a personal computer (PC), a wearable device, a workstation, etc. The communication device includes, but is not limited to, a wireless network device, a fixed network device, a server, a smart broadband device, etc.

[0018] In addition, the technical effects of the corresponding solutions in the third aspect can refer to the technical effects of the corresponding solutions in the first aspect to the second aspect, and the details are not repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of the electronic device in the embodiments of the present application.

[0020] Figure 2 A structure schematic diagram of a semiconductor device in an embodiment of the present application;

[0021] Figure 3 A flow chart of a preparation method of a semiconductor device provided in an embodiment of the present application;

[0022] Figures 4a to 4d A structure schematic diagram of a semiconductor device in an embodiment of the present application;

[0023] Figure 5 A structure schematic diagram of a semiconductor device in an embodiment of the present application;

[0024] Figure 6a A structure schematic diagram of a field effect transistor in an embodiment of the present application;

[0025] Figure 6b A structure schematic diagram of a field effect transistor in an embodiment of the present application.

[0026] Reference signs

[0027] 100 - housing; 200 - circuit board; 300 - semiconductor device; 310 - substrate; 320 - first interval medium layer; 330 - second interval medium layer; GK - via hole; 340 - conductive structure; 350 - conductive part; 361 - channel; 362 - gate structure; 363 - gate side wall; 364 - gate cap layer; 365 - source-drain layer; 366 - source-drain cap layer; 367 - gate contact part; 368 - source-drain contact part; 431 / 432 / 433 - Al2O3 film layer; BS1 - first region; BS2 - second region; CK - contact hole. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings. The specific operation method in the method embodiment can also be applied to the device embodiment or the system embodiment. It should be noted that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, "first", "second", etc. are used only for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying order.

[0029] It should be noted that the same reference signs in the drawings of the present application represent the same or similar structures, and thus repeated description thereof will be omitted. The words expressing position and direction described in the present application are described with reference to the drawings, but can be changed as needed, and the changes made are included in the scope of protection of the present application. The drawings of the present application are only used to show the relative positional relationship and do not represent the true proportion.

[0030] The semiconductor device provided by the embodiments of the present application can be various electronic devices or integrated circuit devices for realizing certain function or functions, wherein the electronic devices or integrated circuit devices include but are not limited to device modules, storage circuits, logic circuits, power devices, artificial intelligence chips, etc. Moreover, the electronic devices or integrated circuit devices can be widely applied in various electronic equipment, wherein the electronic equipment includes but is not limited to terminal equipment, communication equipment, etc. The terminal equipment includes but is not limited to mobile phones, computers, televisions, television set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. The communication equipment includes but is not limited to wireless network equipment, fixed network equipment, servers, intelligent broadband equipment, etc. It can be understood that the specific implementation of the electronic equipment can be determined according to the actual application scenario, which is not limited herein.

[0031] Figure 1 A structural schematic diagram of an electronic equipment in the embodiments of the present application is shown in FIG. 1. Referring to FIG. 1, Figure 1 The electronic equipment includes a housing 100, a circuit board 200 arranged in the housing 100, and a semiconductor device 300 fixed on the circuit board 200. The semiconductor device 300 and the circuit board 200 can be connected by bonding, binding, etc. to realize electrical connection between the semiconductor device 300 and the circuit board 200, so that the semiconductor device 300 and the circuit board 200 can transmit signals. Exemplarily, the circuit board 200 includes but is not limited to a printed circuit board (PCB).

[0032] Figure 2 A structural schematic diagram of a semiconductor device in the embodiments of the present application is shown in FIG. 2. Referring to FIG. 2, Figure 2The semiconductor device in the embodiments of the present application can include a substrate 310, a first spacer dielectric layer 320, and a second spacer dielectric layer 330. The first spacer dielectric layer 320 is arranged on the substrate 310 and has a set structure GK. The second spacer dielectric layer 330 is arranged in the set structure GK. The set structure GK can be a trench or a via. For example, the aspect ratio of the trench or the via is greater than or equal to 2:1. For example, the aspect ratio of the trench or the via is 5:1, 10:1, 20:1, or 50:1. The feature size of the trench or the via is greater than or equal to 5 nm. For example, the feature size of the trench or the via is 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm. It can be understood that the embodiments of the present application take the trench as an example to illustrate the set structure. The implementation of the via as the set structure can refer to the implementation of the trench as the set structure, and the following description will not be repeated.

[0033] In addition, the material of the second spacer dielectric layer 330 and the first spacer dielectric layer 320 is a dielectric material. In order to achieve etching selection, the material of the second spacer dielectric layer 330 and the first spacer dielectric layer 320 is different. Further, the material of the second spacer dielectric layer 330 and the first spacer dielectric layer 320 can have a higher etching selection ratio, so that high selectivity can be achieved in the etching process.

[0034] The material of the first spacer dielectric layer 320 can include silicon nitride, silicon oxynitride, silicon oxycarbide, or the like.

[0035] The material of the second spacer dielectric layer 330 includes an oxide dielectric material containing a first element. In the process of filling the oxide dielectric material by ALD process, the oxide dielectric material needs to occupy the growth site of the hydroxyl on the material surface. In the embodiments of the present application, a Bronsted acid or an aminosilane reacts with the hydroxyl to occupy the growth site of the hydroxyl, so that the oxide dielectric material is not easy to form at the growth site, and the conformality of the oxide dielectric material is changed. In addition, in the process of filling the oxide dielectric material by ALD process, the concentration of the hydroxyl near the bottom of the set structure GK is controlled to be higher than the concentration of the hydroxyl near the top of the set structure GK, so that the growth site of the hydroxyl in the bottom region of the set structure GK is higher than the growth site in the top region of the set structure GK. Then, when the oxide dielectric material is deposited, the deposition rate of the oxide dielectric material in the region near the bottom of the set structure GK is fast, and the deposition rate of the oxide dielectric material in the region near the top of the set structure GK is slow, so that the oxide dielectric material gradually forms a "V" shaped growth effect, realizes seamless filling of the oxide dielectric material, and improves the filling quality of the oxide dielectric material and the electrical performance of the device.

[0036] It can be understood that the bottom of the setting structure GK refers to the side of the setting structure GK facing the substrate, and the top of the setting structure GK refers to the side of the setting structure GK facing away from the substrate.

[0037] The application will be further described below with reference to the embodiments.

[0038] In some examples, in the process of filling the oxide dielectric material in the setting structure GK by using the ALD process, the Bronsted acid can combine with the growth sites where the hydroxyl groups on the surface of the material, an acid-base neutralization displacement reaction occurs, and the growth sites occupied by the carboxyl groups are formed.

[0039] Al2O3 is a common oxide dielectric material in the process, and in the embodiments of the application, the oxide dielectric material can be Al2O3. Based on this, in the process of filling Al2O3 in the setting structure GK by using the ALD process, the reactant containing aluminum elements (i.e. aluminum source) usually occupies the sites of the hydroxyl groups on the surface of the material, and in the embodiments of the application, the Bronsted acid can be used to occupy part of the sites of the hydroxyl groups on the surface of the material, to inhibit the growth of Al2O3, so as to control the growth rate of Al2O3 in the ALD process, achieve fast deposition of Al2O3 in the region close to the bottom of the setting structure GK, slow deposition of Al2O3 in the region close to the top of the setting structure GK, and realize seamless filling of Al2O3 in the COAG process, thereby improving the filling quality of Al2O3 and improving the electrical performance of the device.

[0040] Since the Bronsted acid can have inorganic materials and organic materials, and the acidity of inorganic materials is usually higher than that of organic materials, in order to avoid the adverse effects of too strong acidity on semiconductor devices, in the embodiments of the application, the Bronsted acid is set to an organic material to improve the safety of the device. Further, the organic material is not limited in the embodiments of the application, for example, the organic material can be one or more of acetic acid, acetylacetone and ethanol.

[0041] The application will be further described below with reference to the embodiments. Figure 3 The preparation method provided in the embodiments of the application is described. Among them, Figure 3 The flow chart of a preparation method of the semiconductor device provided in the embodiments of the application. The preparation method provided in the embodiments of the application can include the following processes:

[0042] S110, forming a first interval dielectric layer and a setting structure in the first interval dielectric layer on a substrate.

[0043] Exemplarily, with reference to Figure 4a , Figure 4aA structure diagram of a semiconductor device in the preparation process of an embodiment of the present application is shown in FIG. 1. A first spacer dielectric layer 320 is deposited on a substrate 310 by using a deposition process such as ALD, CVD, etc. Then, an etching process is used to form a trench in the first spacer dielectric layer 320. Exemplarily, the substrate 310 can be made of a suitable elemental semiconductor such as silicon, diamond or germanium; a suitable alloy or compound semiconductor such as a group IV compound semiconductor (e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), a group III-V compound semiconductor (e.g., gallium arsenide, indium gallium arsenide, indium arsenide, indium phosphide, indium antimony, gallium arsenide phosphide or indium gallium phosphide), etc. A group IV semiconductor material doped with a group III or group V, e.g., SiP / SiGe:B. An insulating material such as glass can also be used as the substrate. Exemplarily, a Si substrate is used as an example in the present application.

[0044] In S120, the substrate with the first spacer dielectric layer is placed in an atomic layer deposition reaction chamber, and an atomic layer deposition process is used to alternately deposit an oxide dielectric material and a space-occupying compound to fill the second spacer dielectric layer in the set structure.

[0045] Exemplarily, the step S120 can include the following steps:

[0046] (1), refer to Figure 4b , Figure 4b A structure diagram of another semiconductor device in the preparation process of an embodiment of the present application is shown in FIG. 2. The substrate 310 with the first spacer dielectric layer 320 is placed in an ALD reaction chamber, and trimethylaluminum (TMA) as an aluminum source is introduced into the reaction chamber. The TMA is adsorbed on the hydroxyl group on the surface of the material and reacts with it, so that the aluminum completes monolayer adsorption on the surface of the trench. After sufficient adsorption, a purge gas is used to purge the reaction chamber, and the unreacted aluminum source or other impurity products in the reaction chamber are blown away. Then, water (or oxygen plasma) is introduced into the reaction chamber, and the monolayer Al2O3 is generated through the corresponding reaction of the water and the Al-containing monolayer. After sufficient reaction, a purge gas is used to blow away the unreacted water and CH4 in the reaction chamber. Then, one or more times of the above steps can be performed to form an Al2O3 film layer 431 with a desired thickness (e.g., 2-10 nm). The Al2O3 film layer 431 not only covers the surface of the bottom and sidewall of the trench, but also covers the surface of the side of the first spacer dielectric layer 320 away from the substrate 310.

[0047] (2), refer to Figure 4c , Figure 4cThis is another structural schematic diagram of the semiconductor device in the embodiment of this application during the fabrication process. Acetylacetone, which is a Brønsted acid, is introduced into the reaction chamber, so that the acetylacetone reacts with the hydroxyl groups on the surface of the Al2O3 film 431 material. The reaction formula is: -OH+C5H8O2→(C5H7O2). -1 +H₂O, -OH represents hydroxyl groups. Furthermore, by controlling process parameters, the concentration of hydroxyl groups can be controlled to decrease from high to low in the direction from the bottom to the top of the trench. For example, by controlling the introduction rate and time of Brønsted acid, since the top of the trench is more easily approached by Brønsted acid than the bottom, the adsorbed Brønsted acid can be increased in the direction from the bottom to the top of the trench, thus ensuring that the concentration of the remaining hydroxyl groups decreases from high to low in the direction indicated by arrow F0 after the reaction is complete. Afterwards, unreacted organic materials or other impurity products in the reaction chamber are blown away using purge gas. Exemplarily, not only is (C₅H₇O₂) adsorbed on the surface of the Al₂O₃ film layer 431 on the trench sidewalls... -1 The surface of the Al2O3 film 431 on the side of the first spacer layer 320 facing away from the substrate 310 is also adsorbed with (C5H7O2). -1 Furthermore, the surface of the Al2O3 film 431 at the bottom of the trench can adsorb (C5H7O2). -1 It is also possible that there is no adsorption of (C5H7O2). -1 .in, Figure 4c In the middle, 331 represents the adsorbed (C5H7O2). -1 .

[0048] To further achieve seamless filling of oxide dielectric materials, refer to Figure 4c In the direction from the bottom of the set structure GK to the top of the set structure GK (i.e., the direction pointed to by arrow F0), (C5H7O2) based on Brønsted acid adsorption can be made in the second spacer medium layer 330. -1 The concentration of 331 is distributed from low to high, so after the reaction is completed, the concentration of the remaining hydroxyl groups is distributed from high to low in the direction indicated by the F0 arrow, thereby gradually reducing the deposition rate of the oxide medium material in the direction indicated by the arrow F0, and further achieving seamless filling of the oxide medium material.

[0049] Exemplarily, the trench can have a first region BS1 and a second region BS2 in the direction indicated by the arrow F0, and the first region BS1 is located between the second region BS2 and the substrate 310. In the direction from the bottom of the set structure GK to the top of the set structure GK (i.e., the direction indicated by the arrow F0), the region where the remaining hydroxyl groups in the first region BS1 are located is discontinuously distributed, so that the growth sites where the hydroxyl groups are located in the first region BS1 are not completely occupied by the Bronsted acid, i.e., the adsorbed (C5H7O2) -1 occupy the growth sites where the hydroxyl groups are located in the first region BS1, so that the oxide dielectric material can be preferentially formed in the growth sites where the hydroxyl groups in the first region BS1 are not occupied by the occupation compound, further ensuring the effect that the deposition rate of the oxide dielectric material is fast in the region close to the bottom of the set structure GK and the deposition rate of the oxide dielectric material is slow in the region close to the top of the set structure GK. In addition, in the direction from the bottom of the set structure GK to the top of the set structure GK (i.e., the direction indicated by the arrow F0), the adsorbed (C5H7O2) -1 may be continuously distributed, further reducing the deposition rate of the oxide dielectric material in the region close to the top of the set structure GK.

[0050] It is worth mentioning that the second spacer dielectric layer 330 can also not distinguish the first region BS1 and the second region BS2, and in the direction from the bottom of the set structure GK to the top of the set structure GK (i.e., the direction indicated by the arrow F0), the adsorbed (C5H7O2) -1 is discontinuously distributed. Alternatively, the region close to the bottom of the set structure GK does not contain the adsorbed (C5H7O2) -1 .

[0051] (3), referring to Figure 4d , Figure 4d is another schematic structural diagram of a semiconductor device in the preparation process in the embodiment of the present application, and the process of step (1) is performed. Due to the action of the adsorbed (C5H7O2) -1 , the deposition of Al2O3 at the bottom of the trench is fast, the deposition of Al2O3 at the top of the trench is slow, and then the Al2O3 film layer 432 is formed. Then, the process of step (2) to step (1) is repeated to form the Al2O3 film layer 433. Based on this, the ALD process can be used to form the second spacer dielectric layer without gaps. It can be understood that in actual application, the processes of step (1) and step (2) can be repeated multiple times to fill the trench and form the second spacer dielectric layer 330.

[0052] It is understood that the aluminum source is not limited to trimethylaluminum (TMA), and can also be isopropyl alcohol dimethylaluminum (DMAI) and the like, which are not limited herein. Further, the purge gas includes, but is not limited to, an inert gas. Further, the process of step (2) can also be performed before step (1) is performed. In addition, the adsorbed (C5H7O2) -1 The C or N impurities in the second spacer dielectric layer can also be removed by means of H2or O2plasma treatment to reduce the content of C or N impurities in the second spacer dielectric layer.

[0053] Example 2: The difference between the example 2 and the foregoing example 1 is that the Bronsted acid is ethanol (EtOH), and the EtOH reacts with the hydroxyl groups on the surface of the Al2O3film layer 431 material, and the reaction formula is: -OH (s) + EtOH (g) → -OEt (s) + H2O (g), -OH represents a hydroxyl group.

[0054] Example 3: The difference between the example 3 and the foregoing example 1 is that the Bronsted acid is acetic acid.

[0055] Example 4: The difference between the example 4 and the foregoing example 1 is that the reactant containing the first element introduced into the reaction chamber in step (2) is aminosilane, so as to combine the aminosilane with the sites of the hydroxyl groups on the surface of the material, dehydrogenate the hydroxyl groups on the surface of the material through the aminosilane branch, and adsorb on the surface of the material, so as to control the concentration of the hydroxyl groups to be distributed from high to low in the direction from the bottom of the trench to the top of the trench.

[0056] Exemplarily, the aminosilane introduced into the reaction chamber in step (2) can be bis(dimethylamino)dimethylsilane (DMADMS), so as to react the DMADMS with the hydroxyl groups on the surface of the material, and the reaction formula is: 2Al-OH + C6H 18 N2Si → 2Al-O-Si (CH3) 2 + 2NH (CH3) 2, wherein, Al-OH represents an Al-OH bond.

[0057] Example 5: The difference between the example 5 and the foregoing example 4 is that the aminosilane can be dimethylaminotrimethylsilane (DMTMS).

[0058] Comparative Example 1: The difference between the comparative example 1 and the foregoing example 1 is that the material of the second spacer dielectric layer is Al2O3.

[0059] Transmission electron microscopy (TEM) was used to test cross-sections at the same location in Examples 1 to 5 and Comparative Example 1, resulting in TEM images of Examples 1 to 5 and Comparative Example 1. These TEM images show that by using Brønsted acid to occupy some of the hydroxyl sites on the material surface and controlling the growth rate of Al2O3 during the ALD process, the second spacer dielectric layer 330 formed by filling is seamless, thus achieving seamless filling of Al2O3, improving the filling quality of Al2O3, and enhancing the electrical performance of the device.

[0060] It is worth mentioning that the oxide dielectric material containing the first element can also be other materials. For example, the first element can be other metallic elements, such as hafnium, in which case the oxide dielectric material is HfO2. Alternatively, the first element can be a non-metallic element, such as silicon, in which case the oxide dielectric material is SiO2.

[0061] Figure 5 This is another schematic diagram of the semiconductor device in the embodiments of this application, referring to... Figure 5 The semiconductor device in this embodiment is a modification of the semiconductor device in the above embodiments. The similarities are not repeated here, but the differences are: it also includes a conductive structure 340 and a contact hole CK. The conductive structure 340 is located between the second spacer dielectric layer 330 and the substrate 310. The conductive structure 340 is covered by the second spacer dielectric layer 330, and the structure CK is set to expose a portion or all of the surface of the conductive structure 340 facing away from the substrate 310. Furthermore, the conductive structure 340 can be surrounded by the first spacer dielectric layer 320 or located between the first spacer dielectric layer 320 and the substrate 310. The contact hole CK penetrates the second spacer dielectric layer 330 and is used to expose a portion of the surface of the conductive structure 340 facing away from the substrate 310. Additionally, the contact hole CK is filled with a conductive portion 350, which is electrically connected to the conductive structure 340 to transmit signals. During fabrication, the second spacer dielectric layer 330 is patterned after step S102 to form the contact hole CK. The contact hole CK is then filled with a conductive material (e.g., metal) to form the conductive part 350.

[0062] Exemplarily, a field effect transistor (FET) is formed on the substrate. For example, the FET includes one or more of a fin field effect transistor (Fin FET), a gate all around field effect transistor (GAAFET), a fork sheet (FS) field effect transistor, and a complementary field effect transistor (CFET).

[0063] After the semiconductor device is prepared, a dielectric layer is prepared, and a metal interconnection layer in a back-end-of-line is prepared on the dielectric layer. The interconnection between semiconductor devices and the interconnection between the semiconductor device and other signal lines are completed through the conductive portion 350. Exemplarily, the conductive structure 340 is one of a source, a drain, and a gate of the FET; or the conductive structure 340 is a metal wire of an interconnection structure, and the conductive structure 340 can also be another conductive structure 340, which is not limited herein.

[0064] Exemplarily, a Fin FET is taken as an example for description.

[0065] Figure 6a FIG. 1 is a structure diagram of a field effect transistor according to an embodiment of the present application, Figure 6b FIG. 2 is another structure diagram of a field effect transistor according to an embodiment of the present application, referring to Figure 6a and Figure 6bThe field-effect transistor includes: a channel 361 (e.g., a fin channel), a gate structure 362, a gate sidewall 363, a gate capping layer 364, a source-drain layer 365, and a source-drain capping layer 366. The gate structure 362 is located on a substrate 310 and covers the channel region of the channel 361. The gate sidewall 363 is located on both sides of the gate structure 362 and covers the region of the channel 361 other than the channel region. The gate capping layer 364 is located on the side of the gate structure 362 facing away from the substrate 310 and covers the gate structure 362. The gate sidewall 363 also covers part or all of the sidewall of the gate capping layer 364. The source-drain layer 365 is located on both sides of the channel 361 and is electrically connected to both sides of the channel 361. The source-drain capping layer 366 is located on the side of the source-drain layer 365 facing away from the substrate 310 and covers the source-drain layer 365. For example, the gate sidewall 363 also covers a portion of the sidewall of the gate capping layer 364, and the source / drain capping layer 366 also covers the surface of the gate sidewall 363 facing away from the substrate 310, and the source / drain capping layer 366 also covers the area of ​​the sidewall of the gate capping layer 364 not covered by the gate sidewall 363. Alternatively, the gate sidewall 363 may cover the entire sidewall of the gate capping layer 364, and the source / drain capping layer 366 may not cover the surface of the gate sidewall 363 facing away from the substrate 310, but rather the source / drain capping layer 366 is in contact with the sidewall of the gate sidewall 363.

[0066] The field-effect transistor also includes a gate contact 367, which penetrates the gate cap layer 364 and connects to the gate structure 362. This configuration allows for the interconnection between the gate structure 362 and the metal interconnect layer using a COAG process, enabling signal transmission. Exemplarily, the gate structure 362 may include a gate dielectric layer and a gate conductive layer, with the gate dielectric layer located between the gate conductive layer and the channel 361. Further, the gate structure 362 may be configured as a high-k metal gate (HKMG), in which case the gate structure 362 may include a gate dielectric layer, a high-k dielectric layer, and a gate conductive layer. Of course, one or more of a work function layer and a pad layer may also be disposed between the high-k dielectric layer and the gate conductive layer.

[0067] The second spacer dielectric layer 330 can be configured as a gate cap layer 364, wherein, as referenced Figure 6a The first spacer dielectric layer 320 can be a combination of a gate sidewall 363 and a source / drain cap layer 366. Alternatively, refer to... Figure 6b The first spacer dielectric layer 320 can be a gate sidewall 363. With this configuration, the gate cap layer 364 can be formed using the above-described fabrication method, achieving seamless filling of the gate cap layer 364.

[0068] The field effect transistor further includes a source-drain contact 368, which penetrates the source-drain cap layer 366 and is connected with the source-drain layer 365, so that the interconnection between the source-drain layer 365 and the metal interconnection layer can be achieved, and the transmission signal can be achieved. Exemplarily, the source-drain layer 365 can include an epitaxial doped layer 3651 and a metal layer (for example, Li) 3652, the epitaxial doped layer 3651 is located between the metal layer 3652 and the substrate 310, and the epitaxial doped layer 3651 is in direct contact with the channel 361.

[0069] The second spacer medium layer 330 can be provided as the source-drain cap layer 366, wherein, referring to Figure 6a , the first spacer medium layer 320 can be the gate cap layer 364. Alternatively, referring to Figure 6b , the first spacer medium layer 320 can be the gate side wall 363. Thus, the source-drain cap layer 366 can be formed by using the preparation method described above, and the seamless filling of the source-drain cap layer 366 can be achieved.

[0070] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The semiconductor device comprises a substrate and a first spacer dielectric layer formed on the substrate, the first spacer dielectric layer having a set structure, which is a trench or a via; The method comprises: placing the substrate with the first spacer dielectric layer in an atomic layer deposition reaction chamber, and filling a second spacer dielectric layer in the set structure by using an atomic layer deposition process; The filling of the second spacer dielectric layer in the set structure comprises: introducing a reactant containing a first element into the reaction chamber, the reactant reacting with the hydroxyl group on the surface of the set structure material; purging the reaction chamber with a purge gas; introducing water or oxygen plasma into the reaction chamber to form an oxide dielectric material containing the first element, and the surface of the oxide dielectric material has a hydroxyl group; purging the reaction chamber with a purge gas; After one or more times of the above steps, a Bronsted acid or an aminosilane is introduced into the reaction chamber, the Bronsted acid or the aminosilane reacts with the hydroxyl group on the surface of the oxide dielectric material, and after the reaction is completed, the concentration of the hydroxyl group near the bottom of the set structure is higher than that near the top of the set structure; This is repeated until the second spacer dielectric layer is formed.

2. The production method according to claim 1, wherein The Bronsted acid is an organic material.

3. The production method according to claim 2, wherein The organic material includes one or more of acetic acid, acetylacetone, and ethanol.

4. The production method according to claim 1, wherein The aminosilane includes one or more of bis(dimethylamino)dimethylsilane and dimethylaminotrimethylsilane.

5. The production method according to any one of claims 1 to 4, wherein The first element is an aluminum element, and the oxide dielectric material is Al2O3; or, The first element is a hafnium element, and the oxide dielectric material is HfO2; or, The first element is a silicon element, and the oxide dielectric material is SiO2.

6. The production method according to any one of claims 1 to 5, wherein In a direction from the bottom of the set structure to the top of the set structure, the concentration of the hydroxyl group is distributed from high to low.

7. The production method according to claim 6, wherein The second spacer dielectric layer includes a first region and a second region, and the first region is located between the second region and the substrate; In a direction from the bottom of the set structure to the top of the set structure, the region where the hydroxyl group is located is discontinuously distributed.

8. The production method according to any one of claims 1 to 7, wherein After the second spacer dielectric layer is filled in the set structure, the method further comprises: patterning the second spacer dielectric layer to form a contact hole in the second spacer dielectric layer; filling a conductive material in the contact hole.

9. A semiconductor device produced by the production method according to any one of claims 1 to 8, characterized by It comprises: a substrate; a first spacer dielectric layer disposed on the substrate, the first spacer dielectric layer having a set structure, which is a trench or a via; a second spacer dielectric layer disposed in the set structure; In a TEM image, the second spacer dielectric layer has no gap.

10. The semiconductor device of claim 9, wherein, A field effect transistor is formed on the substrate, and the field effect transistor comprises: a channel; a gate structure located on the substrate and covering a channel region of the channel; a gate sidewall located on both sides of the gate structure and covering a region of the channel other than the channel region; a gate structure located on the substrate and covering a channel region of the channel; a gate cap layer on a side of the gate structure facing away from the substrate and covering the gate structure, the gate sidewall further covering at least a portion of a sidewall of the gate cap layer; a source / drain layer on both sides of the channel; a source / drain cap layer on a side of the source / drain layer facing away from the substrate and covering the source / drain layer; the field effect transistor further comprising a gate contact and / or a source / drain contact, the gate contact penetrating the gate cap layer and being connected to the gate structure, the source / drain contact penetrating the source / drain cap layer and being connected to the source / drain layer; wherein the second spacer layer is the gate cap layer or the source / drain cap layer, and the first spacer layer comprises the gate sidewall.

11. An electronic device, comprising: comprising: a circuit board and a semiconductor device as claimed in claim 9 or 10, the semiconductor device being arranged on the circuit board.

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