An optical proximity correction optimization method

By dividing the layout into small blocks and optimizing the target culprit graphic, the problem of EPE inconsistency in optical proximity effect correction was solved, the convergence of OPC correction results was achieved, and the product yield was improved.

CN121069711BActive Publication Date: 2026-02-03NEXCHIP SEMICON CO LTD
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Patent Information

Application Number
CN202511544772.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-10-28
Publication Date
2026-02-03
Estimated Expiration
2045-10-28

AI Technical Summary

Technical Problem

During the optical proximity effect correction process, the different OPC correction parameters of adjacent small blocks lead to inconsistent EPE in the overlapping area, resulting in non-convergence of verification results and affecting product yield.

Method used

The initial map is divided into small blocks, including the main graphic area and the extended area. Each small block overlaps with the adjacent small blocks. OPC correction and simulation verification are performed on each small block to identify the suspected murderer graphic and optimize the target murderer graphic to form an intermediate map. Finally, OPC correction is performed.

Benefits of technology

This significantly reduces EPE at the edges of small regions, solves the problem of non-convergence of OPC correction verification results, and improves product yield.

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Abstract

The application provides an optical proximity correction optimization method, comprising the following steps: providing an initial layout, dividing the initial layout into a plurality of small blocks, the small blocks comprising a main pattern area and an extension area surrounding the main pattern area, each of the small blocks overlapping with the extension area of the adjacent small blocks; performing OPC correction and simulation verification on each of the small blocks, and obtaining problem patterns and a plurality of suspected culprit patterns in the overlapping area between two adjacent small blocks in the simulation verification pattern; finding out target culprit patterns causing the problem patterns from all the suspected culprit patterns; optimizing the target culprit patterns in all the small blocks to obtain an intermediate layout; and performing OPC correction on the intermediate layout to greatly reduce the EPE at the edge of the small area, thereby solving the problem of non-converged verification result of OPC correction.
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Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an optical proximity correction (OPC) optimization method. Background Technology

[0002] As process nodes continue to shrink, Optical Proximity Correction (OPC) has become widely used in integrated circuit design. To accelerate OPC correction efficiency, the software typically divides the design pattern into several small templates, and these different templates can be calculated simultaneously by the software. For example... Figure 1 As shown, each small block includes a main graphic region and an extended region extending outward from the main region. The overlapping area between two adjacent small blocks includes their respective extended regions. For example, small block 1 includes the main graphic region MA1 and the extended region slot1, and small block 2 includes the main graphic region MA2 and the extended region slot2. The extended region slot1 overlaps with the main graphic region MA2, and the extended region slot2 overlaps with the main graphic region MA1. During OPC correction, each small block simultaneously performs OPC correction on the main region of another small block. However, due to the different correction parameters of the two small blocks, the sizes of the two small blocks after OPC correction in the overlapping region are inconsistent. This results in an increase in EPE (Edge Placement Error) at the edges of the small blocks (i.e., the overlapping region), leading to a non-convergence problem in the verification results of OPC correction, which seriously affects the product yield. Summary of the Invention

[0003] The purpose of this invention is to provide an optical proximity effect correction optimization method that can reduce EPE at the edge of small regions and solve the problem of non-convergence of OPC correction results.

[0004] To address the above technical problems, this invention provides an optical proximity effect correction and optimization method, comprising the following steps:

[0005] An initial layout is provided, which is divided into several small blocks. Each small block includes a main graphic area and an extended area surrounding the main graphic area. Each small block overlaps with the extended area of ​​the adjacent small block.

[0006] For each of the aforementioned small blocks, OPC correction and simulation verification were performed, and in the simulation verification graph, problem graphs and several suspected culprit graphs appeared in the overlapping area between two adjacent small blocks;

[0007] Identify the target culprit image that caused the appearance of the problematic image from all the suspected culprit images;

[0008] Optimize the target perpetrator graphics in all the aforementioned small blocks to obtain an intermediate map;

[0009] The intermediate layout is modified using OPC.

[0010] Optionally, the main graphic area is rectangular in shape, and the extended area is a rectangular ring in shape.

[0011] Furthermore, the specific method for dividing the initial map into several small blocks includes:

[0012] The side length of the main graphic area is fixed, and the outer ring edge of the extended area is gradually expanded outward from the corresponding edge of the main graphic area by a preset length. After each expansion, the small block is corrected and simulated for verification. When the simulated EPE value in the overlapping area is greater than the designed EPE value, the expansion of the outer ring edge of the extended area is stopped to obtain the divided small block.

[0013] Furthermore, the specific method for dividing the initial map into several small blocks includes:

[0014] The outer side length of the extended region is fixed, and the edge of the main graphic region is gradually shrunk inward from the corresponding outer side of the extended region by a preset length. After each shrunk, the small block is corrected by OPC and simulated for verification. When the simulated EPE value in the overlapping region is greater than the designed EPE value, the shrunk of the main graphic region is stopped to obtain the divided small block.

[0015] Optionally, the overlapping area includes a Z-shaped pattern, on which the problem graphic is located.

[0016] Optionally, the suspected murderer graphic is a stepped line.

[0017] Furthermore, specific methods for identifying the target perpetrator's image include:

[0018] The graphic lines containing the problem graphic are fragmented to obtain several cutting points. Each cutting point is a small clipping region with a preset length interval between it and its adjacent cutting points.

[0019] Centered on all the cutting points in the problem image, the cutting points are projected in the direction of increasing EPE simulation value, and a parallel search is performed to find the suspected murderer image whose step edge is aligned with the cutting point as the target murderer image.

[0020] Furthermore, the small clipping area is square in shape.

[0021] Furthermore, specific methods for optimizing the target perpetrator image in all the aforementioned small blocks include:

[0022] Move the edge of the step in the target murderer graphic so that the edge of the step moves toward the main graphic area adjacent to the main graphic area where the target murderer graphic is located.

[0023] Optionally, specific methods for performing OPC corrections on the intermediate layout include:

[0024] The intermediate layout is corrected using OPC and then simulated for verification. If no problematic graphics appear in the overlapping areas in the verification results, the layout corrected using OPC will be used as the final layout.

[0025] Compared with the prior art, the present invention has the following unexpected technical effects:

[0026] This invention provides an optical proximity effect (OPE) correction and optimization method, comprising the following steps: providing an initial layout, dividing the initial layout into several small blocks, each small block including a main graphic region and an extended region surrounding the main graphic region, each small block overlapping with the extended region of an adjacent small block; performing OPC correction and simulation verification on each small block, and identifying problematic graphics and several suspected culprit graphics in the overlapping region between two adjacent small blocks in the simulation verification graphics; identifying the target culprit graphics causing the problematic graphics from all the suspected culprit graphics; optimizing the target culprit graphics in all the small blocks to obtain an intermediate layout; and performing OPC correction on the intermediate layout to significantly reduce EPE at the edges of small regions, thus solving the problem of non-convergence of OPC correction verification results. Attached Figure Description

[0027] Figure 1 This is a schematic diagram showing the locations of the two small blocks.

[0028] Figure 2 This is a schematic diagram of the original layout of the two small blocks.

[0029] Figure 3 for Figure 2 An enlarged view of the X-shaped diagram in the image.

[0030] Figure 4 This is a flowchart illustrating an optical proximity effect correction and optimization method according to an embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram showing the location of two adjacent small blocks according to an embodiment of the present invention.

[0032] Figure 6 The image shows a problem diagram and a suspected culprit diagram in the overlapping area of ​​two adjacent small blocks, as provided in an embodiment of the present invention.

[0033] Figure 7This is a method for modifying the image of the murderer provided in an embodiment of the present invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] Figure 1-3 Middle: 1, 2 - small blocks;

[0036] Figures 5-7 In the middle: 10, 20 - small blocks; 11, 21 - main graphic area; 12, 22 - extended area; 121, 221 - overlapping area; 30 - small clipping area; 40 - target murderer graphic. Detailed Implementation

[0037] The following will provide a more detailed description of an optical proximity effect correction and optimization method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0038] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0039] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0040] It needs to be explained that: in order to make it clear Figure 6 ,exist Figure 6 In the diagram, A1 is the straight line containing the edge of the overlapping area of ​​small block 20 and small block 10 in the main graphic area 11, A2 is the boundary line between the main graphic area 11 and the main graphic area 12, and A3 is the straight line containing the edge of the overlapping area of ​​small block 20 and small block 10 in the main graphic area 21.

[0041] The current method for optimizing the map layout is as follows:

[0042] First, the initial layout is divided into several small blocks. Then, OPC correction is performed on each small block. Next, simulation verification (OPCV) is performed on the OPC-corrected graphic to obtain the verification results. The verification results include the EPE (Edge Placement Error) at the edges of the small blocks (i.e., the overlapping area). When the simulated EPE value is greater than the EPE design value, the process returns to the step "Perform OPC Correction on Each Small Block". When the simulated EPE value is less than the EPE design value, the OPC graphic is the final layout that can be used to form a photomask.

[0043] like Figure 2 As shown, during the simulation verification process, a problematic graph X appeared in the overlapping area slot1. This problematic graph X appeared in the main graph area MA2, overlapping with the corrections for small block 1 and small block 2. After the two corrections, the superposition of the graphs in the main graph area MA1 resulted in the simulated EPE value being greater than the design EPE value (e.g., Figure 3 As shown in the figure, there is a problem, such as an EPE of 8.5nm, which means that the EPE (e.g., 8.5nm) increases at the edge of the small block. This causes the verification results of OPC correction to not converge, which seriously affects the product yield.

[0044] Figure 4 This is a flowchart illustrating an optical proximity effect correction and optimization method provided in this embodiment. Figure 4 As shown, this embodiment provides an optical proximity effect correction and optimization method, including the following steps:

[0045] Step S1: Provide an initial layout and divide the initial layout into several small blocks. Each small block includes a main graphic area and an extended area surrounding the main graphic area. Each small block overlaps with the extended area of ​​the adjacent small block.

[0046] Step S2: Correct and simulate the OPC of each cell block, and in the simulation verification graph, the problem graph and several suspected culprit graphs appear in the overlapping area between two adjacent cells;

[0047] Step S3: Identify the target culprit image that caused the appearance of the problematic image from all the suspected culprit images;

[0048] Step S4: Optimize the target murderer graphics in all the aforementioned small blocks to obtain an intermediate map;

[0049] Step S5: Perform OPC correction on the intermediate layout.

[0050] This embodiment can significantly reduce EPE at the edge of small regions by using the above method, thus solving the problem of non-convergence of verification results for OPC correction.

[0051] The following combination Figures 5-7 This embodiment provides a detailed description of an optical proximity effect correction and optimization method.

[0052] like Figure 5 As shown, step S1 is first executed to provide an initial layout, which is divided into several small blocks. Each small block includes a main graphic area and an extended area surrounding the main graphic area. Each small block overlaps with the extended area of ​​the adjacent small block.

[0053] This step specifically includes:

[0054] First, an initial layout is provided, and the software divides this initial layout into several small blocks. Each small block includes a main graphic area and an extended area surrounding the main graphic area. Each overlapping area includes the total area of ​​the extended areas of two adjacent small blocks within each other's main graphic area. Both the small blocks and the main graphic area are rectangular, and the extended areas are rectangular rings. See also... Figure 5 Taking two adjacent small blocks 10 and 20 in the first direction as an example, small block 10 includes a main graphic area 11 and an extended area 12, and small block 20 includes a main graphic area 21 and an extended area 22. The extended area 12 of small block 10 and the main graphic area 21 have an overlapping area 121, and the extended area 22 of small block 20 and the main graphic area 11 have an overlapping area 221. Therefore, the overlapping area between small block 10 and small block 20 includes the overlapping area 121 and the overlapping area 221.

[0055] The specific method for dividing the initial map into several small blocks is as follows: the software is designed with at least two methods for dividing the initial map (i.e., at least method one and method two). Specifically:

[0056] Method 1: Fix the side length of the main graphic area, and gradually expand the outer ring edge of the expansion area outward from the corresponding edge of the main graphic area by a preset length. During each expansion, OPC correction and simulation verification are required for the small block. During the simulation verification process, if the simulated EPE value in the overlapping area is less than the designed EPE value, the outer ring edge of the expansion area is further expanded; if the simulated EPE value in the overlapping area is greater than the designed EPE value, the expansion of the outer ring edge of the expansion area is stopped, and the divided small block is obtained. It should be noted that the preset length for each expansion can be the same or different, and can be adjusted according to actual needs.

[0057] Method Two: The outer edge length of the extended region is fixed, and the edges of the main graphic region are gradually shrunk inwards by a preset length from the corresponding outer edge of the extended region. During each shrunk, OPC correction and simulation verification are performed on the small blocks. During the simulation verification, if the simulated EPE value in the overlapping region is less than the designed EPE value, the edges of the main graphic region are further shrunk inwards; if the simulated EPE value in the overlapping region is greater than the designed EPE value, the shrunking of the main graphic region stops, and the divided small blocks are obtained. It should be noted that the preset shrunk length can be the same or different each time, and can be adjusted according to actual needs.

[0058] Next, step S2 is executed: OPC correction and simulation verification are performed on each of the small blocks, and problem graphics and several suspected culprit graphics appear in the overlapping area between two adjacent small blocks in the simulation verification graphics.

[0059] This step specifically includes the following steps:

[0060] First, locate the problematic graphic and several suspected culprit graphics within the overlapping area. The suspected culprit graphics are located near the problematic graphic and are adjacent to all other suspected culprit graphics in a direction perpendicular to the extension of the problematic graphic. At this point, there is at least one suspected culprit graphic. It has been found that the problematic graphic typically occurs in stepped graphics within the overlapping area, such as Z-shaped graphics.

[0061] like Figures 6-7 As shown, a problematic graphic appears in the Z-shaped graph of the overlapping area; specifically, a local line graphic in the Z-shaped graph where the simulated EPE value is greater than the designed EPE value. Figures 6-7 In the simulation, if the problem image extends along the first direction a, then the suspected culprit image appears along the second direction b, encompassing all suspected culprit images near the problem image. The suspected culprit images are straight lines in the initial image, but appear as stepped lines in the simulated image.

[0062] Next, step S3 is executed to identify the target culprit graphic from all the suspected culprit graphics. Specifically, the lines of the problematic graphic are fragmented to obtain several cutting points. These cutting points are small clipping regions with a preset length interval between adjacent cutting points. Then, using all the cutting points in the problematic graphic as centers, the cutting points are projected in the direction of increasing EPE simulation value, and a parallel search is performed to identify the suspected culprit graphic whose step edge aligns with the cutting points as the target culprit graphic. The small clipping region can be a 10μm*10μm square area.

[0063] by Figure 6Taking the example of the Z-shaped pattern in the overlapping area (such as...) as an example, Figure 3 Example of determining whether a suspected culprit graphic is the target culprit graphic: The problematic graphic appears on the line where the simulated EPE value is greater than the designed EPE value, and there is a stepped, suspected culprit graphic below the problematic graphic.

[0064] First, locate the corner points c1 and c2 of the Z-shaped figure; then, find an extension line Y parallel to the second direction extending from the edge of the suspected culprit figure's step. This extension line Y intersects with the line containing the problem figure. Locate this intersection point, such as... Figure 6 The intersection point is point B2.

[0065] Next, along the lines containing the problem image, starting from corner point c1 and moving towards intersection point B2, find the positions where the small clipping area 30 can be placed. Figure 6 First, starting from corner point c1, a small clipping region 30 is placed at the endpoint B1 of a line segment of length C. Then, corner point c2 is projected onto the line containing the problem figure. If the distance between the projections of point B1 and corner point c2 is less than the design value Lmin, no small clipping region 30 is placed at the projection of corner point c2. If the distance between the projections of point B1 and corner point c2 is between the design values ​​Lmin and Lmax, a small clipping region 30 needs to be placed at the projection of corner point c2. Then, starting from point B1, several points with lengths between the design values ​​Lmin and Lmax are found in sequence along the direction from corner point c1 to intersection point B2, and a small clipping region 30 is placed at each of these points. The spacing between point B1 and intersection point B2 is designed to be between Lmin and Lmax. For example, when it is L1, a small clipping region 30 is placed at intersection point B2. When the spacing between point B1 and intersection point B2 is not between Lmin and Lmax, a small clipping region 30 is placed near intersection point B2 at a position that meets the design requirements. Simultaneously, small clipping regions 30 are placed on other lines in the overlapping area, and these positions meet the preset length requirement, i.e., between Lmin and Lmax. Since intersection point B2 and the edge of the step of the suspected murderer graphic are on the same extension line Y, i.e., the edge of the step of the suspected murderer graphic is aligned with the cutting point, the suspected murderer graphic is the target murderer graphic 40. Next, step S4 is executed to optimize the target murderer graphic in all the small blocks to obtain an intermediate layout.

[0066] Specifically, the edge of the step in the target murderer's graphic is moved so that it moves towards the main graphic area adjacent to the main graphic area where the target murderer's graphic is located. For example... Figure 7As shown, when the target murderer graphic 40 is located in the main graphic region 12 (i.e., the overlapping region 121), the step edge is moved towards the main graphic region 11 in the first direction a. When the target murderer graphic 40 is located in the main graphic region 11 (i.e., the overlapping region 221), the step edge is moved towards the main graphic region 12 in the first direction a to form an intermediate layout, thereby ensuring the consistency of contour convergence between the overlapping regions of adjacent small blocks during the OPC correction process.

[0067] Among them, in the projection of each corner point on the Z-shaped figure where the problem figure is located onto the target murderer figure 40, when the distance M between the projection closest to the edge of the step and the edge of the step is less than the design value, the edge of the step moves to the position of the small clipping area 30 near the projection; when the distance M between the projection closest to the edge of the step and the edge of the step is greater than the design value, the edge of the step moves to the projection.

[0068] Next, step S5 is executed to perform OPC correction on the intermediate layout. Specifically, the intermediate layout undergoes OPC correction and simulation verification. If no problematic graphics appear in the overlapping areas of the verification results (i.e., no EPE simulation value exceeds the EPE design value), the OPC-corrected layout will be used as the final layout. If problematic graphics with EPE simulation values ​​exceeding the EPE design value still appear in the overlapping areas of the verification results, the process returns to step S3 to further optimize the target problematic graphics until no more problematic graphics appear in this step. It has been found that, using the method of this embodiment, the final layout, during simulation, reduces the EPE simulation value at the location where problematic graphics previously appeared from the existing 8.5nm to 0.5nm, thereby reducing the linewidth (CD) error by 95%.

[0069] In summary, this invention provides an optical proximity effect correction and optimization method, comprising the following steps: providing an initial layout, dividing the initial layout into several small blocks, each small block including a main graphic region and an extended region surrounding the main graphic region, each small block overlapping the extended regions of adjacent small blocks; performing OPC correction and simulation verification on each small block, and identifying problematic graphics and several suspected culprit graphics in the overlapping region between two adjacent small blocks in the simulation verification graphics; identifying the target culprit graphics causing the appearance of the problematic graphics from all the suspected culprit graphics; optimizing the target culprit graphics in all the small blocks to obtain an intermediate layout; and performing OPC correction on the intermediate layout to significantly reduce EPE at the edges of small regions, thus solving the problem of non-convergence of OPC correction verification results.

[0070] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0071] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for correcting and optimizing the optical proximity effect, characterized in that, Includes the following steps: An initial layout is provided, which is divided into several small blocks. Each small block includes a main graphic area and an extended area surrounding the main graphic area. Each small block overlaps with the extended area of ​​the adjacent small block. For each of the aforementioned small blocks, OPC correction and simulation verification are performed. In the simulation verification graph, problem graphs and several suspected culprit graphs appear in the overlapping area between two adjacent small blocks. The suspected culprit graphs are stepped lines. The graphic lines containing the problem graphic are fragmented to obtain several cutting points. Each cutting point is a small clipping region with a preset length interval between it and its adjacent cutting points. Centered on all the cutting points in the problem image, the cutting points are projected in the direction of increasing EPE simulation value, and a parallel search is performed to find the suspected murderer image whose step edge is aligned with the cutting point as the target murderer image. Optimize the target perpetrator graphics in all the aforementioned small blocks to obtain an intermediate map; The intermediate layout is modified using OPC.

2. The optical proximity effect correction and optimization method as described in claim 1, characterized in that, The main graphic area is rectangular in shape, and the extended area is a rectangular ring in shape.

3. The optical proximity effect correction and optimization method as described in claim 2, characterized in that, The specific methods for dividing the initial map into several small blocks include: The side length of the main graphic area is fixed, and the outer ring edge of the extended area is gradually expanded outward from the corresponding edge of the main graphic area by a preset length. After each expansion, the small block is corrected and simulated for verification. When the simulated EPE value in the overlapping area is greater than the designed EPE value, the expansion of the outer ring edge of the extended area is stopped to obtain the divided small block.

4. The optical proximity effect correction and optimization method as described in claim 2, characterized in that, The specific methods for dividing the initial map into several small blocks include: The outer side length of the extended region is fixed, and the edge of the main graphic region is gradually shrunk inward from the corresponding outer side of the extended region by a preset length. After each shrunk, the small block is corrected by OPC and simulated for verification. When the simulated EPE value in the overlapping region is greater than the designed EPE value, the shrunk of the main graphic region is stopped to obtain the divided small block.

5. The optical proximity effect correction and optimization method as described in claim 1, characterized in that, The overlapping area includes a Z-shaped pattern, and the problem image is located on the Z-shaped pattern.

6. The optical proximity effect correction and optimization method as described in claim 1, characterized in that, The small clipping area is square in shape.

7. The optical proximity effect correction and optimization method as described in claim 1, characterized in that, The specific methods for optimizing the target perpetrator image in all the aforementioned small blocks include: Move the edge of the step in the target murderer graphic so that the edge of the step moves toward the main graphic area adjacent to the main graphic area where the target murderer graphic is located.

8. The optical proximity effect correction and optimization method as described in claim 1, characterized in that, The specific methods for performing OPC correction on the intermediate layout include: The intermediate layout is corrected using OPC and then simulated for verification. If no problematic graphics appear in the overlapping areas in the verification results, the layout corrected using OPC will be used as the final layout.

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