Allocation method, electronic device, and storage medium

Abstract

Embodiments of the present disclosure provide a distribution method, an electronic device and a storage medium. The distribution method is executed by a compiler and includes: grouping second type instructions corresponding to first type instructions according to positions of the first type instructions in an intermediate representation corresponding to a program to be compiled, wherein there is a dependency relationship between the first type instructions and the second type instructions; and distributing hardware synchronization channels to the second type instructions according to a grouping result, wherein the hardware synchronization channels are configured to implement synchronization of the first type instructions and the second type instructions. Under the premise that hardware synchronization channel resources are limited, the method effectively reduces synchronization channel conflicts and additional waiting time between different instructions by using a reasonable grouping and distribution strategy in combination with hardware instructions, improves hardware concurrency, reduces dependence on hardware synchronization capability, and thus reduces hardware design complexity.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of computer technology, and more specifically to an allocation method, electronic device, and storage medium. Background Technology

[0002] In parallel computing architectures, there exists a class of instructions with execution latency, characterized by a non-negligible and indeterminate time interval between their issuance and result readiness. These instructions may include, for example, memory access instructions, matrix calculation instructions, cache control instructions, or Special Function Unit (SFU) instructions. To improve program responsiveness and performance, these instructions typically employ asynchronous execution (or non-blocking execution). Instructions using asynchronous execution are also called asynchronous instructions. In this mode, the processor can continue executing subsequent instructions without waiting for the operation to complete, thereby masking execution latency through computational parallelism and improving hardware resource utilization.

[0003] However, although asynchronous instructions do not block pipeline execution, if subsequent instructions depend on the execution result of asynchronous instructions, they still need to wait for the result of the asynchronous instructions to be ready before they can be executed. Therefore, how to implement a low-overhead, high-concurrency synchronization control mechanism while ensuring the accuracy of data dependencies has become an urgent problem to be solved in order to improve system concurrency and execution efficiency. Summary of the Invention

[0004] At least one embodiment of this disclosure provides an allocation method, wherein the allocation method is executed by a compiler, comprising: grouping second type instructions corresponding to the first type instructions according to the position of the first type instructions in the intermediate representation corresponding to the program to be compiled, wherein there is a dependency relationship between the first type instructions and the second type instructions; and allocating a hardware synchronization channel for the second type instructions according to the grouping result, wherein the hardware synchronization channel is configured to realize the synchronization between the first type instructions and the second type instructions.

[0005] In the allocation method provided in at least one embodiment of this disclosure, the step of grouping the second type instructions corresponding to the first type instructions according to the position of the first type instructions in the intermediate representation corresponding to the program to be compiled includes: determining the second instruction group to which the second type instructions corresponding to the first type instructions belong based on the position of the first type instructions in the intermediate representation and in combination with a preset grouping size, wherein the preset grouping size indicates the maximum number of first type instructions corresponding to all second type instructions in each second instruction group.

[0006] In the allocation method provided in at least one embodiment of this disclosure, the step of determining the second instruction group to which the second type instruction corresponding to the first type instruction belongs based on the position of the first type instruction in the intermediate representation and in combination with a preset grouping size includes: dividing the first type instruction in the intermediate representation into at least one first instruction group according to the preset grouping size, wherein the number of first type instructions in the first instruction group does not exceed the preset grouping size, and the positions of each first type instruction in the first instruction group are consecutive in the intermediate representation; for each first instruction group, the second type instructions corresponding to all the first type instructions in the first instruction group are taken as a second instruction group.

[0007] In at least one embodiment of the allocation method provided in this disclosure, the step of grouping the second type instructions corresponding to the first type instructions according to the position of the first type instructions in the intermediate representation corresponding to the program to be compiled includes: determining the second instruction group to which the second type instructions corresponding to the first type instructions belong by combining the position of the first type instructions in the intermediate representation with the position of the second type instructions corresponding to the first type instructions in the intermediate representation.

[0008] In the allocation method provided in at least one embodiment of this disclosure, the step of determining the second instruction group to which the second type instruction corresponding to the first type instruction belongs based on the position of the first type instruction in the intermediate representation and the position of the second type instruction corresponding to the first type instruction in the intermediate representation includes: according to the instruction order, for each first type instruction in the intermediate representation: in response to the second type instruction corresponding to the first type instruction not being grouped, the second type instruction and the ungrouped second type instruction located before the second type instruction are regarded as a second instruction group.

[0009] In at least one embodiment of the allocation method provided in this disclosure, each hardware synchronization channel includes at least one hardware synchronization channel unit. The step of allocating a hardware synchronization channel for the second type of instruction according to the grouping result includes: allocating the second type of instructions in the same second instruction group to the same hardware synchronization channel; in response to the existence of an idle hardware synchronization channel, determining that different second instruction groups correspond to different hardware synchronization channels, and allocating the second type of instructions in different second instruction groups to different hardware synchronization channels; or in response to the absence of an idle hardware synchronization channel, determining that different second instruction groups correspond to different hardware synchronization channel units, and allocating the second type of instructions in different second instruction groups to different hardware synchronization channel units.

[0010] In at least one embodiment of the allocation method provided in this disclosure, the method further includes: inserting an operation instruction into the intermediate representation according to the grouping result, wherein the operation instruction includes a waiting instruction and a switching instruction, the waiting instruction is configured to wait for the execution of the second type instruction corresponding to the target number of hardware synchronization channel units to end, and the switching instruction is configured to switch to the next hardware synchronization channel unit of the current hardware synchronization channel unit.

[0011] In at least one embodiment of the allocation method provided in this disclosure, the intermediate representation includes multiple basic blocks. Based on the grouping result, a hardware synchronization channel is allocated for the second type of instruction, and an operation instruction corresponding to the hardware synchronization channel is inserted into the intermediate representation. This includes: for each basic block, during the traversal of instructions in the basic block, the following operations are performed: in response to the current instruction being a second type of instruction, and the second type of instructions in the second instruction group to which the current instruction belongs not yet being allocated, an idle hardware synchronization channel or an idle hardware synchronization channel unit is allocated to the current instruction, and a hardware synchronization channel marker is added to the current instruction; in response to the allocation of an idle hardware synchronization channel unit to the current instruction, a switching instruction is inserted before the current instruction; in response to the current instruction being a second type of instruction, and the second type of instructions in the second instruction group to which the current instruction belongs have already been allocated, the same hardware synchronization channel or hardware synchronization channel unit is allocated to the current instruction, and a hardware synchronization channel marker is added to the current instruction; or in response to the current instruction being a first type of instruction, a waiting instruction is inserted before the current instruction.

[0012] In at least one embodiment of the allocation method provided in this disclosure, the method further includes: setting register definition information for each basic block, wherein the register definition information is used to manage the destination register information of the second type of instructions in the basic block based on the hardware synchronization channel index, wherein setting register definition information for each basic block includes: initializing the register definition information of the first basic block to empty; updating the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction during the traversal of instructions in the current basic block; and initializing the register definition information of the subsequent basic blocks of the current basic block based on the register definition information of the current basic block in response to the end of instruction traversal in the current basic block.

[0013] In at least one embodiment of the allocation method provided in this disclosure, updating the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction includes: in response to inserting a switching instruction before the current instruction, performing a circular shift operation on the target information queue in the register definition information, wherein the target information queue corresponds to the hardware synchronization channel corresponding to the current instruction; or in response to allocating a hardware synchronization channel or hardware synchronization channel unit for the current instruction, updating the register definition information based on the hardware synchronization channel index corresponding to the hardware synchronization channel or hardware synchronization channel unit and the destination register information of the current instruction.

[0014] In at least one embodiment of the allocation method provided in this disclosure, the step of inserting a waiting instruction before the current instruction in response to the current instruction being a first type instruction includes: in response to the current instruction being a first type instruction, determining the target index corresponding to the source register information of the current instruction in the target information queue in the register definition information, wherein the target information queue corresponds to the hardware synchronization channel corresponding to the current instruction; determining the target number corresponding to the waiting instruction according to the target index, and inserting the waiting instruction before the current instruction.

[0015] In the allocation method provided in at least one embodiment of this disclosure, updating the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction further includes: in response to inserting a wait instruction before the current instruction, deleting all elements in the target information queue from the position corresponding to the target index to the tail of the queue.

[0016] In at least one embodiment of the allocation method provided in this disclosure, the step of initializing the register definition information of the successor basic block based on the register definition information of the current basic block includes: in response to the existence of other predecessor basic blocks besides the current basic block in the successor basic block, merging the register definition information of the current basic block and the register definition information of other predecessor basic blocks to obtain the register definition information of the successor basic block; or in response to the absence of other predecessor basic blocks besides the current basic block in the successor basic block, using the register definition information of the current basic block as the register definition information of the successor basic block.

[0017] In at least one embodiment of the allocation method provided in this disclosure, the allocation method further includes: for a basic block including a loop back edge, in response to the fact that the register definition information of the basic block at the end of the traversal has not changed compared with the previous loop, determining to jump to the successor basic block of the current basic block to continue the traversal operation.

[0018] At least one embodiment of this disclosure provides an allocation device applied to a compiler. The allocation device includes: a grouping module configured to group second type instructions corresponding to the first type instructions according to the position of the first type instructions in the intermediate representation corresponding to the program to be compiled, wherein there is a dependency relationship between the first type instructions and the second type instructions; and an allocation module configured to allocate a hardware synchronization channel for the second type instructions according to the grouping result, wherein the hardware synchronization channel is configured to realize the synchronization between the first type instructions and the second type instructions.

[0019] At least one embodiment of this disclosure provides an electronic device, including: at least one processor; at least one memory including one or more computer program modules; wherein the one or more computer program modules are stored in the at least one memory and configured to be executed by the at least one processor, and the one or more computer program modules are used to implement the allocation method provided in at least one embodiment of this disclosure.

[0020] At least one embodiment of this disclosure provides a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, wherein the computer-readable instructions, when executed by at least one processor, perform the allocation method provided in at least one embodiment of this disclosure.

[0021] This disclosure provides at least one embodiment of an allocation method, allocation device, electronic device, and non-transitory computer-readable storage medium, offering a software-level allocation scheme. Based on the dependencies and order of instructions, instructions requiring synchronization are grouped, ensuring that related instructions are allocated to the same hardware synchronization channel, while unrelated instructions are allocated to different hardware synchronization channels, thereby reducing unnecessary waiting. Given limited hardware synchronization channel resources, this scheme, through a reasonable grouping and allocation strategy, effectively reduces synchronization channel conflicts and additional waiting between different instructions, improves hardware concurrency, reduces dependence on hardware synchronization capabilities, and thus reduces hardware design complexity. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0023] Figure 1A This is a diagram illustrating the execution of an instruction.

[0024] Figure 1B A schematic block diagram of a streaming multiprocessor provided for at least one embodiment of this disclosure;

[0025] Figure 2A flowchart illustrating an allocation method provided in at least one embodiment of this disclosure;

[0026] Figure 3A A schematic diagram illustrating an intermediate representation provided for at least one embodiment of this disclosure;

[0027] Figure 3B A schematic diagram illustrating another intermediate representation provided for at least one embodiment of this disclosure;

[0028] Figure 3C A schematic diagram of a control flow graph provided for at least one embodiment of this disclosure;

[0029] Figure 3D A flowchart illustrating another allocation method provided for at least one embodiment of this disclosure;

[0030] Figure 4A A schematic diagram of an updated intermediate representation provided for at least one embodiment of this disclosure;

[0031] Figure 4B A schematic diagram illustrating another updated intermediate representation provided for at least one embodiment of this disclosure;

[0032] Figure 5 A schematic diagram of another control flow graph provided for at least one embodiment of this disclosure;

[0033] Figure 6 A schematic block diagram of a dispensing device provided for at least one embodiment of this disclosure;

[0034] Figure 7 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure;

[0035] Figure 8 A schematic block diagram of another electronic device provided for at least one embodiment of this disclosure;

[0036] Figure 9 This is a schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0038] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0040] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0041] Taking memory access instructions (such as load or store instructions) as an example, the Load instruction is used to load data from memory into a register, and the Store instruction is used to write data from the register back into memory. Parallel computing architectures typically include dedicated Load / Store Units (LSUs) and Compute Units (CUs). Initial data is usually stored in memory, but the Compute Unit cannot directly access memory; it needs to load the required data from memory into registers using load instructions before subsequent operations can be performed.

[0042] In high-performance parallel computing using accelerators such as Graphics Processing Units (GPUs) or General-Purpose Graphics Processing Units (GPGPUs), a large number of threads are used to achieve high concurrency. Multiple threads can be combined into warps, each warp consisting of a fixed number (or less) of threads, for example, 32 threads. These threads execute the same instructions in a Single Instruction Multiple Threading (SIMT) manner, but process different data. Within a warp, each thread can share some register resources with other threads, while also having its own independent register resources for loading or computing different data. Warps are scheduled and allocated within each computing unit so that multiple computing cores within that unit can run them. Depending on the number of computing cores in the computing unit, multiple warps within a warp can execute concurrently or in a time-sharing manner. Direct data interaction between different warps is not supported, but data exchange and synchronization can be achieved using shared memory.

[0043] Taking a thread bundle containing 32 threads as an example, a single load instruction can load the data required by up to 32 threads in parallel within that bundle. When subsequent computation instructions are executed concurrently on the same thread bundle, each thread uses data from its private registers (e.g., thread local registers (TLRs)). The completion time of a load instruction is uncertain, influenced by factors such as data length, caching behavior, and memory bandwidth. In parallel computing architectures, load instructions typically employ an asynchronous execution mode, meaning that after initiating a load operation, subsequent instructions can continue execution without waiting for its completion. This mechanism helps improve program responsiveness and overall performance, especially suitable for memory-intensive tasks. However, asynchronous loading also introduces instruction synchronization issues: because the completion time of a load operation is uncertain, synchronization mechanisms are needed to ensure data availability and maintain execution efficiency. Without effective synchronization control, calculation errors may occur due to threads using data that is not yet ready, or excessive waiting may cause thread blocking and idle execution resources, thereby reducing overall throughput.

[0044] Figure 1A This is a diagram illustrating the execution of an instruction.

[0045] For example, such as Figure 1AAs shown, after the Load1 instruction is issued, several instructions that do not depend on the data returned by Load1 can be executed in parallel. Similarly, after the Load2 instruction is issued, several instructions that do not depend on the data returned by Load2 can be executed in parallel. When the Use1 instruction is executed, since its source register (A) is the same as the destination register of Load1, meaning Use1 needs to use the data loaded by Load1, it must wait for Load1 to complete before it can execute. However, the number of loading units in hardware is often limited. Since Load1 and Load2 share a loading unit, even if Load1 has finished executing, as long as Load2 has not finished executing, the overall task of that loading unit is not complete, and Use1 still cannot obtain the loading result of Load1 and needs to continue waiting for Load2 to finish. This leads to unnecessary delays and affects performance. During the program compilation stage, Use1 can be moved before Load2 through instruction scheduling to alleviate this problem. However, this method is only suitable for cases with simple code structure and few asynchronous instructions. When a program contains a large number of asynchronous loading instructions with varying delay times, static scheduling is difficult to optimize effectively and may still result in serious waiting and resource contention issues.

[0046] Synchronization operations for data loading can be implemented using a purely hardware approach. For example, hardware (such as streaming multiprocessors in a GPGPU or other similar parallel processors) needs to synchronize the entire process of load instructions—from issuance and data reading to register writing—before using thread-local register data. This approach requires no software intervention, but the hardware design is highly complex, especially when multiple load instructions are executed concurrently. It requires maintaining multiple sets of synchronization state information and ensuring the correctness and consistency of register data in a multi-threaded environment, posing significant challenges to chip design and resource overhead.

[0047] To overcome the high complexity and resource pressure of pure hardware synchronization schemes, a hardware-software co-operational synchronization mechanism can be adopted. In this mechanism, the hardware needs to support asynchronous execution between LSU units and computation units, and provide a thread-beam-level synchronization channel to track the completion status of each load instruction. When a load instruction completes its task, the hardware automatically releases its corresponding synchronization channel, allowing subsequent operations to continue. The software (e.g., a compiler) can allocate independent synchronization channels for different load instructions based on the number of synchronization channels supported by the hardware, combined with static code analysis, to reduce resource conflicts. Through this approach, efficient synchronization can be achieved simply by checking whether the corresponding synchronization channel has been released before using data. This reduces hardware design complexity, improves execution efficiency, effectively reduces waiting overhead caused by channel contention, and thus optimizes overall performance.

[0048] It should be noted that the above-mentioned hardware and software coordination synchronization mechanism is not only applicable to the synchronization of loading instructions, but also to the various instructions (or asynchronous instructions) with execution delay attributes described above. Different types of synchronization channels can be provided for different types of instructions.

[0049] For example, in Figure 1A In the example, a synchronization channel sc1 can be assigned to Load1, and a synchronization channel sc2 can be assigned to Load2. When Use1 is executed, it only needs to check whether the instructions assigned to sc1 have finished executing, without waiting for the instructions in other channels (such as sc2) to finish executing; similarly, Use2 only needs to check whether the instructions assigned to sc2 have finished executing. In this way, Load1 can be executed in parallel with several subsequent x instructions, and Load2 can be executed in parallel with several subsequent y instructions and Load1, thereby improving instruction execution efficiency.

[0050] In theory, given a sufficient number of synchronization channels, software can allocate an independent synchronization channel to each load instruction, maximizing the parallelism of all loading and computation tasks and avoiding additional waiting caused by synchronization channel conflicts between load instructions. However, due to limited hardware resources, an unlimited number of synchronization channels cannot be supported; typically, only a limited number can be provided. Therefore, the following problem needs to be addressed: under the constraint of a limited number of synchronization channels provided by the hardware, how to design an efficient allocation strategy at the software level to rationally allocate the limited hardware synchronization channels to multiple asynchronous instructions in order to minimize synchronization channel conflicts between different instructions.

[0051] This disclosure provides at least one embodiment of a distribution method, a distribution apparatus, an electronic device, and a storage medium.

[0052] The allocation method provided in at least one embodiment of this disclosure, executed by a compiler, includes: grouping second-type instructions corresponding to the first-type instructions according to their positions in the intermediate representation of the program to be compiled, wherein there is a dependency relationship between the first-type instructions and the second-type instructions; and allocating a hardware synchronization channel for the second-type instructions according to the grouping result, wherein the hardware synchronization channel is configured to synchronize the first-type instructions and the second-type instructions.

[0053] In at least one embodiment of the allocation method provided in this disclosure, a software-level allocation scheme is offered. This method groups instructions requiring synchronization based on inter-instruction dependencies and instruction order, ensuring that related instructions are allocated to the same hardware synchronization channel, while unrelated instructions are allocated to different hardware synchronization channels, thereby reducing unnecessary waiting. Given limited hardware synchronization channel resources, this scheme, through a reasonable grouping and allocation strategy, effectively reduces synchronization channel conflicts and additional waiting between different instructions, improves hardware concurrency, reduces dependence on hardware synchronization capabilities, and thus reduces hardware design complexity.

[0054] The allocation method provided in at least one embodiment of this disclosure can be applied to various types of processors. Processors may include graphics processing units (GPUs), tensor processing units (TPUs), general-purpose graphics processing units (GPGPUs), deep learning processing units (DPUs), accelerated processing units (APUs), neural network processing units (NPUs), etc. Of course, the embodiments of this disclosure are not limited to these, and the processor may also be any other type of processor.

[0055] Figure 1B This is a schematic block diagram of a streaming multiprocessor (SM) provided for at least one embodiment of the present disclosure. Each streaming multiprocessor 10 can execute multiple thread bundles simultaneously. The execution between different thread bundles can be independent or sequential.

[0056] like Figure 1BAs shown. The streaming multiprocessor 10 includes an instruction cache 11 for storing multiple instructions from the kernel. The streaming multiprocessor 10 also includes a warp instruction scheduler 12 for fetching a series of instructions for each warp and storing them in the instruction cache 11, retrieving instructions to be executed from the instruction cache 11 for each warp based on a program counter. Each warp has an independent program counter (PC) register to record the location (i.e., the instruction address) of the instruction currently being executed. Each time an instruction is fetched from the instruction cache for a warp, the corresponding program counter is incremented. The warp instruction scheduler 12 delivers instructions to the Arithmetic Logic Unit (ALU), Special Function Unit (SFU), or Load Store Unit (LSU) 15 for execution at appropriate times; these instructions are defined in the instruction set architecture (ISA) of the specific computing system.

[0057] The arithmetic logic unit 13 can perform various operations, such as addition and multiplication of integers and floating-point numbers, comparison operations, Boolean operations, bit shifting, etc. During execution, the arithmetic logic unit 13 can read data from a specified location (also known as the source address) in the general-purpose register 16 (GPR) and write the execution result back to a specified location (also known as the destination address) in the general-purpose register 16. The special function unit 14 can implement various mathematical operations (such as finding reciprocals, square roots, trigonometric functions, etc.). The load-store unit 15 can execute load and store instructions, handling memory load and store operations.

[0058] The streaming multiprocessor 10 also includes a barrier register 17, which allows software to synchronize execution between different thread bundles, and a resource-per-warp register 18, which allows software to dynamically configure the space range of general-purpose registers 16 available to each thread bundle during execution. It should be noted that... Figure 1B The streaming multiprocessor shown is merely an example, and those skilled in the art will understand that a streaming multiprocessor may include more or fewer components. For example, a streaming multiprocessor may also include shared memory, a Level 1 cache, and other components.

[0059] For example, the hardware synchronization channel in this embodiment of the disclosure can be located as follows: Figure 1B The hardware synchronization channel can be managed by the thread bundle instruction scheduler 12 in the barrier register 17 shown.

[0060] Figure 2 A flowchart illustrating an allocation method provided in at least one embodiment of this disclosure.

[0061] For example, such as Figure 2 As shown, the allocation method provided in this embodiment is executed by a compiler and may include steps S101 to S102.

[0062] Step S101: Based on the position of the first type instruction in the intermediate representation of the program to be compiled, group the second type instructions corresponding to the first type instruction into groups, wherein there is a dependency relationship between the first type instruction and the second type instruction.

[0063] Step S102: Based on the grouping results, allocate a hardware synchronization channel for the second type of instructions, wherein the hardware synchronization channel is configured to synchronize the first type of instructions with the second type of instructions.

[0064] A compiler typically consists of three processing stages: front-end, middle-end (optimizer), and back-end, which work together to complete the conversion from source code (i.e., the program to be compiled) into executable machine code.

[0065] The compiler's front end is responsible for converting source code from different programming languages ​​or programming models into a common intermediate representation (IR). This process may include lexical analysis, syntax analysis, semantic analysis, construction of an abstract syntax tree (AST), and generation of the intermediate representation.

[0066] The compiler receives the intermediate representation generated by the front end, transforms and optimizes the intermediate representation to obtain the optimized intermediate representation.

[0067] The compiler's backend is responsible for converting the optimized intermediate representation into machine code or assembly code executable by the target hardware platform, based on the platform's characteristics. Specific backend tasks can include register modeling, instruction modeling, instruction selection and translation, register allocation, instruction scheduling optimization, and code generation, with the specific order customizable according to different physical architectures. Backend analysis can include the aforementioned instruction selection and translation, register allocation, and instruction scheduling optimization tasks. For example, register modeling refers to the formal description of the structure, type, purpose, constraints, or relationships of available registers on the target processor; instruction modeling refers to the formal description of the syntax, semantics, operands, or performance characteristics of instructions in the target processor's instruction set architecture; instruction selection and translation refers to mapping the optimized intermediate representation to the target hardware platform's instruction set, obtaining the Machine Intermediate Representation (MIR); register allocation refers to mapping virtual registers in the intermediate representation to actual registers in the target hardware; instruction scheduling optimization refers to rearranging the instruction order to maximize hardware resource utilization; and code generation refers to generating machine code or assembly code executable by the target hardware platform.

[0068] The allocation method provided in at least one embodiment of this disclosure can be executed in the back-end analysis stage. For example, it can be located after instruction selection and conversion, and before instruction issuance (code generation). To ensure the stability of the grouping results, the grouping operation should be performed after all optimizations and scheduling that may change the instruction order have been completed, that is, in the final stage after the compiler's entire optimization analysis process has ended.

[0069] For example, in step S101, the "intermediate representation corresponding to the program to be compiled" can be an intermediate representation processed by the compiler backend. This intermediate representation can consist of multiple basic blocks (BBs), each of which includes a sequence of instructions executed sequentially, without any start or end points for jumps or branches (except for the last instruction, which may be a control transfer instruction). Each basic block has only one entry point and one exit point. Basic blocks are the basic units in the control flow analysis, optimization, and compilation process, and help to understand and manipulate the program's control structure. For example, basic blocks can be connected according to control transfer instructions (branch, jump, function call / return) to form a control flow graph (CFG) for subsequent optimization, analysis, and target code generation. A control flow graph is a directed graph describing the program execution path, where nodes are basic blocks and edges are jump logic.

[0070] For example, in step S101, there is an operand dependency between the first type instruction and the second type instruction. One example is that the source operand of the first type instruction depends on the execution result of the second type instruction. In other words, the second type instruction can be an instruction whose execution result is depended upon by subsequent instructions.

[0071] Furthermore, the second type of instructions can include instructions with execution latency, where there is a non-negligible and indeterminate time interval between the issuance of the instruction and the readiness of the result. For example, instructions with execution latency can include memory access instructions, matrix calculation instructions, cache control instructions, or special function unit (SMU) instructions. Memory access instructions can be, for example, load instructions or store instructions; matrix calculation instructions can be, for example, matrix multiply-accumulate (MMA) instructions or convolution (Conv) instructions; cache control instructions can be, for example, flush instructions, ack instructions, invalidate instructions, fence instructions, etc.; SMU instructions, also known as transcendental function instructions, can be, for example, instructions used to calculate square functions, root functions, trigonometric functions, and other special functions. These instructions typically employ asynchronous execution and can also be called asynchronous instructions. For example, when the second type of instruction is a load instruction that loads data from memory into a register, its corresponding first type of instruction is an instruction that subsequently uses the loaded result as an operand.

[0072] For example, in step S101, the position of an instruction in the intermediate representation can be reflected in the order in which the instructions are arranged in the intermediate representation, as well as the positional relationship between the instruction and other instructions.

[0073] For example, in step S101, for each basic block in the intermediate representation, the second type of instructions corresponding to the first type of instructions can be grouped according to the position of the first type of instructions in the basic block.

[0074] For example, in step S102, a hardware synchronization channel is allocated for the second type of instruction according to the grouping result, wherein the hardware synchronization channel is configured to realize the synchronization between the first type of instruction and the second type of instruction.

[0075] For example, second-type instructions in the same second instruction group can be assigned to the same hardware synchronization channel.

[0076] In this embodiment, the hardware synchronization channel is a thread bundle-level resource used to implement synchronization within a thread bundle. The hardware synchronization channel may include one or more hardware synchronization channel units (slots), thereby providing more flexible synchronization capabilities based on limited channel resources. Subdividing the hardware synchronization channel into multiple hardware synchronization channel units helps to organize tasks into a more fine-grained pipeline structure.

[0077] The allocation method provided in this disclosure is applicable to hardware synchronization channels that include one or more hardware synchronization channel units. Taking a load instruction as an example, the hardware can provide x dedicated hardware synchronization channels (sc0~scx-1) for the load instruction. Different hardware synchronization channels are completely independent and do not share state or data, ensuring the isolation and reliability of synchronization control. Each hardware synchronization channel includes y hardware synchronization channel units (slot0~sloty-1). This disclosure does not limit the actual number of hardware synchronization channels and hardware synchronization channel units in the processor, and this allocation method can be applied to hardware configurations of different scales. In a hardware synchronization channel, the hardware synchronization channel units are used cyclically. Switching to the next hardware synchronization channel unit is possible as needed, and after switching to the last hardware synchronization channel unit, the cycle returns to the first hardware synchronization channel unit.

[0078] Hardware synchronization channels can be managed through wait commands and switch commands, which will be described in detail later.

[0079] In the allocation method provided in at least one embodiment of this disclosure, an example of step S101 may include the following step S1011.

[0080] Step S1011: Based on the position of the first type instruction in the intermediate representation and in conjunction with the preset grouping size, determine the second instruction group to which the second type instruction corresponding to the first type instruction belongs, wherein the preset grouping size indicates the maximum number of first type instructions corresponding to all second type instructions in each second instruction group.

[0081] For example, step S1011 can be processed on a basic block basis, that is, step S1011 is executed for each basic block in the intermediate representation.

[0082] For example, the default value for the preset grouping size is 1, meaning that at most, all second-type instructions (e.g., data loading instructions) corresponding to a first-type instruction (e.g., a data usage instruction) can be grouped together. For example, when the preset grouping size is N, it means that at most, all second-type instructions corresponding to N consecutive first-type instructions in the intermediate representation can be grouped together. It should be noted that this disclosure does not limit the size of the preset grouping size and can be flexibly configured according to actual needs. For example, it can be determined based on data dependencies in the code, or it can be manually set by the user during the compilation stage according to the specific application scenario.

[0083] For example, step S1011 can divide one or more second instruction groups, and each second instruction group may include one or more second type instructions.

[0084] For example, one example of step S1011 may include: dividing the first type of instructions in the intermediate representation into at least one first instruction group according to a preset grouping size, wherein the number of first type instructions in the first instruction group does not exceed the preset grouping size, and the positions of each first type instruction in the first instruction group are consecutive in the intermediate representation; for each first instruction group, taking the second type instructions corresponding to all the first type instructions in the first instruction group as a second instruction group.

[0085] For example, when the preset group size is N, the first instruction group consists of at most N consecutive first-type instructions in the intermediate representation. That is, in the intermediate representation, there are no other instructions between any two first-type instructions in the first instruction group. In this example, if there are fewer than N consecutive first-type instructions, such as only N-1 consecutive first-type instructions, then the first instruction group consists of those N-1 first-type instructions. Therefore, in this embodiment of the disclosure, it is not required that each first instruction group must contain exactly N first-type instructions.

[0086] For example, after determining one or more first instruction groups, for each first instruction group, all second type instructions that the first type instructions in it depend on are aggregated into a second instruction group.

[0087] The above grouping scheme is designed based on the execution characteristics of Type II instructions. If continuously used data all depend on Type II instructions, then regardless of whether these Type II instructions are assigned to the same or different hardware synchronization channels, their waiting time is essentially the same. Therefore, these Type II instructions can be grouped into the same Type II instruction group and subsequently assigned to the same hardware synchronization channel, effectively saving hardware synchronization channel resources.

[0088] Figure 3A This is a schematic diagram of an intermediate representation provided for at least one embodiment of the present disclosure.

[0089] The following will be based on Figure 3A The pseudocode shown in the intermediate representation details an example of step S1011. For example, Figure 3A This diagram shows a basic block representing the intermediate representation. This basic block includes four load instructions ld0~ld3 and two addition instructions add0~add1. There may be zero or more other instructions between the load instructions. Figure 3A (The ellipsis indicates that it has no dependency on the load instruction). Here, there is a dependency between the load instruction and the addition instruction; the load instruction is a type II instruction, and the addition instruction is a type I instruction.

[0090] It should be noted that, for ease of expression, when referring to specific instructions in the following text, the full form may be used as "load instruction a1 = ld0" to reflect its destination register and operation; or it may be simplified to "load instruction ld0" depending on the context. Both expressions refer to the same instruction, and the simplified description does not affect its technical meaning; it is only used to improve the conciseness of the writing.

[0091] First, for each basic block in the intermediate representation, a register-to-instruction mapping table can be initialized, which can be, for example, a first-in-first-out (FIFO) structure. The instructions in the basic block are traversed in ascending order: if the current instruction is a type II instruction, its destination register information and the instruction itself are saved in the mapping table as key-value pairs (e.g., for the load instruction a1 = ld0, an entry can be recorded in the mapping table).<a1,ld0> When the mapping table is not empty, for each instruction encountered, it is necessary to check whether the data used by the current instruction depends on the second type instruction (by comparing it with the entry in the mapping table). If the data used by the current instruction depends on the second type instruction (for example, the source register of the current instruction is the same as the destination register of a second type instruction), the second type instruction corresponding to the current instruction can be grouped and saved. After grouping, the corresponding entry of the second type instruction in the mapping table needs to be deleted.

[0092] by Figure 3A For example, assuming the preset group size is 1, when traversing to the addition instruction add0, since the current instruction depends on the data loaded into registers a1 and a2, both of these data need to be ready before the current instruction can be executed. Therefore, the loading instructions ld0 and ld1 are grouped together, and the entries in the mapping table are deleted.<a1,ld0> and<a2,ld1> Similarly, the load instructions ld2 and ld3 are grouped into another set, and entries in the mapping table are deleted.<b1,ld2> and<b2,ld3> At this point, the mapping table has been cleared, and the grouping of load instructions in this basic block is complete.

[0093] by Figure 3A For example, assuming the preset group size is 2, since the addition instructions add0 and add1 are two consecutive Type 1 instructions, the corresponding load instructions need to be grouped together. That is, the four load instructions ld0~ld3 are grouped together, and entries in the mapping table are deleted.<a1,ld0> ,<a2,ld1> ,<b1,ld2> and<b2,ld3> At this point, the mapping table has been cleared, and the grouping of load instructions in this basic block is complete.

[0094] In the allocation method provided in at least one embodiment of this disclosure, another example of step S101 may include step S1012.

[0095] Step S1012: Based on the position of the first type instruction in the intermediate representation and the position of the second type instruction corresponding to the first type instruction in the intermediate representation, determine the second instruction group to which the second type instruction corresponding to the first type instruction belongs.

[0096] For example, step S1012 can be processed on a basic block basis, that is, step S1012 is executed for each basic block in the intermediate representation. For example, by analyzing the relative positional relationship between the first type of instruction and the second type of instruction it depends on in the intermediate representation, it can be determined which second type of instructions should be assigned to the same second instruction group.

[0097] For example, one example of step S1012 may include: in the order of instructions, for each first type instruction in the intermediate representation: in response to the second type instruction corresponding to the first type instruction not being grouped, the second type instruction and the ungrouped second type instruction located before the second type instruction are combined into a second instruction group.

[0098] For example, instruction order refers to the order in which instructions are arranged in the intermediate representation.

[0099] The above grouping scheme is designed based on the positional relationship between the first type of instructions and the second type of instructions in the intermediate representation. Taking load instructions as an example, since the order in which load data is used in the program is not necessarily consistent with the order in which load instructions are issued, there may be situations where the result of an earlier issued load instruction is used later, or the result of a later issued load instruction is used first. In the case where there is only one load unit in the hardware, all load instructions are still executed serially in the order of instructions on the load unit. Therefore, once a load instruction is completed, all load instructions issued before it have also been completed. Therefore, when processing the first type of instructions sequentially, it is only necessary to aggregate the second type of instructions corresponding to that first type of instruction and the ungrouped second type of instructions located before it into a second instruction group.

[0100] Figure 3B This is a schematic diagram illustrating another intermediate representation provided for at least one embodiment of the present disclosure.

[0101] The following will be based on Figure 3B The pseudocode shown below provides a detailed description of an example of step S1012. For example, Figure 3B This diagram shows a basic block representing the intermediate representation. This basic block includes four load instructions ld0~ld3 and four data use instructions use0~use3. There may be zero or more other instructions between the load instructions. Figure 3B (Not shown in the diagram, and has no dependency on load instructions), there may also be 0 or more other instructions between data usage instructions. Figure 3B(The ellipsis indicates that it has no dependency on the load instruction). Here, there is a dependency between the load instruction and the data usage instruction; the load instruction is a type II instruction, and the data usage instruction is a type I instruction.

[0102] First, for each basic block in the intermediate representation, a register-to-instruction mapping table can be initialized, which can be, for example, a first-in-first-out (FIFO) structure. The instructions in the basic block are traversed in ascending order: if the current instruction is a type II instruction, its destination register information and the instruction itself are saved in the mapping table as key-value pairs (e.g., for the load instruction a = ld0, an entry can be recorded in the mapping table).<a,ld0> When the mapping table is not empty, for each instruction encountered, it is necessary to check whether the data used by the current instruction depends on a second-type instruction (compared to entries in the mapping table). If the data used by the current instruction depends on a second-type instruction, the search can begin from the beginning of the mapping table until the corresponding second-type instruction is found (e.g., the source register of the current instruction and the destination register of the second-type instruction are the same). At this point, all entries in the mapping table from the beginning to the corresponding entry of the second-type instruction can be selected, and the associated second-type instructions of these entries can be grouped into the same second-type instruction group. After grouping, these entries need to be removed from the mapping table. If the corresponding second-type instruction is not found in the mapping table, it means that the corresponding second-type instruction has been grouped, and the traversal can continue to the next instruction.

[0103] by Figure 3BFor example, when iterating to the data using the instruction `use0`, the entries recorded in the mapping table are as follows:<a,ld0> ,<b,ld1> ,<c,ld2> ,<d,ld3> Since the current instruction depends on the data loaded into register c, it can be determined that the current instruction corresponds to the load instruction ld2. Therefore, the instruction is selected from the beginning position in the mapping table to...<c,ld2> All entries (i.e.)<a,ld0> ,<b,ld1> ,<c,ld2> The load instructions (ld0, ld1, ld2) associated with these entries are grouped into the same second instruction group, and these entries are removed from the mapping table. Next, the data use instruction use1 is traversed. This instruction depends on the data loaded into register b, but the current mapping table only contains the entries.<d,ld3> Therefore, the load instruction ld1 corresponding to the current instruction cannot be found in the mapping table (the load instruction ld1 has been grouped). At this point, we can continue to traverse the next instruction. Next, we traverse to the data use instruction use2. The current instruction depends on the data loaded into register a, but the current mapping table only has one entry left.<d,ld3> Therefore, the load instruction ld0 corresponding to the current instruction cannot be found in the mapping table (the load instruction ld0 has been grouped). At this point, we can continue traversing to the next instruction. Next, we traverse to the data usage instruction use3. The current instruction depends on the data loaded into register d, so we select the instruction from the beginning of the mapping table to...<d,ld3> All entries (i.e., only)<d,ld3> ),Will<d,ld3> The associated load instruction (ld3) is grouped into the same second instruction group, and the entry is removed from the mapping table. At this point, the mapping table is empty, and the grouping of load instructions in this basic block is complete. Through the above operations, two second instruction groups are obtained, namely (ld0, ld1, ld2) and (ld3).

[0104] An example of step S102 includes the following steps S1021 to S1022.

[0105] Step S1021: Assign the second type of instructions in the same second instruction group to the same hardware synchronization channel.

[0106] Step S1022: In response to the existence of an idle hardware synchronization channel, determine that different second instruction groups correspond to different hardware synchronization channels, and assign the second type of instructions in the different second instruction groups to the different hardware synchronization channels; or in response to the absence of an idle hardware synchronization channel, determine that different second instruction groups correspond to different hardware synchronization channel units, and assign the second type of instructions in the different second instruction groups to the different hardware synchronization channel units.

[0107] For example, in step S1021, based on the grouping results obtained in step S101, the second type of instructions in the same second instruction group can be assigned to the same hardware synchronization channel.

[0108] For example, in step S1022, "idle hardware synchronization channel" refers to a hardware synchronization channel unit in which no instruction has been assigned. "Idle hardware synchronization channel unit" refers to a hardware synchronization channel unit that has not yet been assigned an instruction. It should be noted that assigning an instruction to an idle hardware synchronization channel as mentioned above can mean assigning the instruction to the first hardware synchronization channel unit in that idle hardware synchronization channel. By prioritizing the assignment of instructions to idle synchronization channels, excessive irrelevant instructions can be prevented from being blocked during subsequent instruction waiting, thereby eliminating unnecessary execution dependencies and improving parallel execution efficiency.

[0109] In the allocation method provided in at least one embodiment of this disclosure, by allocating instructions in the same instruction group to the same hardware synchronization channel and allocating instructions in different instruction groups to different hardware synchronization channels or hardware synchronization channel units, the synchronization channel conflicts and additional waiting between different instructions are effectively reduced under the condition of limited hardware synchronization channel resources.

[0110] The allocation method provided in at least one embodiment of this disclosure may further include step S103.

[0111] Step S103: Based on the grouping results, insert operation instructions into the intermediate representation. The operation instructions include waiting instructions and switching instructions. The waiting instructions are configured to wait for the second type of instruction corresponding to the target number of hardware synchronization channel units to finish executing. The switching instructions are configured to switch to the next hardware synchronization channel unit of the current hardware synchronization channel unit.

[0112] For example, in step S103, the operation instruction is an instruction to operate the hardware synchronization channel. The insertion operation instruction refers to inserting the corresponding instruction at the corresponding position in the intermediate representation, which is equivalent to updating the intermediate representation.

[0113] For example, one example of a wait instruction is waittle.sc n, which blocks the execution of subsequent instructions, but only waits for the completion of the second-type instructions corresponding to the hardware synchronization channel (sc) excluding the most recent n hardware synchronization channel units. Here, "most recent" refers to the hardware synchronization channel unit most recently assigned a second-type instruction. In this example, the target number = the total number of hardware synchronization channel units in the hardware synchronization channel that have been assigned second-type instructions - n. For example, assuming that hardware synchronization channel units slots 0 to 4 in hardware synchronization channel sc1 have been assigned second-type instructions, the wait instruction waittle.sc1 2 means blocking the execution of subsequent instructions, only waiting for the second-type instructions in slots 0 to 2 in hardware synchronization channel sc1 to complete (without waiting for slots 3 to 4).

[0114] For example, another example of a wait instruction is waiter.sc 0, which blocks the execution of subsequent instructions until all Type II instructions in the current hardware synchronization channel (sc) have finished executing. In this example, the target number equals the total number of hardware synchronization channel units in that hardware synchronization channel.

[0115] For example, one example of a switching instruction is inc.sc. In a hardware synchronization channel (sc), hardware synchronization channel units are used in a cyclical manner. The inc.sc instruction can be used to switch to the next hardware synchronization channel unit (which is used to assign to the second type of instruction following the inc.sc instruction). After switching to the last hardware synchronization channel unit, it will cycle back to the first hardware synchronization channel unit.

[0116] For ease of understanding, the allocation method provided in at least one embodiment of this disclosure can be considered as two stages: an instruction grouping stage and an instruction allocation and insertion stage. The instruction grouping stage can be referred to step S101 and its specific examples, and the instruction allocation and insertion stage can be referred to steps S102-S103 and their specific examples. Each stage performs one instruction traversal.

[0117] In the allocation method provided in at least one embodiment of this disclosure, an example of steps S102 and S103 is as follows:

[0118] For each basic block, during the traversal of instructions within the basic block, the following operations are performed: If the current instruction is a second-type instruction and the second-type instructions in the second instruction group to which the current instruction belongs have not yet been allocated, allocate an idle hardware synchronization channel or an idle hardware synchronization channel unit to the current instruction and add a hardware synchronization channel marker to the current instruction; if an idle hardware synchronization channel unit is allocated to the current instruction, insert a switching instruction before the current instruction; if the current instruction is a second-type instruction and the second-type instructions in the second instruction group to which the current instruction belongs have already been allocated, allocate the same hardware synchronization channel or hardware synchronization channel unit to the current instruction and add a hardware synchronization channel marker to the current instruction; or if the current instruction is a first-type instruction, insert a waiting instruction before the current instruction.

[0119] For example, the current instruction refers to the instruction currently being traversed.

[0120] For example, if the current instruction is a type 2 instruction, and other type 2 instructions in the second instruction group to which the current instruction belongs have not yet been assigned, this indicates that the current instruction is the first instruction in that second instruction group, or that there is only one instruction in that second instruction group (i.e., the current instruction itself). In this case, an available hardware synchronization channel can be preferentially allocated to the current instruction. It should be noted that allocating an available hardware synchronization channel to the current instruction can mean assigning the current instruction to the first available hardware synchronization channel unit (e.g., slot0). If there is no available hardware synchronization channel, an available hardware synchronization channel unit can be allocated to the current instruction. Furthermore, a hardware synchronization channel marker can be added to the current instruction to identify which hardware synchronization channel (or hardware synchronization channel unit) the current instruction is assigned to. For example, if the current instruction a1=ld0 is assigned to hardware synchronization channel sc1, an example of the current instruction after adding the hardware synchronization channel marker would be a1=ld0.sc1.

[0121] For example, when allocating an idle hardware synchronization channel unit for the current instruction, a switching instruction can be inserted before the current instruction to switch to the next hardware synchronization channel unit. During instruction execution, the channel switching operation is performed first, followed by the current instruction, which is equivalent to allocating a new hardware synchronization channel unit for the current instruction.

[0122] For example, if the current instruction is a type 2 instruction, and other type 2 instructions in the second instruction group to which the current instruction belongs have already been assigned, it means that the current instruction is not the first instruction in that second instruction group. In this case, the current instruction needs to be assigned to the same hardware synchronization channel unit within the same hardware synchronization channel as other instructions in that second instruction group. That is, the current instruction needs to be assigned to the hardware synchronization channel unit corresponding to the first instruction in that second instruction group. Furthermore, a hardware synchronization channel marker can be added to the current instruction to identify which hardware synchronization channel (hardware synchronization channel unit) the current instruction is assigned to. For example, assuming the second instruction group includes two instructions, a1=ld0 and a2=ld1, and a1=ld0 has already been assigned to slot0 of hardware synchronization channel sc1, the current instruction a2=ld1 also needs to be assigned to slot0 of hardware synchronization channel sc1. An example of the current instruction after adding the hardware synchronization channel marker would be a2=ld1.sc1.

[0123] For example, when the current instruction is a type 1 instruction, a wait instruction can be inserted before the current instruction to ensure that the required data is ready before executing the type 1 instruction, thus achieving synchronous instruction control. To achieve more precise control and avoid reduced execution efficiency due to excessively long wait times or insufficient data due to excessively short wait times, the register information of type 2 instructions can be recorded during instruction traversal, and the wait time of the wait instruction can be determined based on the data dependency relationship between type 1 and type 2 instructions.

[0124] For example, if the current instruction is not a first-type instruction or a second-type instruction, no operation is required, and the process can continue to traverse the next instruction.

[0125] After inserting wait instructions, toggle instructions, and adding hardware synchronization channel markers for the second type of instructions, the intermediate representation can be considered updated accordingly. These updates explicitly encode asynchronous loading operations and their synchronization requirements into the intermediate representation, reflecting the new execution order and resource dependencies, thus supporting subsequent code generation. For example, after updating the entire intermediate representation, the compiler can generate machine code or assembly code executable for the target hardware platform based on the updated intermediate representation. The generated code will contain hardware-recognizable wait instructions, toggle instructions, and encoded information for identifying synchronization channels, thereby ensuring correct synchronization between the second type of instructions and the first type of instructions, fully leveraging the hardware's support for asynchronous execution and synchronization management.

[0126] The allocation method provided in at least one embodiment of this disclosure may further include step S104.

[0127] Step S104: Set register definition information for each basic block, wherein the register definition information is used to manage the destination register information of the second type of instructions in the basic block based on the hardware synchronization channel index.

[0128] For example, register definition information can be used to record the destination register information of second-type instructions in a basic block. It can be simplified to a two-dimensional array, RegDef[sync_num][slot_num], where sync_num represents the number of hardware synchronization channels, and slot_num represents the number of hardware synchronization channel units (slots) within each hardware synchronization channel. Each line of the register definition information corresponds to a synchronization channel and can be considered as a queue of length slot_num, storing the destination register information of second-type instructions. The destination register information refers to the register number to which the execution result of the second-type instruction will be written after execution; for example, the destination register information for the instruction a1=ld0.sc1 is a1. Since each hardware synchronization channel unit can be allocated one or more second-type instructions, each item in the queue is configured to store one or more destination register information entries.

[0129] Register definition information can be accessed through the hardware synchronization channel index. For example, the register definition information line corresponding to hardware synchronization channel sc0 is denoted as RegDef[0][0…slot_num-1], which is used to record the destination register information of the second type of instruction allocated to hardware synchronization channel sc0, and to manage its life cycle. The register definition information line will also be referred to as the information queue below.

[0130] By setting register definition information, the hardware synchronization channel, destination register information, and instruction order of the second type of instruction can be recorded, providing basic support for instruction synchronization management. When processing the first type of instruction, by querying the register definition information in conjunction with its source register information, the hardware synchronization channel to which the second type of instruction depends can be identified. Based on this, it can be determined how many synchronization channel units the first type of instruction needs to wait for the second type of instruction to complete, and corresponding wait instructions can be inserted to ensure that the first type of instruction is executed only after the data is ready, thereby achieving precise and convenient synchronization control.

[0131] Correspondingly, an example of "inserting a wait instruction before the current instruction in response to the current instruction being a first-type instruction" is as follows: In response to the current instruction being a first-type instruction, determine the target index corresponding to the source register information of the current instruction in the target information queue in the register definition information, where the target information queue corresponds to the hardware synchronization channel corresponding to the current instruction; determine the number of targets corresponding to the wait instructions based on the target index, and insert the wait instructions before the current instruction.

[0132] For example, if the current instruction is a first-type instruction, the target information queue refers to the register definition information line under the hardware synchronization channel index where the second-type instruction corresponding to the current instruction is located, such as RegDef[sc_idx][0…slot_num-1], where sc_idx is the hardware synchronization channel index corresponding to the second-type instruction corresponding to the current instruction.

[0133] The specific content of the waiting instruction can be determined through the above method, that is, the sc value and n value in the waiting instruction waittle.sc n. The following is an example: Suppose the current instruction is c1=add a1, a2, then the source register information corresponding to the current instruction is a1 and a2. Suppose that in the hardware synchronization channel allocation process above, the second type of instructions a1=ld0 and a2=ld1 have been allocated to the hardware synchronization channel unit slot0 of hardware synchronization channel sc1. At this time, by querying the register definition information, it can be found that a1 and a2 are located in the register definition information line corresponding to hardware synchronization channel sc1, and the sc value in the waiting instruction can be determined to be sc1. Further, suppose that the target information queue is determined to be RegDef[1][0…3] according to the hardware synchronization channel index sc1, and its content is read as RegDef[1][0…3]=[c1c2, b1b2, a1a2, NULL]. Therefore, we can determine that the target index corresponding to the source register information a1 and a2 of the current instruction in the target information queue is 2. Setting the value of n in the waiting instruction to be equal to the target index allows us to insert the waiting instruction waiter.sc1 2 before the current instruction c1=add a1, a2. At this point, the target quantity = the total number of hardware synchronization channel units allocated with second-type instructions in this hardware synchronization channel - n = 3 - 2 = 1. The current instruction needs to wait for the second-type instructions corresponding to the hardware synchronization channel units (slot1~slot2) containing b1, b2, c1, and c2 to finish executing, which means it needs to wait for the second-type instructions corresponding to the hardware synchronization channel unit (slot0) containing a1 and a2 to finish executing.

[0134] For example, to further facilitate information management, two sets of register definition information can be set for each basic block: entry register definition information and exit register definition information, corresponding to the entry and exit of the basic block. The entry register definition information records the initial register definition information of the basic block, and the exit register definition information records the register definition information after the traversal of the basic block is completed (that is, the updated register definition information).

[0135] An example of step S104 may include the following steps S1041 to S1043.

[0136] Step S1041: Initialize the register definition information of the first basic block to empty.

[0137] Step S1042: During the process of traversing the instructions in the current basic block, update the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction.

[0138] Step S1043: In response to the end of instruction traversal in the current basic block, initialize the register definition information of the successor basic block based on the register definition information of the current basic block.

[0139] For example, in step S1041, the first basic block refers to the first basic block in the intermediate representation, that is, the first basic block where the control flow begins to execute, and each element in its corresponding register definition information can be set to empty (NULL).

[0140] For example, in step S1042, with the allocation of the hardware synchronization channel and the insertion of switching instructions, it is necessary to update the register definition information of the current basic block.

[0141] For example, one example of step S1042 is as follows: In response to inserting a switching instruction before the current instruction, a circular shift operation is performed on the target information queue in the register definition information, wherein the target information queue corresponds to the hardware synchronization channel corresponding to the current instruction; In response to allocating a hardware synchronization channel or hardware synchronization channel unit to the current instruction, the register definition information is updated based on the hardware synchronization channel index corresponding to the hardware synchronization channel or hardware synchronization channel unit and the destination register information of the current instruction; or In response to inserting a wait instruction before the current instruction, all elements in the target information queue from the position corresponding to the target index to the tail of the queue are deleted.

[0142] For example, in response to inserting a switching instruction before the current instruction, a circular shift operation needs to be performed on the target information queue in the register definition information. Here, the current instruction is a Type II instruction, and the target information queue corresponds to the hardware synchronization channel where the current instruction is located. The circular shift operation is, for example, a right circular shift operation, which moves the tail element of the target information queue to the head, and the other elements shift to the right in sequence. For example, in response to inserting a switching instruction before the current instruction, assuming that the current hardware synchronization channel sc1 includes four hardware synchronization channel units slot0~slot3, before performing the circular shift operation, the target information queue RegDef[1][0…3]=[a1a2, NULL, NULL, NULL], and after performing the circular shift operation, the target information queue RegDef[1][0…3]=[NULL, a1a2, NULL, NULL], where NULL represents blank. In the above process, the pointer that operates on the target information queue always points to RegDef[1][0].

[0143] For example, when a hardware synchronization channel is allocated to the current instruction (whether it is idle or not), the register definition information can be updated based on the hardware synchronization channel index and the destination register information of the current instruction. As mentioned above, allocating a hardware synchronization channel to the current instruction is equivalent to allocating the current instruction to the first hardware synchronization channel unit. At this time, the register definition information line to be updated (also called the target information queue) can be determined according to the hardware synchronization channel index, and the destination register information of the current instruction is written to the first element of the target information queue. For example, if the current instruction a1=ld0 is allocated to the hardware synchronization channel sc1, the target information queue RegDef[1][0…slot_num-1] is determined according to the hardware synchronization channel index sc1, and a1 is added to its first element RegDef[1][0].

[0144] For example, when allocating a hardware synchronization channel unit (whether it is idle or not) for the current instruction, the register definition information can be updated based on the hardware synchronization channel index corresponding to the hardware synchronization channel unit and the destination register information of the current instruction. At this time, the register definition information line to be updated (also called the target information queue) can be determined according to the hardware synchronization channel index, and the destination register information of the current instruction is written into the first element of the target information queue. For example, if the current instruction a2=ld1 is allocated to hardware synchronization channel slot1 of hardware synchronization channel sc2, then the target information queue RegDef[2][0…slot_num-1] is determined according to the hardware synchronization channel index sc2, and a2 is added to its first element RegDef[2][0].

[0145] It should be noted that for the same current instruction, when both a circular shift operation and an update of register definition information based on the hardware synchronization channel index and destination register information are required, the circular shift operation is performed first, and then the register definition information is updated based on the hardware synchronization channel index and destination register information.

[0146] For example, in response to inserting a waiting instruction before the current instruction, all elements in the target information queue from the position corresponding to the target index to the tail need to be deleted. Here, the current instruction is a first-type instruction, and the target information queue corresponds to the hardware synchronization channel where the second-type instruction corresponding to the current instruction is located. Referring to the above embodiment for determining the waiting instruction, the meanings of the target index and the target information queue have been introduced, and will not be repeated here. For example, assuming the target information queue is RegDef[1][0…3] =[c1c2, b1b2, a1a2, NULL], and the target index is 2, then the elements in RegDef[1][2] need to be deleted, and the updated target information queue is RegDef[1][0…3] =[c1c2, b1b2, NULL, NULL]. For example, assuming the target information queue remains unchanged and the target index is 1, then the elements in RegDef[1][1], RegDef[1][2] and RegDef[1][3] need to be deleted, and the updated target information queue is RegDef[1][0…3] =[c1c2, NULL, NULL, NULL].

[0147] The above-described method of updating register definition information helps maintain the accuracy of data dependencies between instructions and the orderliness of synchronization control, thereby improving hardware concurrency and reducing the complexity of hardware implementation.

[0148] For example, in step S1043, when the instruction traversal in the current basic block has ended, the register definition information of the current basic block is the final result obtained after multiple updates. When setting the entry register definition information and exit register definition information, this register definition information is equivalent to the exit register definition information. The current basic block may have one or more successor basic blocks. A successor basic block refers to a basic block that is located after the current basic block in the program's control flow and may be directly executed, as opposed to a "predecessor basic block." A predecessor basic block refers to a basic block that is located before the current basic block in the program's control flow and may directly jump to the current basic block. Based on the exit register definition information of the current basic block, the register definition information of its successor basic blocks can be initialized.

[0149] For example, one example of step S1043 is as follows: In response to the existence of other predecessor basic blocks besides the current basic block, the register definition information of the current basic block and the register definition information of other predecessor basic blocks are merged to obtain the register definition information of the successor basic block; or in response to the existence of other predecessor basic blocks besides the current basic block, the register definition information of the current basic block is used as the register definition information of the successor basic block.

[0150] For example, if the current basic block has only one predecessor basic block as its successor, the register definition information of the current basic block after traversal can be directly used as the initial register definition information of the successor basic block.

[0151] For example, if the successor basic block of the current basic block has other predecessor basic blocks besides the current basic block, the register definition information of the current basic block after traversal needs to be merged with the register definition information of the other predecessor basic blocks after traversal, and then used as the initial register definition information of the successor basic block. For example, the merging operation is an element-level aggregation based on the index. For example, in the RegDef[syncnum][slot_num] structure, the union of elements at the same position is taken to integrate the register definition information from multiple predecessor basic blocks.

[0152] Figure 3C This is a schematic diagram of a control flow graph provided for at least one embodiment of the present disclosure.

[0153] like Figure 3C As shown, each rectangle represents a basic block, and the arrows indicate the control flow transfer from one basic block to another.

[0154] For example, if the current basic block is BB1, and its exit register definition information is denoted as RegDef_OUT_BB1, and its successor basic blocks BB2 and BB3 each have only one predecessor basic block (BB1), then the entry register definition information RegDef_IN_BB2 of the successor basic block BB2 and the entry register definition information RegDef_IN_BB3 of the successor basic block BB3 can be initialized to be consistent with RegDef_OUT_BB1.

[0155] For example, if the current basic block is BB3, and its exit register definition information is denoted as RegDef_OUT_BB3, and its successor basic block BB4 has two predecessor basic blocks (BB2 and BB3), then when initializing the entry register definition information RegDef_IN_BB4 of BB4, it is necessary to merge the exit register definition information RegDef_OUT_BB2 of BB2 and the exit register definition information RegDef_OUT_BB3 of BB3. Assuming RegDef_OUT_BB2[0][0…3]=[a1, b1, NULL,NULL] and RegDef_OUT_BB3[0][0…3]=[a2, b2b3, c1, NULL], then after the initialization operation, RegDef_IN_BB4[0][0…3]= [a1a2, b1b2b3, c1, NULL].

[0156] By using the above method, register definition information from different execution paths can be integrated during control flow convergence, thereby ensuring the integrity of register definition information and enabling reliable transmission of register definition information between basic blocks.

[0157] Figure 3D A flowchart illustrating another allocation method provided for at least one embodiment of this disclosure.

[0158] For example, such as Figure 3D As shown, an example of the instruction allocation and insertion stage of the allocation method provided in this embodiment may include steps S301 to S316. Figure 3D This is a specific example of steps S102 to S104.

[0159] Step S301: Initialize the register definition information of the current basic block.

[0160] For example, if the current basic block is the first basic block in the intermediate representation, the register definition information is initialized to empty; if the current basic block is not the first basic block in the intermediate representation, this step is not required, because its predecessor basic block has already executed step S316 after the traversal is completed, and the current basic block has been initialized.

[0161] Step S302: Begin traversing the instructions within the current basic block.

[0162] Step S303: Determine whether the current instruction is a type 2 instruction. If yes, proceed to step S304; otherwise, proceed to step S311.

[0163] For example, the second type of instruction has been defined in the foregoing embodiments, and it can be determined whether the current instruction is a second type of instruction based on the definition of the second type of instruction.

[0164] Step S304: Determine whether the second type of instruction in the second instruction group to which the current instruction belongs has been assigned. If yes, proceed to step S308; if no, proceed to step S305.

[0165] For example, allocated second-type instructions can be marked after each allocation, so that during traversal, it can be determined whether second-type instructions in the second instruction group to which the current instruction belongs have been allocated. Of course, other equivalent methods can also be used, such as using a status register, etc., and this disclosure does not limit this. For example, allocated second-type instructions can also be deleted from the group after each allocation. If the elements in the group are empty, the update information UpdateSC=true can be set, which means that when allocating hardware synchronization channels later, it is necessary to switch the hardware synchronization channel or hardware synchronization channel unit; if the elements in the group are not empty, the update information UpdateSC=false can be set, which means that when allocating hardware synchronization channels later, it is not necessary to switch the hardware synchronization channel or hardware synchronization channel unit.

[0166] Step S305: Allocate an idle hardware synchronization channel or an idle hardware synchronization channel unit for the current instruction.

[0167] For example, if no allocation is made, it means that the current instruction is the first instruction in the second instruction group, or that there is only one instruction in the second instruction group (i.e., the current instruction itself). In this case, an idle hardware synchronization channel can be allocated to the current instruction first. If there is no idle hardware synchronization channel, an idle hardware synchronization channel unit can be allocated to the current instruction.

[0168] Step S306: In response to allocating an idle hardware synchronization channel unit, insert a switching instruction before the current instruction.

[0169] For example, if an idle hardware synchronization channel unit is to be allocated for the current instruction, a switching instruction needs to be inserted before the current instruction. The switching instruction has been described in the previous embodiments and will not be repeated here.

[0170] Step S307: Perform a circular shift operation on the target information queue in the register definition information.

[0171] For example, after inserting a switching instruction, a circular shift operation needs to be performed on the target information queue in the register definition information. The target information queue corresponds to the hardware synchronization channel where the current instruction resides. The circular shift operation has been described in the previous embodiments and will not be repeated here.

[0172] Step S308: Assign the same hardware synchronization channel or hardware synchronization channel unit to the current instruction.

[0173] For example, if an assignment has already been made, it means that the current instruction is not the first instruction in the second instruction group. In this case, the current instruction and other instructions in the second instruction group need to be assigned to the same hardware synchronization channel unit in the same hardware synchronization channel.

[0174] Step S309: Add a hardware synchronization channel marker to the current instruction.

[0175] For example, after allocating a channel, a hardware synchronization channel marker needs to be added to the current instruction to identify which hardware synchronization channel (hardware synchronization channel unit) the current instruction has been allocated to.

[0176] Step S310: Update the register definition information based on the hardware synchronization channel index and the destination register information of the current instruction.

[0177] For example, after allocating a channel, the register definition information needs to be updated based on the hardware synchronization channel index and the destination register information of the current instruction. The specific method has been described in the foregoing embodiments and will not be repeated here.

[0178] Step S311: Determine whether the register definition information contains the source register information corresponding to the current instruction. If yes, proceed to step S312; otherwise, proceed to step S315.

[0179] For example, if the register definition information contains the source register information corresponding to the current instruction, it means that the current instruction is a first-type instruction and needs further processing; otherwise, it means that the current instruction is an instruction other than the first-type instruction or the second-type instruction, and no processing is required. You can directly jump to the traversal end judgment step.

[0180] Step S312: Determine the target index corresponding to the source register information of the current instruction in the target information queue of the register definition information.

[0181] For example, for the first type of instruction, it is necessary to determine the target index in order to determine the waiting instruction. The specific method has been described in the foregoing embodiments and will not be repeated here.

[0182] Step S313: Determine the waiting instruction based on the target index and insert the waiting instruction before the current instruction.

[0183] For example, for the first type of instruction, after determining the waiting instruction, a waiting instruction needs to be inserted before the current instruction. The specific method has been described in the foregoing embodiments and will not be repeated here.

[0184] Step S314: Delete all elements in the target information queue from the position corresponding to the target index to the end of the queue.

[0185] For example, for the first type of instruction, after inserting the wait instruction, the register definition information needs to be updated. The specific method has been described in the foregoing embodiments and will not be repeated here.

[0186] Step S315: Determine if the current basic block has been traversed. If yes, proceed to step S316. If no, return to step S302.

[0187] For example, if the traversal is complete, the register definition information of the current basic block can be passed to the next basic block; if it is not complete, it returns to continue traversing the next instruction.

[0188] Step S316: Based on the register definition information of the current basic block, initialize the register definition information of the successor basic block of the current basic block.

[0189] For example, the information flow can be transmitted in the basic block through step S316. The specific method has been described in the previous embodiments and will not be repeated here.

[0190] Figure 4A This is a schematic diagram of an updated intermediate representation provided for at least one embodiment of the present disclosure.

[0191] The following will be based on Figure 4A The pseudocode shown in the intermediate representation details examples of steps S102 to S104. Figure 4A Yes Figure 3A The provided intermediate representation represents the result after executing steps S102 to S104 (for simplicity, Figure 4A Not shown in the middle Figure 3A (The ellipsis between instructions)

[0192] In this example, load instructions ld0~ld1 are grouped together, and ld2~ld3 are grouped together (for details on the grouping process, please refer to the documentation). Figure 3A (Description).

[0193] First, for each basic block in the intermediate representation, register definition information RegDef can be set. During the initialization phase, the register definition information of the first basic block can be initialized to NULL, and the initial information CurrentSC and update information UpdateSC for the hardware synchronization channel can be set. For example, during the initialization phase, CurrentSC can be set to sc1, which means that when allocating a hardware synchronization channel for the first load instruction in this basic block, it will be allocated to hardware synchronization channel sc1. For example, during the initialization phase, UpdateSC can be set to false, which means that when allocating a hardware synchronization channel for the first load instruction in this basic block, the hardware synchronization channel or hardware synchronization channel unit will not be switched.

[0194] The instructions in the current basic block are traversed in ascending order. Since the load instruction a1=ld0 is a second-type instruction, and the instructions in its instruction group (ld0, ld1) have not yet been allocated, an idle hardware synchronization channel sc1 is allocated to the load instruction ld0 according to CurrentSC=sc1. Assuming that the current hardware synchronization channel sc1 includes four hardware synchronization channel units slot0~slot3, after the above operation, the load instruction ld0 is allocated to hardware synchronization channel unit slot0 of hardware synchronization channel sc1. Next, a hardware synchronization channel marker is added to the load instruction ld0, such as... Figure 4A As shown, the load instruction after adding the mark is a1=ld0.sc1. Next, the register definition information is updated, and the destination register information a1 of the load instruction ld0 is added to the register definition information, so that the target information queue RegDef[1][0…3]=[a1, NULL, NULL, NULL].

[0195] When traversing to the load instruction a2=ld1, since load instruction ld1 is a second-type instruction and instruction ld0 in its instruction group (ld0, ld1) has already been allocated, we continue using CurrentSC=sc1, similarly allocating load instruction ld1 to the hardware synchronization channel unit slot0 of hardware synchronization channel sc1. Next, f, as... Figure 4A As shown, the load instruction after adding the marker is a2=ld1.sc1. Next, the register definition information is updated, and the destination register information a2 of the load instruction ld1 is added to the register definition information. Since the pointer always points to RegDef[1][0], the target information queue RegDef[1][0…3]=[a1a2, NULL, NULL, NULL]. At this time, in response to the fact that all instructions in the instruction group to which the load instruction ld1 belongs have been allocated channels, UpdateSc=true can be set to indicate that the next group of load instructions should be allocated to a hardware synchronization channel unit different from slot0 of sc1.

[0196] Assuming there are no other available hardware synchronization channels in this example, when the load instruction b1=ld2 is encountered, based on UpdateSc=true, it can be allocated to the available hardware synchronization channel unit slot1 in sc1. Since there are still unallocated instructions in the instruction group (ld0, ld1) to which the load instruction ld2 belongs, UpdateSc can be reset to false. Next, a hardware synchronization channel flag is added to the load instruction ld2, such as... Figure 4AAs shown, the load instruction after adding the marker is b1=ld2.sc1. Furthermore, a switching instruction inc.sc1 needs to be inserted before this load instruction. This instruction is used to switch from hardware synchronization channel unit slot0 in sc1 to hardware synchronization channel unit slot1. After inserting the switching instruction, the register definition information needs to be updated by performing a circular shift operation on the target information queue RegDef[1][0…3]=[a1a2, NULL, NULL, NULL], resulting in RegDef[1][0…3]=[NULL, a1a2, NULL, NULL]. Next, the register definition information is updated again, adding the destination register information b1 of the load instruction ld2 to the register definition information, making the target information queue RegDef[1][0…3]=[b1, a1a2, NULL, NULL].

[0197] When the load instruction b2=ld3 is encountered, based on UpdateSc=false, it is further allocated to the hardware synchronization channel unit slot1 of hardware synchronization channel sc1. Next, a hardware synchronization channel marker is added to the load instruction ld3, such as... Figure 4A As shown, the load instruction after adding the marker is b2=ld3.sc1. Next, the register definition information is updated, and the destination register information b2 of the load instruction ld3 is added to the register definition information. Since the pointer always points to RegDef[1][0], the target information queue RegDef[1][0…3]=[b1b2, a1a2, NULL, NULL]. At this time, in response to the fact that all instructions in the instruction group to which the load instruction ld3 belongs have been allocated channels, UpdateSc=true can be set to indicate that the next group of load instructions should be allocated to a hardware synchronization channel unit different from slot0 and slot1 of sc1.

[0198] When iterating through a data-using instruction (such as a calculation instruction), it is necessary to determine whether the source operand information of the data-using instruction exists in the register definition information. If it does not exist, continue iterating to the next instruction; if it does exist, refer to the following example:

[0199] When traversing to the addition instruction c1=add0 a1,a2, it can be determined that its source operand information a1 and a2 exist in the register definition information. A wait instruction needs to be inserted before the addition instruction add0. The operand n of the wait instruction is determined according to the target information queue RegDef[1][0…3]=[b1b2, a1a2, NULL, NULL]. Since the target index corresponding to the source operands a1 and a2 of the addition instruction add0 in the target information queue is 1, the operand n of the wait instruction is determined to be 1. That is, inserting the wait instruction waittle.sc1 1 before the addition instruction c1=add0 a1,a2 means that it is necessary to wait for the execution of the second type instruction corresponding to the hardware synchronization channel unit (slot0) in the hardware synchronization channel sc1, except for the latest hardware synchronization channel unit (slot1). After inserting the wait instruction, all elements from the position corresponding to the target index to the tail of the queue need to be deleted from the target information queue. At this time, the target information queue RegDef[1][0…3]=[b1b2, NULL, NULL, NULL].

[0200] When traversing to the addition instruction c2=add1 b1,b2, it can be determined that its source operand information b1 and b2 exist in the register definition information. A wait instruction needs to be inserted before the addition instruction add1. The operand n of the wait instruction is determined according to the target information queue RegDef[1][0…3]=[b1b2, NULL, NULL, NULL]. Since the target index corresponding to the source operands b1 and b2 of the addition instruction add1 in the target information queue is 0, the operand n of the wait instruction is determined to be 0. That is, inserting the wait instruction wait.sc1 0 before the addition instruction c2=add1 b1,b2 means that it is necessary to wait for the second type instruction corresponding to all hardware synchronization channel units (slot0) in the hardware synchronization channel sc1 to finish executing. After inserting the wait instruction, all elements from the position corresponding to the target index to the tail of the queue need to be deleted from the target information queue. At this time, the target information queue RegDef[1][0…3]=[NULL, NULL, NULL, NULL].

[0201] At this point, Figure 4A The instruction allocation and insertion tasks, as well as the register definition information update tasks, in the basic block shown have all been completed.

[0202] Figure 4B This is a schematic diagram of another updated intermediate representation provided for at least one embodiment of the present disclosure.

[0203] The following will be based on Figure 4B The pseudocode shown in the intermediate representation details examples of steps S102 to S104. Figure 4B Yes Figure 3B The provided intermediate representation represents the result after executing steps S102 to S104.

[0204] In this example, load instructions ld0~ld2 are grouped together, and ld3 is grouped together (for details on the grouping process, please refer to the documentation). Figure 3B (Description).

[0205] Since the overall process has been described in detail above, this example will not repeat it, but only shows the process of updating register definition information.

[0206] When the load instruction a=ld0 is reached, assuming it is allocated to slot0 of sc1, the target information queue in the register definition information is updated to RegDef[1][0…3]=[a, NULL, NULL, NULL].

[0207] When the traversal reaches the load instruction b=ld1, since it is in the same group as instruction ld0, it continues to be allocated to slot0 of sc1, and the target information queue in the register definition information is updated to RegDef[1][0…3]=[ab, NULL, NULL,NULL].

[0208] When the traversal reaches the load instruction c=ld2, since it is in the same group as instruction ld0, it continues to be allocated to slot0 of sc1, and the target information queue in the register definition information is updated to RegDef[1][0…3]=[abc, NULL, NULL,NULL].

[0209] Assuming there are no other idle hardware synchronization channels in this example, when the load instruction d=ld3 is reached, since the instructions in its instruction group have not yet been allocated, it is allocated to the idle hardware instruction channel unit slot1. Furthermore, a switching instruction inc.sc1 needs to be inserted before this load instruction. After inserting the switching instruction, the register definition information needs to be updated by performing a circular shift operation on the target information queue RegDef[1][0…3]=[abc, NULL, NULL, NULL], resulting in RegDef[1][0…3]=[NULL, abc, NULL, NULL]. Next, the register definition information is updated again, adding the destination register information d of the load instruction ld3 to the register definition information, making the target information queue RegDef[1][0…3]=[d, abc, NULL, NULL].

[0210] When iterating through a data-using instruction (such as a calculation instruction), it is necessary to determine whether the source operand information of the data-using instruction exists in the register definition information. If it does not exist, continue iterating to the next instruction; if it does exist, refer to the following example:

[0211] When the data usage instruction `use0 c` is reached, it can be determined that its source operand information `c` exists in the register definition information. A wait instruction needs to be inserted before the `use0` instruction. The operand `n` of the wait instruction is determined based on the target information queue `RegDef[1][0…3]=[d, abc, NULL, NULL]`. Since the target index corresponding to the source operand `c` of the `use0` instruction in the target information queue is 1, the operand `n` of the wait instruction is determined to be 1. That is, the wait instruction `waitle.sc1 1` is inserted before the `use0` instruction `c`. After inserting the wait instruction, all elements from the position corresponding to the target index to the tail of the target information queue need to be deleted. At this time, the target information queue `RegDef[1][0…3]=[d,NULL, NULL, NULL]`.

[0212] When the traversal reaches the data usage instruction use1 b, since the deletion operation was performed in the previous step, its source operand information b does not exist in the register definition information, so the traversal continues to the next instruction.

[0213] When the traversal reaches the data usage instruction use2 a, since its source operand information 'a' does not exist in the register definition information, the traversal continues to the next instruction.

[0214] When traversing to the data usage instruction `use3 d`, it can be determined that its source operand information `d` exists in the register definition information. A wait instruction needs to be inserted before the data usage instruction `use3`. The operand `n` of the wait instruction is determined based on the target information queue `RegDef[1][0…3]=[d, NULL, NULL, NULL]`. Since the target index corresponding to the source operand `d` of the data usage instruction `use3` in the target information queue is 0, the operand `n` of the wait instruction is determined to be 0. That is, the wait instruction `waitle.sc1 0` is inserted before the data usage instruction `use3 d`. After inserting the wait instruction, all elements from the position corresponding to the target index to the tail of the queue need to be deleted from the target information queue. At this time, the target information queue `RegDef[1][0…3]=[NULL,NULL, NULL, NULL]`.

[0215] At this point, Figure 4B The instruction allocation and insertion tasks, as well as the register definition information update tasks, in the basic block shown have all been completed.

[0216] The allocation method provided in at least one embodiment of this disclosure further includes: for a basic block including a loop back edge, in response to the fact that the register definition information of the basic block at the end of the traversal has not changed compared with the previous loop, determining that the subsequent basic block of the current basic block continues to perform the traversal operation.

[0217] For example, a basic block that includes a circular back edge is a basic block that has one or more edges pointing from that basic block to a previous basic block.

[0218] Figure 5 This is a schematic diagram of another control flow graph provided for at least one embodiment of the present disclosure.

[0219] like Figure 5 As shown, each rectangle represents a basic block, the arrows indicate the control flow transfer from one basic block to another, and the dashed arrows indicate loop back edges.

[0220] exist Figure 5 In the example, BB2 is a basic block that includes a loop back edge. In the BB1-BB2-BB1 loop, if the exit register definition of BB2 remains unchanged compared to the previous loop, the loop has converged (reached a fixed point), and the traversal of BB2's successor basic block BB3 can continue. Therefore, for basic blocks that include loop back edges, the exit register definition information for each loop can be saved to support comparisons.

[0221] By using the above methods, we can avoid infinite loop analysis, significantly reduce time complexity, and at the same time ensure the accuracy and completeness of data flow analysis.

[0222] It should also be noted that the execution order of the various steps of the allocation method in the various embodiments of this disclosure is not limited. Although the execution process of each step has been described in a specific order above, this does not constitute a limitation on the embodiments of this disclosure. The various steps in the allocation method can be executed serially or in parallel, which can be determined according to actual needs.

[0223] For example, compared to the above description, the allocation method provided in at least one embodiment of this disclosure may include more or fewer steps, and the embodiments of this disclosure do not limit this.

[0224] Figure 6 This is a schematic block diagram of an allocation device provided for at least one embodiment of the present disclosure. The allocation device may be, for example, a component of a compiler, or a device that works in conjunction with a compiler.

[0225] For example, such as Figure 6 As shown, the allocation device 600 provided in at least one embodiment of this disclosure may include a grouping module 601 and an allocation module 602.

[0226] In some examples, the grouping module 601 is configured to group second-type instructions corresponding to the first-type instructions according to the position of the first-type instructions in the intermediate representation corresponding to the program to be compiled, wherein there is a dependency between the first-type instructions and the second-type instructions.

[0227] In some examples, the allocation module 602 is configured to allocate a hardware synchronization channel for the second type of instruction based on the grouping result, wherein the hardware synchronization channel is configured to synchronize the first type of instruction with the second type of instruction.

[0228] For example, in at least one embodiment of this disclosure, the grouping module 601 includes a first grouping unit. The first grouping unit is configured to: determine a second instruction group to which a second type instruction corresponding to the first type instruction belongs, based on the position of the first type instruction in the intermediate representation and in conjunction with a preset grouping size, wherein the preset grouping size indicates the maximum number of first type instructions corresponding to all second type instructions in each second instruction group.

[0229] For example, in at least one embodiment of this disclosure, the first grouping unit is further configured to: divide the first type of instructions in the intermediate representation into at least one first instruction group according to a preset grouping size, wherein the number of first type instructions in the first instruction group does not exceed the preset grouping size, and the positions of each first type instruction in the first instruction group are consecutive in the intermediate representation; for each first instruction group, the second type instructions corresponding to all the first type instructions in the first instruction group are taken as a second instruction group.

[0230] For example, in at least one embodiment of this disclosure, the grouping module 601 includes a second grouping unit. The second grouping unit is configured to: determine the second instruction group to which the second type instruction corresponding to the first type instruction belongs, based on the position of the first type instruction in the intermediate representation and the position of the second type instruction corresponding to the first type instruction in the intermediate representation.

[0231] For example, in at least one embodiment of this disclosure, the grouping module 601 includes a second grouping unit. The second grouping unit is further configured to: in accordance with the instruction order, for each first type instruction in the intermediate representation: in response to the second type instruction corresponding to the first type instruction not being grouped, group the second type instruction and the ungrouped second type instruction located before the second type instruction as a second instruction group.

[0232] For example, in at least one embodiment of this disclosure, each hardware synchronization channel includes at least one hardware synchronization channel unit, and the allocation module 602 is configured to allocate second type instructions in the same second instruction group to the same hardware synchronization channel; in response to the existence of an idle hardware synchronization channel, determine that different second instruction groups correspond to different hardware synchronization channels, and allocate the second type instructions in different second instruction groups to different hardware synchronization channels; or in response to the absence of an idle hardware synchronization channel, determine that different second instruction groups correspond to different hardware synchronization channel units, and allocate the second type instructions in different second instruction groups to different hardware synchronization channel units.

[0233] For example, in at least one embodiment of this disclosure, the allocation device 600 further includes an insertion module. The insertion module is configured to insert operation instructions into the intermediate representation based on the grouping results, wherein the operation instructions include a wait instruction and a switch instruction, the wait instruction being configured to wait for the execution of the second type of instruction corresponding to the target number of hardware synchronization channel units to end, and the switch instruction being configured to switch to the next hardware synchronization channel unit of the current hardware synchronization channel unit.

[0234] For example, in at least one embodiment of this disclosure, for each basic block, during the traversal of instructions in the basic block, the allocation module is configured to, in response to the current instruction being a second type instruction and the second type instructions in the second instruction group to which the current instruction belongs not yet being allocated, allocate an idle hardware synchronization channel or an idle hardware synchronization channel unit for the current instruction and add a hardware synchronization channel marker to the current instruction; or, in response to the current instruction being a second type instruction and the second type instructions in the second instruction group to which the current instruction belongs already being allocated, allocate the same hardware synchronization channel or hardware synchronization channel unit for the current instruction and add a hardware synchronization channel marker to the current instruction. For each basic block, during the traversal of instructions in the basic block, the insertion module is configured to, in response to allocating an idle hardware synchronization channel unit for the current instruction, insert a switching instruction before the current instruction; or, in response to the current instruction being a first type instruction, insert a waiting instruction before the current instruction.

[0235] For example, in at least one embodiment of this disclosure, the allocation device 600 further includes a setting module. The setting module is configured to set register definition information for each basic block, wherein the register definition information is used to manage destination register information for second-type instructions in the basic block based on a hardware synchronization channel index.

[0236] For example, in at least one embodiment of this disclosure, the setting module includes an initialization unit and an update unit. The initialization unit is configured to initialize the register definition information of the first basic block to empty; in response to the end of instruction traversal in the current basic block, it initializes the register definition information of the subsequent basic blocks based on the register definition information of the current basic block. The update unit is configured to update the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction during instruction traversal in the current basic block.

[0237] For example, in at least one embodiment of this disclosure, the updating unit is further configured to: in response to inserting a switching instruction before the current instruction, perform a circular shift operation on the target information queue in the register definition information, wherein the target information queue corresponds to the hardware synchronization channel corresponding to the current instruction; or in response to allocating a hardware synchronization channel or hardware synchronization channel unit for the current instruction, update the register definition information based on the hardware synchronization channel index corresponding to the hardware synchronization channel or hardware synchronization channel unit and the destination register information of the current instruction.

[0238] For example, in at least one embodiment of this disclosure, the insertion module is further configured to: in response to the current instruction being a first type instruction, determine the target index corresponding to the source register information of the current instruction in the target information queue in the register definition information, wherein the target information queue corresponds to the hardware synchronization channel corresponding to the current instruction; determine the target number corresponding to the waiting instruction based on the target index, and insert the waiting instruction before the current instruction.

[0239] For example, in at least one embodiment of this disclosure, the update unit is further configured to: in response to inserting a wait instruction before the current instruction, delete all elements in the target information queue from the position corresponding to the target index to the tail of the queue.

[0240] For example, in at least one embodiment of this disclosure, the initialization unit is further configured to: in response to the existence of other predecessor basic blocks besides the current basic block in the subsequent basic block, merge the register definition information of the current basic block and the register definition information of other predecessor basic blocks to obtain the register definition information of the subsequent basic block; or in response to the existence of other predecessor basic blocks besides the current basic block in the subsequent basic block, use the register definition information of the current basic block as the register definition information of the subsequent basic block.

[0241] For example, in at least one embodiment of this disclosure, the allocation device 600 further includes a jump module. The jump module is configured to: for a basic block including a loop back edge, in response to the basic block's register definition information at the end of traversal not changing compared to the previous loop, determine to jump to the successor basic block of the current basic block to continue the traversal operation.

[0242] It should be noted that the above-mentioned modules and units can be implemented by software, hardware, firmware or any combination thereof. For example, the grouping module and the allocation module can be implemented as grouping circuit and allocation circuit respectively. The embodiments of this disclosure do not limit their specific implementation methods.

[0243] It should be understood that the dispensing device 600 provided in at least one embodiment of this disclosure can be used to implement the aforementioned dispensing method and can also achieve similar technical effects as the aforementioned dispensing method, which will not be elaborated here.

[0244] It should be noted that in the embodiments of this disclosure, the distribution device 600 may include more or fewer modules or units, and the connection relationship between the various modules or units is not limited and can be determined according to actual needs. The specific configuration of each module or unit is not limited; it can be constructed from analog devices according to circuit principles, or from digital chips, or in other suitable ways.

[0245] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0246] For example, such as Figure 7 As shown, the electronic device 700 includes at least one processor 701 and at least one memory 702. The at least one memory 702 includes one or more computer program modules. These computer program modules are stored in the memory 702 and configured to be executed by the at least one processor 701. The one or more computer program modules include instructions for performing the allocation method described above. When executed by the at least one processor 701, they can perform one or more steps of the allocation method provided in at least one embodiment of this disclosure. The memory 702 and the processor 701 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0247] For example, processor 701 can be a central processing unit (CPU), digital signal processor (DSP), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), artificial intelligence (AI) accelerator, or other form of processing unit with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) can be an x86, ARM, or RISC-V architecture. Processor 701 can be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 700 to perform desired functions.

[0248] For example, memory 702 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0249] Figure 8 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0250] The electronic devices in at least one embodiment of this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, and fixed terminals such as digital TVs and desktop computers. Figure 8 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0251] The electronic device includes at least one processor and a memory. The processor may be referred to as processing device 801 as described below, and the memory may include at least one of read-only memory (ROM), random access memory (RAM), and storage device 808 as described below. The memory is used to store programs for performing the methods described in the various method embodiments above; the processor is configured to execute the programs stored in the memory. The processor may include a central processing unit (CPU) or other forms of processing unit having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0252] like Figure 8 As shown, the electronic device 800 may include a processing unit 801 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) or a program loaded from a storage device 808 into a random access memory (RAM). Various programs and data required for the operation of the electronic device 800 are also stored in RAM 803. The processing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. Input / output (I / O) interfaces are also connected to the bus 804.

[0253] Typically, the following devices can be connected to I / O interface 805: input devices 806 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 807 including, for example, displays, speakers, vibrators, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and communication devices 809. Communication device 809 allows electronic device 800 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 8 An electronic device 800 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0254] In particular, according to at least one embodiment of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, at least one embodiment of this disclosure includes a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device 809, or installed from a storage device 808, or installed from a ROM 802. When the computer program is executed by a processing device 801, it performs the functions defined in the methods of at least one embodiment of this disclosure.

[0255] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In at least one embodiment of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In at least one embodiment of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, radio frequency (RF), etc., or any suitable combination thereof.

[0256] The aforementioned computer-readable medium may be included in the aforementioned electronic device 800; or it may exist independently and not assembled into the electronic device 800.

[0257] Figure 9 This is a schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure.

[0258] For example, such as Figure 9 As shown, a non-transitory computer-readable storage medium 900 stores computer-readable instructions 901, which, when executed by at least one processor, perform one or more steps of the above-described allocation method.

[0259] For example, the storage medium may include a memory card for a smartphone, a storage component for a tablet computer, a hard drive for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media. For example, the readable storage medium may also be... Figure 7 The memory 702 in the memory is described in the foregoing content and will not be repeated here.

[0260] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0261] The following points should be noted regarding this disclosure:

[0262] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0263] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0264] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0265] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A method of dispensing, characterized by, The distribution method is executed by a compiler, comprising: grouping, according to positions of first type instructions in an intermediate representation corresponding to a program to be compiled, second type instructions corresponding to the first type instructions, wherein there is a dependency relationship between the first type instructions and the second type instructions; allocating, according to a grouping result, hardware synchronization channels for the second type instructions, wherein the hardware synchronization channels are configured to realize synchronization of the first type instructions and the second type instructions, wherein the allocating, according to the grouping result, of the hardware synchronization channels for the second type instructions comprises: allocating the second type instructions in a same second instruction group to a same hardware synchronization channel; in response to there being idle hardware synchronization channels, determining that different second instruction groups correspond to different hardware synchronization channels, and allocating the second type instructions in the different second instruction groups to the different hardware synchronization channels.

2. The dispensing method of claim 1, wherein, The grouping, according to positions of first type instructions in an intermediate representation corresponding to a program to be compiled, of second type instructions corresponding to the first type instructions comprises: determining, according to positions of the first type instructions in the intermediate representation, second instruction groups to which the second type instructions corresponding to the first type instructions belong, in combination with a preset grouping size, wherein the preset grouping size indicates a maximum number of first type instructions corresponding to all second type instructions in each second instruction group.

3. The dispensing method of claim 2, wherein, The determining, according to positions of the first type instructions in the intermediate representation, of second instruction groups to which the second type instructions corresponding to the first type instructions belong, in combination with a preset grouping size, comprises: dividing, according to the preset grouping size, the first type instructions in the intermediate representation into at least one first instruction group, wherein a number of first type instructions in the first instruction group does not exceed the preset grouping size, and positions of the first type instructions in the first instruction group in the intermediate representation are continuous; for each first instruction group, taking the second type instructions corresponding to all first type instructions in the first instruction group as a second instruction group.

4. The dispensing method of claim 1, wherein, The grouping, according to positions of first type instructions in an intermediate representation corresponding to a program to be compiled, of second type instructions corresponding to the first type instructions comprises: determining, according to positions of the first type instructions in the intermediate representation, second instruction groups to which the second type instructions corresponding to the first type instructions belong, in combination with positions of the second type instructions corresponding to the first type instructions in the intermediate representation.

5. The dispensing method of claim 4, wherein, The determining, according to positions of the first type instructions in the intermediate representation, of second instruction groups to which the second type instructions corresponding to the first type instructions belong, in combination with positions of the second type instructions corresponding to the first type instructions in the intermediate representation, comprises: for each first type instruction in the intermediate representation, in an order of the instructions: in response to the second type instruction corresponding to the first type instruction not being grouped, taking the second type instruction and ungrouped second type instructions before the second type instruction in position as a second instruction group.

6. The method of distributing according to claim 1, wherein, Each hardware synchronization channel comprises at least one hardware synchronization channel unit, The method further comprises: In response to the absence of an idle hardware synchronization channel, determining that a different second instruction group corresponds to a different hardware synchronization channel unit, and allocating a second type instruction in the different second instruction group to the different hardware synchronization channel unit.

7. The dispensing method of claim 6, wherein, The allocation method further comprises: According to the grouping result, inserting an operation instruction in the intermediate representation, The operation instruction comprises a wait instruction and a switch instruction, the wait instruction is configured to wait for the end of execution of a second type instruction corresponding to a target number of hardware synchronization channel units, and the switch instruction is configured to switch to a next hardware synchronization channel unit of a current hardware synchronization channel unit.

8. The dispensing method of claim 7, wherein, The intermediate representation comprises a plurality of basic blocks, According to the grouping result, allocating a hardware synchronization channel to the second type instruction, and inserting an operation instruction corresponding to the hardware synchronization channel in the intermediate representation, comprising: For each basic block, the following operations are performed in the process of traversing the instructions in the basic block: In response to the current instruction being a second type instruction and the second type instruction in the second instruction group to which the current instruction belongs not having been allocated, allocating an idle hardware synchronization channel or an idle hardware synchronization channel unit to the current instruction and adding a hardware synchronization channel tag to the current instruction; In response to allocating an idle hardware synchronization channel unit to the current instruction, inserting a switch instruction before the current instruction; In response to the current instruction being a second type instruction and the second type instruction in the second instruction group to which the current instruction belongs having been allocated, allocating the same hardware synchronization channel or hardware synchronization channel unit to the current instruction and adding a hardware synchronization channel tag to the current instruction; or In response to the current instruction being a first type instruction, inserting a wait instruction before the current instruction.

9. The dispensing method of claim 8, wherein, The allocation method further comprises: Setting register definition information for each basic block, wherein the register definition information is used to manage destination register information of a second type instruction in the basic block based on a hardware synchronization channel index, The setting of the register definition information for each basic block comprises: Initializing the register definition information of a first basic block as empty; In the process of traversing the instructions in a current basic block, updating the register definition information of the current basic block based on a hardware synchronization channel index corresponding to a current instruction; In response to the end of traversal of the instructions in the current basic block, initializing the register definition information of a successor basic block of the current basic block based on the register definition information of the current basic block.

10. The dispensing method of claim 9, wherein, The updating of the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction comprises: In response to the insertion of a switch instruction before the current instruction, performing a circular shift operation on a target information queue in the register definition information, wherein the target information queue corresponds to a hardware synchronization channel corresponding to the current instruction; or In response to the insertion of a switch instruction before the current instruction, performing a circular shift operation on a target information queue in the register definition information, wherein the target information queue corresponds to a hardware synchronization channel corresponding to the current instruction; or In response to the hardware synchronization channel or the hardware synchronization channel unit being allocated for the current instruction, the register definition information is updated based on a hardware synchronization channel index corresponding to the hardware synchronization channel or the hardware synchronization channel unit and destination register information of the current instruction.

11. The dispensing method of claim 9, wherein, The inserting the wait instruction before the current instruction in response to the current instruction being a first type instruction comprises: In response to the current instruction being a first type instruction, a target index corresponding to source register information of the current instruction in a target information queue in the register definition information is determined, wherein the target information queue corresponds to a hardware synchronization channel corresponding to the current instruction. A target number corresponding to the wait instruction is determined according to the target index, and the wait instruction is inserted before the current instruction.

12. The dispensing method of claim 11, wherein, The updating the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction further comprises: In response to the wait instruction being inserted before the current instruction, all elements in the target information queue from a position corresponding to the target index to the end of the queue are deleted.

13. The dispensing method of claim 9, wherein, The initializing the register definition information of a successor basic block of the current basic block based on the register definition information of the current basic block comprises: In response to the successor basic block having other predecessor basic blocks in addition to the current basic block, the register definition information of the current basic block and the register definition information of the other predecessor basic blocks are merged to obtain the register definition information of the successor basic block; or In response to the successor basic block not having other predecessor basic blocks in addition to the current basic block, the register definition information of the current basic block is taken as the register definition information of the successor basic block.

14. The dispensing method of claim 9, wherein, The allocation method further comprises: For a basic block comprising a loop back edge, in response to register definition information of the basic block at the end of a traversal operation not being changed compared with a previous loop, it is determined to jump to a successor basic block of the current basic block to continue the traversal operation.

15. An electronic device, comprising: The electronic device comprises: at least one processor; at least one memory including one or more computer program modules; The one or more computer program modules are stored in the at least one memory and configured to be executed by the at least one processor, and are used to implement the allocation method in any one of claims 1-14.

16. A non-transitory computer-readable storage medium, comprising: The non-transitory computer readable storage medium has computer readable instructions stored thereon, wherein the computer readable instructions are executed by at least one processor to perform the allocation method in any one of claims 1-14.

Images