Load balancing method and system for low-power ai processor

Abstract

The application discloses a load balancing method and system of a low-power-consumption AI processor, task sets of each core in a neural quasi-state processor are acquired to determine a task allocation priority sequence; according to the task allocation priority sequence, a core-to-core communication delay and a cache resource utilization rate are combined to obtain an initial task allocation scheme; if there is core overload or resource idling in the initial task allocation scheme, a load balancing algorithm is used to analyze the initial task allocation scheme, high-priority tasks are acquired from the overloaded core and are re-allocated to an idle core to determine an optimized task allocation scheme; for the optimized task allocation scheme, a cache resource allocation proportion is determined; according to the cache resource allocation proportion, a communication efficiency optimization algorithm is used to dynamically adjust a core-to-core communication path to obtain a final task execution scheme. The application significantly improves the balance of the neural quasi-state processor task allocation, the resource utilization rate and the communication efficiency, and optimizes the system performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processors, and particularly discloses a load balancing method and system for a low-power AI processor. BACKGROUND

[0002] Artificial intelligence processors play a crucial role in driving the development of intelligent computing, and their low-power design is essential for achieving efficient and sustainable computing, especially in edge devices and large-scale neural network tasks. However, existing methods often face problems of uneven resource allocation and low efficiency when processing complex computing tasks, leading to performance bottlenecks and energy waste. These problems are not caused by a single method, but rather by the lack of dynamic adaptation of hardware resources and the insufficient refinement of task allocation, making it difficult to cope with diverse task demands and the complexity of hardware architecture.

[0003] Specifically, the utilization rate of cache resources is low when a neuromorphic processor executes large-scale neural network tasks. Due to the lack of an efficient cache partitioning mechanism, data access between cores often requires frequent cross-layer communication, leading to increased latency and rising energy consumption. For example, when processing real-time image recognition tasks, cores may frequently wait due to cache access conflicts, resulting in decreased computing efficiency.

[0004] This cache resource management problem further exacerbates the imbalance of task allocation. Due to insufficient task characteristic analysis, the processor cannot reasonably divide tasks based on their computational demands and dependency relationships, leading to overloading of some cores and idling of others, resulting in low overall utilization of computing resources. For example, in speech processing tasks, some cores may experience processing delays due to taking on too many subtasks, while other cores may have idle resources due to improper task allocation.

[0005] Therefore, how to optimize cache resource partitioning and task allocation mechanisms to achieve load balancing and communication efficiency improvement between cores has become a key issue for performance optimization of low-power artificial intelligence processors. SUMMARY

[0006] The present application provides a load balancing method and system for a low-power AI processor, aiming to solve at least one of the above-mentioned deficiencies in the prior art.

[0007] One aspect of the present application relates to a load balancing method for a low-power AI processor, comprising the following steps:

[0008] Obtaining a task set for each core in a neuromorphic processor, the task set including multiple tasks, each task having a corresponding task dependency relationship and computational demand; analyzing the task dependency relationship and computational demand through a pre-established task characteristic analysis model to determine a task allocation priority sequence;

[0009] According to the task allocation priority sequence, in combination with the inter-core communication delay and the cache resource utilization, a dynamic scheduling algorithm is used to allocate tasks to each core to obtain an initial task allocation scheme;

[0010] If there is core overload or resource idling in the initial task allocation scheme, a load balancing algorithm is used to analyze the initial task allocation scheme, obtain high-priority tasks from the overloaded core, and re-allocate them to the idle core to determine an optimized task allocation scheme.

[0011] For the optimized task allocation scheme, the access frequency of inter-core communication data is analyzed, and a cache partitioning mechanism is used to determine the cache resource allocation ratio.

[0012] According to the cache resource allocation ratio, a communication efficiency optimization algorithm is used to dynamically adjust the inter-core communication path to obtain a final task execution scheme.

[0013] Further, the task set of each core in the neural quasi-state processor is obtained, the task set including a plurality of tasks, each task having a corresponding task dependency relationship and a calculation requirement; by a pre-established task characteristic analysis model, the task dependency relationship and the calculation requirement are analyzed, and the steps of determining the task allocation priority sequence include:

[0014] The task set and the task dependency relationship of each core in the neural quasi-state processor are obtained, the execution order constraint between tasks is represented by a directed acyclic graph, and a task dependency graph is obtained, the task dependency graph being obtained by the following formula:

[0015]

[0016] Wherein, represents the task dependency graph of the neural quasi-state processor, represents the set of all task nodes, represents the set of directed edges between tasks, represents the task dependency relationship matrix, each element representing the execution order constraint relationship between tasks;

[0017] The task set of each core in the neural quasi-state processor is obtained by the following formula:

[0018]

[0019] Wherein, represents the th neural quasi-state processor core, represents the th task allocated to the th core, represents the total number of tasks carried by the th core;

[0020] The execution order constraint between tasks is represented by a directed acyclic graph, which is derived by the following formula:

[0021]

[0022] wherein, represents the reachability function of task to task , represents if there is a directed path from task to task ; when there is a directed path from task to task , it is 1, otherwise 0, which is used to determine whether the execution order constraint between tasks exists;

[0023] Through the pre-established task characteristic analysis model, the earliest start time and the latest start time of each task are calculated by the critical path method according to the task dependency graph and the computing demand, and the task allocation priority sequence is determined. The earliest start time of each task is derived by the following formula:

[0024]

[0025] wherein, represents the earliest start time of task , represents the set of all predecessor tasks of task , represents the earliest start time of predecessor task , represents the duration of predecessor task ;

[0026] The latest start time of each task is derived by the following formula:

[0027]

[0028] wherein, represents the latest start time of task , represents the set of all successor tasks of task , represents the latest start time of successor task , represents the duration of task ;

[0029] The task allocation priority sequence is derived by the following formula:

[0030]

[0031] wherein, represents the assignment priority of a task , represents the weight coefficient of a task , represents the computing demand of a task , represents the total float time of a task , represents the resource amount required by a task .

[0032] Further, according to the task assignment priority sequence, in combination with the inter-core communication delay and the cache resource utilization, a dynamic scheduling algorithm is adopted to assign the tasks to the cores, and the step of obtaining the initial task assignment scheme comprises:

[0033] obtaining the task assignment priority sequence and the real-time resource state, extracting the communication delay data from the communication topology structure, calculating the shortest communication path between each core by using a graph traversal algorithm, and determining the inter-core communication delay matrix;

[0034] if the delay of a path in the inter-core communication delay matrix exceeds a preset threshold, recalculating the suboptimal path according to the communication topology structure to obtain an adjusted communication delay matrix;

[0035] according to the adjusted communication delay matrix and the cache resource utilization, adopting a priority queue mechanism, combining the task computing demand and the core processing capacity, generating a preliminary mapping relationship between the tasks and the cores, and obtaining the initial task assignment scheme.

[0036] Further, in the step of obtaining the task assignment priority sequence and the real-time resource state, extracting the communication delay data from the communication topology structure, calculating the shortest communication path between each core by using a graph traversal algorithm, and determining the inter-core communication delay matrix, the shortest communication path between each core is obtained by the following formula:

[0037]

[0038] wherein, represents the shortest communication delay between core and core , represents the number of all possible paths from core to core , represents the th path, represents the edge in the path, represents the communication delay time of the edge ;

[0039] The inter-core communication delay matrix is ​​derived using the following formula:

[0040]

[0041] in, The number of cores in the inter-core communication delay matrix represents the number of cores in the inter-core communication delay matrix. Line number The elements of the column, when the core equals core A latency of 0 indicates communication within the same core. and core When there is no connection between them, the delay is infinite. Indicates core To the core The actual communication latency value.

[0042] Furthermore, if the delay of a path in the inter-core communication delay matrix exceeds a preset threshold, the suboptimal path is recalculated based on the communication topology to obtain the adjusted communication delay matrix. The suboptimal path is derived using the following formula:

[0043]

[0044] in, This represents the optimal or suboptimal path based on the topology. This represents the set of all feasible paths in the communication topology. Represents the edges in the path The weight, Representing an edge The delay factor, This represents the path complexity penalty factor. Representing a path The number of jumps or the complexity function;

[0045] The adjusted communication delay matrix is ​​obtained using the following formula:

[0046]

[0047] in, This represents the adjusted communication delay matrix. Represents the original communication delay matrix. The matrix represents the indication of positions exceeding the threshold. This represents the delay matrix after rerouting. This indicates an element-wise multiplication operation.

[0048] Further, in the step of generating the preliminary mapping relationship between the tasks and the cores and obtaining the initial task allocation scheme according to the adjusted communication delay matrix and the cache resource utilization, the preliminary mapping relationship between the tasks and the cores is obtained by the following formula:

[0049]

[0050] wherein, represents the preliminary mapping relationship between the tasks and the cores, represents the resource requirement of the task represents the processing speed of the core represents the maximum allowed execution time, represents the current load of the core represents the load threshold value. Further, if there is core overload or resource idling in the initial task allocation scheme, the initial task allocation scheme is analyzed by the load balancing algorithm, the high-priority tasks are obtained from the overloaded cores and are re-allocated to the idle cores to determine the optimized task allocation scheme, and the step includes: The load data and the resource utilization data of each core are obtained from the initial task allocation scheme, the load balancing algorithm is used to calculate the difference between the current load value of each core and the preset load threshold value, it is judged whether there is core overload or resource idling, and a core load state list is obtained;

[0051] If there is an overloaded core in the core load state list, a high-priority task sequence is extracted from the overloaded core, the priority queue mechanism is used to sort the tasks according to the task calculation requirement and the communication delay data, and a task list to be migrated is obtained;

[0052] According to the task list to be migrated and the processing capacity data of the idle cores, the tasks are matched with the idle cores by using the greedy algorithm, a new task mapping relationship is generated, and an adjusted task allocation scheme is determined;

[0053] The cache utilization and the communication delay data of the cores are obtained from the adjusted task allocation scheme, the graph traversal algorithm is used to re-calculate the communication path between the cores, the communication delay matrix is updated, and an optimized task allocation scheme is obtained.

[0054] Further, for the optimized task allocation scheme, the access frequency of the communication data between the cores is analyzed, the cache partition mechanism is used to determine the cache resource allocation ratio, and the step includes:

[0055]

[0056] Further, for the optimized task allocation scheme, the access frequency of the communication data between the cores is analyzed, the cache partition mechanism is used to determine the cache resource allocation ratio, and the step includes:

[0057] ​​​Access frequency and communication path length of inter-core communication data are obtained from the optimized task allocation scheme, and distribution characteristics of the access frequency and average value of the communication path length are calculated by statistical analysis method to obtain inter-core communication characteristic data;

[0058] According to the inter-core communication characteristic data and the cache capacity data, a linear programming algorithm is used to calculate the cache allocation ratio of each core, and an initial cache allocation scheme is determined in combination with the data locality characteristics;

[0059] If the cache hit rate of the initial cache allocation scheme is lower than a preset threshold, the access mode of high-priority tasks is extracted from the core load data and the task calculation demand data, and a priority queue mechanism is used to adjust the cache allocation ratio to obtain an updated cache allocation scheme.

[0060] Inter-core communication volume and data access delay data are obtained from the updated cache allocation scheme, a graph traversal algorithm is used to recalculate the communication path, and an updated communication delay matrix is obtained to determine the final cache resource allocation ratio.

[0061] Further, according to the cache resource allocation ratio, a communication efficiency optimization algorithm is used to dynamically adjust the inter-core communication path to obtain the final task execution scheme, which comprises the steps of:

[0062] Communication frequency and path length data are obtained from the inter-core communication data, a graph analysis algorithm is used to calculate the weight of each path to obtain a communication path weight matrix, and the weight of each path is obtained by the following formula:

[0063]

[0064] Wherein, represents the weight of each path, represents the communication frequency, and L represents the path length;

[0065] According to the communication path weight matrix and the cache allocation ratio, a linear programming algorithm is used to optimize the path allocation ratio to determine an initial communication path scheme, and the path allocation ratio is obtained by the following formula:

[0066]

[0067] Wherein, represents the path allocation ratio, represents the cache capacity;

[0068] If the communication delay of the initial communication path scheme is higher than a preset threshold, the communication demand of high-priority tasks is extracted from the task priority data, and a priority queue algorithm is used to adjust the path allocation ratio to obtain an updated communication path scheme.

[0069] Obtain communication delay and load balancing data from the updated communication path scheme, recompute the inter-core communication path by using a graph traversal algorithm, and determine a final task execution scheme.

[0070] Another aspect of the application relates to a load balancing system of a low-power AI processor for executing the above-mentioned load balancing method of a low-power AI processor, the load balancing system of a low-power AI processor comprising:

[0071] A task allocation priority sequence determination module is configured to obtain a task set of each core in the neural quasi-state processor, the task set comprising a plurality of tasks, each task having a corresponding task dependency relationship and a computing demand; analyze the task dependency relationship and the computing demand by using a pre-established task characteristic analysis model, and determine a task allocation priority sequence;

[0072] An initial task allocation scheme acquisition module is configured to allocate tasks to each core by using a dynamic scheduling algorithm according to the task allocation priority sequence in combination with inter-core communication delay and cache resource utilization, and obtain an initial task allocation scheme;

[0073] A task allocation scheme determination module is configured to analyze the initial task allocation scheme by using a load balancing algorithm if there is core overload or resource idling in the initial task allocation scheme, obtain high-priority tasks from the overloaded core, and re-allocate the high-priority tasks to the idle core to determine an optimized task allocation scheme;

[0074] A cache resource allocation proportion determination module is configured to analyze the access frequency of inter-core communication data for the optimized task allocation scheme, and determine a cache resource allocation proportion by using a cache partitioning mechanism;

[0075] A task execution scheme acquisition module is configured to dynamically adjust the inter-core communication path by using a communication efficiency optimization algorithm according to the cache resource allocation proportion, and obtain a final task execution scheme.

[0076] The application has the following beneficial effects:

[0077] This invention provides a load balancing method and system for low-power AI processors, aiming to solve problems in business scenarios involving complex task dependencies, uneven core load, and low communication efficiency. By analyzing task dependencies and computational requirements, a task characteristic analysis model is constructed to generate a task allocation priority sequence. Combining inter-core communication latency and cache resource utilization, a dynamic scheduling algorithm is employed to form an initial task allocation scheme. For core overload or resource idleness issues, a load balancing algorithm is used to reallocate high-priority tasks from overloaded cores to idle cores, optimizing the task allocation scheme. Simultaneously, the access frequency of inter-core communication data is analyzed, a cache partitioning mechanism is used to determine the resource allocation ratio, and a communication efficiency optimization algorithm dynamically adjusts the communication path, ultimately generating an efficient task execution scheme. This invention significantly improves the balance of task allocation, resource utilization, and communication efficiency of neuromorphic processors, optimizing system performance. Attached Figure Description

[0078] Figure 1 This is a flowchart illustrating an embodiment of the load balancing method for a low-power AI processor according to the present invention.

[0079] Figure 2 This is a functional block diagram of an embodiment of the load balancing system for the low-power AI processor of the present invention.

[0080] Explanation of icon numbers:

[0081] 10. Task allocation priority sequence determination module; 20. Initial task allocation scheme acquisition module; 30. Task allocation scheme determination module; 40. Cache resource allocation ratio determination module; 50. Task execution scheme acquisition module. Detailed Implementation

[0082] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0083] like Figure 1 As shown, the first embodiment of the present invention proposes a load balancing method for a low-power AI processor, including the following steps:

[0084] Step S100: Obtain the task set of each core in the neuromorphic processor. The task set includes multiple tasks, each with corresponding task dependencies and computational requirements. Analyze the task dependencies and computational requirements using a pre-established task characteristic analysis model to determine the task allocation priority sequence.

[0085] The task allocation priority sequence refers to an ordered task list generated for guiding task allocation to processor cores, by quantitatively analyzing the dependency constraint strength, calculation demand urgency and core resource adaptability of the task set (containing multiple tasks and corresponding task dependency relationships, calculation demands) of each core in the neuromorphic processor through a pre-established task characteristic analysis model.

[0086] Step S200, according to the task allocation priority sequence, in combination with the inter-core communication delay and cache resource utilization, a dynamic scheduling algorithm is used to allocate tasks to each core to obtain an initial task allocation scheme.

[0087] The initial task allocation scheme refers to an initial task-core allocation mapping relationship that satisfies the priority constraint, minimizes the communication cost and efficiently utilizes the cache resources, which is formed by mapping the tasks in the task set to specific cores through a dynamic scheduling algorithm (such as a scheduling algorithm based on a greedy strategy or reinforcement learning) in combination with the task allocation priority sequence, the inter-core communication delay matrix (inter-core data transmission delay) and the cache resource utilization (current cache occupancy rate, remaining capacity) of each core. The initial task allocation scheme balances the priority, communication overhead and resource load at the initial stage of task scheduling, lays a foundation for efficient initial resource allocation for subsequent dynamic adjustment, and guarantees the overall computing fluency of the processor.

[0088] Step S300, if there is core overload or resource idling in the initial task allocation scheme, a load balancing algorithm is used to analyze the initial task allocation scheme, obtain high-priority tasks from the overloaded cores and re-allocate them to idle cores to determine an optimized task allocation scheme.

[0089] The optimized task allocation scheme refers to a task-core mapping scheme that balances the load, efficiently utilizes the resources and satisfies the task dependency and priority constraints, which is finally formed by analyzing the core load state and task characteristics through a load balancing algorithm to select migratable high-priority tasks from overloaded cores and re-allocate them to resource idle cores, in order to solve the problem of core overload (such as excessive load rate and high cache utilization) or resource idling (such as low core load and insufficient resource utilization) in the initial task allocation scheme. The optimized task allocation scheme solves the problem of unbalanced resource allocation through dynamic task migration, guarantees the execution efficiency of high-priority tasks, and improves the overall computing power utilization rate and running stability of the neuromorphic processor.

[0090] Step S400, for the optimized task allocation scheme, analyze the access frequency of inter-core communication data, adopt a cache partitioning mechanism, and determine the cache resource allocation ratio.

[0091] The cache resource allocation ratio refers to, for the optimized task allocation scheme, by analyzing the access frequency (such as high-frequency shared data, low-frequency private data) and data characteristics (such as sharing, real-time) of inter-core communication data, adopting a cache partitioning mechanism (combination of static partitioning and dynamic adaptation), determining the resource proportion of different functional areas (such as private data area, shared data area, high-frequency access area) in the cache of each core of the neuromorphic processor, and forming a quantitative allocation rule that takes into account data access efficiency and cache utilization. The cache resource allocation ratio allocates cache space according to the priority of access frequency, reduces cache misses and conflicts in inter-core data access, improves the access speed of communication data, and supports efficient execution of the optimized task allocation scheme.

[0092] Step S500, according to the cache resource allocation ratio, adopt a communication efficiency optimization algorithm to dynamically adjust the inter-core communication path, and obtain the final task execution scheme.

[0093] The final task execution scheme refers to, based on the cache resource allocation ratio (such as the resource proportion of the high-frequency shared data area and the private data area), through the communication efficiency optimization algorithm to analyze the inter-core data transmission demand, the current communication path load and the cache data location in real time, dynamically adjust the inter-core communication path (such as selecting a low-latency link and avoiding a congested path), and finally form a complete task execution blueprint containing task-core mapping, optimized communication path, cache resource adaptation and performance guarantee mechanism. The core is to realize the goal of efficient task execution, low-latency data transmission and full utilization of resources in the neuromorphic processor through the coordinated optimization of task allocation, cache partitioning and communication path, and to provide a directly executable operation guide for the stable operation of the processor.

[0094] Further, the load balancing method of the low-power AI processor provided by the embodiment includes steps S100:

[0095] Step S110, obtaining the task set and task dependency relationship of each core in the neuromorphic processor, using a directed acyclic graph to represent the execution order constraint between tasks, obtaining a task dependency graph, and the task dependency graph is obtained by the following formula:

[0096] (1)

[0097] In formula (1), denotes the task dependency graph of the neuromorphic processor, denotes the set of all task nodes, denotes the set of directed edges between tasks, denotes a task dependency matrix, each element of which represents an execution order constraint relationship between tasks.

[0098] The task set of each core in the neurosynaptic processor is obtained by the following formula:

[0099] (2)

[0100] In formula (2), denotes the th neurosynaptic processor core, denotes the th task allocated to the th core, denotes the total number of tasks carried by the th core.

[0101] The execution order constraint between tasks represented by a directed acyclic graph is obtained by the following formula:

[0102] (3)

[0103] In formula (3), denotes the reachability function of task to task in the directed acyclic graph, denotes that if there is a directed path from task to task ; when there is a directed path from task to task , the value is 1, otherwise 0, which is used to determine whether the execution order constraint between tasks exists.

[0104] A neurosynaptic processor is a computing architecture that simulates the neural network structure of the human brain, and is widely used in real-time task processing with high parallelism and low power consumption. Obtaining the task set of each core and the task dependency is the basis for task allocation. For example, in a neurosynaptic processor, there are 4 cores, each of which is responsible for processing a specific set of tasks, such as feature extraction, classification and post-processing in image recognition tasks. The task set is extracted from the input data stream by the task scheduler, containing task ID, computing requirements and dependency information. Task dependency usually manifests as some tasks waiting for the completion of other tasks. The classification task depends on the results of the feature extraction task. Using a directed acyclic graph to represent the execution order constraint between tasks is a common method for constructing a task dependency graph. Specifically, the nodes in the task dependency graph represent tasks, and the edges represent dependency relationships. For example, task A (feature extraction) points to task B (classification), indicating that B must start after A is completed. The task dependency graph ensures the acyclic nature of task execution, avoiding deadlocks.

[0105] Step S120, through the pre-established task characteristic analysis model, the earliest start time and the latest start time of each task are calculated by using the critical path method for the task dependency graph and the computing demand, the task allocation priority sequence is determined, the earliest start time of each task is obtained by the following formula:

[0106] (4)

[0107] In formula (4), the earliest start time of task , the set of all predecessor tasks of task , the earliest start time of predecessor task , the duration of predecessor task .

[0108] The latest start time of each task is obtained by the following formula:

[0109] (5)

[0110] In formula (5), the latest start time of task , the set of all successor tasks of task , the latest start time of successor task , the duration of task .

[0111] The task allocation priority sequence is obtained by the following formula:

[0112] (6)

[0113] In formula (6), the allocation priority of task , the weight coefficient of task , the computing demand amount of task , the total float time of task , the resource amount required by task .

[0114] The task dependency graph is analyzed by a task characteristic analysis model. The task characteristic analysis model estimates the execution time and resource requirement of each task based on the computational load, data dependency, and real-time requirement of the task. For example, a feature extraction task can require 100 clock cycles, and a classification task can require 50 clock cycles. The task characteristic analysis model generates a table of attributes of the tasks in combination with the computing power and communication delay of the cores. The critical path method is used to calculate the earliest start time and the latest start time of each task. The critical path is the longest path from the start to the end of the task dependency graph, which determines the completion time of the entire task set. For example, if the total length of the path from task A to B to C is 200 cycles, and the path from A to D is 150 cycles, then A-B-C is the critical path. The earliest start time is calculated by forward traversal, and the start time of task A is 0, the start time of B is 100, and the start time of C is 150. The latest start time is calculated by backward traversal to ensure that the total duration is not delayed. For example, the latest start time of C is 150, the latest start time of B is 100, and the latest start time of A is 0. Based on this, the priority sequence of task allocation is determined as A is prior to B, and B is prior to C.

[0115] Preferably, the generation of the priority sequence of task allocation takes into account the heterogeneity of the cores and the real-time requirement of the tasks. For example, core 1 is good at matrix operations and is suitable for allocating a feature extraction task; core 2 is suitable for logical operations and is suitable for allocating a classification task. Through the priority sequence, the scheduler can dynamically allocate tasks to suitable cores to reduce the waiting time.

[0116] Preferably, the load balancing method of the low-power AI processor provided by the embodiment comprises the following steps:

[0117] In step S210, the priority sequence of task allocation and the real-time resource state are obtained, the communication delay data is extracted from the communication topology structure, the shortest communication path between the cores is calculated by using a graph traversal algorithm, and the communication delay matrix between the cores is determined.

[0118] The shortest communication path between the cores is obtained by the following formula:

[0119] (7)

[0120] In formula (7), denotes the core denotes the core denotes the shortest communication delay between the core denotes the number of all possible paths from the core to the core denotes the th path, denotes the edge in the path, denotes the edge denotes the communication delay time of the edge .

[0121] The inter-core communication delay matrix is ​​derived using the following formula:

[0122] (8)

[0123] In formula (8), The number of cores in the inter-core communication delay matrix represents the number of cores in the inter-core communication delay matrix. Line number The elements of the column, when the core equals core A latency of 0 indicates communication within the same core. and core When there is no connection between them, the delay is infinite. Indicates core To the core The actual communication latency value.

[0124] In neuromorphic processors, task allocation and communication optimization are crucial for achieving efficient parallel computing. When acquiring task allocation priority sequences and real-time resource status, the task scheduler monitors the load and cache usage of each core. Assuming a neuromorphic processor has four cores processing image recognition tasks, including feature extraction, edge detection, and classification, the priority sequence is generated based on task dependencies; for example, feature extraction takes precedence over classification. Real-time resource status can be obtained from the cores' runtime data, such as core 1 currently having a 60% cache utilization rate and core 2 having 30%. This status information provides a basis for subsequent allocation.

[0125] Step S220: If the delay of a certain path in the inter-core communication delay matrix exceeds a preset threshold, the suboptimal path is recalculated according to the communication topology to obtain the adjusted communication delay matrix.

[0126] The suboptimal path is derived using the following formula:

[0127] (9)

[0128] In formula (9), This represents the optimal or suboptimal path based on the topology. This represents the set of all feasible paths in the communication topology. Represents the edges in the path The weight, Representing an edge The delay factor, This represents the path complexity penalty factor. Representing a path The number of jumps or the complexity function;

[0129] The adjusted communication delay matrix is ​​obtained using the following formula:

[0130] (10)

[0131] In formula (10), This represents the adjusted communication delay matrix. Represents the original communication delay matrix. The matrix represents the indication of positions exceeding the threshold. This represents the delay matrix after rerouting. This indicates an element-wise multiplication operation.

[0132] The communication topology reflects the data transmission paths between cores. Neuromorphic processors typically have a mesh topology, with cores connected via on-chip networks. Communication latency data is extracted from the topology; for example, the latency from core 1 to core 2 is 10 clock cycles, and from core 1 to core 3 it is 15 cycles. A graph traversal algorithm, such as Dijkstra's algorithm, is used to calculate the shortest communication path, generating a communication latency matrix. For example, the matrix shows that the shortest path from core 1 to core 4 passes through core 2, with a total latency of 20 cycles. If a path latency exceeds a preset threshold, such as 18 cycles, the suboptimal path needs to be recalculated. Assuming the direct path latency from core 1 to core 4 is 25 cycles, exceeding the threshold, a path passing through core 3 is chosen, reducing the total latency to 17 cycles, generating an adjusted communication latency matrix.

[0133] Step S230: Based on the adjusted communication delay matrix and cache resource utilization, a priority queue mechanism is adopted, combined with task computing requirements and core processing capabilities, to generate a preliminary mapping relationship between tasks and cores, and obtain an initial task allocation scheme.

[0134] The initial mapping relationship between tasks and cores is derived using the following formula:

[0135] (11)

[0136] In formula (11), Indicates task With core The initial mapping relationship, Indicates task resource requirements, Indicates core Processing speed Indicates the maximum allowed execution time. Indicates core Current load, This indicates the load threshold.

[0137] Based on the adjusted communication latency matrix and cache resource utilization, a priority queue mechanism is used to generate an initial mapping between tasks and cores. The priority queue is sorted according to the task's computational requirements and the core's processing capacity. For example, a feature extraction task requiring 100 cycles is suitable for allocation to core 1, which excels in matrix operations; a classification task requiring 50 cycles is allocated to core 2. Cores with low cache utilization are prioritized; for example, core 2, with its low cache utilization, is prioritized for allocation to classification tasks. The initial mapping relationship generates an initial task allocation scheme, such as assigning feature extraction to core 1, edge detection to core 3, and classification to core 2, thereby ensuring efficient task execution while optimizing communication and resource utilization. In this embodiment, the adjustment of the communication latency matrix effectively reduces data transmission bottlenecks. The selection of suboptimal paths reduces inter-core communication overhead, and the efficient utilization of cache resources avoids core overload. The priority queue mechanism ensures rapid response for high-priority tasks, improving overall system performance.

[0138] Furthermore, the load balancing method for the low-power AI processor provided in this embodiment includes step S300:

[0139] Step S310: Obtain the load data and resource utilization data of each core from the initial task allocation scheme, use the load balancing algorithm to calculate the difference between the current load value of each core and the preset load threshold, determine whether there is core overload or resource idleness, and obtain the core load status list.

[0140] The current load value for each core is calculated using the following formula:

[0141] (12)

[0142] In formula (12), Indicates the first The current load value of each core. Indicates the first The workload of each core. Indicates the first CPU utilization per core Indicates the first Memory utilization per core, Indicates the first Total resource capacity of each core This represents the CPU utilization weighting coefficient. This represents the weighting coefficient for memory utilization.

[0143] The core load status list is derived using the following formula:

[0144] (13)

[0145] In formula (13), Indicates the first The load difference of each core, Indicates the first The current load value of each core. This indicates the system's preset load threshold. A value greater than 0 indicates core overload. A value less than a negative idle threshold indicates that the resource is idle.

[0146] In neuromorphic processors, task allocation and load balancing are crucial for achieving efficient parallel computing. The following analysis and examples focus on task allocation optimization, load balancing, task migration, and communication path updates, using an image recognition scenario as a case study. Maintaining consistency with historical information, the analysis remains focused on a single business scenario.

[0147] In the initial task allocation scheme, it is assumed that a neuromorphic processor has 4 cores, and the image recognition tasks include feature extraction, edge detection, and classification. After the initial task allocation, the load data and cache utilization of each core are obtained through the task scheduler. For example, core 1 processes feature extraction with a load of 80% and a cache utilization of 70%; core 2 processes classification with a load of 40% and a cache utilization of 30%; core 3 processes edge detection with a load of 60% and a cache utilization of 50%; core 4 is idle with a load of 10% and a cache utilization of 20%.

[0148] The preset load threshold is 75%. By comparing the load value with the load threshold, the load value of core 1 is 80%, which exceeds the load threshold and is determined to be core overload; the load value of core 4 is only 10%, which is determined to be idle. Thus, the core load status list shows that core 1 is overloaded and core 4 is idle.

[0149] Step S320: If there are overloaded cores in the core load status list, extract the high-priority task sequence from the overloaded cores, and sort them using a priority queue mechanism based on the task computation requirements and communication latency data to obtain the task list to be migrated.

[0150] The following formula can be used to determine whether there are overloaded cores in the core load status list:

[0151] (14)

[0152] In formula (14), Indicates the first The load status of each core, Indicates the first The current computing load of each core. This represents the core's maximum computing power. Indicates the overload threshold. When When greater than the overload threshold, the core is identified as an overloaded core.

[0153] The list of tasks to be migrated is derived by the following equation:

[0154] (15)

[0155] In equation (15), represents the list of tasks to be migrated for the thoverloaded core, represents the priority value of task , represents the priority value of task , represents the migration priority threshold, represents the state of task , represents that the task is in the ready state. Only tasks with priority higher than the migration priority threshold and in the ready state will be added to the list of tasks to be migrated.

[0156] The priority value of task is derived by the following equation:

[0157] (16)

[0158] In equation (16), represents the comprehensive priority score of task , represents the computational resource requirement of task , represents the maximum resource requirement, represents the communication delay of task , represents the maximum communication delay, represents the deadline of task , , , represents the weight coefficient of each item.

[0159] For task migration of the overloaded core, a high-priority task sequence needs to be extracted from core 1. Assume that the feature extraction task is divided into subtasks A and B, subtask A has a higher priority, a computational requirement of 60 cycles, and a communication dependency on data of core 2. Using a priority queue mechanism, based on task computational requirement and communication delay sorting, a list of tasks to be migrated is generated, with subtask A having the highest priority. The communication delay data comes from the initial communication delay matrix, for example, the delay from core 1 to core 2 is 10 cycles, and the delay from core 1 to core 4 is 20 cycles. Subtask A, due to its dependency on core 2 data, is given priority to migrate to a core with lower communication delay.

[0160] Step S330, according to the task list to be migrated and the processing capacity data of the idle core, a greedy algorithm is used to match the tasks and the idle core, a new task mapping relationship is generated, and an adjusted task allocation scheme is determined.

[0161] A new task mapping relationship is generated by selecting the optimal core in batches:

[0162] (17)

[0163] In formula (17), represents the global optimization target value of the greedy algorithm, represents the total number of batches of migrated tasks, represents the batch of available idle core set, represents the batch of task resource requirements, represents the computing capacity of core .

[0164] Suppose the original core 4 is idle, the processing capacity is 100 cycles, the cache utilization is low, and it is suitable to receive the subtask A. A greedy algorithm is used to match the tasks and the idle core, and a new task mapping relationship is generated: the subtask A is migrated to core 4, core 1 continues to process the subtask B, and cores 2 and 3 remain unchanged. In the new task mapping relationship, the load of core 1 is reduced to 50%, and the load of core 4 is increased to 40%, both of which are lower than the threshold, and the load balancing is improved.

[0165] Step S340, the cache utilization and communication delay data of the core are obtained from the adjusted task allocation scheme, the graph traversal algorithm is used to recalculate the communication path between the cores, the communication delay matrix is updated, and the optimized task allocation scheme is obtained.

[0166] The cache utilization of the core is obtained by the following formula:

[0167] (18)

[0168] In formula (18), represents the cache utilization of the th core, represents the used cache capacity of the th core, represents the total cache capacity of the th core, represents the number of tasks allocated to the th core, represents the cache space size required by the th task.

[0169] The optimal communication path is found by a graph traversal algorithm and the corresponding delay value is calculated:

[0170] (19)

[0171] In formula (19), represents the updated core communication delay to core , represents the set of all possible paths from core to core , represents a specific path, represents the weight of the edge in the path, represents the path length penalty factor, represents the number of edges contained in the path .

[0172] The optimal task allocation strategy is found by considering the cache utilization and communication delay, and the optimized task allocation scheme is obtained by the following formula:

[0173] (20)

[0174] In formula (20), represents the optimized task allocation scheme, represents all possible task allocation schemes, represents the total number of cores, represents the cache utilization weight coefficient of the th core, represents the cache utilization of the th core, represents the importance weight of communication between core and core , represents the communication delay between core and core , represents the communication frequency between core and core .

[0175] The adjusted task allocation scheme needs to update the communication path. The graph traversal algorithm is used to recalculate the communication path between cores, and the communication delay matrix is updated. The initial matrix shows that the delay from core 1 to core 4 is 20 cycles, and after adjustment, it is found that the path from core 1 to core 4 through core 3 has a delay of 15 cycles, which is better than the direct path. The updated communication delay matrix reflects a shorter communication path, and after core 4 receives subtask A, the data transmission efficiency is improved.

[0176] The cache utilization monitoring ensures efficient allocation of resources. For example, after core 4 receives subtask A, the cache utilization rate increases to 40%, which is still lower than the saturation threshold, avoiding waste of resources. The communication path optimization reduces the data transmission bottleneck, and the task migration improves the core load balancing. In this embodiment, by dynamically adjusting, the real-time resource changes are adapted, and the system robustness is improved.

[0177] Preferably, the load balancing method of the low-power AI processor provided in the embodiment comprises the following steps:

[0178] In step S410, the access frequency and the communication path length of the inter-core communication data are obtained from the optimized task allocation scheme, and a statistical analysis method is used to calculate the distribution characteristics of the access frequency and the average value of the communication path length to obtain the inter-core communication characteristic data.

[0179] The distribution characteristics of the access frequency are calculated by the following formula:

[0180] (21)

[0181] In formula (21), represents the variance of the access frequency distribution, represents the total number of communication frequency samples, represents the th communication frequency value, represents the average value of all communication frequencies.

[0182] The average value of the communication path length is calculated by the following formula:

[0183] (22)

[0184] In formula (22), represents the average value of the communication path length, represents the total number of all communication paths, represents the length of the th communication path.

[0185] In the optimized task allocation scheme, it is assumed that a neural quasi-state processor has four cores, which respectively process feature extraction, edge detection, classification, and preprocessing tasks of image recognition. The access frequency and path length of the inter-core communication data are the basis for analyzing the communication characteristics. Core 1 processes feature extraction and needs to frequently access the classification data of core 2, with an access frequency of 100 times per second and a communication path length of 10 cycles; core 3 processes edge detection and accesses the preprocessing data of core 4, with a frequency of 50 times per second and a path length of 15 cycles.

[0186] Statistical analysis was used to calculate the distribution characteristics of access frequency, revealing that communication between core 1 and core 2 accounted for 60% of the total communication volume, exhibiting a high-frequency, concentrated distribution; the average communication path length was 12.5 cycles. These communication characteristics reflect the density of data interaction between cores, providing a basis for subsequent cache allocation.

[0187] Step S420: Based on the inter-core communication characteristic data and cache capacity data, use a linear programming algorithm to calculate the cache allocation ratio of each core, and combine the data locality characteristics to determine the initial cache allocation scheme.

[0188] The linear programming objective function for setting the core cache allocation ratio is:

[0189] (twenty three)

[0190] In formula (23), Indicates the total number of cores. Indicates the first Each core communication weight coefficient Indicates assignment to the first The cache ratio of each core, This represents the total cache capacity constraint, and the goal is to maximize the efficiency of weighted cache allocation while satisfying the capacity constraint.

[0191] The initial cache allocation scheme is derived using the following formula:

[0192] (twenty four)

[0193] In formula (24), Indicates allocation to the core Initial cache size, Indicates core Communication bandwidth requirements, Indicates core Data access frequency, This represents the total system cache capacity, and the cache allocation for each core is determined by the ratio of the product of bandwidth and frequency.

[0194] Based on communication characteristic data and cache capacity data, a linear programming algorithm is used to calculate the cache allocation ratio. Assuming that the cache capacity of each core is 1000 units, core 1, due to its high frequency of accessing data from core 2 and strong data locality, is initially allocated a cache ratio of 40%; cores 2, 3, and 4 are allocated 30%, 20%, and 10% respectively.

[0195] Step S430: If the cache hit rate of the initial cache allocation scheme is lower than the preset threshold, the access patterns of high-priority tasks are extracted from the core load data and task computing requirement data, and the cache allocation ratio is adjusted using a priority queue mechanism to obtain an updated cache allocation scheme.

[0196] High-priority tasks are extracted from core workload data and task computation requirements data using the following formula:

[0197] (25)

[0198] In formula (25), Indicates the first The priority weight of each task. Indicates task Importance weights Indicates task Access frequency, Indicates task The urgency of the deadline , , These are the corresponding weighting coefficients.

[0199] The cache allocation ratio for each task is dynamically adjusted based on a priority queue mechanism. The updated cache allocation scheme is derived using the following formula:

[0200] (26)

[0201] In formula (26), Indicates task Updated cache allocation ratio Indicates task The original cache allocation ratio, Indicates task The sorting value in the priority queue. This represents the average sorting value of the tasks in the queue. This represents the maximum sorted value in the queue. This indicates an adjustment to the strength coefficient.

[0202] After the initial cache allocation scheme is formed, the cache hit rate is checked, with a preset threshold of 85%.

[0203] Actual testing showed that the hit rate of Core 1 was 80%, which is below the threshold and needs optimization. Analysis of the core load data and task computation requirements revealed that the feature extraction task of Core 1 includes a high-priority subtask C, with a sequential read-write access mode and a large data volume.

[0204] A priority queue mechanism was adopted, allocating more cache to subtask C first. The cache ratio for core 1 was adjusted to 50%, while that for core 2 was reduced to 25%, with other settings remaining unchanged. The updated cache allocation scheme improved the hit rate of core 1 to 88%. After updating the cache allocation, the inter-core communication volume and data access latency needed to be re-analyzed. The communication volume between core 1 and core 2 decreased to 80 times per second due to the improved cache hit rate, and the data access latency decreased from 10 cycles to 8 cycles.

[0205] Step S440: Obtain the inter-core communication volume and data access latency data from the updated cache allocation scheme, recalculate the communication path using a graph traversal algorithm, update the communication latency matrix, and determine the final cache resource allocation ratio.

[0206] Inter-core communication volume is calculated using the following formula:

[0207] (27)

[0208] In formula (27), Indicates core With core Communication volume between them Indicates the total number of cache blocks. Indicates core For cache blocks Data access frequency, Indicates cache block At the core The allocation status on, Indicates cache block bandwidth capacity, Indicates core With core The communication weight coefficient between them. Formula (27) is used to calculate the communication load between cores after updating the cache allocation scheme.

[0209] Find the communication path with minimum latency using a graph traversal algorithm:

[0210] (28)

[0211] In formula (28), This represents the total delay of the optimal communication path. Represents the set of all possible paths. Indicates one of the paths, Represents the edges in the path. Representing an edge The basic weights, Indicates the delay penalty factor. Representing an edge Current transmission time, Maximal transmission time allowed by the system.

[0212] The optimal cache resource allocation ratio is determined according to the performance and delay characteristics of each core:

[0213] (29)

[0214] In formula (29), the final cache resource allocation ratio of the core , the resource allocation score of the core , the total number of cores, the utilization rate index of the core , the access delay value of the core , the delay sensitivity parameter, the resource allocation score of the core , the utilization rate index of the core , the access delay value of the core .

[0215] The communication path is recalculated using the graph traversal algorithm, and it is found that the path delay from core 1 to core 2 through core 3 is 7 cycles, which is better than the direct path. The communication delay matrix is updated to reflect the new path selection, and the communication efficiency of core 1 to core 2 is further improved. The final cache resource allocation ratio is determined as core 1 accounts for 50%, core 2 accounts for 25%, core 3 accounts for 15%, and core 4 accounts for 10%, balancing the cache utilization rate and communication efficiency.

[0216] According to the data locality feature, the high-priority subtask C of core 1 is suitable for using the prefetch mechanism due to the sequential access mode, further reducing the access delay. The data access of the edge detection task of core 3 is relatively random, and a smaller cache is allocated but a pre-reading buffer is added to adapt to its access mode. Through fine-grained cache allocation and communication path optimization, efficient resource utilization and low data transmission delay are ensured, providing support for real-time processing of image recognition tasks.

[0217] Further, the load balancing method of the low-power AI processor provided in the embodiment comprises the following steps:

[0218] In step S510, communication frequency and path length data are obtained from inter-core communication data, a graph analysis algorithm is used to calculate the weight of each path, a communication path weight matrix is obtained, and the weight of each path is calculated by the following formula:

[0219] (30)

[0220] In formula (30), Indicates the weight of each path. L represents the communication frequency, and L represents the path length.

[0221] The communication path weight matrix is ​​derived using the following formula:

[0222] (31)

[0223] In formula (31), Represents the first element in the communication path weight matrix. Line number The element values ​​of the column, Indicates time Inner Core With core Communication rate between them Indicates the total length of the observation time window. Indicates core To the core The number of hops. Formula (31) constructs the elements of the weight matrix by the ratio of the time average communication rate to the number of hops.

[0224] A neuromorphic processor comprises four cores, each responsible for convolution, pooling, feature fusion, and fully connected classification tasks in image recognition. The frequency and path length of inter-core communication data access are fundamental to the analysis. Core 1, responsible for convolution, frequently accesses the feature fusion data from Core 3 at a frequency of 120 times per second, with a path length of 8 cycles. Core 2, responsible for pooling, accesses the fully connected classification data from Core 4 at a frequency of 60 times per second, with a path length of 12 cycles. Statistical analysis shows that communication between Core 1 and Core 3 accounts for 55% of the total communication, exhibiting a high-frequency concentration characteristic; the average path length is 10 cycles.

[0225] Based on communication frequency and path length, a graph analysis algorithm is used to calculate path weights. Path weight is defined as communication frequency divided by path length. For example, the weight from core 1 to core 3 is 120 / 8=15, and the weight from core 2 to core 4 is 60 / 12=5, forming a communication path weight matrix.

[0226] Step S520: Based on the communication path weight matrix and cache allocation ratio, optimize the path allocation ratio using a linear programming algorithm to determine the initial communication path scheme. The path allocation ratio is obtained through the following formula:

[0227] (32)

[0228] In formula (32), Indicates the path allocation ratio. Indicates the cache capacity.

[0229] Based on cache capacity data, assuming each core has a cache capacity of 800 units, a linear programming algorithm is used to calculate the initial path allocation ratio. The initial path allocation ratio is defined as the ratio of path weight to cache capacity. For example, the path allocation ratio from core 1 to core 3 is 15 / 800 = 0.01875, and from core 2 to core 4 it is 0.00625.

[0230] Step S530: If the communication delay of the initial communication path scheme is higher than the preset threshold, the communication requirements of high-priority tasks are extracted from the task priority data, and the path allocation ratio is adjusted by the priority queue algorithm to obtain the updated communication path scheme.

[0231] The total communication delay of the initial communication path scheme is obtained by the following formula:

[0232] (33)

[0233] In formula (33), This represents the total communication delay of the initial communication path scheme. Indicates the total number of communication paths. Indicates the first Data transfer volume on the path, Indicates the first Bandwidth capacity of each path, Indicates the first The propagation delay along the path.

[0234] The communication requirements of high-priority tasks are derived using the following formula:

[0235] (34)

[0236] In formula (34), Indicates high priority task The proportion of communication demand, Indicates task The data transmission demand, Indicates task priority weight value, This represents the total number of all high-priority tasks.

[0237] The updated communication path scheme is derived using the following formula:

[0238] (35)

[0239] In formula (35), Representing a path Updated allocation ratio, representing a path original allocation ratio, representing an adjustment coefficient, representing a high-priority task set, representing a task scheduling factor in a priority queue, representing a high-priority task communication demand proportion.

[0240] If the communication delay of the initial path scheme is higher than a preset threshold, for example, 10 cycles, further optimization is needed. Extract the communication demand of high-priority tasks from the task priority data, for example, the convolution operation of core 1 contains high-priority sub-tasks, involving large-scale feature extraction, and the communication demand is high. Adopt the priority queue algorithm, adjust the path allocation ratio, and increase the path ratio of core 1 to core 3 to 0.025 and decrease the path ratio of core 2 to core 4 to 0.005. After adjustment, the communication delay is reduced from 11 cycles to 9 cycles, meeting the threshold requirement.

[0241] Step S540, obtain the communication delay and load balancing data from the updated communication path scheme, and use the graph traversal algorithm to recalculate the inter-core communication path to determine the final task execution scheme.

[0242] The final task execution scheme is obtained by the following formula:

[0243] (36)

[0244] In formula (36), representing the optimal path cost of the task execution scheme, representing the set of all available cores, representing the core node currently considered, representing the set of cores adjacent to core representing the execution overhead of core to core representing the execution overhead of core to core representing the fixed cost of executing a task on core .

[0245] Based on the updated path scheme, the graph traversal algorithm is used to recalculate the inter-core communication path. For example, analysis finds that the indirect path delay of core 1 through core 2 to core 3 is 6 cycles, which is better than the direct path of 8 cycles. Update the communication delay matrix to reflect the new path selection, and the communication efficiency of core 1 to core 3 is improved.

[0246] If the load balancing data shows that core 1 is under high load, part of the low-priority sub-tasks are allocated to core 4 through task migration to balance the load. For the data access mode, the convolution operation of core 1 has high locality, which is suitable for increasing the prefetch cache to reduce the delay; the data access of the pooling processing of core 2 is random, and a small capacity cache is allocated to adapt to its characteristics. In this embodiment, through weight analysis, path optimization and task adjustment, the balance between communication efficiency and resource utilization is ensured, and efficient support is provided for image recognition tasks.

[0247] See Figure 2 The application provides a load balancing system of a low-power AI processor for executing the load balancing method of the low-power AI processor described above, which comprises a task allocation priority sequence determination module 10, an initial task allocation scheme acquisition module 20, a task allocation scheme determination module 30, a cache resource allocation proportion determination module 40 and a task execution scheme acquisition module 50. The task allocation priority sequence determination module 10 is used to acquire a task set of each core in the neural quasi-state processor, the task set comprising a plurality of tasks, each task having a corresponding task dependency relationship and a calculation demand; the task dependency relationship and the calculation demand are analyzed by a pre-established task characteristic analysis model to determine a task allocation priority sequence; the initial task allocation scheme acquisition module 20 is used to allocate tasks to each core by using a dynamic scheduling algorithm according to the task allocation priority sequence in combination with inter-core communication delay and cache resource utilization rate to obtain an initial task allocation scheme; the task allocation scheme determination module 30 is used to acquire high-priority tasks from an overloaded core by analyzing the initial task allocation scheme through a load balancing algorithm if there is core overload or resource idling in the initial task allocation scheme, and re-allocate the high-priority tasks to an idle core to determine an optimized task allocation scheme; the cache resource allocation proportion determination module 40 is used to analyze the access frequency of inter-core communication data by using a cache partition mechanism to determine a cache resource allocation proportion for the optimized task allocation scheme; and the task execution scheme acquisition module 50 is used to dynamically adjust an inter-core communication path by using a communication efficiency optimization algorithm according to the cache resource allocation proportion to obtain a final task execution scheme.

[0248] The load balancing method and system of the low-power AI processor provided by the embodiment, compared with the prior art, constructs a task characteristic analysis model by analyzing task dependency and computing demand, generates a task allocation priority sequence, combines inter-core communication delay and cache resource utilization, and adopts a dynamic scheduling algorithm to form an initial task allocation scheme. In view of the core overload or resource idling problem, the high-priority task is redistributed from the overloaded core to the idle core through the load balancing algorithm, and the task allocation scheme is optimized. At the same time, the access frequency of inter-core communication data is analyzed, the cache partition mechanism is adopted to determine the resource allocation ratio, and the communication path is dynamically adjusted through the communication efficiency optimization algorithm, and finally an efficient task execution scheme is generated. The embodiment significantly improves the balance, resource utilization and communication efficiency of the neural para-state processor task allocation, and optimizes the system performance.

[0249] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such variations and modifications as fall within the scope of the application. It should be apparent that the application is not limited to the specific embodiments described herein, but can be practiced with modifications within the spirit and scope of the application. Accordingly, the specification is to be regarded as merely illustrative of the broad application and the scope of the application is indicated by the appended claims, rather than by the foregoing description.

Claims

1. A load balancing method for a low-power AI processor, characterized in that, The method comprises the following steps: Obtain a task set of each core in a neural paradigm processor, the task set comprising a plurality of tasks, each task having a corresponding task dependency relationship and a computing requirement; analyze the task dependency relationship and the computing requirement by a pre-established task characteristic analysis model to determine a task allocation priority sequence; According to the task allocation priority sequence, combined with the inter-core communication delay and the cache resource utilization rate, a dynamic scheduling algorithm is used to allocate the tasks to each core to obtain an initial task allocation scheme, specifically including: Obtain the task allocation priority sequence and real-time resource state, extract communication delay data from the communication topology structure, use a graph traversal algorithm to calculate the shortest communication path between each core, and determine the inter-core communication delay matrix; If the delay of a certain path in the inter-core communication delay matrix exceeds a preset threshold, then according to the communication topology structure, a suboptimal path is recalculated to obtain an adjusted communication delay matrix; According to the adjusted communication delay matrix and the cache resource utilization rate, a priority queue mechanism is used to generate a preliminary mapping relationship between the tasks and the cores in combination with the task computing requirement and the core processing capability to obtain the initial task allocation scheme; If there is core overload or resource idling in the initial task allocation scheme, then through a load balancing algorithm, the initial task allocation scheme is analyzed, high-priority tasks are obtained from the overloaded cores and are re-allocated to idle cores to determine an optimized task allocation scheme, specifically including: Obtain the load data and resource utilization rate data of each core from the initial task allocation scheme, use a load balancing algorithm to calculate the difference between the current load value of each core and the preset load threshold, and determine whether there is core overload or resource idling to obtain a core load state list; If there is an overloaded core in the core load state list, then a high-priority task sequence is extracted from the overloaded core, and a priority queue mechanism is used to sort in combination with the task computing requirement and the communication delay data to obtain a task list to be migrated; According to the task list to be migrated and the processing capability data of the idle cores, a greedy algorithm is used to match the tasks and the idle cores to generate a new task mapping relationship and determine an adjusted task allocation scheme; Obtain the cache utilization rate and communication delay data of the cores from the adjusted task allocation scheme, use a graph traversal algorithm to recalculate the communication path between the cores, update the communication delay matrix, and obtain the optimized task allocation scheme; For the optimized task allocation scheme, analyze the access frequency of the inter-core communication data, use a cache partitioning mechanism to determine a cache resource allocation ratio; According to the cache resource allocation ratio, use a communication efficiency optimization algorithm to dynamically adjust the inter-core communication path to obtain a final task execution scheme, specifically including: Obtain the communication frequency and path length data from the inter-core communication data, use a graph analysis algorithm to calculate the weight of each path to obtain a communication path weight matrix, and the weight of each path is obtained by the following formula: wherein, represents each path weight, represents a communication frequency, L represents a path length; According to the communication path weight matrix and the cache allocation ratio, use a linear programming algorithm to optimize the path allocation ratio to determine an initial communication path scheme, and the path allocation ratio is obtained by the following formula: wherein, represents a path allocation ratio, represents a cache capacity; If the communication delay of the initial communication path scheme is higher than a preset threshold, communication requirements of high-priority tasks are extracted from the task priority data, a priority queue algorithm is used to adjust a path allocation ratio, and an updated communication path scheme is obtained; Communication delay and load balancing data are obtained from the updated communication path scheme, a graph traversal algorithm is used to recalculate the communication path between cores, and a final task execution scheme is determined. 2.The load balancing method of a low-power AI processor of claim 1, wherein, The task set of each core in the neural quasi-state processor is obtained, the task set includes a plurality of tasks, each task has a corresponding task dependency relationship and a calculation requirement; the task dependency relationship and the calculation requirement are analyzed by a pre-established task characteristic analysis model, and the steps of determining the task allocation priority sequence include: The task set and the task dependency relationship of each core in the neural quasi-state processor are obtained, the execution order constraint between tasks is represented by a directed acyclic graph, and a task dependency graph is obtained, the task dependency graph is obtained by the following formula: wherein, a task dependency graph representing a neural paradigm processor, a set of all task nodes, a set of directed edges between tasks, a task dependency relation matrix, each element of which represents an execution order constraint relation between tasks; The task set of each core in the neural quasi-state processor is obtained by the following formula: wherein, represents the neurogenetic processor core, represents the task assigned to the core, represents the total number of tasks carried by the core. The execution order constraint between tasks is represented by a directed acyclic graph by the following formula: wherein, represents the reachability function of tasks in a directed acyclic graph to task , represents if there is a directed path from task to task ; 1 when there is a directed path from task to task , otherwise 0, used to determine if the execution order constraint between tasks exists; The earliest start time of each task is calculated by the following formula by using a critical path method for the task dependency graph and the calculation requirement according to the pre-established task characteristic analysis model, and the task allocation priority sequence is determined. wherein, denotes the earliest start time of the task , denotes the set of all predecessor tasks of the task , denotes the earliest start time of the predecessor task , denotes the duration of the predecessor task . The latest start time of each task is calculated by the following formula: wherein, denotes the earliest start time of a task , denotes the set of all successor tasks of a task , denotes the earliest start time of a successor task , denotes the duration of a task ; The task allocation priority sequence is calculated by the following formula: wherein, represents an assignment priority of the task , represents a weight coefficient of the task , represents a computing demand amount of the task , represents a total float time of the task , represents a resource amount required for the task . 3.The load balancing method of a low-power AI processor of claim 1, wherein, In the steps of obtaining the task allocation priority sequence and the real-time resource state, extracting the communication delay data from the communication topology structure, and calculating the shortest communication path between each core by using a graph traversal algorithm to determine the inter-core communication delay matrix, the shortest communication path between each core is obtained by the following formula: wherein, denotes a core to a core between the shortest communication delay, denotes the number of all paths from a core to a core denotes the i-th path, denotes an edge in the path, denotes the communication delay time of the edge denotes the communication delay time of the edge​​ The inter-core communication delay matrix is obtained by the following formula: wherein, denotes the element of the inter-core communication delay matrix at row and column , denotes the delay between core and core when there is no connection between them, denotes infinity; the delay is 0 when core is equal to core , which means intra-core communication, the delay is infinity when there is no connection between core and core , denotes the actual communication delay value from core to core . 4.The load balancing method of a low-power AI processor of claim 3, wherein If the delay of a certain path in the inter-core communication delay matrix exceeds a preset threshold, the suboptimal path is recalculated according to the communication topology structure in the steps of obtaining the adjusted communication delay matrix, and the suboptimal path is obtained by the following formula: wherein, represents the optimal suboptimal path based on the topology, represents the set of all paths in the communication topology, represents the weight of an edge in the path, represents the delay coefficient of an edge , represents the path complexity penalty factor, represents the hop count or complexity function of a path . The adjusted communication delay matrix is obtained by the following formula: wherein, denotes the adjusted communication delay matrix, denotes the original communication delay matrix, denotes the indicator matrix of positions exceeding the threshold, denotes the delay matrix after re-routing, denotes an element-wise multiplication operation. 5.The load balancing method of a low-power AI processor of claim 4, wherein, In the steps of generating a preliminary mapping relationship between tasks and cores by using a priority queue mechanism in combination with task calculation requirements and core processing capabilities according to the adjusted communication delay matrix and the cache resource utilization rate to obtain an initial task allocation scheme, the preliminary mapping relationship between tasks and cores is obtained by the following formula: in, Indicates task With core The initial mapping relationship, Indicates task resource requirements, Indicates core Processing speed Indicates the maximum allowed execution time. Indicates core Current load, This indicates the load threshold. 6.The load balancing method of a low-power AI processor of claim 1, wherein, The steps of analyzing the access frequency of inter-core communication data and determining the cache resource allocation ratio by using a cache partitioning mechanism for the optimized task allocation scheme include: The access frequency of inter-core communication data and the communication path length are obtained from the optimized task allocation scheme, and a statistical analysis method is used to calculate the distribution characteristics of the access frequency and the average value of the communication path length to obtain inter-core communication characteristic data; According to the inter-core communication characteristic data and the cache capacity data, a linear programming algorithm is used to calculate the cache allocation ratio of each core, and an initial cache allocation scheme is determined in combination with the data locality feature. If the cache hit rate of the initial cache allocation scheme is lower than a preset threshold, an access mode of a high-priority task is extracted from core load data and task computation demand data, a priority queue mechanism is used to adjust a cache allocation proportion, and an updated cache allocation scheme is obtained; Inter-core communication volume and data access delay data are obtained from the updated cache allocation scheme, a graph traversal algorithm is used to recalculate a communication path, a communication delay matrix is updated, and a final cache resource allocation proportion is determined.

7. A load balancing system of a low-power AI processor for performing the load balancing method of the low-power AI processor according to any one of claims 1 to 6, wherein The load balancing system of the low-power AI processor comprises: A task allocation priority sequence determination module (10) is configured to obtain a task set of each core in a neural state processor, the task set comprising a plurality of tasks, each task having a corresponding task dependency relationship and computation demand; a task characteristic analysis model is pre-established, the task dependency relationship and computation demand are analyzed, and a task allocation priority sequence is determined; An initial task allocation scheme acquisition module (20) is configured to combine inter-core communication delay and cache resource utilization rate, and use a dynamic scheduling algorithm to allocate the tasks to the cores according to the task allocation priority sequence, and obtain an initial task allocation scheme; A task allocation scheme determination module (30) is configured to, if there is core overload or resource idling in the initial task allocation scheme, analyze the initial task allocation scheme, obtain a high-priority task from the overloaded core, and reallocate the high-priority task to an idle core by using a load balancing algorithm, and determine an optimized task allocation scheme; A cache resource allocation proportion determination module (40) is configured to analyze access frequency of inter-core communication data for the optimized task allocation scheme, and determine a cache resource allocation proportion by using a cache partitioning mechanism; A task execution scheme acquisition module (50) is configured to use a communication efficiency optimization algorithm to dynamically adjust an inter-core communication path according to the cache resource allocation proportion, and obtain a final task execution scheme.

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