UCIe-based fault diagnosis and debugging methods, storage media, and artificial intelligence chips
By using pause state registers, bypass registers, and timers in the UCIe link training and state machine, effective chip fault diagnosis and debugging were achieved, solving the problem of insufficient test coverage and improving chip yield and startup success rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-07
- Publication Date
- 2026-04-03
AI Technical Summary
Insufficient test coverage during the initialization phase of the UCIe link training and state machine leads to a decrease in yield and an inability to effectively screen out defective chips during mass production, increasing the risk of chip startup failure.
By enabling and disabling the pause status register and bypass register of the chip, configuring correction signals, and using timers to control state transitions, fault diagnosis and debugging can be achieved.
It improves the debugging efficiency during the chip initialization stage, ensuring that defects can be effectively screened out during the mass production stage and reducing the risk of startup failure.
Smart Images
Figure CN121070676B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, and in particular to a fault diagnosis and debugging method based on UCIe, a computer-readable storage medium, and an artificial intelligence chip. Background Technology
[0002] UCIe (Universal Chiplet Interconnect Express) lacks a Design for Debug (DFD) mechanism during the link training and status state machine (LTSM) state transitions. As a result, the chip may face insufficient test coverage during the initialization phase, leading to a decrease in yield and the inability to effectively screen defective chips during the mass production phase. It also increases the risk of chip startup failure. Summary of the Invention
[0003] This invention relates to a fault diagnosis and debugging method based on UCIe, a computer-readable storage medium, and an artificial intelligence chip, which can achieve effective chip debugging and fault diagnosis, and improve post-silicon debugging efficiency.
[0004] According to an embodiment of the present invention, the UCIe-based fault diagnosis and debugging method of the present invention includes the following steps: performing link training between a first core and a second core; when a state execution error occurs, enabling the first pause state register of the first core to stop the state transition of the first core; enabling the first bypass register of the first core to configure the first correction signal stored in the first bypass register; and disabling the first pause state register of the first core to continue the state transition of the first core.
[0005] In the fault diagnosis and debugging method according to an embodiment of the present invention, the fault diagnosis and debugging method further includes the following steps: when a state execution error occurs, enabling the second pause state register of the second core to stop the state transition of the second core; enabling the second bypass register of the second core to configure the second correction signal stored in the second bypass register; and disabling the second pause state register of the second core to continue the state transition of the second core.
[0006] In the fault diagnosis and debugging method according to an embodiment of the present invention, the fault diagnosis and debugging method further includes the following steps: enabling the first timer of the first chip; and disabling the first pause state register of the first chip when the first timer of the first chip counts to a first preset value.
[0007] In the fault diagnosis and debugging method according to an embodiment of the present invention, the fault diagnosis and debugging method further includes the following steps: enabling the second timer of the second chip; and disabling the second pause state register of the second chip when the second timer of the second chip counts to a second preset value.
[0008] In the fault diagnosis and debugging method according to an embodiment of the present invention, the difference between the first preset value and the second preset value is less than or equal to the preset difference.
[0009] In the fault diagnosis and debugging method according to an embodiment of the present invention, the preset difference is 8 milliseconds.
[0010] In the fault diagnosis and debugging method according to an embodiment of the present invention, the fault diagnosis and debugging method further includes the following steps: receiving a first correction signal through a first chip and writing the first correction signal into a first bypass register.
[0011] In the fault diagnosis and debugging method according to an embodiment of the present invention, the fault diagnosis and debugging method further includes the following steps: receiving a second correction signal through a second chip, and writing the second correction signal into a second bypass register.
[0012] In the fault diagnosis and debugging method according to an embodiment of the present invention, the first correction signal is different from the second correction signal.
[0013] In the fault diagnosis and debugging method according to an embodiment of the present invention, the first chip includes a plurality of first pause state registers and a plurality of first bypass registers. The plurality of first pause state registers correspond to different states of link training and state machine, respectively. The plurality of first bypass registers correspond to different states of link training and state machine, respectively.
[0014] In the fault diagnosis and debugging method according to an embodiment of the present invention, the second chip includes a plurality of second pause state registers and a plurality of second bypass registers. The plurality of second pause state registers correspond to different states of the link training and the state machine, respectively. The plurality of second bypass registers correspond to different states of the link training and the state machine, respectively.
[0015] According to embodiments of the present invention, the computer-readable storage medium is used to store a computer program. The computer program is executed by a processor to implement the steps of the above-described UCIe-based fault diagnosis and debugging method.
[0016] According to an embodiment of the present invention, the artificial intelligence chip of the present invention includes a first chip and a second chip. The first chip includes a first pause state register and a first bypass register. The second chip is coupled to the first chip and is used to communicate with the first chip. Link training is performed between the first chip and the second chip. When a state execution error occurs, the first chip enables the first pause state register to stop the stop state transition of the first chip. The first chip enables the first bypass register to configure a first correction signal stored in the first bypass register, and the first chip then disables the first pause state register to continue the state transition of the first chip.
[0017] Based on the above, the fault diagnosis and debugging method, computer-readable storage medium, and artificial intelligence chip based on UCIe of the present invention may have a DFD mechanism to enable effective chip debugging and fault diagnosis during the chip initialization phase.
[0018] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of a data transmission system according to an embodiment of the present invention;
[0020] Figure 2 This is a schematic diagram of the physical layer architecture of UCIe according to an embodiment of the present invention;
[0021] Figure 3 This is a flowchart of a fault diagnosis and debugging method according to an embodiment of the present invention;
[0022] Figure 4 This is a flowchart of another fault diagnosis and debugging method according to an embodiment of the present invention;
[0023] Figure 5 This is a flowchart of another fault diagnosis and debugging method according to an embodiment of the present invention;
[0024] Figure 6 This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present invention.
[0025] Explanation of icon numbers
[0026] 100: Data transmission system;
[0027] 110: First chip;
[0028] 111: First physical layer architecture;
[0029] 112: First pause status register;
[0030] 113: First bypass register;
[0031] 114: First timer;
[0032] 120: Second core;
[0033] 121: Second physical layer architecture;
[0034] 122: Second pause status register;
[0035] 123: Second bypass register;
[0036] 124: Second timer;
[0037] 600: Artificial intelligence chip;
[0038] D1: Passing parameter status;
[0039] D2: Calibration status;
[0040] D3: Clock repair status;
[0041] D4: Valid repair status;
[0042] D5: Main belt inverted state;
[0043] D6: Main band repair status. Detailed Implementation
[0044] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.
[0045] Throughout this specification and the appended claims, specific terms are used to represent specific components. Those skilled in the art will understand that chip manufacturers may use different names to represent the same component. This document is not intended to distinguish between components that have the same function but different names. In the following description and claims, words such as “comprising” and “including” are open-ended terms and should be interpreted as “including but not limited to…”.
[0046] The term "coupled (or connected)" as used throughout this disclosure (including the appended claims) can represent any direct or indirect connection element. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device via other devices or specific connection elements. The terms "first," "second," and similar terms used throughout this disclosure (including the appended claims) are used only to name discrete elements or to distinguish them in different embodiments or scopes. Therefore, the terms should not be considered as upper or lower limits on the number of elements or to limit the order of arrangement of elements. Additionally, where possible, elements / components / steps using the same reference numerals in the drawings and embodiments denote the same or similar parts. The same reference numerals or the same terminology may be used in different embodiments to refer to related descriptions of elements / components / steps.
[0047] refer to Figure 1 The data transmission system 100 includes a first chiplet 110 and a second chiplet 120. The first chiplet 110 and the second chiplet 120 are used to realize inter-chiplet communication based on UCIe. The first chiplet 110 can be coupled to the second chiplet 120, for example, through multiple bump lanes.
[0048] In this embodiment, bypass communication can be established between the first chip 110 and the second chip 120, wherein the bypass is independent of the main data channel between the first chip 110 and the second chip 120. In this embodiment, the bypass can be composed of a clock channel (i.e., a clock signal line) and a data channel (i.e., a data signal line). In this embodiment, the first chip 110 and the second chip 120 can transmit information through sideband messages to, for example, implement link initialization and link training between the first chip 110 and the second chip 120.
[0049] In this embodiment, the bypass is used to transmit control signals or management information and to ensure efficient collaboration between the cores. For example, the first core 110 and the second core 120 can transmit control commands through the bypass to help coordinate the operation of the main data channel. The first core 110 and the second core 120 can also transmit core status information, such as error detection or performance monitoring, through the bypass.
[0050] In one embodiment of the present invention, the data transmission system 100 may be implemented in an electronic device, and the electronic device includes a storage unit and a processor. The storage unit is used to store a computer program. The processor is coupled to the storage unit and is used to execute the computer program stored in the storage unit to cause the electronic device to perform the UCIe-based fault diagnosis and debugging method as described in the embodiments of the present invention.
[0051] Processors may include, for example, a central processing unit (CPU) or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), other similar processing devices, or combinations thereof.
[0052] Storage units may include, for example, random access memory (RAM), non-volatile memory, hard disk drive (HDD), or solid state drive (SSD). Random access memory may include, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). Non-volatile memory may include, for example, flash memory or read-only memory (ROM).
[0053] refer to Figure 1 as well as Figure 2 , Figure 1 The first core 110 may have the following characteristics: Figure 2 The configuration of the first physical layer architecture 111 shown is illustrated, and the second core 120 may have, as shown in the diagram. Figure 2 The configuration of the second physical layer architecture 121 is shown. In this embodiment, the first physical layer architecture 111 of the first chip 110 includes a first pause state register 112, a first bypass register 113, and a first timer 114. The second physical layer architecture 121 of the second chip 120 includes a second pause state register 122, a second bypass register 123, and a second timer 124.
[0054] It should be noted that the number of pause status registers and bypass registers in the first chip 110 is not limited to... Figure 2 As shown, the number of pause status registers and bypass registers in the second chip 120 is not limited to... Figure 2 As shown. In one embodiment, the first chip 110 may include a plurality of first pause state registers and a plurality of first bypass registers. The plurality of first pause state registers correspond to different states of link training and the state machine, respectively. The plurality of first bypass registers correspond to different states of link training and the state machine, respectively. The second chip 120 may include a plurality of second pause state registers and a plurality of second bypass registers. The plurality of second pause state registers correspond to different states of link training and the state machine, respectively. The plurality of second bypass registers correspond to different states of link training and the state machine, respectively.
[0055] refer to Figure 2 and Figure 3 The first core 110 can execute the following steps S310 to S350. In step S310, the data transmission system 100 performs link training between the first core 110 and the second core 120. In step S320, when a state execution error occurs, the first core 110 enables the first pause state register 112 to stop the state transition of the first core 110. In step S330, the first core 110 enables the first bypass register 113 to configure the first correction signal stored in the first bypass register 113. In step S340, the first core 110 disables the first pause state register 112 to continue the state transition of the first core 110.
[0056] Specifically, the first chip 110 can execute link training and state machine. In this embodiment, since the state transition logic or algorithm execution within a single state may malfunction due to design or manufacturing factors during the startup process (or chip design power-on process) of the first chip 110 and the second chip 120, the first chip 110 can pause the state transition during the execution of LTSM by enabling the first pause state register 112 based on the debug control mechanism configured in the register. Then, the first chip 110 can bypass the first correction signal stored in the first bypass register 113 to ensure that the sub-state meets the key conditions for LTSM state transition. Finally, the first chip 110 can resume the execution of LTSM state transitions by disabling the first pause state register 112. Therefore, the first chip 110 can implement fault diagnosis through the first pause state register 112 and debug through the first bypass register 113.
[0057] refer to Figure 2 as well as Figure 4Taking the process of the first chip 110 executing multiple sub-states of the bypass initialization state as an example, the first chip 110 can sequentially enter the following states during the bypass initialization process: PARAM state D1, Calibration state D2, Clock Repair state D3, Valid Repair state D4, Main Band Reversal state D5, and Main Band Repair state D6.
[0058] Taking the error occurring in clock repair state D3 in the first chip 110 as an example, the first chip 110 can execute the following steps S410 to S450. In step S410, the first chip 110 determines whether to enable the first pause state register 112. If not (for example, the state bit stored in the first pause state register 112 is "0"), it means that clock repair state D3 can proceed normally. If yes (for example, the state bit stored in the first pause state register 112 is "1"), then step S420 is executed. In step S420, the first chip 110 performs error detection. For this, chip testers can perform manual error detection. The first chip 110 can receive a first correction signal and write the first correction signal into the first bypass register 113. The first correction signal may, for example, include relevant logic parameters or instructions for correcting clock repair state D3 so that the corrected clock repair state D3 can proceed normally. In step S430, the first chip 110 configures the first correction signal stored in the first bypass register 113.
[0059] In step S440, the first chip 110 determines whether to disable the first pause status register 112. After the first correction signal is configured, the first chip 110 can disable the first pause status register 112 (e.g., the status bit stored in the first pause status register 112 is set to "0"). Furthermore, the first chip 110 can start the first timer 114 to implement the LTSM delay. In step S450, the first chip 110 determines whether the first timer 114 has counted to a first preset value. To this end, the first chip 110 enables the first timer 114. When the first timer 114 counts to the first preset value, the first chip 110 disables the first pause status register 112 (e.g., the status bit stored in the first pause status register 112 is set to "1"), and the first chip 110 can continue state transitions to perform clock repair state D3.
[0060] Therefore, the first chip 110 can be effectively used for fault diagnosis and repair of the clock repair state D3 during the LTSM process based on DFD design. Furthermore, steps S410 to S450 can also be applied to fault diagnosis and repair of the transmission parameter state D1, calibration state D2, valid repair state D4, main band inversion state D5, and main band repair state D6, and are not limited to these applications. Figure 4 .
[0061] refer to Figure 2 as well as Figure 5 The second core 120 can also have the fault diagnosis and repair functions of the first core 110 described above, and can perform fault diagnosis and repair synchronously. The data transmission system 100 can execute the following steps S501 to S509. In step S501, the data transmission system 100 performs link training between the first core 110 and the second core 120. When a state execution error occurs, in step S502, the first core 110 enables the first pause state register 112 to stop the state transition of the first core 110. In step S503, the second core 120 enables the second pause state register 122 to stop the state transition of the second core 120. In step S504, the first core 110 enables the first bypass register 113 to configure the first correction signal stored in the first bypass register 113. In step S505, the second core 120 enables the second bypass register 123 to configure the second correction signal stored in the second bypass register 123. In response, the first chip 110 can receive a first correction signal input by the tester and write the first correction signal into the first bypass register 113. Furthermore, the second chip 120 can receive a second correction signal input by the tester and write the second correction signal into the second bypass register 123. The first correction signal is different from the second correction signal, but this invention is not limiting.
[0062] In step S506, the first chip 110 enables the first timer 114. In step S507, the second chip 120 enables the second timer 124. In step S508, when the first timer 114 counts to a first preset value, the first pause state register 112 is disabled to continue the state transition of the first chip 110. In step S509, when the second timer 124 counts to a second preset value, the second pause state register 122 is disabled to continue the state transition of the second chip 120. Since the LTSM delays of the first chip 110 and the second chip 120 cannot differ too much (not exceeding the delay difference preset by the LTSM protocol), which could cause the startup process of the first chip 110 and the second chip 120 to fail, the difference between the first preset value and the second preset value is less than or equal to a preset difference. In one embodiment, the preset difference is 8 milliseconds, but the present invention is not limited to this.
[0063] refer to Figure 6 In one embodiment, the artificial intelligence chip 600 may include a first chip 110 and a second chip 120. The first chip 110 and the second chip 120 are used to realize inter-chip communication based on general chip interconnect technology. The first chip 110 and the second chip 120 can form a data transmission system. For related implementation methods and technical details regarding the first chip 110 and the second chip 120, please refer to the descriptions of the first chip 110 and the second chip 120 in the above embodiments. Furthermore, the fault diagnosis and debugging methods between the first chip 110 and the second chip 120 can also refer to the processes in the above embodiments, thus obtaining sufficient illustrations, suggestions, and implementation instructions. In addition, in another embodiment, the number of chips in the artificial intelligence chip 600 is not limited to... Figure 6 The first core 110 and the second core 120 are shown.
[0064] In one embodiment, the artificial intelligence chip 600 may be a system-on-chip (SoC) and include multiple small chips or modules with specific functions. In another embodiment, the artificial intelligence chip 600 may be any one of a central processing unit, a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU).
[0065] In summary, the UCIe-based fault diagnosis and debugging method, computer-readable storage medium, and artificial intelligence chip of the present invention can achieve fault diagnosis and debugging of the chip by setting a pause status register and a bypass register. Furthermore, the UCIe-based fault diagnosis and debugging method, computer-readable storage medium, and artificial intelligence chip of the present invention can set a timer to ensure that the delay between two communicating chips does not exceed a preset difference, thereby ensuring that the two chips can continue to perform startup operations.
[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A fault diagnosis and debugging method based on UCIe, characterized in that, include: Perform link training between the first and second core particles; During the execution of link training and state machine, when a state execution error occurs, the first pause state register of the first core is enabled to stop the state transition of the first core, thereby pausing the state transition during the execution of the link training and state machine. Enable the first bypass register of the first chip to configure the first correction signal stored in the first bypass register, thereby ensuring that the sub-state of the link training and state machine meets the state transition conditions of the link training and state machine. The first correction signal includes logical parameters or instructions for correcting the state so that the corrected state can proceed normally. as well as The first pause state register of the first chip is disabled to continue the state transition of the first chip, thereby resuming the state transition during the link training and state machine process.
2. The fault diagnosis and debugging method based on UCIe according to claim 1, characterized in that, Also includes: When a state execution error occurs, enable the second pause state register of the second core to stop the state transition of the second core; Enable the second bypass register of the second chip to configure the second correction signal stored in the second bypass register; as well as Disable the second pause state register of the second chip to continue the state transition of the second chip.
3. The fault diagnosis and debugging method based on UCIe according to claim 2, characterized in that, Also includes: Enable the first timer of the first chip; as well as When the first timer of the first chip counts to a first preset value, the first pause state register of the first chip is disabled.
4. The fault diagnosis and debugging method based on UCIe according to claim 3, characterized in that, Also includes: Enable the second timer of the second chip; as well as When the second timer of the second chip counts to the second preset value, the second pause status register of the second chip is disabled.
5. The fault diagnosis and debugging method based on UCIe according to claim 4, characterized in that, The difference between the first preset value and the second preset value is less than or equal to the preset difference.
6. The fault diagnosis and debugging method based on UCIe according to claim 5, characterized in that, The preset difference is 8 milliseconds.
7. The fault diagnosis and debugging method based on UCIe according to claim 2, characterized in that, Also includes: The first correction signal is received by the first chip and written into the first bypass register.
8. The fault diagnosis and debugging method based on UCIe according to claim 7, characterized in that, Also includes: The second correction signal is received by the second chip and written into the second bypass register.
9. The fault diagnosis and debugging method based on UCIe according to claim 8, characterized in that, The first correction signal is different from the second correction signal.
10. The fault diagnosis and debugging method based on UCIe according to claim 1, characterized in that, The first chip includes multiple first pause state registers and multiple first bypass registers. The plurality of first pause state registers respectively correspond to different states of link training and state machine, and the plurality of first bypass registers respectively correspond to different states of link training and state machine.
11. The fault diagnosis and debugging method based on UCIe according to claim 1, characterized in that, The second chip includes multiple second pause status registers and multiple second bypass registers. The plurality of second pause state registers correspond to different states of link training and state machine, respectively, and the plurality of second bypass registers correspond to different states of link training and state machine, respectively.
12. A computer-readable storage medium for storing a computer program, characterized in that, The computer program is executed by a processor to implement the steps of the UCIe-based fault diagnosis and debugging method according to any one of claims 1 to 11.
13. An artificial intelligence chip, characterized in that, include: The first chip includes a first pause state register and a first bypass register; as well as The second core is coupled to the first core and is used to communicate with the first core. The first core and the second core perform link training. During the link training and state machine process, when a state execution error occurs, the first core enables the first pause state register to stop the state transition of the first core, thereby pausing the state transition during the link training and state machine process. The first core enables the first bypass register to configure the first correction signal stored in the first bypass register, thereby ensuring that the sub-states of the link training and state machine meet the state transition conditions of the link training and state machine. The first correction signal includes logical parameters or instructions for correcting the state so that the corrected state proceeds normally. The first core then disables the first pause state register to continue the state transition of the first core, thereby resuming the state transition during the link training and state machine process.
Citation Information
Patent Citations
Link test method, electronic device, storage medium, product and computing device
CN119473744A