Data control system and measurement and control system

Abstract

This invention discloses a data control system and a measurement and control system, relating to the field of control technology. The data control system includes a processor, a relay chip, and at least one peripheral module. The processor includes a first interface and a second interface, configured to parse a preset control sequence to obtain first type of data and second type of data, and to send the first type of data through the first interface and the second type of data through the second interface, wherein the delay of the first interface is less than the delay of the second interface. The relay chip includes a first data control module, a second data control module, and a sending module. The sending module is configured to receive the first type of data forwarded by the first data control module and the second type of data forwarded by the second data control module, and to send the first type of data and the second type of data to the corresponding peripheral modules, so that the corresponding peripheral modules can execute at least one of the first type of data and the second type of data. This data control system has a small feedback delay.

Description

Technical Field

[0001] This application relates to the field of control technology, and in particular to a data control system and a measurement and control system. Background Technology

[0002] In the field of quantum computing measurement and control, with the technological iteration of ion trap computing platforms, the quantum scale is constantly increasing, and the timing complexity of manipulation is continuously improving. This has led to the need for real-time feedback of quantum states in next-generation platforms. Specifically, in quantum feedback control experiments, the result of a single measurement of the quantum state can be used as a decision input to provide instantaneous feedback to the qubit. Shorter feedback times mean lower feedback error rates and higher operational fidelity in quantum information processing, which can be applied to rapid quantum state initialization, quantum state stabilization, and quantum error correction.

[0003] The measurement and control system in related technologies requires the host computer to process the control sequence, resulting in a very large feedback delay (on the order of milliseconds), which cannot meet the coherence time requirements of quantum states. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, the first objective of this invention is to propose a data control system that uses a processor to analyze manipulation sequences in real time and a relay chip to control the data flow, thereby shortening the data feedback time, reducing feedback delay, and ultimately meeting the coherence time requirements of quantum states.

[0005] The second objective of this invention is to provide a measurement and control system.

[0006] To achieve the above objectives, a data control system is provided according to a first aspect of the present invention, comprising: a processor, a relay chip, and at least one peripheral module; the processor includes a first interface and a second interface, and is configured to parse a preset control sequence to obtain first type data and second type data, and to send the first type data through the first interface and the second type data through the second interface, wherein the first type data includes event data and a timestamp, and the delay of the first interface is less than the delay of the second interface; the relay chip includes a first data control module, a second data control module, and a sending module, wherein the first data control module is configured to receive the first type data, the second data control module is configured to receive the second type data, and the sending module is configured to receive the first type data forwarded by the first data control module and the second type data forwarded by the second data control module, and to send the first type data and the second type data to the corresponding peripheral module so that the corresponding peripheral module executes at least one of the first type data and the second type data, wherein the sending priority of the first type data is higher than the sending priority of the second type data.

[0007] A data control system according to an embodiment of the present invention includes: a processor, a relay chip, and at least one peripheral module; the processor includes a first interface and a second interface, and is configured to parse a preset manipulation sequence to obtain first type data and second type data, and to send the first type data through the first interface and the second type data through the second interface, wherein the first type data includes event data and a timestamp, and the delay of the first interface is less than the delay of the second interface; the relay chip includes a first data control module, a second data control module, and a sending module, wherein the first data control module is configured to receive the first type data, the second data control module is configured to receive the second type data, and the sending module is configured to receive the first type data forwarded by the first data control module and the second type data forwarded by the second data control module, and to send the first type data and the second type data to the corresponding peripheral modules so that the corresponding peripheral modules execute at least one of the first type data and the second type data, wherein the sending priority of the first type data is higher than the sending priority of the second type data. Thus, by having the processor parse the manipulation sequence in real time and the relay chip control the data flow, the data feedback time is shortened, the feedback delay is reduced, and the coherence time requirement of the quantum state is met.

[0008] According to one embodiment of the present invention, the processor further includes a first storage module and a second storage module; the first storage module is connected to a first interface and is used to store a first type of data; the second storage module is connected to a second interface and is used to store a second type of data.

[0009] According to one embodiment of the present invention, the processor is further configured to send a wake-up command to the relay chip after parsing the preset control sequence, so that the first data control module can read the first storage module through the first interface.

[0010] According to one embodiment of the present invention, each peripheral module includes a data parsing module and an execution module; the data parsing module is configured to parse the data sent by the sending module, and store the first type of data if the data sent by the sending module is a first type of data; the execution module is configured to retrieve the first type of data from the data parsing module and execute the first type of data if the timestamp matches the timestamp corresponding to the first type of data.

[0011] According to one embodiment of the present invention, the relay chip is further configured to clear the time axis of all peripheral modules after the data control system initialization is completed.

[0012] According to an embodiment of the present invention, when the peripheral module is a counting device or an image acquisition device, the peripheral module further includes a data classification module. The data classification module is configured to classify the feedback data sent by the execution module to obtain a third type of data and a fourth type of data, and send the third type of data and the fourth type of data to the relay chip. The execution module generates feedback data after executing the first type of data. The sending priority of the third type of data is higher than that of the fourth type of data, and the data volume of the third type of data is less than that of the fourth type of data.

[0013] According to one embodiment of the present invention, the relay chip further includes a receiving module, which is configured to receive data sent by the data classification module, classify the data sent by the data classification module, and send a third type of data to a first data control module so that the first data control module sends the third type of data to the processor through a first interface, and sends a fourth type of data to a second data control module so that the second data control module sends the fourth type of data to the processor through a second interface when it receives an interrupt signal from the processor.

[0014] According to one embodiment of the present invention, the first data control module includes a first data sending module and a first data receiving module; the first data sending module is configured to receive a first type of data and forward the first type of data to the sending module; the first data receiving module is configured to receive a third type of data and forward the third type of data to the processor.

[0015] According to one embodiment of the present invention, the data parsing module is further configured to send a cache warning to the first data sending module through the sending module when the amount of stored data is greater than a first preset amount of data. The first data sending module pulls the event receiving signal low upon receiving the cache warning, so as to cause the processor to stop sending the first type of data.

[0016] According to one embodiment of the present invention, the data parsing module is further configured to send a warning cancellation to the first data sending module through the sending module when the amount of stored data is less than a second preset data amount, wherein the first data sending module pulls up the event receiving signal when it receives the warning cancellation, and the first preset data amount is greater than the second preset data amount.

[0017] According to one embodiment of the present invention, the second data control module includes a second data sending module and a second data receiving module; the second data sending module is configured to receive a second type of data and forward the second type of data to the sending module; the second data receiving module is configured to receive a fourth type of data, store the fourth type of data, and forward the fourth type of data to the processor when an interrupt signal is received.

[0018] According to one embodiment of the present invention, the second data receiving module is configured to send a cache warning to the first data sending module when the amount of stored fourth type data is greater than the amount of third preset data. The first data sending module pulls the event receiving signal low upon receiving the cache warning, so as to cause the processor to stop sending the first type of data.

[0019] According to one embodiment of the present invention, the second data receiving module is configured to send a warning cancellation to the first data sending module when the amount of stored fourth type of data is less than the fourth preset data amount, wherein the first data sending module pulls up the event receiving signal when it receives the warning cancellation, and the third preset data amount is greater than the fourth preset data amount.

[0020] According to one embodiment of the present invention, the processor and the relay chip are integrated in the same controller, wherein the processor is an ARM processor and the relay chip is an FPGA.

[0021] To achieve the above objectives, a measurement and control system is provided according to a second aspect of the present invention, comprising: a data control system of any of the foregoing embodiments.

[0022] According to the measurement and control system of the present invention, by adopting the above-described measurement and control system, the processor analyzes the control sequence in real time and the relay chip controls the data flow, thereby shortening the data feedback time, reducing the feedback delay, and thus meeting the coherence time requirements of the quantum state.

[0023] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a data control system according to an embodiment of the present invention;

[0025] Figure 2 This is a system schematic diagram of a data control system according to another embodiment of the present invention;

[0026] Figure 3 This is a system schematic diagram of a processor according to an embodiment of the present invention;

[0027] Figure 4 This is a system schematic diagram of a peripheral module according to an embodiment of the present invention;

[0028] Figure 5 This is a system schematic diagram of a relay chip according to an embodiment of the present invention;

[0029] Figure 6This is a schematic diagram of the workflow between the processor and the relay chip according to an embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of a measurement and control system according to an embodiment of the present invention. Detailed Implementation

[0031] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0032] In related technologies, in quantum feedback control experiments, the result of a single measurement of a quantum state can be used as a decision input to provide instant feedback to the qubit. Shorter feedback time means a lower feedback error rate and higher operational fidelity of quantum information processing, which can be applied to fast quantum state initialization, quantum state stabilization and quantum error correction.

[0033] The workflow of the measurement and control system in related technologies is as follows: the host computer presets the control sequence; the host computer translates the control sequence into communication protocol code according to a certain data structure and sends it down; the peripheral module receives the control sequence and decodes it into control parameters, such as TTL (Transistor-transistor Logic) pulse sequence parameters and DDS (Direct Digital Frequency Synthesis) pulse sequence parameters, and stores them in a local large-capacity buffer; the control sequence parameters are played according to the trigger signal; the results are read and uploaded to the host computer; the host computer processes and sends down the next control sequence.

[0034] As can be seen from the above workflow, the feedback delay of the measurement and control system in related technologies is extremely large (on the order of milliseconds) due to processing by the host computer, which cannot meet the coherence time requirements of quantum states. Furthermore, since the entire sequence is transmitted each time, the lower-level FPGA (Field Programmable Gate Array) requires a large amount of storage space for data storage to achieve large-scale control sequence generation. Therefore, the measurement and control system in related technologies suffers from large feedback delays and high storage space requirements.

[0035] The data control system and measurement and control system of the present invention are described below with reference to the accompanying drawings.

[0036] Figure 1 This is a system schematic diagram of a data control system according to an embodiment of the present invention. Figure 1As shown, the data control system includes: a processor 100, a relay chip 200, and at least one peripheral module 300.

[0037] The processor 100 includes a first interface 110 and a second interface 120. The processor 100 is configured to parse a preset control sequence to obtain first type data and second type data, and to send the first type data through the first interface 110 and the second type data through the second interface 120. The first type data includes event data and timestamps, and the delay of the first interface 110 is less than the delay of the second interface 120. The relay chip 200 includes a first data control module 210, a second data control module 220, and a sending module 230. The first data control module 210 is configured to receive the first type data, the second data control module 220 is configured to receive the second type data, and the sending module 230 is configured to receive the first type data forwarded by the first data control module 210 and the second type data forwarded by the second data control module 220, and to send the first type data and the second type data to the corresponding peripheral module 300 so that the corresponding peripheral module 300 executes at least one of the first type data and the second type data. The sending priority of the first type data is higher than the sending priority of the second type data.

[0038] Specifically, the preset data sequence includes experimental sequences and feedback structures, such as waveform / pulse definitions and pulse width information, as well as feedback branch judgment and jump logic. The processor 100 parses the preset control sequence to obtain a first type of data and a second type of data. The first type of data includes event data and time stamps (Event / Time, abbreviated as E / T). All events / times constitute a timeline, so the first type of data is a critical data type. The second type of data is a non-critical data type, such as device search, register issuance, and calibration parameter issuance. The second type of data is also important but cannot occupy the data transmission bandwidth of the E / T type; otherwise, it will affect real-time performance and feedback delay. The first interface 110 and the second interface 120 are two parallel interfaces that do not interfere with each other and do not occupy their respective data stream bandwidth. The delay of the first interface 110 is less than the delay of the second interface 120. The first type of data is sent to the first data control module 210 through the first interface 110, and the second type of data is sent to the second data control module 220 through the second interface 120. Therefore, the data transmission bandwidth of the second type of data will not occupy the data transmission bandwidth of the first type of data, and the transmission speed of the first type of data is faster. The sending module 230 receives first-type data forwarded by the first data control module 210 and second-type data forwarded by the second data control module 220. The first and second types of data include routing and addressing information for the peripheral channels. Therefore, the sending module 230 can send the first and second types of data to the corresponding peripheral modules 300 based on the address information in the first and second types of data, respectively. The sending module 230 will prioritize sending the first type of data to ensure the real-time performance of the E / T data stream. Upon receiving at least one of the first and second types of data, the peripheral module 300 will execute the corresponding data.

[0039] It should be noted that the types of peripheral modules 300 include, but are not limited to, external devices for signal generation and acquisition such as DDS, TTL, COUNT, AWG (Arbitrary Waveform Generator), and camera accelerator boards.

[0040] In one alternative implementation, such as Figure 2As shown, the processor 100 is connected to the host computer 400 via Gigabit Ethernet or USB 3.0. The host computer 400 includes a host computer software / script operation interface to realize user interaction functions. The user edits the experimental sequence and feedback structure (waveform / pulse definition and pulse width information, as well as feedback branch judgment and jump logic) on the host computer 400 interface to generate a preset operation sequence. The preset operation sequence is then sent to the processor 100 via Gigabit Ethernet or USB 3.0. The regular code executed on the host computer 400 and the kernel code executed on the processor 100 can mutually call and convert between each other. The sending module 230 can be an interconnected SerDes (Serializer / Deserializer).

[0041] For example, processor 100 and relay chip 200 are integrated in the same controller, processor 100 is an ARM (Advanced RISC Machine, a processor architecture) processor, and relay chip 200 is an FPGA.

[0042] For example, the controller can be a Zynq chip, which includes a PS (Processing System) and a PL (Programmable Logic), where the PS is an ARM processor and the PL is an FPGA. The processor 100 can be an ARM processor of the Zynq chip, the relay chip 200 can be an FPGA of the Zynq chip, the first interface 110 is an AXI-ACP interface (AXI cache coherency interface), and the second interface 120 is an AXI-HP interface (AXI high-performance interface).

[0043] In the above embodiments, the processor parses the manipulation sequence in real time, and the relay chip controls the data flow, thereby shortening the data feedback time, reducing the feedback delay, and thus meeting the coherence time requirements of the quantum state.

[0044] In some embodiments, such as Figure 3 As shown, the processor 100 also includes a first storage module 130 and a second storage module 140; the first storage module 130 is connected to the first interface 110 and is used to store a first type of data; the second storage module 140 is connected to the second interface 120 and is used to store a second type of data.

[0045] In other words, after the processor 100 parses and obtains the first type of data and the second type of data, it stores the first type of data in the first storage module 130 and stores the second type of data in the second storage module 140.

[0046] For example, when the processor 100 is an ARM processor with a Zynq chip, the first storage module 130 is an L2 cache, and the second storage module 140 is a DDR (Double Data Rate Synchronous Dynamic Random Access Memory).

[0047] In some embodiments, the processor 100 is further configured to send a wake-up command to the relay chip 200 after parsing a preset control sequence, so that the first data control module 210 reads the first storage module 130 through the first interface 110.

[0048] Specifically, because the processor 100 parses the preset control sequence, the relay chip 200 does not know when the processor 100 will complete the parsing, so the relay chip 200 cannot determine the acquisition time of the first type of data. Therefore, after the processor 100 completes the parsing of the preset control sequence, it stores the first type of data at a fixed address and then sends a wake-up command to the relay chip 200. When the relay chip 200 receives the wake-up command, the first data control module 210 reads the first type of data stored in the first storage module 130 through the first interface 110.

[0049] It should be noted that the reading method for the second type of data is different from that for the first type of data. The relay chip 200 reads the second type of data stored in the second storage module 140 according to the preset descriptor.

[0050] In some embodiments, such as Figure 4 As shown, each peripheral module 300 includes a data parsing module 310 and an execution module 320. The data parsing module 310 is configured to parse the data sent by the sending module 230, and store the first type of data if the data sent by the sending module 230 is the first type of data. The execution module 320 is configured to retrieve the first type of data from the data parsing module 310, execute the first type of data, and output the peripheral signal if the timestamp matches the timestamp corresponding to the first type of data.

[0051] In other words, after receiving the data sent by the sending module 230, the data parsing module 310 parses the data sent by the sending module 230 and stores the first type of data in a FIFO (First Input First Output) buffer. When the timestamp matches the timestamp corresponding to the first type of data, the execution module 320 retrieves the first type of data from the FIFO buffer and executes it.

[0052] Optional, such as Figure 4 As shown, the sending module 230 sends the first type of data and the second type of data to the corresponding peripheral module 300 through the backplane 500, and the corresponding peripheral module 300 performs data parsing and storage.

[0053] In some embodiments, the relay chip 200 is also configured to clear the time axis of all peripheral modules 300 after the data control system initialization is completed.

[0054] Understandably, after the data control system is initialized, the relay chip 200 automatically performs a unified time axis operation, that is, the trigger edge signal is sent to all peripheral modules 300 through the Serdes long hard interconnect backplane 500 line. The peripheral modules 300 use the trigger edge signal as a reference to clear their respective local time axes, thus realizing the unification of high-precision time marking.

[0055] In some embodiments, such as Figure 4 As shown, when the peripheral module 300 is a counting device or an image acquisition device, the peripheral module 300 also includes a data classification module 330. The data classification module 330 is configured to classify the feedback data sent by the execution module 320 to obtain third-class data and fourth-class data, and send the third-class data and fourth-class data to the relay chip 200. The execution module 320 generates feedback data after executing the first-class data. The sending priority of the third-class data is higher than that of the fourth-class data, and the data volume of the third-class data is less than that of the fourth-class data.

[0056] Specifically, when the peripheral module 300 is a technical device or an image acquisition device, it will generate feedback data due to the execution of the first type of data. This feedback data can be divided into two categories: the third type and the fourth type. The third type of data requires real-time feedback and has a relatively small volume. This third type of data needs to be uploaded to the relay chip 200 and processor 100 with minimal delay for feedback determination and the issuance of new first-type data, directly affecting the feedback delay. The fourth type of data has lower timeliness requirements and a larger volume. The data classification module 330 classifies the feedback data to obtain the third and fourth types of data, and sends both to the relay chip 200. The data classification module 330 prioritizes sending the third type of data.

[0057] In some embodiments, such as Figure 4As shown, the relay chip 200 also includes a receiving module 240, which is configured to receive data sent by the data classification module 330, classify the data sent by the data classification module 330, and send the third type of data to the first data control module 210 so that the first data control module 210 can send the third type of data to the processor 100 through the first interface 110, and send the fourth type of data to the second data control module 220 so that the second data control module 220 can send the fourth type of data to the processor 100 through the second interface 120 when it receives an interrupt signal from the processor 100.

[0058] Specifically, the data classification module 330 sends third-class and fourth-class data to the receiving module 240 through the backplane 500. The receiving module 240 receives the data sent by the classification module and filters and classifies the data sent by the data classification module 330 to determine whether the data sent by the data classification module 330 is third-class or fourth-class data. If it is third-class data, the receiving module 240 will directly send it to the RAM (Random Access Memory) of the first data control module 210, so that the processor 100 can quickly read the feedback data from the first data control module 210 through the first interface 110. If it is fourth-class data and other data that needs to be uploaded (such as register readback, device search feedback, etc.), it is cached by the second data control module 220 and uploaded by an interrupt signal between the processor 100 and the relay chip 200. When the second data control module 220 receives the interrupt signal from the processor 100, it sends the fourth-class data to the second storage module 140 of the processor 100 through the second interface 120.

[0059] In the above embodiments, the read results of the peripheral module are directly sent to the processor's real-time control system for rapid feedback and judgment, thereby reducing the total feedback latency to below 10µs.

[0060] In some embodiments, such as Figure 5 As shown, the first data control module 210 includes a first data sending module 211 and a first data receiving module 212; the first data sending module 211 is configured to receive a first type of data and forward the first type of data to the sending module 230; the first data receiving module 212 is configured to receive a third type of data and forward the third type of data to the processor 100.

[0061] In other words, the first data control module 210 includes a first data sending module 211 and a first data receiving module 212. The first data sending module 211 is used to receive the first type of data sent by the first storage module 130 of the processor 100 through the first interface 110, and forward the first type of data to the sending module 230. The first data receiving module 212 is used to receive the third type of data sent by the data classification module 330 through the receiving module 240, and send the third type of data to the first storage module 130 of the processor 100.

[0062] In some embodiments, the data parsing module 310 is further configured to send a cache warning to the first data sending module 211 via the sending module 230 when the amount of stored data is greater than the first preset amount of data. In this case, the first data sending module 211 pulls the event receiving signal low upon receiving the cache warning, so that the processor 100 stops sending the first type of data.

[0063] Specifically, in the data flow of the entire data control system, the interval between the processor 100 parsing and sending the first type of data is approximately 40-50 ns to achieve low-latency feedback. The first type of data is ultimately buffered in the FIFO of the peripheral module 300 and retrieved according to the timestamp timing. That is to say, if the pulse width interval during timestamp matching is too long, the FIFO of the peripheral module 300 will inevitably overflow if not limited. Therefore, when the amount of data stored in the FIFO of the data parsing module 310 exceeds the first preset data amount, the data parsing module 310 pushes a buffer warning to the first data sending module 211 through the sending module 230. When the first data sending module 211 receives the buffer warning, it pulls the event receiving signal low, and the processor 100 stops sending the first type of data.

[0064] In some embodiments, the data parsing module 310 is further configured to send a warning cancellation to the first data sending module 211 via the sending module 230 when the amount of stored data is less than the second preset data amount. In this case, the first data sending module 211 pulls up the event receiving signal when it receives the warning cancellation, and the first preset data amount is greater than the second preset data amount.

[0065] Specifically, as the timestamp advances, the FIFO of the peripheral module 300 is gradually retrieved and executed. The amount of data stored in the data parsing module 310 quickly falls below the first preset data amount. If the cache warning is immediately lifted at this point, repeated triggering and lifting of the cache warning will occur within a certain time period, which is detrimental to system stability. Therefore, when the amount of data stored in the data parsing module 310 falls below the second preset data amount, the data parsing module 310 pushes a warning lifting notification to the first data sending module 211 through the sending module 230. When the first data sending module 211 receives the warning lifting notification, it raises the event receiving signal, and the processor 100 continues to send the first type of data.

[0066] For example, suppose the FIFO depth of peripheral module 300 is 2048, the first preset data volume is 1024, and the second preset data volume is 100. When the amount of data stored in the FIFO of data parsing module 310 exceeds 1024, data parsing module 310 pushes a buffer warning to first data sending module 211 through sending module 230. When first data sending module 211 receives the buffer warning, it pulls the event receiving signal low, and processor 100 stops sending the first type of data. When the amount of data stored in the FIFO of data parsing module 310 is less than 100, data parsing module 310 pushes a warning cancellation to first data sending module 211 through sending module 230. When first data sending module 211 receives the warning cancellation, it pulls the event receiving signal high, and processor 100 continues to send the first type of data.

[0067] Figure 6 The workflow between the processor and the relay chip is shown, such as... Figure 6 As shown, the workflow includes the following steps:

[0068] S401, the processor completes the parsing of the preset operation sequence to obtain the first type of data 1-N.

[0069] S402, the processor stores the first type of data 1-N at a first fixed address (with the address location of the first type of data 1-N).

[0070] S403, the processor pulls high to send a signal.

[0071] S404, the relay chip reads and parses from the first fixed address, and reads the first type of data at the address positions 1-N of the first type of data.

[0072] S405, the relay chip has completed data retrieval and writes a completion flag to the second fixed address.

[0073] S406, relay chip high-level event reception signal.

[0074] S407, the processor reads the completion marker from the second fixed address, and the downlink process ends.

[0075] When the relay chip 200 receives a cache warning, it pulls the event receiving signal low, and the processor 100 stops parsing and interacting until the relay chip 200 receives a warning cancellation. Then, the relay chip 200 pulls the event receiving signal high again, and the first type of data transmission resumes normally. Therefore, although the processor 100 is the master end of data control and the relay chip 200 is the slave end of data flow control, the relay chip 200 can still control the data.

[0076] In the above embodiments, the processor parses the control sequence in real time, the relay chip performs flow control on the data, and the peripheral module only needs to design a small-capacity FIFO to achieve playback of an infinitely long control sequence, thereby reducing the requirements for storage space.

[0077] In some embodiments, such as Figure 5 As shown, the second data control module 220 includes a second data sending module 221 and a second data receiving module 222; the second data sending module 221 is configured to receive a second type of data and forward the second type of data to the sending module 230; the second data receiving module 222 is configured to receive a fourth type of data, store the fourth type of data, and forward the fourth type of data to the processor 100 when an interrupt signal is received.

[0078] Similarly, the second data control module 220 also includes a second data sending module 221 and a second data receiving module 222. The second data sending module 221 is used to receive the second type of data sent by the second storage module 140 of the processor 100 through the second interface 120, and forward the second type of data to the sending module 230. The second data receiving module 222 is used to receive the fourth type of data sent by the data classification module 330 through the receiving module 240, and send the fourth type of data to the second storage module 140 of the processor 100.

[0079] In some embodiments, the second data receiving module 222 is configured to send a cache warning to the first data sending module 211 when the amount of stored fourth type data is greater than the third preset data amount. In this case, the first data sending module 211 pulls the event receiving signal low upon receiving the cache warning, so that the processor 100 stops sending the first type of data.

[0080] It should be noted that since the transmission of the third type of data is initiated by the processor 100, while the fourth type of data is uploaded via an interrupt signal, the second data receiving module 222 may store a large amount of the fourth type of data. Although the fourth type of data is only generated when the peripheral module 300 executes the first type of data, theoretically, when the peripheral module 300 stores too much first type of data, the processor 100 will stop sending the first type of data, and therefore, a large amount of the fourth type of data will not be generated. However, in practical applications, the flow of first type of data and the flow of fourth type of data for the same event do not match, and the residual data in the FIFO of the peripheral module 300 may also cause a large amount of fitted data to clog the second data receiving module 222. Therefore, when the amount of fourth type of data stored in the second data receiving module 222 exceeds the third preset data amount, the processor 100 needs to stop sending the first type of data.

[0081] Specifically, each GT (Gigabit Transceiver) end of the relay chip 200 corresponds to a peripheral module 300. Each GT end is independently designed with a buffer FIFO to receive the fourth type of data sent by the peripheral module 300. When the amount of data stored in the buffer FIFO exceeds the third preset data amount, the second data receiving module 222 generates a buffer warning high level and pushes the buffer warning to the first data sending module 211. When the first data sending module 211 receives the buffer warning high level, it pulls the event receiving signal low, and the processor 100 stops sending the first type of data.

[0082] In some embodiments, the second data receiving module 222 is configured to send a warning cancellation to the first data sending module 211 when the amount of stored fourth type data is less than the fourth preset data amount. The first data sending module 211 pulls up the event receiving signal when it receives the warning cancellation, and the third preset data amount is greater than the fourth preset data amount.

[0083] In other words, the fourth type of data in the FIFO at the GT end is transferred to the second storage module 140 through the second interface 120. The amount of data stored in the second data receiving module 222 quickly falls below the third preset data amount. If the cache warning is immediately released at this time, the cache warning will be repeatedly triggered and released within a certain period of time, which is not conducive to system stability. Therefore, when the amount of data stored in the second data receiving module 222 is less than the fourth preset data amount, the second data receiving module 222 pushes a warning release low level to the first data sending module 211. When the first data sending module 211 receives the warning release low level, it pulls the event receiving signal high, and the processor 100 continues to send the first type of data.

[0084] For example, suppose the FIFO depth at the GT end is 4096, the third preset data volume is 1280, and the fourth preset data volume is 256. When the data volume stored in the FIFO at the GT end exceeds 1280, the second data receiving module 222 pushes a buffer warning high level to the first data sending module 211. When the first data sending module 211 receives the buffer warning high level, it pulls the event receiving signal low, and the processor 100 stops sending the first type of data. When the data volume stored in the FIFO at the GT end is less than 256, the second data receiving module 222 pushes a warning release low level to the first data sending module 211. When the first data sending module 211 receives the warning release low level, it pulls the event receiving signal high, and the processor 100 continues to send the first type of data.

[0085] In the above embodiments, the processor parses the control sequence in real time, the relay chip performs flow control on the data, and the GT end only needs to design a small-capacity FIFO to achieve playback of an infinitely long control sequence, thereby reducing the requirements for storage space.

[0086] In summary, the data control system according to embodiments of the present invention shortens the data feedback time and reduces the feedback delay by having the processor analyze the manipulation sequence in real time and the relay chip control the data flow, thereby meeting the coherence time requirements of the quantum state. Furthermore, the readout results from the peripheral module are directly sent to the processor's real-time control system for rapid feedback judgment, thus reducing the total feedback delay to below 10µs. In addition, with the processor analyzing the manipulation sequence in real time and the relay chip controlling the data flow, the peripheral module only needs a small-capacity FIFO to play an infinitely long manipulation sequence, thereby reducing the storage space requirements.

[0087] Corresponding to the above embodiments, embodiments of the present invention also provide a measurement and control system. For example... Figure 7 As shown, the measurement and control system 2000 includes: the data control system 1000 of any of the foregoing embodiments.

[0088] According to the measurement and control system of the present invention, by adopting the above-described measurement and control system, the processor analyzes the control sequence in real time and the relay chip controls the data flow, thereby shortening the data feedback time, reducing the feedback delay, and thus meeting the coherence time requirements of the quantum state.

[0089] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0090] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0091] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0092] Furthermore, the terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this invention can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this invention, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly specified in the embodiments.

[0093] In this invention, unless otherwise explicitly specified or limited in the embodiments, the terms "installation," "connection," "joining," and "fixing" appearing in the embodiments should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral part; it can also be a mechanical connection, an electrical connection, etc. Of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components, or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific implementation.

[0094] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A data control system, characterized in that, include: Processor, relay chip and at least one peripheral module; The processor includes a first interface and a second interface. The processor is configured to parse a preset control sequence to obtain a first type of data and a second type of data, and to send the first type of data through the first interface and the second type of data through the second interface. The first type of data includes event data and timestamps. The delay of the first interface is less than the delay of the second interface. The first interface is an AXI-ACP interface and the second interface is an AXI-HP interface. The relay chip includes a first data control module, a second data control module, and a sending module. The first data control module is configured to receive the first type of data, the second data control module is configured to receive the second type of data, and the sending module is configured to receive the first type of data forwarded by the first data control module and the second type of data forwarded by the second data control module, and send the first type of data and the second type of data to the corresponding peripheral module so that the corresponding peripheral module can execute at least one of the first type of data and the second type of data, wherein the sending priority of the first type of data is higher than the sending priority of the second type of data. The processor also includes a first storage module and a second storage module; The first storage module is connected to the first interface, and the first storage module is used to store the first type of data. The first storage module is an L2-Cache. The second storage module is connected to the second interface, and the second storage module is used to store the second type of data. The second storage module is DDR. The processor is further configured to send a wake-up command to the relay chip after parsing the preset control sequence, so that the first data control module can read the first storage module through the first interface.

2. The data control system according to claim 1, characterized in that, Each peripheral module includes a data parsing module and an execution module; The data parsing module is configured to parse the data sent by the sending module, and store the first type of data if the data sent by the sending module is the first type of data. The execution module is configured to retrieve the first type of data from the data parsing module and execute the first type of data if the timestamp matches the timestamp corresponding to the first type of data.

3. The data control system according to claim 2, characterized in that, The relay chip is also configured to clear the time axis of all peripheral modules after the data control system has been initialized.

4. The data control system according to claim 2, characterized in that, When the peripheral module is a counting device or an image acquisition device, the peripheral module further includes a data classification module. The data classification module is configured to classify the feedback data sent by the execution module to obtain a third type of data and a fourth type of data, and send the third type of data and the fourth type of data to the relay chip. The execution module generates the feedback data after executing the first type of data. The sending priority of the third type of data is higher than that of the fourth type of data, and the data volume of the third type of data is less than that of the fourth type of data.

5. The data control system according to claim 4, characterized in that, The relay chip further includes a receiving module configured to receive data sent by the data classification module, classify the data sent by the data classification module, and send the third type of data to the first data control module so that the first data control module sends the third type of data to the processor through the first interface, and sends the fourth type of data to the second data control module so that the second data control module sends the fourth type of data to the processor through the second interface when it receives an interrupt signal from the processor.

6. The data control system according to claim 5, characterized in that, The first data control module includes a first data sending module and a first data receiving module; The first data sending module is configured to receive the first type of data and forward the first type of data to the sending module; The first data receiving module is configured to receive the third type of data and forward the third type of data to the processor.

7. The data control system according to claim 6, characterized in that, The data parsing module is further configured to send a cache warning to the first data sending module through the sending module when the amount of stored data exceeds a first preset amount of data. Upon receiving the cache warning, the first data sending module pulls the event receiving signal low to cause the processor to stop sending the first type of data.

8. The data control system according to claim 7, characterized in that, The data parsing module is further configured to send a warning cancellation message to the first data sending module through the sending module when the amount of stored data is less than the second preset data amount. The first data sending module will raise the event receiving signal upon receiving the warning cancellation message, and the first preset data amount is greater than the second preset data amount.

9. The data control system according to claim 6, characterized in that, The second data control module includes a second data sending module and a second data receiving module; The second data sending module is configured to receive the second type of data and forward the second type of data to the sending module; The second data receiving module is configured to receive the fourth type of data, store the fourth type of data, and forward the fourth type of data to the processor upon receiving the interrupt signal.

10. The data control system according to claim 9, characterized in that, The second data receiving module is configured to send a cache warning to the first data sending module when the amount of stored fourth type of data is greater than the third preset amount of data. Upon receiving the cache warning, the first data sending module pulls the event receiving signal low to cause the processor to stop sending the first type of data.

11. The data control system according to claim 10, characterized in that, The second data receiving module is configured to send a warning cancellation to the first data sending module when the amount of stored fourth type of data is less than the fourth preset data amount. The first data sending module will raise the event receiving signal upon receiving the warning cancellation, and the third preset data amount is greater than the fourth preset data amount.

12. The data control system according to claim 1, characterized in that, The processor and the relay chip are integrated in the same controller. The processor is an ARM processor, and the relay chip is an FPGA.

13. A measurement and control system, characterized in that, include: The data control system according to any one of claims 1-12.

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