Real-time ultrafast ultrasonic image reconstruction system and method based on FPGA

Abstract

The invention discloses a real-time ultrafast ultrasonic image reconstruction system and method based on an FPGA, and the system comprises an analog front-end collection chip, the FPGA, and an upper computer which is used for transmitting collected multi-channel ultrasonic data to the FPGA through the analog front-end collection chip, receiving a control command sent by the FPGA, and transmitting the control command to the FPGA through the upper computer. And the FPGA performs data preprocessing, beam forming calculation and image post-processing on the multi-channel ultrasonic data, processes a received command and an external trigger signal, and uploads inter-board cascade communication and an image sampling and processing result to an upper computer for real-time display. According to the invention, real-time acquisition of high-channel ultrafast ultrasonic signals and medical ultrafast ultrasonic image reconstruction can be realized, equipment cascading is supported, the data processing speed is high, the bandwidth is high, the number of channels is large, the system can be expanded, real-time reconstruction can be directly carried out on an FPGA, and the ultrasonic image reconstruction rate is greatly improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of ultrafast ultrasound signal acquisition and processing, and particularly relates to a real-time ultrafast ultrasound image reconstruction system and method based on FPGA. BACKGROUND

[0002] With the continuous progress of medical imaging and ultrasound technology, the ultrafast ultrasound imaging technology has shown great potential in biomedical research and clinical applications. Ultrafast ultrasound imaging can achieve real-time imaging up to thousands of frames per second, providing unprecedented resolution and speed for observing dynamic biological processes. This technology provides a revolutionary observation method for the visualization of dynamic biological processes such as cardiovascular dynamics research, tumor neovascular evaluation, and brain neural activity monitoring.

[0003] There are many methods and systems for fast reconstruction of ultrafast ultrasound images at present, among which the commonly used image reconstruction method is the compound plane wave coherent imaging algorithm. The core of the compound plane wave coherent imaging algorithm is to sequentially transmit multiple beams of ultrasonic plane waves with different preset deflection angles into the medium; then, the received ultrasonic echo signals from these different angle plane wave transmission events are combined and superimposed to synthesize the final ultrasonic image. This process essentially replaces and compensates for the beam focusing link necessary in the transmission stage of traditional imaging methods by introducing a coherent compound mechanism of multiple angle plane waves. The specific steps of ultrafast ultrasound based on compound plane wave imaging are as follows: transmitting n plane waves with different deflection angles, receiving echo data using array elements; calculating the transmission delay and reception delay of any point in the imaging plane for any receiving channel; performing delay summation for each plane wave with a deflection angle, and spatially combining the plane wave echo data after delay processing, which can obtain the pixel value of any point in the imaging area of the plane wave spatial compound imaging algorithm.

[0004] Traditional ultrafast ultrasound image reconstruction mainly focuses on the acceleration method using a series of hardware such as field-programmable gate array (FPGA), graphics processing unit (GPU), etc. Although a single FPGA chip or GPU can achieve relatively good performance, it is difficult to meet the needs of future high-resolution image reconstruction, has low parallelism, and cannot achieve high energy-efficient acceleration effect, thus having many limitations.

[0005] A common problem is how to store and access large-scale ultrafast ultrasound images. With the increase of the number of channels, imaging frame rate or single sampling time length of ultrafast ultrasound images, due to the limited parallel processing capability of CPU, it is impossible to perform real-time high-frame-rate ultrafast ultrasound image reconstruction with high channel number. The beamforming rate of the traditional CPU-based ultrafast ultrasound equipment is only 133 MSPS, and the sampling data must be stored locally for offline beamforming. In addition, the existing ultrafast ultrasound equipment has bottlenecks in processing speed, data storage and real-time processing capability. With the increase of image resolution, channel number or imaging frame rate, the required computing resources will exceed the operation performance of the common FPGA architecture in the existing fast imaging system, and it is impossible to meet the extremely high requirement of real-time for high-channel-number ultrafast ultrasound imaging.

[0006] In summary, it is urgent to build a high-speed computing platform for ultrafast ultrasound, develop a dedicated processing system with real-time image reconstruction function, and break through the limitation of the on-chip memory of the current FPGA on the size of the reconstructable ultrafast ultrasound image to support on-chip real-time image reconstruction. SUMMARY

[0007] The application provides a real-time ultrafast ultrasound image reconstruction system and method based on FPGA, which provides a real-time ultrafast ultrasound image reconstruction system and method for the field of medical ultrafast ultrasound signal acquisition and processing, and is used for realizing real-time medical ultrafast ultrasound imaging with high sampling rate, high channel number, strong scalability and fast processing speed.

[0008] A real-time ultrafast ultrasound image reconstruction system based on FPGA, comprising: An analog front-end acquisition chip, an FPGA and an upper computer; the FPGA sends a control command to the analog front-end acquisition chip, the analog front-end acquisition chip collects multi-channel ultrasound data and sends them to the FPGA in response to the control command, the FPGA performs data preprocessing, beamforming calculation and image post-processing on the multi-channel ultrasound data, analyzes and responds to the received configuration command and external trigger signal, uploads the ultrasound image sampling and processing results to the upper computer and displays them in real time.

[0009] In one embodiment, the FPGA comprises an analog front-end sampling module, a DDR arbiter, a parameter calculation unit, a data preprocessing module, a beamforming calculation module, an image post-processing module, an optical module transceiver module, a command analysis module, a control core module and an analog front-end configuration module. The analog front-end sampling module is used for receiving and decoding the multi-channel ultrasound data of the analog front-end acquisition chip, and outputting the decoded multi-channel ultrasound data to the DDR arbiter. The DDR arbitrator is configured to receive multi-channel ultrasonic data from the analog front-end configuration module, write the multi-channel ultrasonic data into the DDR memory, receive timing parameters provided by the parameter calculation unit, and store the timing parameters in the DDR memory; The parameter calculation unit is configured to receive configuration parameters scheduled by the control core module, calculate total delay, and store the total delay in the DDR memory for real-time lookup and use by the beamforming calculation module; The data preprocessing module is configured to read the multi-channel ultrasonic data stored in the DDR memory, perform multi-channel ultrasonic data averaging and filtering processing, and output the averaged and filtered multi-channel ultrasonic data; The beamforming calculation module is configured to receive the averaged and filtered multi-channel ultrasonic data, perform beamforming calculation in combination with the calculated total delay, and generate a preliminary ultrafast ultrasound image in real time; The image post-processing module is configured to perform image post-processing calculation on the preliminary ultrafast ultrasound image, and output a processed ultrafast ultrasound image; The optical module transceiver module is configured to receive the processed ultrafast ultrasound image, encapsulate the processed ultrafast ultrasound image into a protocol frame, upload the protocol frame to the host computer, receive control commands and configuration parameters sent by the host computer, and forward the control commands and configuration parameters to the command analysis module; The command analysis module is configured to receive and analyze the control commands and configuration parameters forwarded by the optical module transceiver module, verify the validity of the control commands and configuration parameters, and forward the control commands and configuration parameters to the control core module; The control core module is configured to receive the control commands and configuration parameters forwarded by the command analysis module, configure parameters of each module, schedule and manage a business logic execution flow of each module, and respond to and synchronize with external trigger signals; The analog front-end configuration module is configured to configure an analog front-end acquisition chip, receive external trigger signals, synchronization clocks, and delay parameters, and control data acquisition by receiving control commands output by the control core module.

[0010] In one embodiment, the FPGA-based real-time ultrafast ultrasound image reconstruction system further includes an inter-board high-speed bus transceiver module. The inter-board high-speed bus transceiver module controls output of ultrafast ultrasound image data in the image post-processing module according to a system cascading state, and specifically includes: If the cascading is not enabled, the processed ultrafast ultrasound image output by the image post-processing module is sent to the host computer; If the cascading is enabled, the processed ultrafast ultrasound image output by the image post-processing module is integrated with an ultrafast ultrasound image sent by a previous FPGA, and the integrated ultrafast ultrasound image is sent to the host computer, or the processed ultrafast ultrasound image is transmitted to a next FPGA to support multi-FPGA cascading communication and realize data exchange with other FPGAs in the cascade.

[0011] In one embodiment, the analog front-end acquisition chip can acquire 16 channels of ultrafast ultrasound data, and the system uses 8 analog front-end acquisition chips, each of which acquires 16 channels of ultrasound data and completes analog-to-digital conversion, each channel including a voltage-controlled amplifier, a synchronous sampling analog-to-digital converter, and a continuous wave mixer.

[0012] In one embodiment, the analog front-end acquisition chip supports a sampling precision of 12 bits and a sampling rate of 80 MSPS per channel. Or, a sampling precision of 14 bits and a sampling rate of 65 MSPS.

[0013] In one embodiment, the analog front-end acquisition chip receives configuration commands from the FPGA through the SPI interface and transmits sampling data to the FPGA through the LVDS interface.

[0014] In one embodiment, the delay of each processing stage in the FPGA is controlled within 250 μs.

[0015] In one embodiment, the parameter calculation unit calculates the total delay and stores it in the DDR memory, including: after the parameter calculation unit receives the array element coordinates and pixel point coordinates of the ultrasound image sent by the control core module, the transmission delay and the reception delay are calculated respectively combined with the preset plane wave transmission angle, and the transmission delay and the reception delay are calculated respectively combined with the preset plane wave transmission angle. The total delay is stored in the DDR memory after being summarized. The transmission delay is used to calculate the time delay corresponding to the distance from the virtual wave source to each ultrafast ultrasound image imaging point for a specific angle of the plane wave transmission angle. The reception delay is used to calculate the time delay corresponding to the distance from the ultrafast ultrasound image imaging point to each receiving array element for each ultrafast ultrasound image imaging point.

[0016] In one embodiment, the data preprocessing module performs multi-channel ultrasound data averaging and filtering processing, including: The multi-channel ultrasound data averaging is used to accumulate and sum the multi-channel ultrasound data within a certain time and then divide by the number of samples, and the calculated average value is used as valid data. The filtering processing is used to implement band-pass filtering using a digital filter to receive frequency components near the center frequency of the ultrasound probe in the received ultrasound signal, while removing electronic noise and high-frequency noise.

[0017] In one embodiment, the beamforming calculation module performs delay-and-sum operation based on the plane wave coherent imaging algorithm, specifically including: receive average and filtered multi-channel ultrasonic data output from the data preprocessing module; For each imaging point in the average and filtered multi-channel ultrasonic data, the total delay corresponding to each channel is found from the DDR memory according to the corresponding coordinate parameters; The sampling data of the corresponding channel is delay corrected according to the total delay, and the pixel value of the ultrasonic image imaging point is generated by summing the delay corrected sampling data of all channels; Wherein, the beamforming calculation module simultaneously processes multiple ultrasonic image imaging points in a spatial parallel manner, and simultaneously processes data of multiple channels in the calculation of each ultrasonic image imaging point in a channel parallel manner.

[0018] In an embodiment, in the image post-processing module, the image post-processing calculation of the preliminary ultrafast ultrasonic image is performed, and the processed ultrafast ultrasonic image is output, including: The Hilbert transform is used to obtain the analytical signal of the preliminary ultrafast ultrasonic image output by the beamforming calculation module, and the envelope signal is obtained by taking the modulus operation; The envelope signal data is logarithmically compressed based on a preset lookup table to convert linear values to logarithmic values, realize nonlinear compression of the dynamic range of the ultrafast ultrasonic image, and output the processed ultrafast ultrasonic image.

[0019] On the other hand, the application also provides a real-time ultrafast ultrasonic image reconstruction method based on FPGA, which adopts the real-time ultrafast ultrasonic image reconstruction system, and the real-time ultrafast ultrasonic image reconstruction method includes the following steps: In the starting stage, the delay sum operation is performed by using the plane wave coherent imaging algorithm according to the coordinate parameters and the transmission parameters sent by the upper computer; The processes of ultrafast ultrasonic image data acquisition, data preprocessing, beamforming calculation and image post-processing are completed in parallel, real-time conversion from the original ultrasonic image to the ultrafast ultrasonic image is realized, and the ultrafast ultrasonic image is output.

[0020] Compared with the prior art, the application has the following beneficial effects: (1) The real-time superfast ultrasonic image reconstruction system and method based on FPGA provided by the application can realize real-time acquisition of 128-channel superfast ultrasonic signals and medical superfast ultrasonic image reconstruction, support device cascading, the peak total sampling rate of a single board (128 channels) can reach 10 GSPS, the peak data transmission rate can reach 120 Gbps, and the number of cascaded channels can reach 512 channels; the system has fast data processing speed, high bandwidth, many channels and scalability, the cascading design takes into account the scalability and device size, the ultrasonic image reconstruction can be performed on the FPGA in real time, compared with the traditional CPU-based image reconstruction system, the reconstruction rate is greatly improved, and the FPGA can also complete part of the image post-processing algorithm, so that the operation efficiency of the system is improved compared with the traditional image reconstruction mode by the host computer.

[0021] (2) The FPGA provided by the application adopts pipeline design, utilizes the parallel processing capability of the FPGA to perform data acquisition, data preprocessing, beam forming calculation and image post-processing, each stage is controlled within 250 mu s, each frame of medical superfast ultrasonic image is processed in parallel, and the frame rate of the medical superfast ultrasonic image reaches 4000 fps. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 The structure overview diagram of the real-time superfast ultrasonic image reconstruction system based on FPGA provided by the embodiment of the application is shown.

[0023] Figure 2 The principle schematic diagram of the real-time superfast ultrasonic image reconstruction system based on FPGA provided by the embodiment of the application is shown.

[0024] Figure 3 The use flowchart of the real-time superfast ultrasonic image reconstruction system based on FPGA provided by the embodiment of the application is shown.

[0025] Figure 4 The flowchart of the real-time superfast ultrasonic image reconstruction method based on FPGA provided by the embodiment of the application is shown.

[0026] Figure 5 The specific flowchart of the real-time superfast ultrasonic image reconstruction method based on FPGA provided by the embodiment of the application is shown. DETAILED DESCRIPTION

[0027] The application will be further described in detail below with reference to the drawings and embodiments, and it should be pointed out that the following embodiments are intended to facilitate the understanding of the application and do not limit the application in any way.

[0028] In order to realize data acquisition and processing in medical superfast ultrasonic imaging and support real-time image reconstruction on a chip, a real-time superfast ultrasonic image reconstruction system based on FPGA is provided, as shown in Figure 1As shown, the real-time ultrafast ultrasound image reconstruction system comprises an analog front-end acquisition chip, an FPGA, and an upper computer, can realize 128-channel ultrafast ultrasound data acquisition and processing, beamforming calculation, and image post-processing, the device can be cascaded, supports expansion to 512 channels or even more, adopts a pipeline architecture design image reconstruction process, the single-frame ultrafast ultrasound image calculation delay is controlled within 250 μs, and real-time ultrafast ultrasound imaging of 4000 frames per second can be realized.

[0029] The analog front-end acquisition chip can process up to sixteen channels of ultrafast ultrasound signals simultaneously, and can perform synchronous acquisition operations on the signals of these channels. Eight analog front-end acquisition chips are used in a single system to realize 128-channel ultrafast ultrasound image data acquisition. Each channel contains a voltage-controlled amplifier, a synchronous sampling analog-to-digital converter, and a continuous wave mixer. The chip receives control configuration instruction information from the FPGA through the SPI interface and transmits sampling data to the FPGA through the LVDS interface.

[0030] The FPGA undertakes core processing tasks, on the one hand, sends necessary control command signals to the analog front-end acquisition chip, and on the other hand, receives raw ultrasound image sampling data transmitted by the analog front-end chip. The FPGA internally implements a medical ultrafast ultrasound image data real-time processing flow, first performs preliminary preprocessing operations on the received raw medical ultrafast ultrasound image sampling data, then performs beamforming calculation based on a multi-angle coherent delay-and-sum algorithm, calculates the required imaging data, and performs image post-processing. The FPGA will complete specific protocol packaging of these image data and prepare to send them. Meanwhile, the FPGA also needs to realize the reception and processing of control commands, configuration commands, and external trigger signals, inter-board cascading communication, and sampling and calculation result uploading.

[0031] The upper computer completes command and parameter issuing, and displays real-time ultrafast ultrasound images from the FPGA, specifically: the upper computer issues configuration commands to configure the working state of the FPGA, issues control signals to control the working mode of the FPGA, and in addition, receives image data uploaded by the FPGA through an optical module and displays them in real time.

[0032] As Figure 2 As shown in the principle diagram of the FPGA-based ultrafast ultrasound real-time image reconstruction system, the FPGA comprises an analog front-end sampling module, a DDR arbiter, a parameter calculation unit, a data preprocessing module, a beamforming calculation module, an image post-processing module, an optical module transceiver module, a command analysis module, a control core module, and an analog front-end configuration module. Specifically as follows: The analog front-end sampling module receives digital sampling signals transmitted by an analog front-end acquisition chip through an LVDS interface. In the analog front-end sampling module, an LVDS input buffer primitive (such as IBUFDS) of an FPGA is used to receive differential signals and convert them into internal single-ended digital signals. The sampling data is decoded and received, and after the 128-channel superfast ultrasonic signals are sorted and merged, the output is output through a FIFO interface for reading and writing into a DDR memory by a DDR arbiter.

[0033] The DDR arbiter, as a core scheduling unit of a system data stream, is mainly responsible for coordinating data access operations of the DDR memory. Its functions include: controlling the DDR memory to obtain multi-channel ultrasonic data of an original ultrasonic image from the analog front-end sampling module, and transmitting the multi-channel ultrasonic data to a data preprocessing module for subsequent processing. Meanwhile, the DDR arbiter is also responsible for receiving generated timing parameter configuration information from a parameter calculation unit, and supporting the reception and update of related configuration files through an external interface.

[0034] The parameter calculation unit performs key calculation tasks in the system initialization and startup phase. Specifically, the parameter calculation unit first obtains the required element coordinates and pixel point coordinates of the ultrasonic image from the control core module, and then completes the accurate timing parameter calculation process based on these input data, calculates the transmission delay and the reception delay respectively in combination with the preset plane wave transmission angle, and stores the transmission delay and the reception delay as the total delay in the DDR memory after being summarized, thereby providing necessary configuration parameters for subsequent data processing links. The transmission delay is used to calculate the time delay corresponding to the distance from a virtual wave source to each superfast ultrasonic image imaging point for a specific angle of the plane wave transmission angle. The reception delay is used to calculate the time delay corresponding to the distance from each superfast ultrasonic image imaging point to each receiving element.

[0035] The data preprocessing module reads the original multi-channel ultrasonic data from the DDR memory and executes specific data processing algorithms. Its main operations include average calculation processing and band-pass filtering of continuous multi-frame sampling data, and finally outputs the processed frame sampling data to the downstream module for further calculation and analysis.

[0036] Among them, frame sampling average is to calculate the average value as valid data by accumulating and summing continuous multi-frame sampling data within a certain time and then dividing by the number of samples; filtering processing is to realize band-pass filtering by using a digital filter, receive frequency components near the center frequency of the ultrasonic probe in the received ultrasonic signal, and remove electronic noise and high-frequency noise at the same time, and output the multi-channel ultrasonic data after averaging and filtering.

[0037] The beamforming calculation module is the calculation core of the imaging process, responsible for receiving the average and filtered multi-channel ultrasonic data from the data preprocessing module, and directly obtaining the calculation parameters from the DDR memory. Based on these input data, the module performs the beamforming algorithm calculation required for ultrafast ultrasonic imaging, ultimately generating preliminary ultrafast ultrasonic image data, providing a basis for subsequent image optimization processing. Specifically, the beamforming calculation module receives the average and filtered multi-channel ultrasonic data from the data preprocessing module; for each point in the average and filtered multi-channel ultrasonic data, the corresponding total delay for each channel is found from the DDR memory according to the corresponding coordinate parameters; the sampling data of the corresponding channel is delay-corrected according to the total delay, and the data of all channels after delay correction is summed to generate the pixel value of the ultrasonic image imaging point; wherein the beamforming calculation module simultaneously processes multiple ultrasonic image imaging points in a spatial parallel manner, and simultaneously processes the data of multiple channels in the calculation of each ultrasonic image imaging point in a channel parallel manner, to generate preliminary ultrafast ultrasonic images in real time.

[0038] The image post-processing module is responsible for image optimization processing, performs Hilbert transform and logarithmic compression on image data, and can also perform various image post-processing algorithms including correlation calculation as needed. By enhancing and optimizing the input image data, the processed image data meeting the system requirements is finally output to meet the high-quality imaging requirements. Specifically, the image post-processing module performs Hilbert transform on the preliminary ultrafast ultrasonic image data generated in real time to obtain the analytic signal, and obtains the envelope signal through modulo operation; The envelope signal data is logarithmically compressed based on a pre-set lookup table to convert linear values to logarithmic values, achieving nonlinear compression of the dynamic range of the ultrasonic image; The ultrafast ultrasonic image data and the ultrafast ultrasonic image data of the upstream FPGA are summarized and output to obtain fused ultrafast ultrasonic image data, and in addition, the image post-processing module can also be responsible for other image post-processing work as needed.

[0039] The image data is encapsulated by the optical module transceiver module and uploaded to the host computer for real-time display. The image data includes frame number, reserved bits, length and data. Specifically, the frame number data bit width length is 32 bits, the reserved bit data bit width length is 32 bits, the length data bit width length is 32 bits, and then the pixel data bit width length is N*32 bits. Specifically: the optical module transceiver module receives the processed ultrafast ultrasound image and encapsulates it into a protocol frame, and uploads the protocol frame to the host computer. At the same time, the host computer sends control commands and coordinate parameter information to the optical module transceiver module through the network. The optical module transceiver module receives data stream direction analysis, sends data stream balance, completes optical module state function configuration, realizes optical module data transceiver interface control and data transmission, and completes 40 Gbps high-speed data communication.

[0040] The command analysis module is the instruction processing center of the system, and is responsible for analyzing and responding to the received external commands. Its workflow includes obtaining control commands and coordinate parameter information from the optical module transceiver module, decoding the commands, verifying the validity of the instructions, and generating corresponding system response actions according to the analysis results, to ensure that the system can correctly execute various control instructions.

[0041] The control core module is the central control unit of the entire system, and undertakes the core functions of system scheduling and process management. Its main responsibilities include coordinating and managing the business logic execution process of each functional module in the system, including but not limited to: issuing corresponding control instructions according to the network commands of the host computer, ensuring that the data processing process is executed correctly in the predetermined order, and configuring the analog front end and updating the calculation parameters of the parameter calculation unit according to the received information.

[0042] The analog front end configuration module can upload the current analog front end acquisition chip state or update its state information, complete the read-write drive of the analog front end acquisition chip internal register interface, and provide the analog front end acquisition chip configuration module. In addition, the analog front end configuration module also receives the sampling synchronization clock and external trigger signal, receives the delay parameter, and controls the data acquisition.

[0043] As Figure 3As shown, it is the working flow chart of the FPGA-based real-time ultrafast ultrasound image reconstruction device. The FPGA first collects the original medical ultrasound image signal, and then the sampled data successively passes through data preprocessing, beam forming calculation, image post-processing, and finally outputs to the host computer. In addition, if cascading is required, the ultrasound image data of the previous cascade FPGA is received through the inter-board high-speed bus and directly input to the image post-processing module of the FPGA; during the startup process, the calculation parameters are transmitted to the parameter calculation unit by the host computer for parameter calculation. Among them, the inter-board high-speed bus transceiver module receives the cascade device data stream, analyzes the data stream direction, and balances the data stream transmission, realizes the control and data transmission of the single inter-board high-speed bus transceiver interface, completes the high-speed data communication of 40Gbps, which specifically includes: If the cascade is not enabled, the processed ultrafast ultrasound image output by the image post-processing module is sent to the host computer; If the cascade is enabled, the processed ultrafast ultrasound image output by the image post-processing module is integrated with the ultrafast ultrasound image sent by the previous FPGA, and the integrated ultrafast ultrasound image is sent to the host computer, or the processed ultrafast ultrasound image is transmitted to the next FPGA, supporting multi-FPGA cascade communication and realizing data exchange with other FPGAs in the cascade.

[0044] On the other hand, the application also provides a real-time ultrafast ultrasound image reconstruction method based on FPGA, which adopts the real-time ultrafast ultrasound image reconstruction system, and the real-time ultrafast ultrasound image reconstruction method, as shown in Figure 4 includes the following steps: In the startup phase, the plane wave coherent imaging algorithm is used to perform delay sum operation according to the coordinate parameters and transmission parameters sent by the host computer; The processes of ultrafast ultrasound image data acquisition, data preprocessing, beam forming calculation and image post-processing are completed in parallel, realizing real-time conversion from original ultrasound image to ultrafast ultrasound image and outputting the ultrafast ultrasound image.

[0045] In the embodiment, as shown in Figure 5 The flow of the real-time ultrafast ultrasound image reconstruction method includes four stages of ultrafast ultrasound data acquisition, data preprocessing, beam forming calculation and image post-processing, and the pipeline design method is adopted. When the current image is processed, the beam forming calculation of the next frame image can be performed in parallel; when the current ultrasound data is processed, the data preprocessing of the next frame image ultrasound raw data can be performed in parallel; when the current ultrasound raw data is processed, the raw ultrasound data acquisition of the next frame image can be performed in parallel, and so on. The calculation delay of each stage is 250us, and a frame of image is output every 250us, completing 4000 frames of real-time ultrafast ultrasound and providing a real-time ultrafast ultrasound image reconstruction scheme with high frame rate and high data bandwidth.

[0046] It should be noted that the FPGA-based real-time ultrafast ultrasound image reconstruction system and method provided in the above embodiments should be illustrated by the above division of functional modules when performing real-time ultrafast ultrasound image reconstruction. The above functions can be completed by different functional modules according to needs, that is, the internal structure of the terminal or server is divided into different functional modules to complete all or part of the functions described above. In addition, the FPGA-based real-time ultrafast ultrasound image reconstruction system and the FPGA-based real-time ultrafast ultrasound image reconstruction method provided in the above embodiments belong to the same concept, and the specific implementation process is detailed in the FPGA-based real-time ultrafast ultrasound image reconstruction system embodiment, which will not be described here.

[0047] The above embodiments have described the technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only a specific embodiment of the present application and is not used to limit the present application. Any modification, supplement and equivalent replacement made within the principle range of the present application should be included in the protection range of the present application.

Claims

1. A real-time ultrafast ultrasound image reconstruction system based on FPGA, characterized in that, The real-time ultrafast ultrasound image reconstruction system comprises an analog front-end acquisition chip, an FPGA and a host computer; the FPGA sends a control command to the analog front-end acquisition chip; the analog front-end acquisition chip collects multi-channel ultrasound data and sends the multi-channel ultrasound data to the FPGA in response to the control command; the FPGA performs data preprocessing, beam forming calculation and image post-processing on the multi-channel ultrasound data, and analyzes and responds to the received configuration command and external trigger signal, and uploads the ultrasound image sampling and processing result to the host computer and displays the ultrasound image sampling and processing result in real time.

2. The FPGA-based real-time ultrafast ultrasound image reconstruction system of claim 1, wherein, The FPGA comprises an analog front-end sampling module, a DDR arbitrator, a parameter calculation unit, a data preprocessing module, a beam forming calculation module, an image post-processing module, an optical module transceiver module, a command analysis module, a control core module and an analog front-end configuration module. The analog front-end sampling module is configured to receive and decode the multi-channel ultrasound data of the analog front-end acquisition chip, and output the decoded multi-channel ultrasound data to the DDR arbitrator. The DDR arbitrator is configured to receive the multi-channel ultrasound data from the analog front-end configuration module and write the multi-channel ultrasound data into a DDR memory, and receive timing parameters provided by the parameter calculation unit and store the timing parameters in the DDR memory. The parameter calculation unit is configured to receive configuration parameters dispatched by the control core module, calculate a total delay and store the total delay in the DDR memory for real-time lookup and use by the beam forming calculation module. The data preprocessing module is configured to read the multi-channel ultrasound data stored in the DDR memory, perform multi-channel ultrasound data averaging and filtering processing, and output the averaged and filtered multi-channel ultrasound data. The beam forming calculation module is configured to receive the averaged and filtered multi-channel ultrasound data, perform beam forming calculation in combination with the calculated total delay, and generate a preliminary ultrafast ultrasound image in real time. The image post-processing module is configured to perform image post-processing calculation on the preliminary ultrafast ultrasound image, and output a processed ultrafast ultrasound image. The optical module transceiver module is configured to receive the processed ultrafast ultrasound image, encapsulate the processed ultrafast ultrasound image into a protocol frame, upload the protocol frame to the host computer, receive a control command and configuration parameters sent by the host computer and forward the control command and configuration parameters to the command analysis module. The command analysis module is configured to receive and analyze the control command and configuration parameters forwarded by the optical module transceiver module, verify the validity of the control command and configuration parameters, and forward the control command and configuration parameters to the control core module. The control core module is configured to receive the control command and configuration parameters forwarded by the command analysis module, configure parameters of each module, dispatch and manage a business logic execution flow of each module, and respond to and synchronize an external trigger signal. The analog front-end configuration module is configured to configure the analog front-end acquisition chip, receive an external trigger signal, a synchronization clock and a delay parameter, and control data acquisition by receiving a control command output by the control core module.

3. The FPGA-based real-time ultrafast ultrasound image reconstruction system of claim 2, wherein, The real-time ultrafast ultrasound image reconstruction system based on the FPGA further comprises an inter-board high-speed bus transceiver module; the inter-board high-speed bus transceiver module controls output of the ultrafast ultrasound image data in the image post-processing module according to a system cascade state, and specifically comprises: If the cascade is not enabled, the processed ultrafast ultrasound image output by the image post-processing module is sent to the host computer; If the cascade is enabled, the processed ultrafast ultrasound image output by the image post-processing module is integrated with the ultrafast ultrasound image sent by the previous-stage FPGA, and the integrated ultrafast ultrasound image is sent to the host computer; or the processed ultrafast ultrasound image is transmitted to the next-stage FPGA to support multi-FPGA cascade communication and realize data exchange with other FPGAs in the cascade.

4. The FPGA-based real-time ultrafast ultrasound image reconstruction system of claim 1, wherein, In the analog front-end acquisition chip, each channel supports 12-bit sampling precision and 80 MSPS sampling rate of ultrasound data. Alternatively, the sampling precision is 14 bits, and the sampling rate is 65 MSPS of ultrasound data.

5. The FPGA-based real-time ultrafast ultrasound image reconstruction system of claim 4, wherein, The analog front-end acquisition chip receives the configuration command of the FPGA through the SPI interface and transmits the sampling data to the FPGA through the LVDS interface.

6. The FPGA-based real-time ultrafast ultrasound image reconstruction system of claim 2, wherein, In the parameter calculation unit, the total delay is calculated and stored in the DDR memory, which includes: after the parameter calculation unit receives the array element coordinates and pixel point coordinates of the ultrasound image sent by the control core module, the transmission delay and the reception delay are calculated respectively combined with the preset plane wave transmission angle, and the transmission delay and the reception delay are summarized as the total delay and stored in the DDR memory. The transmission delay is used to calculate the time delay corresponding to the distance from the virtual wave source to each ultrafast ultrasound image imaging point for a specific angle of the plane wave transmission angle. The reception delay is used to calculate the time delay corresponding to the distance from the ultrafast ultrasound image imaging point to each receiving array element.

7. The FPGA-based real-time ultrafast ultrasound image reconstruction system of claim 2, wherein, In the data preprocessing module, the multi-channel ultrasound data average and filtering processing includes: The multi-channel ultrasound data average is used to accumulate and sum the multi-channel ultrasound data within a certain time and then divide by the number of samples, and the calculated average value is used as valid data; The filtering processing is used to realize band-pass filtering by using a digital filter to receive the frequency components near the center frequency of the ultrasonic probe in the received ultrasonic signal, while removing electronic noise and high-frequency noise.

8. The FPGA-based real-time ultrafast ultrasound image reconstruction system of claim 7, wherein, In the beamforming calculation module, the beamforming calculation is based on the plane wave coherent imaging algorithm to perform delay summation operation, specifically including: Receiving the received average and filtered multi-channel ultrasound data output from the data preprocessing module; For each imaging point in the average and filtered multi-channel ultrasound data, the total delay corresponding to each channel is found from the DDR memory according to the corresponding coordinate parameters; According to the total delay, the sampling data of the corresponding channel is delay corrected, and the sampling data of all channels after delay correction is summed to generate the pixel value of the ultrasound image imaging point; The beamforming calculation module simultaneously processes multiple ultrasound image imaging points in a spatial parallel manner and simultaneously processes the data of multiple channels in the calculation of each ultrasound image imaging point in a channel parallel manner.

9. The FPGA-based real-time ultrafast ultrasound image reconstruction system of claim 8, wherein, In the image post-processing module, the image post-processing calculation of the preliminary ultrafast ultrasound image includes: The preliminary ultrafast ultrasound image output by the beam forming calculation module is subjected to Hilbert transform to obtain an analytic signal, and an envelope signal is obtained through a modulo operation; The envelope signal data is subjected to logarithmic compression based on a preset lookup table, linear values are converted into logarithmic values, the dynamic range of the ultrafast ultrasound image is subjected to nonlinear compression, and a processed ultrafast ultrasound image is output.

10. A real-time FPGA-based ultrafast ultrasound image reconstruction method, characterized in that, The real-time ultrafast ultrasound image reconstruction system and the real-time ultrafast ultrasound image reconstruction method of any one of claims 1-9 comprise the following steps: In the starting stage, a delay-and-sum operation is performed according to the coordinate parameters and the transmission parameters sent by the upper computer using a plane wave coherent imaging algorithm; The processes of ultrafast ultrasound image data acquisition, data preprocessing, beam forming calculation and image post-processing are completed in parallel, real-time conversion from an original ultrasound image to an ultrafast ultrasound image is realized, and an ultrafast ultrasound image is output.

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