Driving circuit, driving method, and display device

Abstract

This application discloses a driving circuit, driving method, and display device. The driving circuit includes N gate driving units, a charge rate detection circuit, and a driving chip. Each gate driving unit outputs a gate driving signal to a gate line. The driving chip is connected to the N gate driving units via a clock signal line. The charge rate detection circuit is connected to the input terminal of the gate driving unit corresponding to the first gate line and the output terminal of the gate driving unit corresponding to the last gate line. The charge rate detection circuit generates a corresponding charging compensation control signal based on the voltage signal at the input terminal of the gate driving unit corresponding to the first gate line and the voltage signal at the output terminal of the gate driving unit corresponding to the last gate line. The driving chip controls the timing of the gate driving units generating the corresponding gate driving signals based on the charging compensation control signal, thereby controlling the charging duration of pixels in the display panel and preventing insufficient charging at high refresh rates.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit, driving method and display device. Background Technology

[0002] As LCD panel sizes increase, the charging difference between the near and far ends becomes more pronounced when the data cable charges the panel. The portion of the panel closer to the data cable driver end charges better and has higher brightness, while the portion farther from the driver end charges poorer and has lower brightness, resulting in inconsistent display performance.

[0003] Currently, due to the inherent disadvantages of a-Si materials, such as low electron mobility and weak driving capability, a-Si LCD (liquid crystal display) products on the market perform poorly in high refresh rate applications. This is mainly reflected in the severely insufficient charging rate at high refresh rates. Therefore, in order to ensure that the pixel charging efficiency meets the requirements of high refresh rates, it is necessary to improve the characteristics of thin-film transistor (TFT) devices, increase the on-state current of TFT devices, and enable TFTs to open more fully at low temperatures, thereby improving panel charging efficiency. Alternatively, the number of CLKs in the Gate Driven on Array (GOA) circuit can be increased to reduce the load on each clock signal CLK line, allowing the GOA circuit to have better charging efficiency. However, improving the characteristics of thin-film transistor TFT devices is usually a complex process, and increasing the number of clock signal lines will increase the edge width of the display panel and increase wiring costs. Summary of the Invention

[0004] The purpose of this application is to provide a driving circuit, driving method, and display device that can perform charging compensation on pixels based on the charging state of the gate driving unit by detecting the charging state of the gate driving unit.

[0005] This application discloses a driving circuit for driving a display panel. The driving circuit includes N gate driving units, a charge rate detection circuit, and a driving chip. The gate driving units output gate driving signals to gate lines. The driving chip is connected to the N gate driving units via clock signal lines. The charge rate detection circuit is connected to the input terminal of the gate driving unit corresponding to the first gate line and the output terminal of the gate driving unit corresponding to the last gate line. N is a natural number greater than 1. The charge rate detection circuit generates corresponding charging compensation control signals based on the voltage signals at the input terminals of the gate driving units corresponding to the first gate line and the output terminals of the gate driving units corresponding to the last gate line. The driving chip controls the gate driving units to generate corresponding gate driving signal timings based on the charging compensation control signals, thereby controlling the charging duration of pixels in the display panel.

[0006] Optionally, the charging rate detection circuit includes a voltage divider circuit, a first voltage generation circuit, a second voltage generation circuit, and a voltage comparison circuit. The voltage divider circuit divides the voltage at the output terminal of the gate driving unit corresponding to the last gate line and outputs the divided voltage to the voltage generation circuit. The first voltage generation circuit generates a first voltage based on the divided voltage and the output voltage of the gate driving unit corresponding to the last gate line. The second voltage generation circuit generates a second voltage based on the input voltage of the gate driving unit corresponding to the first gate line and the output voltage of the gate driving unit corresponding to the last gate line. The voltage comparison circuit generates a charging state control voltage based on the first and second voltages. The driving chip controls the gate driving unit to generate the corresponding gate driving signal timing based on the magnitude of the charging state control voltage, thereby controlling the charging duration of the pixels in the display panel.

[0007] Optionally, the voltage divider circuit includes a first resistor, a second resistor, a third resistor, and a fourth resistor connected in series. The input terminal of the first resistor is connected to the output terminal of the gate driving unit corresponding to the last gate line, and the output terminal of the fourth resistor is grounded. The first voltage generation circuit includes a first non-inverting subtractor, a second non-inverting subtractor, and a third non-inverting subtractor. The negative input terminal of the first non-inverting subtractor is connected between the first and second resistors, and the positive input terminal is connected to the output terminal of the gate driving unit corresponding to the last gate line. The negative input terminal of the second non-inverting subtractor is connected between the second and third resistors, and the positive input terminal is connected to the output terminal of the gate driving unit corresponding to the last gate line. The negative input terminal of the third non-inverting subtractor is connected between the third and fourth resistors, and the positive input terminal is connected to the output terminal of the gate driving unit corresponding to the last gate line. The output terminal of the driving unit; the second voltage generation circuit includes a fourth in-phase subtractor, the negative input terminal of which is connected to the input terminal of the gate driving unit corresponding to the first gate line, and the positive input terminal of which is connected to the output terminal of the gate driving unit corresponding to the last gate line; the voltage comparison circuit includes a first voltage comparator, a second voltage comparator, and a third voltage comparator, the negative input terminal of which is connected to the output terminal of the fourth in-phase subtractor, and the positive input terminal of which is connected to the output terminal of the first in-phase subtractor; the negative input terminal of which is connected to the output terminal of the fourth in-phase subtractor, and the positive input terminal of which is connected to the output terminal of the second in-phase subtractor; the negative input terminal of which is connected to the output terminal of the fourth in-phase subtractor, and the positive input terminal of which is connected to the output terminal of the third in-phase subtractor.

[0008] Optionally, the multiple gate driving units are divided into at least two gate driving unit groups. The driving circuit further includes a partition control circuit, which is configured between the gate driving unit groups. The first gate driving unit of the current gate driving unit group is connected to the driving chip to receive a first frame start signal. The first input terminal of the partition control circuit is connected to the driving chip to receive a second frame start signal, and the second input terminal is connected to the charge rate detection circuit to receive a charge compensation control signal. The output terminal is connected to the input terminal of the first gate driving unit of the next gate driving unit group. The first frame start signal and the second frame start signal operate independently. The partition control circuit controls the second frame start signal to be input to the input terminal of the first gate driving unit of the next gate driving unit group based on the charge compensation control signal.

[0009] Optionally, the partition control circuit includes a first transistor and a first control switch. The input terminal of the first transistor is connected to the first input terminal of the partition control circuit to receive a frame start signal. The output terminal of the first transistor is connected to the input terminal of the first gate driving unit of the next gate driving unit group. The control terminal of the first transistor is connected to the second input terminal of the partition control circuit to receive a charge compensation control signal. The input terminal of the first control switch is connected to the input terminal of the last gate driving unit of the current gate driving unit group to receive the gate driving signal of the gate driving unit. The output terminal of the first control switch is connected to the input terminal of the first gate driving unit of the next gate driving unit group. The control terminal of the first control switch is connected to the second input terminal of the partition control circuit to receive a charge compensation control signal.

[0010] Optionally, the driving circuit further includes a display scene detection module and a frame compensation module. The display scene detection module detects the display scene of the display panel, and the frame compensation module inserts a preset number of compensation frames into the normal display frames based on the display scene, thereby changing the timing of the gate driving signal and controlling the charging time of the pixels in the display panel.

[0011] Optionally, the driving circuit further includes a temperature detection module. The driving chip stores a charging compensation mapping table, which stores the temperature and the corresponding charging compensation control signal. The temperature detection module detects the temperature of the display panel. The driving chip obtains the corresponding charging compensation control signal based on the temperature of the display panel detected by the temperature detection module and the charging compensation mapping table. Based on the charging compensation control signal, the driving chip controls the gate driving unit to generate the corresponding gate driving signal timing, thereby controlling the charging duration of the pixels in the display panel.

[0012] This application also discloses a driving method for using the driving circuit described in any of the above to drive a display panel, the driving method comprising:

[0013] The voltage signal at the input terminal of the gate driving unit corresponding to the first gate line and the voltage signal at the output terminal of the gate driving unit corresponding to the last gate line are obtained to generate the corresponding charging compensation control signal; and

[0014] Based on the charging compensation control signal, the gate driving unit is controlled to generate the corresponding gate driving signal timing, thereby controlling the charging duration of the pixels in the display panel.

[0015] Optionally, the step of controlling the charging duration of pixels in the display panel by controlling the gate driving unit to generate corresponding gate driving signal timing based on the charging compensation control signal includes:

[0016] Detect the temperature of the display panel;

[0017] Detect the display scene of the display panel; and

[0018] Based on the temperature of the display panel and the display scene of the display panel, a preset number of compensation frames are inserted into the normal display frames to obtain a charging compensation control signal. Based on the charging compensation control signal, the timing of the gate drive signal is changed to control the charging time of the pixels in the display panel.

[0019] This application also discloses a display device, which includes a display panel and a driving circuit as described above, wherein the driving circuit drives the display panel using a driving method as described above.

[0020] Compared to solutions that increase the on-state current of TFT devices or increase the number of CLKs in the GOA circuit, this application provides a driving circuit. The driving circuit includes N gate driving units, a charge rate detection circuit, and a driving chip. The charge rate detection circuit is connected to the input terminal of the gate driving unit corresponding to the first gate line and the output terminal of the gate driving unit corresponding to the last gate line; where N is a natural number greater than 1. The charge rate detection circuit generates corresponding charging compensation control signals based on the voltage signals at the input terminals of the gate driving units corresponding to the first gate line and the output terminals of the gate driving units corresponding to the last gate line. The driving chip controls the gate driving units to generate corresponding gate driving signal timings based on the charging compensation control signals, thereby controlling the charging duration of pixels in the display panel, improving the charging efficiency of the display panel, and thus improving the display effect and user experience. Attached Figure Description

[0021] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0022] Figure 1 This is a circuit diagram of the driving circuit input display panel according to the first embodiment of this application;

[0023] Figure 2 This is a schematic diagram of clock signal waveforms at different refresh rates according to the first embodiment of this application;

[0024] Figure 3 This is a schematic diagram of the charge rate detection circuit according to the second embodiment of this application;

[0025] Figure 4 This is a schematic diagram of the charging rate detection circuit according to the third embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the gate drive circuit according to the fourth embodiment of this application;

[0027] Figure 6 This is a schematic diagram of the drive circuit according to the fourth embodiment of this application;

[0028] Figure 7 This is a schematic diagram of the drive signal waveform of the fourth embodiment of this application;

[0029] Figure 8 This is a schematic diagram of the partition control circuit according to the fourth embodiment of this application;

[0030] Figure 9 This is a schematic diagram of another driving circuit according to the fourth embodiment of this application;

[0031] Figure 10 This is a schematic diagram of the drive circuit according to the fifth embodiment of this application;

[0032] Figure 11 This is a schematic diagram of the drive signal waveform of the fifth embodiment of this application;

[0033] Figure 12 This is a schematic diagram of the temperature scene compensation insertion method according to the fifth embodiment of this application;

[0034] Figure 13 This is a schematic flowchart of the driving method according to the sixth embodiment of this application;

[0035] Figure 14This is a schematic flowchart of the driving method according to the seventh embodiment of this application;

[0036] Figure 15 This is a schematic diagram of the structure of the display device according to the eighth embodiment of this application.

[0037] Among them, 100 is the driving circuit; 110 is the gate driving unit; 120 is the charge rate detection circuit; 121 is the voltage divider circuit; 122 is the first voltage generation circuit; 123 is the second voltage generation circuit; 124 is the voltage comparison circuit; 130 is the driving chip; 140 is the partition control circuit; 150 is the display scene detection module; 160 is the frame compensation module; 170 is the temperature detection module; 200 is the display panel; 300 is the display device; first resistor - R1; second resistor - R2 Third resistor - R3; Fourth resistor - R4; First in-phase subtractor - A1; Second in-phase subtractor - A2; Third in-phase subtractor - A3; Fourth in-phase subtractor - A4; First voltage comparator - OP1; Second voltage comparator - OP2; Third voltage comparator - OP3; First frame start signal - STV1; Second frame start signal - STV2; First transistor - M1; First control switch - T1; Data lines - Data1-DataN; Resistors - R1~R22. Detailed Implementation

[0038] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0039] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0040] refer to Figure 1As shown in the first embodiment of this application, a driving circuit 100 is disclosed. The driving circuit 100 is used to drive a display panel. The driving circuit 100 includes N gate driving units 110, a charge rate detection circuit 120, and a driving chip 130. The gate driving units 110 output gate driving signals to gate lines. The driving chip 130 is connected to the N gate driving units 110 through clock signal lines. The charge rate detection circuit 120 is connected to the input terminal of the gate driving unit 110 corresponding to the first gate line and the output terminal of the gate driving unit 110 corresponding to the last gate line. Wherein, N is a natural number greater than 1. The charge rate detection circuit 120 generates a corresponding charging compensation control signal based on the voltage signal at the input terminal of the gate driving unit 110 corresponding to the first gate line and the voltage signal at the output terminal of the gate driving unit 110 corresponding to the last gate line. The driving chip 130 controls the gate driving units 110 to generate the corresponding gate driving signal timing based on the charging compensation control signal, thereby controlling the charging time of the pixels in the display panel.

[0041] For panel displays, the main difference between high and low refresh rates lies in the line time (the time it takes for each line to open). A 120Hz refresh rate has less than half the line time of a 60Hz refresh rate. Figure 2 As shown in the image, this results in a very short panel charging time, which easily leads to insufficient charging. The longer the row time, the longer the charging time.

[0042] In this embodiment, the line scan time is increased by adjusting the gate drive signal timing, thereby improving the charging effect of the display panel. Specifically, based on the commonly used GOA circuit, the input terminal of the first gate drive unit (GOA) and the output terminal of the last GOA unit are connected to the charging rate detection circuit 120. The overall charging state of the panel is determined by the output of the GOA unit in the charging rate detection circuit 120. When the charging rate detection circuit 120 detects different charging states, it feeds back different signals, namely different charging compensation control signals. The driver chip 130 adjusts the gate drive signal timing according to the received charging compensation control signals to increase the line scan time, so that the TFT corresponding to each pixel has a longer charging time, avoiding the occurrence of insufficient charging at high refresh rates, improving the display effect and user experience. This can greatly enhance the adaptability of the current a-si LCD panel under high refresh rate conditions and extreme environmental conditions, and there is no need to set up additional clock signal lines or increase the on-state current of each row of TFTs.

[0043] refer to Figure 3 As shown, the second embodiment of this application is a further refinement and improvement of the first embodiment described above. The charging rate detection circuit 120 includes a voltage divider circuit 121, a first voltage generation circuit 122, a second voltage generation circuit 123, and a voltage comparison circuit 124. The voltage divider circuit 121 divides the voltage at the output terminal of the gate driving unit 110 corresponding to the last gate line. The voltage is divided and the divided voltage is output to the voltage generation circuit. The first voltage generation circuit 122 generates a first voltage based on the divided voltage and the voltage at the output terminal of the gate driving unit 110 corresponding to the last gate line. The second voltage generation circuit 123 generates a first voltage based on the voltage at the input terminal of the gate driving unit 110 corresponding to the first gate line. The voltage at the output of the gate driving unit 110 corresponding to the last gate line generates a second voltage. The voltage comparison circuit 124 generates a charging state control voltage based on the first voltage and the second voltage. The driving chip 130 controls the gate driving unit 110 to generate the corresponding gate driving signal timing based on the magnitude of the charging state control voltage, thereby controlling the charging duration of the pixels in the display panel.

[0044] In this embodiment, reference Figure 1 and Figure 3 As shown, a typical LCD panel input circuit diagram ( Figure 1 The GOA unit is controlled by multiple CLKs, and each GOA unit individually controls the pixels in each row. Therefore, the output signal quality of the GOA unit directly determines the display effect of each row of pixels, thus affecting the display of the entire panel. Because of the loading in the panel circuitry, the signal attenuates from the top (first-level GOA) to the bottom (last-level GOA). This signal attenuation is more pronounced under high refresh rate and low temperature conditions. The last level, where the signal attenuation is most severe, is used as the criterion for judging the panel's charging rate. The signal input to the last stage GOA unit They are respectively connected to the charge rate detection circuit 120, and the charge rate detection circuit 120 will... and After comparing the voltages, the overall charging state of the panel is determined, and then the corresponding output signal is pulled low. The first voltage generation circuit 122 generates a first voltage based on the voltage after voltage division and the voltage at the output of the gate driving unit 110 corresponding to the last gate line. Typically, there are multiple first voltages. The second voltage generation circuit 123 generates a second voltage based on the voltage at the input of the gate driving unit 110 corresponding to the first gate line and the voltage at the output of the gate driving unit 110 corresponding to the last gate line. Typically, there are multiple second voltages. The voltage comparison circuit 124 generates a charging state control voltage based on different first voltages and different second voltages. The driving chip 130 controls the gate driving unit 110 to generate the corresponding gate driving signal timing based on the magnitude of the charging state control voltage, controlling the charging duration of the pixels in the display panel and adjusting the line scan time at different levels.

[0045] refer to Figure 4 As shown, the third embodiment of this application is a further refinement and improvement of the second embodiment described above. The voltage divider circuit 121 includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4 connected in series. The input terminal of the first resistor R1 is connected to the output terminal of the gate driving unit 110 corresponding to the last gate line, and the output terminal of the fourth resistor R4 is grounded. The first voltage generation circuit 122 includes a first in-phase subtractor A1, a second in-phase subtractor A2, and a third in-phase subtractor A3. The negative polarity of the first in-phase subtractor A1 is... The input terminal is connected between the first resistor R1 and the second resistor R2, and the positive input terminal is connected to the output terminal of the gate driving unit 110 corresponding to the last gate line; the negative input terminal of the second in-phase subtractor A2 is connected between the second resistor R2 and the third resistor R3, and the positive input terminal is connected to the output terminal of the gate driving unit 110 corresponding to the last gate line; the negative input terminal of the third in-phase subtractor A3 is connected between the third resistor R3 and the fourth resistor R4, and the positive input terminal is connected to the output terminal of the gate driving unit 110 corresponding to the last gate line.

[0046] The second voltage generation circuit 123 includes a fourth in-phase subtractor A4. The negative input terminal of the fourth in-phase subtractor A4 is connected to the input terminal of the gate driving unit 110 corresponding to the first gate line, and the positive input terminal is connected to the output terminal of the gate driving unit 110 corresponding to the last gate line. The voltage comparison circuit 124 includes a first voltage comparator OP1, a second voltage comparator OP2, and a third voltage comparator OP3. The negative input terminal of the first voltage comparator OP1 is connected to the output terminal of the fourth in-phase subtractor A4. The positive input terminal of the first in-phase subtractor A1 is connected to the output terminal of the second voltage comparator OP2; the negative input terminal of the second voltage comparator OP2 is connected to the output terminal of the fourth in-phase subtractor A4, and the positive input terminal is connected to the output terminal of the second in-phase subtractor A2; the negative input terminal of the third voltage comparator OP3 is connected to the output terminal of the fourth in-phase subtractor A4, and the positive input terminal is connected to the output terminal of the third in-phase subtractor A3. Each of the in-phase subtractors and voltage comparators has corresponding resistors R5 to R22. For details, please refer to [reference needed]. Figure 4 .

[0047] In this embodiment, the charging rate can be simply expressed as: /

[0048] The charge rate detection circuit 120 contains two input signals: and The circuit has three output signals: u4, u5, and u6, and includes four in-phase subtractors and three voltage comparators. The circuit's operating logic is as follows: (Input signal of the last GOA unit) and (The signal from the first GOA unit) is used as the input terminal of this circuit. After voltage division by R1, R2, R3, and R4, u1 (0.9 times) is obtained. ), u2 (0.8 times ), u3 (0.6 times These three voltage signals are the voltage signals corresponding to the monitored charge rate levels of 90%, 80%, and 60% in this example. A non-inverting subtractor is used to subtract u1, u2, and u3 from each other. After calculating the voltage difference, we obtain V1, V2, and V3. and The voltage difference is calculated to obtain V4. V4 is the voltage decay value from the first GOA unit to the last GOA unit. A voltage comparator is then used to compare V1, V2, and V3 with V4 respectively. If V1 > V4, u4 outputs a high level, indicating that the overall charging rate is greater than 90%, and vice versa. Similarly, when u4, u5, and u6 are pulled low, it indicates that the charging rate has dropped below 90%, 80%, and 60%, respectively.

[0049] As a fourth embodiment of this application, and a further refinement and improvement of any of the above embodiments, refer to... Figures 4 to 9 As shown, because the GOA units use a cascaded transmission method, the Start of Frame (STV) pre-charges the first GOA unit, and each subsequent GOA unit needs to receive the signal output from the previous GOA unit. Therefore, the signal attenuation becomes more severe in the lower the GOA unit. Figure 6 As shown, assuming the charging rate of the first row is 99%, it may only be 76% by the time it reaches the last row (hypothesis).

[0050] In this embodiment, the multiple gate driving units 110 are divided into at least two groups of gate driving units 110. The driving circuit 100 further includes a partition control circuit 140, which is disposed between the groups of gate driving units 110. The first gate driving unit 110 of the current group of gate driving units 110 is connected to the driving chip 130 to receive the first frame start signal STV1. The first input terminal of the partition control circuit 140 is connected to the driving chip 130 to receive the second frame start signal STV2. The second input terminal is connected to the charge rate detection circuit 120 to receive the charge compensation control signal. The output terminal is connected to the input terminal of the first gate driving unit 110 of the next group of gate driving units 110. The first frame start signal STV1 and the second frame start signal STV2 operate independently and have different waveforms (e.g., ...). Figure 7 The partition control circuit 140 controls the second frame start signal STV2 to be input to the input terminal of the first gate drive unit 110 of the next gate drive unit 110 group based on the charging compensation control signal.

[0051] If a partition control circuit 140 is inserted in the middle of the cascaded GOA units, for example at the n / 2 GOA unit position, allowing the STV signal to pre-charge the first GOA unit and simultaneously pre-charge the n / 2+1 GOA unit, then signal attenuation can be reset at the middle position. Combined with the charging rate detection circuit 120, the output of the charging rate detection circuit 120 can control the partition control circuits 140 at different positions to divide the display area, offsetting most of the signal attenuation's impact on charging. Inserting the partition control circuit 140 at the middle position, making this the first row of GOA in the lower half of the screen, and allowing the STV signal to pre-charge this GOA, then this GOA unit can still achieve the assumed 99% charging rate, maintaining a good charging state even after attenuation.

[0052] Furthermore, the partition control circuit 140 includes a first transistor M1 and a first control switch T1. The input terminal of the first transistor M1 is connected to the first input terminal of the partition control circuit 140 to receive a frame start signal. The output terminal of the first transistor M1 is connected to the input terminal of the first gate driving unit 110 of the next gate driving unit 110 group. The control terminal of the first transistor M1 is connected to the second input terminal of the partition control circuit 140 to receive a charging compensation control signal. The input terminal of the first control switch T1 is connected to the input terminal of the last gate driving unit 110 of the current gate driving unit 110 group to receive the gate driving signal of the gate driving unit 110. The output terminal of the first control switch T1 is connected to the input terminal of the first gate driving unit 110 of the next gate driving unit 110 group. The control terminal of the first control switch T1 is connected to the second input terminal of the partition control circuit 140 to receive a charging compensation control signal.

[0053] Under normal conditions, when the charge rate is detected to be above 80%, u5 outputs H. At this time, the first control switch T1 is always on, and the first transistor M1 is off. The output signal of the nth stage GOA can be directly transmitted to the input of the (n+1)th stage GOA unit, and the circuit operates normally in its usual mode. When the detected charge rate drops below 80%, u5 outputs L. At this time, T1 is off, M1 is on, and the pre-charge of the (n+1)th stage is no longer provided by the nth stage but is provided by the STV. Only the pre-charge of the GOA changes here; the GOA reset remains unchanged, meaning that the reset of the nth stage can still be provided by the output of the (n+1)th stage.

[0054] Further reference Figure 9 As shown, combined with Figure 4 The charging rate detection circuit 120 can be designed as follows. The partition control circuit is represented by GZC. The diagram shows three partition control circuits: GZC1, GZC2, and GZC3. It should be noted that this solution is not limited to three partition control circuits; it can have four or eight, or even one partition control circuit for each row or every two rows. Figure 4 The u5 and u6 signals control the partition control circuit 140. When the u5 output signal is low level L, the partition control circuit 140 divides the GOA, and the panel is divided into 2 parts. When the u5 and u6 output signals are low level L, the panel is divided into 4 parts, the overall charging status is improved, and the situation of insufficient charging is avoided.

[0055] refer to Figure 10As shown, the fifth embodiment of this application is a further improvement on the first embodiment described above. Unlike the second embodiment, the driving circuit 100 further includes a display scene detection module 150 and a frame compensation module 160. The display scene detection module 150 detects the display scene of the display panel, and the frame compensation module 160 inserts a preset number of compensation frames into the normal display frames based on the display scene, thereby changing the timing of the gate driving signal and controlling the charging time of the pixels in the display panel.

[0056] refer to Figures 10 to 12 As shown, GOA Timing is generally divided into two parts in terms of time: one part is the display time, which controls the opening of row pixels, and the other part is the blanking time, which is used for GOA unit reset and TP waveform generation. This embodiment can reduce the TP reporting rate, allowing some frames to skip TP reporting, and allocating the blanking time to the display time, giving the panel a longer line time in these frames, thereby improving the panel's charging rate. We call the normal display frame a TP frame and the frame where TP is canceled a compensatory frame. The ratio of TP frames to compensatory frames, as well as the insertion position of the compensatory frame, can be adjusted according to the actual situation.

[0057] The specific weights for different display application scenarios vary. In the weight (a, b), 'a' represents the weight ratio of TP frames, and 'b' represents the weight ratio of compensation frames. The insertion method is as follows:

[0058] The insertion positions of TP frames and compensation frames, such as 3,2,2+1,1,1, mean inserting one compensation frame after 3 TP frames, then another compensation frame after 2 TP frames, and so on. Different compensation strategies are adopted for different scenarios. In gaming scenarios, the heat generated by the entire device and the panel itself can improve the panel's charging efficiency. Therefore, the weight of TP frames is relatively small, and the requirement for TP feedback speed is high in gaming scenarios, so one frame is inserted after 2-3 TP frames for compensation. In video scenarios, the requirement for reporting is not high, but the screen refresh is more frequent, so one compensation frame is inserted before each TP frame to compensate for charging in the next frame. In text scenarios, the screen is mostly static, and the requirement for TP reporting is low, so three compensation frames are inserted after every 2 TP frames for charging compensation, which can better and more stably improve the panel's charging efficiency and prepare for charging compensation before switching to other scenarios.

[0059] Furthermore, the driving circuit 100 also includes a temperature detection module 170. The driving chip 130 stores a charging compensation mapping table, which stores the temperature and the corresponding charging compensation control signal. The temperature detection module 170 detects the temperature of the display panel. The driving chip 130 obtains the corresponding charging compensation control signal based on the temperature of the display panel detected by the temperature detection module 170 and the charging compensation mapping table. Based on the charging compensation control signal, the driving unit 110 is controlled to generate the corresponding gate driving signal timing to control the charging duration of the pixels in the display panel.

[0060] Based on the overall charging rate, temperature, and application scenario of the display panel, a mapping table can be established through experiments and stored in the driver chip 130. This allows for rapid response when encountering corresponding scenarios, ensuring stable panel operation. For details, please refer to [reference needed]. Figure 12 As shown, different insertion methods are selected based on weights under different temperatures and in different scenarios.

[0061] Referring to Figure 13, as a sixth embodiment of this application, a driving method is disclosed for driving a display panel using the driving circuit described in any of the above embodiments, the driving method comprising:

[0062] S1: Obtain the voltage signal at the input terminal of the gate driving unit corresponding to the first gate line and the voltage signal at the output terminal of the gate driving unit corresponding to the last gate line to generate the corresponding charging compensation control signal; and

[0063] S2: Based on the charging compensation control signal, the gate driving unit is controlled to generate the corresponding gate driving signal timing to control the charging duration of the pixels in the display panel.

[0064] The driving method in this embodiment is mainly used in the above-mentioned driving circuit. Based on the commonly used GOA circuit, the input terminal of the first GOA unit and the output terminal of the last GOA unit are connected to the charge rate detection circuit. The overall charging state of the panel is determined by the output of the GOA unit of the charge rate detection circuit. When the charge rate detection circuit detects different charging states, it feeds back different signals. The driving chip adjusts the GOA Timing according to the received signals to improve the line time and make the TFT have a longer charging time.

[0065] Referring to Figure 14, as the seventh embodiment of this application, a driving method is disclosed, which is a further refinement and improvement of the fifth embodiment described above, and is mainly used in the driving circuit 100 in the fourth embodiment. Figure 9 and Figure 12 As shown, step S2 includes:

[0066] S21: Detects the temperature of the display panel;

[0067] S22: Detect the display scene of the display panel; and

[0068] S23: Based on the temperature of the display panel and the display scene of the display panel, a preset number of compensation frames are inserted into the normal display frames to obtain a charging compensation control signal. Based on the charging compensation control signal, the timing of the gate drive signal is changed to control the charging duration of the pixels in the display panel.

[0069] In this embodiment, the panel charging rate at different temperatures is verified through experiments, and a compensation timing mapping table corresponding to different temperatures is established so that the driver chip can use different strategies to adjust the panel charging rate according to different ambient temperatures.

[0070] Referring to Figure 15, as the eighth embodiment of this application, a display device 300 is disclosed. The display device 300 includes a display panel 200 and a driving circuit 100 as described in any of the above embodiments. The driving circuit 100 drives the display panel 200 using the driving method described in any of the above embodiments.

[0071] It should be noted that the limitations on the steps involved in this solution, without affecting the implementation of the specific solution, are not considered as limiting the order of the steps. That is, the steps listed first can be performed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the protection scope of this application. The inventive concept of this application can form many embodiments, but due to space limitations in the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. The combination of embodiments or technical features will enhance the original technical effect.

[0072] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A drive circuit for driving a display panel, characterized by comprising: The driving circuit comprises N gate driving units, a charging rate detection circuit and a driving chip, the gate driving units output gate driving signals to gate lines, the driving chip is connected to the N gate driving units through a clock signal line, and the charging rate detection circuit is connected to the input end of the gate driving unit corresponding to the first gate line and the output end of the gate driving unit corresponding to the last gate line; wherein N is a natural number greater than 1, the charging rate detection circuit generates a corresponding charging compensation control signal based on the voltage signal of the input end of the gate driving unit corresponding to the first gate line and the voltage signal of the output end of the gate driving unit corresponding to the last gate line, and the driving chip controls the gate driving unit to generate a corresponding gate driving signal timing based on the charging compensation control signal, and controls the charging duration of the pixels in the display panel; The charging rate detection circuit comprises a voltage dividing circuit, a first voltage generating circuit, a second voltage generating circuit and a voltage comparison circuit, the voltage dividing circuit divides the voltage at the output end of the gate driving unit corresponding to the last gate line and outputs the divided voltage to the voltage generating circuit, the first voltage generating circuit generates a first voltage based on the divided voltage and the voltage at the output end of the gate driving unit corresponding to the last gate line, the second voltage generating circuit generates a second voltage based on the voltage at the input end of the gate driving unit corresponding to the first gate line and the voltage at the output end of the gate driving unit corresponding to the last gate line, and the voltage comparison circuit generates a charging state control voltage based on the first voltage and the second voltage, and the driving chip controls the gate driving unit to generate a corresponding gate driving signal timing based on the size of the charging state control voltage, and controls the charging duration of the pixels in the display panel.

2. The drive circuit of claim 1, wherein, The voltage dividing circuit comprises a first resistor, a second resistor, a third resistor and a fourth resistor connected in series, the input end of the first resistor is connected to the output end of the gate driving unit corresponding to the last gate line, and the output end of the fourth resistor is grounded; The first voltage generating circuit comprises a first same-phase subtractor, a second same-phase subtractor and a third same-phase subtractor, the negative polarity input end of the first same-phase subtractor is connected between the first resistor and the second resistor, and the positive polarity input end is connected to the output end of the gate driving unit corresponding to the last gate line; the negative polarity input end of the second same-phase subtractor is connected between the second resistor and the third resistor, and the positive polarity input end is connected to the output end of the gate driving unit corresponding to the last gate line; the negative polarity input end of the third same-phase subtractor is connected between the third resistor and the fourth resistor, and the positive polarity input end is connected to the output end of the gate driving unit corresponding to the last gate line; The second voltage generating circuit comprises a fourth same-phase subtractor, the negative polarity input end of the fourth same-phase subtractor is connected to the input end of the gate driving unit corresponding to the first gate line, and the positive polarity input end is connected to the output end of the gate driving unit corresponding to the last gate line; The voltage comparison circuit comprises a first voltage comparator, a second voltage comparator and a third voltage comparator, the negative polarity input end of the first voltage comparator is connected with the output end of the fourth same-phase subtractor, and the positive polarity input end is connected with the output end of the first same-phase subtractor; the negative polarity input end of the second voltage comparator is connected with the output end of the fourth same-phase subtractor, and the positive polarity input end is connected with the output end of the second same-phase subtractor; the negative polarity input end of the third voltage comparator is connected with the output end of the fourth same-phase subtractor, and the positive polarity input end is connected with the output end of the third same-phase subtractor.

3. The drive circuit according to any one of claims 1 to 2, wherein The plurality of gate driving units are divided into at least two groups of gate driving units, and the driving circuit further comprises a subarea control circuit arranged between the groups of gate driving units, a first gate driving unit of a current group of gate driving units is connected to receive a first frame start signal from a driving chip, a first input end of the subarea control circuit is connected to receive a second frame start signal from the driving chip, a second input end is connected to receive a charging compensation control signal from a charging rate detection circuit, and an output end is connected to an input end of a first gate driving unit of a next group of gate driving units. The first frame start signal and the second frame start signal work independently, and the subarea control circuit controls the second frame start signal to be input to the input end of the first gate driving unit of the next group of gate driving units based on the charging compensation control signal.

4. The drive circuit of claim 3, wherein The subarea control circuit comprises a first transistor and a first control switch, an input end of the first transistor is connected to the first input end of the subarea control circuit to receive a frame start signal, an output end of the first transistor is connected to the input end of the first gate driving unit of the next group of gate driving units, a control end of the first transistor is connected to the second input end of the subarea control circuit to receive a charging compensation control signal, an input end of the first control switch is connected to the input end of the last gate driving unit of the current group of gate driving units to receive a gate driving signal of the gate driving unit, an output end of the first control switch is connected to the input end of the first gate driving unit of the next group of gate driving units, and a control end of the first control switch is connected to the second input end of the subarea control circuit to receive the charging compensation control signal.

5. The drive circuit according to any one of claims 1 to 2, wherein The driving circuit further comprises a display scene detection module and a frame compensation module, the display scene detection module detects a display scene of the display panel, and the frame compensation module inserts a preset number of compensation frames in a normal display frame based on the display scene, so that the timing of the gate driving signal is changed to control the charging duration of the pixels in the display panel.

6. The drive circuit according to any one of claims 1 to 2, wherein The driving circuit further comprises a temperature detection module, the driving chip stores a charging compensation mapping table, the charging compensation mapping table stores temperatures and charging compensation control signals corresponding to the temperatures, the temperature detection module detects a temperature of the display panel, the driving chip obtains a corresponding charging compensation control signal according to the temperature of the display panel detected by the temperature detection module and the charging compensation mapping table, and controls the gate driving unit to generate a corresponding gate driving signal timing sequence based on the charging compensation control signal, so as to control a charging time length of a pixel in the display panel.

7. A driving method for driving the driving circuit according to any one of claims 1 to 6, wherein The driving method comprises: generating a corresponding charging compensation control signal based on a voltage signal of an input end of a gate driving unit corresponding to a first gate line and a voltage signal of an output end of a gate driving unit corresponding to a last gate line; and controlling the gate driving unit to generate a corresponding gate driving signal timing sequence based on the charging compensation control signal, so as to control a charging time length of a pixel in the display panel.

8. The driving method according to claim 7, wherein The step of controlling the gate driving unit to generate a corresponding gate driving signal timing sequence based on the charging compensation control signal, so as to control a charging time length of a pixel in the display panel, comprises: detecting a temperature of the display panel; detecting a display scenario of the display panel; and determining that a preset number of compensation frames are inserted in a normal display frame based on the temperature of the display panel and the display scenario of the display panel, obtaining a charging compensation control signal, and changing a gate driving signal timing sequence based on the charging compensation control signal, so as to control a charging time length of a pixel in the display panel.

9. A display device, characterized by comprising: The display device comprises a display panel and the driving circuit according to any one of claims 1-6, and the driving circuit drives the display panel by using the driving method according to any one of claims 7-8.

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