High thermal conductive fan-out package substrate, preparation process and application thereof

Abstract

The application discloses a high-thermal-conductivity fan-out packaging substrate, a preparation process and application thereof, wherein the preparation process comprises the following steps: S100, performing micro-arc oxidation treatment on a first side of a base material to form a first insulating layer; S200, immersing the base material in a sealing liquid to perform low-temperature sealing treatment and form a dense sealing layer; S300, forming a second insulating layer on the first side of the base material by adopting a magnetron sputtering method and / or an atomic layer deposition method; and S400, forming a micro-heat-dissipation structure on a second side of the base material to obtain the packaging substrate. The application can form the insulating layer on the first side of the base material, effectively improve the insulation, solve the wiring flatness problem and serve as a base wiring packaging device. The micro-heat-dissipation structure formed on the second side of the base material can effectively increase the specific surface area and greatly increase the heat dissipation efficiency of the base material, realize double-function integration of high insulation on the front side and high heat dissipation on the back side and meet the packaging and heat dissipation requirements of high-power chips.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a high-thermal-conductivity fan-out packaging substrate, a preparation process and application thereof. BACKGROUND

[0002] Traditional fan-out packaging substrates such as organic substrates BT (Bismaleimide Triazine, resin substrate), ABF (Ajinomoto Build-up Film) and the like usually have a thermal conductivity <1 W / m·K, and it is difficult to meet the heat dissipation requirements of high-power chips such as GPUs and AI accelerators; while metal substrates such as aluminum substrates and copper substrates have excellent thermal conductivity, usually with a thermal conductivity of 200 W / m·K or more, but direct use as a substrate lacks insulation, and the surface roughness is difficult to be compatible with fine RDL wiring.

[0003] Micro-arc oxidation aluminum substrates have become a possibility for application in packaging substrates due to their insulation and thermal conductivity, but the porosity of existing micro-arc oxidation aluminum substrates is high, usually 10%-30%, so that sealing treatment needs to be carried out at a high temperature of more than 300℃, but high-temperature sealing treatment process is easy to cause substrate deformation or material volatilization, and cannot meet the requirements of semiconductor packaging process. SUMMARY

[0004] In order to overcome the deficiencies of the prior art, the purpose of the present application is to provide a high-thermal-conductivity fan-out packaging substrate, a preparation process and application thereof, which has the advantages of high thermal conductivity, high voltage resistance and compatibility with RDL wiring.

[0005] The purpose of the present application is achieved by the following technical solutions:

[0006] According to a first aspect of the embodiments of the present disclosure, a preparation process of a high-thermal-conductivity fan-out packaging substrate is provided, comprising:

[0007] Step S100, performing micro-arc oxidation treatment on the first side of the substrate to form a first insulating layer;

[0008] Step S200, immersing the substrate in a sealing liquid and performing low-temperature sealing treatment at a temperature of 40-60℃ to form a dense sealing layer;

[0009] Step S300, forming a second insulating layer on the first side of the substrate by using a magnetron sputtering method and / or an atomic layer deposition method;

[0010] Step S400, forming a micro-heat-dissipation structure on the second side of the substrate to obtain a packaging substrate.

[0011] In some exemplary embodiments, in step S100, micro-arc oxidation treatment is performed in a micro-arc oxidation electrolyte, which includes: 10-20 g / L sodium silicate, 5-10 g / L sodium phosphate, and deionized water.

[0012] The micro-arc oxidation process conditions are: voltage 400-600V, pulse frequency 100-500Hz, pulse duty cycle 20-40%, and processing time 10-30min.

[0013] The thickness of the first insulating layer is ≥20μm, the porosity is ≤15%, and the breakdown voltage is ≥700V.

[0014] In some exemplary embodiments, in step S200, the sealing liquid includes: 5-10 wt% of silane coupling agent, 1-3 wt% of nano-silica, 0.1-0.5 wt% of fluorocarbon surfactant and solvent, wherein the solvent is an ethanol / water mixture with a volume ratio of 1:1.

[0015] In some exemplary embodiments, step S200 specifically includes:

[0016] Step S201: Immerse the substrate in the sealing liquid at a temperature of 40-60℃ for 5-10 minutes, and control the vacuum pressure to ≤10⁻² Pa for vacuum-assisted impregnation;

[0017] Step S202: Bake at 120-150℃ for 30-60 minutes to form a sealed pore layer, controlling the porosity to ≤2%.

[0018] In some exemplary embodiments, the magnetron sputtering method in step S300 specifically includes:

[0019] Silicon nitride with a purity ≥99.99% and a thickness of 5-10 μm was used as the target material, and magnetron sputtering was performed under Ar / N2 mixed gas conditions, with a controlled power of 500-2000 W and a substrate temperature ≤150℃; or,

[0020] Alumina with a purity of ≥99.99% and a thickness of 5-10 μm was used as the target material, and magnetron sputtering was performed under Ar atmosphere conditions with a power of 500-2000 W and a substrate temperature of ≤150℃.

[0021] In some exemplary embodiments, the atomic layer deposition method in step S300 specifically includes:

[0022] Deposition was carried out using trimethylaluminum and H2O precursors at temperatures of 80-120℃.

[0023] In some exemplary embodiments, the second insulating layer has a breakdown field strength ≥10 MV / cm and a surface roughness Ra ≤0.1μm.

[0024] In some exemplary embodiments, the micro heat dissipation structure includes one or more of the following: fin array structure, grooved mesh structure, microporous array structure, and fluid biomimetic structure;

[0025] The fin array structure includes a plurality of fins arranged in parallel and / or radial patterns, wherein the height of the fins is 100-500 μm and the spacing is 50-200 μm;

[0026] The grooved mesh structure has a depth of 50-300μm, a width of 50-150μm, and a mesh density of 10-50 lines / cm;

[0027] The microporous array structure has a pore size of 20-100 μm, a pore depth of 50-200 μm, and a porosity of 30-60%.

[0028] The fluid biomimetic structure includes a leaf vein-like structure or a shark skin-like texture structure.

[0029] In some exemplary embodiments, the process for forming the micro heat dissipation structure includes: chemical etching process, laser processing process, and imprinting process;

[0030] The chemical etching process includes etching with an etching solution at a temperature of 25-40℃ and an etching rate of 5-10 μm / min for 5-15 minutes, wherein the etching solution includes 10-20% hydrochloric acid, 5-10% nitric acid and 0.1-0.5% benzotriazole.

[0031] The laser processing technology includes: controlling the wavelength to be 355nm, the power to be 10-50W, and the scanning speed to be 100-500mm / s for laser processing, and controlling the structural size error to be ≤±5μm during laser processing;

[0032] The embossing process includes: embossing with an embossing mold while controlling the pressure to 50-200 MPa, the temperature to 150-250℃, and the holding time to 1-5 minutes.

[0033] In some exemplary embodiments, the method further includes: step S500, forming an RDL wiring layer on the second insulating layer.

[0034] In some exemplary embodiments, the RDL wiring layer is made of electroplated copper or copper / titanium seed layer, and the line width / line spacing is controlled to be ≤5μm, and the bonding force between the RDL wiring layer and the second insulating layer is ≥50 MPa.

[0035] According to a second aspect of the present disclosure, a high thermal conductivity fan-out type packaging substrate is provided, which is manufactured by the fabrication process described in the first aspect.

[0036] According to a third aspect of the present disclosure, the application of a high thermal conductivity fan-out type packaging substrate as described in the second aspect in semiconductor packaging is provided.

[0037] In summary, compared with the prior art, the present invention has the following beneficial effects:

[0038] This invention provides a high thermal conductivity fan-out type packaging substrate, its fabrication process, and its application. The fabrication process includes: step S100, performing micro-arc oxidation treatment on a first side of the substrate to form a first insulating layer; step S200, immersing the substrate in a sealing liquid and performing low-temperature sealing treatment at a temperature of 40-60°C to form a sealed hole layer; step S300, forming a second insulating layer on the first side of the substrate using magnetron sputtering and / or atomic layer deposition; and step 400, forming a micro heat dissipation structure on the second side of the substrate to obtain the packaging substrate. This invention utilizes a micro-arc oxidation process to first form a pre-oxidized layer on the first side of the substrate as a first insulating layer, increasing the substrate's insulation. Then, a low-temperature sealing process fills the micropores in the first insulating layer, further preventing the first insulating layer from breaking down and causing the substrate to lose its insulation. This also facilitates RDL wiring and avoids substrate thermal deformation, while enhancing chemical bonding with the second insulating layer. Next, an oxide film is deposited as a second insulating layer using magnetron sputtering and / or atomic layer deposition. This further seals the pores and improves insulation, while also addressing wiring flatness issues, enabling it to serve as a base-surface wiring package. Furthermore, forming a micro-heat dissipation structure on the second side of the substrate effectively increases the specific surface area, significantly improving the substrate's heat dissipation efficiency. This achieves a dual-functional integration of high insulation on the front and high heat dissipation on the back, meeting the packaging and heat dissipation requirements of high-power chips. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure formed after step S100 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in an embodiment of the present invention.

[0040] Figure 2 This is a microstructure diagram of the surface condition formed after step S100 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in this embodiment of the invention.

[0041] Figure 3 This is a microstructure diagram of the cross-section formed after step S100 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in this embodiment of the invention.

[0042] Figure 4This is a schematic diagram of the structure formed after step S200 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in this embodiment of the invention.

[0043] Figure 5 This is a microstructure diagram of the surface condition formed after step S200 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in this embodiment of the invention.

[0044] Figure 6 This is a microstructure diagram of the cross-section formed after step S200 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in this embodiment of the invention.

[0045] Figure 7 This is a schematic diagram of the structure formed after step S300 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in this embodiment of the invention.

[0046] Figure 8 This is a microstructure diagram of the surface condition formed after step S300 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in this embodiment of the invention.

[0047] Figure 9 This is a microstructure diagram of the cross-section formed after step S300 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in this embodiment of the invention.

[0048] Figure 10 This is a schematic diagram of the fin array structure in the fabrication process of the high thermal conductivity fan-out type packaging substrate in an embodiment of the present invention.

[0049] Figure 11 This is a schematic diagram of the groove grid structure in the fabrication process of the high thermal conductivity fan-out type packaging substrate in an embodiment of the present invention.

[0050] Figure 12 for Figure 11 Enlarged view of part A.

[0051] Figure 13 This is a schematic diagram of the micro-hole array structure in the fabrication process of the high thermal conductivity fan-out type packaging substrate in an embodiment of the present invention.

[0052] Figure 14 for Figure 13 Enlarged view of part B.

[0053] Figure 15 This is a schematic diagram of the fluid biomimetic structure in the fabrication process of the high thermal conductivity fan-out type packaging substrate in an embodiment of the present invention.

[0054] Figure 16 This is a schematic diagram of the structure formed after step S500 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in this embodiment of the invention.

[0055] Figure 17This is a schematic diagram of the three-dimensional structure formed after step S500 in the fabrication process of the high thermal conductivity fan-out type packaging substrate in this embodiment of the invention.

[0056] The numbers and letters in the diagram represent the names of the corresponding components:

[0057] 10. Substrate; 11. First insulating layer; 20. Sealing layer; 21. Second insulating layer; 30. RDL wiring layer; 41. Fin array structure; 42. Groove mesh structure; 43. Micropore array structure; 44. Fluid biomimetic structure. Detailed Implementation

[0058] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] The first aspect of this invention provides a fabrication process for a high thermal conductivity fan-out type packaging substrate, comprising:

[0060] Step S100: Perform micro-arc oxidation treatment on the first side of the substrate 10 to form a first insulating layer 11, the forming structure of which is as follows: Figure 1 As shown, specifically, the material of the substrate 10 can be aluminum, aluminum alloy, copper, copper alloy, etc. Preferably, the substrate 10 can be a 6-series aluminum alloy, such as aluminum alloy with model number 6061 or 6063. Usually, the substrate 10 is pre-cut into a suitable size and specification before processing. During processing, micro-arc oxidation is carried out in a micro-arc oxidation electrolyte. The micro-arc oxidation electrolyte includes: 10-20 g / L sodium silicate, 5-10 g / L sodium phosphate and deionized water, and the pH of the micro-arc oxidation electrolyte is controlled at 9-11. The micro-arc oxidation process conditions are: voltage 400-600V, pulse frequency 100-500Hz, pulse duty cycle 20-40%, and processing time 10-30min.

[0061] After micro-arc oxidation treatment, the thickness of the first insulating layer 11 must be controlled to be ≥20μm, the porosity ≤15%, and the breakdown voltage ≥700V.

[0062] Understandably, before micro-arc oxidation, the surface of the substrate 10 can usually be pretreated by polishing and cleaning to ensure the cleanliness of the substrate 10 surface. After micro-arc oxidation, post-treatments such as washing and drying can be performed. The microstructure diagram of its surface condition after molding is shown in the figure. Figure 2 As shown, the microstructure diagram of the cross-section is as follows. Figure 3 As shown.

[0063] Step S200: The substrate 10 is immersed in a sealing liquid and subjected to low-temperature sealing treatment at 40-60°C to form a sealed pore layer 20, the structure of which is as follows. Figure 4 As shown.

[0064] Specifically, the sealing solution includes: 5-10 wt% silane coupling agent, 1-3 wt% nano silica, 0.1-0.5 wt% fluorocarbon surfactant and solvent. The type of silane coupling agent can be, for example, KH-550 or KH-560. The particle size of nano silica is usually controlled at 10-20 nm. The type of fluorocarbon surfactant can be, for example, FC-4430. The solvent is a 1:1 volume ratio of ethanol / water mixture.

[0065] Step S200 specifically includes:

[0066] Step S201: Immerse the substrate 10 in the sealing liquid at a temperature of 40-60℃ for 5-10 minutes, and control the vacuum pressure to ≤10⁻² Pa for vacuum-assisted immersion. This can be understood as the substrate 10 and the sealing liquid being placed under vacuum conditions during the low-temperature sealing process. The silane coupling agent and nano-silica in the sealing liquid can achieve composite sealing.

[0067] Step S202: Bake at 120-150℃ for 30-60 minutes to form a sealed porous layer 20, controlling the porosity to ≤2%. The baking process can be carried out in an oven, for example. The formed sealed porous layer 20 is non-volatile. The microstructure diagram of its surface condition after molding is shown below. Figure 5 As shown, the microstructure diagram of the cross-section is as follows. Figure 6 As shown.

[0068] Step S300: A second insulating layer 21 is formed on the first side of the substrate 10 using magnetron sputtering and / or atomic layer deposition methods, and its formed structure is as follows. Figure 7 As shown in the figure, the microstructure of its surface after molding is as follows. Figure 8 As shown, the microstructure diagram of the cross-section is as follows. Figure 9 As shown.

[0069] Specifically, the magnetron sputtering method includes:

[0070] Using silicon nitride (Si3N4) with a purity ≥99.99% and a thickness of 5-10 μm as the target material, magnetron sputtering is performed under Ar / N2 mixed gas conditions, with a controlled power of 500-2000 W and a substrate temperature ≤150℃; or,

[0071] Alumina (Al2O3) with a purity of ≥99.99% and a thickness of 5-10 μm was used as the target material, and magnetron sputtering was performed under Ar atmosphere conditions with a power of 500-2000 W and a substrate temperature of ≤150℃.

[0072] Magnetron sputtering is a physical vapor deposition (PVD) technique that uses the combined action of magnetic and electric fields to generate plasma through gas discharge, thereby sputtering the target material onto the substrate 10 to form a thin film.

[0073] Atomic layer deposition methods specifically include:

[0074] Deposition was carried out using trimethylaluminium (TMA) and H2O precursors at temperatures of 80-120℃.

[0075] Atomic layer deposition (ALD) is a method that deposits a material layer by layer onto the surface of a substrate 10 in the form of a single-atom film. It forms the deposited film by alternately pulsedly passing a gaseous precursor into a reactor, where it is chemically adsorbed and reacted on the substrate 10.

[0076] When trimethylaluminum (TMA) and water (H2O) are used as precursors for atomic layer deposition (ALD), they are alternately pulsed into the reaction chamber in gaseous form. The specific process is as follows:

[0077] 1) TMA pulse: First, TMA gas is pulsed into the reaction chamber, reacts with the substrate surface, forms a monolayer adsorption, and releases methane (CH4) as a byproduct;

[0078] 2) Purging: Unreacted TMA and byproducts are removed by purging with an inert gas (such as argon or nitrogen);

[0079] 3) Water pulse: Water vapor is then pulsed into the reaction chamber to react with the adsorbed TMA, replacing the -CH3 groups on the surface with -OH groups;

[0080] 4) Purging: Purging again to remove unreacted water and byproducts;

[0081] This alternating pulse method ensures the self-limitation of the reaction, enabling thin films to grow layer by layer with atomic precision.

[0082] In practical applications, the second insulating layer 21 can be formed by magnetron sputtering alone, atomic layer deposition alone, or magnetron sputtering and atomic layer deposition can be used sequentially to form the second insulating layer 21. The breakdown field strength of the second insulating layer 21 must be controlled to be ≥10 MV / cm and the surface roughness Ra≤0.1μm.

[0083] Step S400: After forming a micro heat dissipation structure on the second side of the substrate 10, an encapsulation substrate is obtained. Specifically, the micro heat dissipation structure includes one or more of the following: fin array structure 41, groove mesh structure 42, micropore array structure 43, and fluid biomimetic structure 44.

[0084] like Figure 10 As shown, the fin array structure 41 includes a plurality of fins arranged in parallel and / or radial patterns, the fins having a height of 100-500 μm and a spacing of 50-200 μm; Figure 11 and Figure 12 As shown, the grooved mesh structure 42 has a depth of 50-300 μm, a width of 50-150 μm, and a mesh density of 10-50 lines / cm; Figure 13 and Figure 14 As shown, the microporous array structure 43 has a pore size of 20-100 μm, a pore depth of 50-200 μm, and a porosity of 30-60%; the fluid biomimetic structure 44 includes a leaf vein-like structure or a shark skin-like texture structure, such as... Figure 15 A structural schematic diagram of the sharkskin-textured structure is shown, and the flow channel design can be optimized through fluid simulation to reduce airflow resistance.

[0085] In some embodiments, a hierarchical combination structure of grooved mesh structure 42 and micropore array structure 43 can also be adopted. The first level is millimeter-level grooves with a depth of 0.5-1mm, and the second level structure is micron-level honeycomb pores with a pore size of 10-50 μm. This hierarchical combination structure can increase the specific surface area by 5-8 times.

[0086] The process for forming the micro heat dissipation structure includes: chemical etching, laser processing, and embossing.

[0087] Specifically, the chemical etching process includes etching at a temperature of 25-40℃ for 5-15 minutes with an etching solution at an etching rate of 5-10 μm / min. The etching solution includes 10-20% hydrochloric acid, 5-10% nitric acid, and 0.1-0.5% benzotriazole. During etching, the surface roughness Ra of the second side of the substrate 10 needs to be controlled to be 1-5 μm.

[0088] The laser processing technology includes controlling the wavelength to 355nm, the power to 10-50W, and the scanning speed to 100-500 mm / s for laser processing. During laser processing, the structural size error is controlled to be ≤±5μm. The laser processing technology is more suitable for processing and forming the fin array structure 41 and the grooved grid structure 42.

[0089] The embossing process includes: controlling the pressure to 50-200 MPa, the temperature to 150-250℃, and the holding time to 1-5 minutes, and embossing with an embossing mold. The embossing mold is preferably made of hard alloy or ceramic with a temperature resistance of >300℃.

[0090] In actual processing, multiple processes can be used in combination. For example, a combination of chemical etching and laser processing can be used to form a multi-scale micro heat dissipation structure on the second side of the substrate 10, which can increase the specific surface area by 3-10 times compared to a flat surface and improve the heat dissipation efficiency by 40%-60%.

[0091] Meanwhile, mechanical strength is usually also considered when designing micro heat dissipation structures. For example, when designing the fin array structure 41, the chamfer at the root of the fin can be optimized by fin element analysis (FEA). The chamfer radius is usually 0.1-0.3 mm to reduce stress concentration. The bending strength of the substrate 10 is ≥300 MPa. The bending strength can be tested according to the ASTM C1341 standard.

[0092] Furthermore, the fabrication process also includes: step S500, forming an RDL wiring layer 30 on the second insulating layer 21, the forming structure of which is as follows: Figure 16 and Figure 17 As shown.

[0093] Specifically, RDL (ReDistribution Layer) technology, by adding an additional wiring layer on the chip surface or interposer, can move I / O pads from the chip center to the edge, distributing them over a wider area. In this application, the RDL wiring layer 30 uses electroplated copper or a copper / titanium seed layer, and the line width / spacing is controlled to be ≤5μm. Furthermore, the adhesion between the RDL wiring layer 30 and the second insulating layer 21 is ≥50 MPa, and the adhesion can be tested according to the ASTM D3359 standard.

[0094] This invention utilizes a micro-arc oxidation process to first form a pre-oxidized layer as a first insulating layer 11 on the first side of the substrate 10, increasing the insulation of the substrate 10. Then, a low-temperature sealing process is used to fill the micropores in the first insulating layer 11, further preventing the first insulating layer 11 from being broken down and causing the substrate 10 to lose its insulation. This also facilitates RDL wiring and avoids thermal deformation of the substrate, while enhancing the chemical bonding with the second insulating layer 21. Next, an oxide film is deposited as the second insulating layer 21 using magnetron sputtering and / or atomic layer deposition. This further seals the pores and improves insulation, while also solving the wiring flatness problem, enabling it to serve as a base-surface wiring packaged device. Meanwhile, forming a micro-heat dissipation structure on the second side of the substrate 10 effectively increases the specific surface area, significantly increasing the heat dissipation efficiency of the substrate 10. This achieves a dual-functional integration of high insulation on the front and high heat dissipation on the back, meeting the packaging and heat dissipation requirements of high-power chips.

[0095] The packaging substrate prepared by the above-described process can form a combined insulating structure on the front side consisting of a first insulating layer 11, a sealing hole layer 20, and a second insulating layer 21. Taking aluminum alloy as the substrate 10 as an example, an Al2O3 layer as the first insulating layer 11, a SiO2-Si-O network layer as the sealing hole layer 20, and a Si3N4 / Al2O3 layer as the second insulating layer 21 can be formed to create a stepped dielectric constant distribution, reduce the concentration of the interface electric field, and improve the withstand voltage to ≥1500V. Furthermore, the thermal conductivity of the packaging substrate is ≥200W / m·K, and the overall packaging thermal resistance is ≤0.5℃·cm2 / W, thus enabling it to be compatible with high-power chips of 100W and above. The thermal performance of the packaging substrate can be tested according to the JEDEC JESD51 standard.

[0096] A second aspect of the present invention provides a high thermal conductivity fan-out type packaging substrate, which is manufactured by the fabrication process described in the first aspect.

[0097] The third aspect of the present invention provides the application of the high thermal conductivity fan-out type packaging substrate as described in the second aspect in semiconductor packaging.

[0098] The high thermal conductivity fan-out type packaging substrate of the present invention will be described below with reference to several specific embodiments: Example 1

[0099] A high thermal conductivity fan-out type packaging substrate is prepared by the following process:

[0100] Step S100: Perform micro-arc oxidation treatment on the first side of the substrate 10 to form a first insulating layer 11. The micro-arc oxidation electrolyte includes: 10 g / L sodium silicate, 5 g / L sodium phosphate and deionized water, and control the pH of the micro-arc oxidation electrolyte to be 9. The micro-arc oxidation treatment process conditions are: voltage 400V, pulse frequency 100Hz, pulse duty cycle 20%, and treatment time 30min. After micro-arc oxidation treatment, the thickness of the first insulating layer 11 needs to be controlled to be ≥20μm, the porosity ≤15%, and the breakdown voltage ≥700V.

[0101] Step S200: The substrate 10 is immersed in a sealing liquid and subjected to low-temperature sealing treatment at 40°C to form a sealed pore layer 20. The sealing liquid includes 5 wt% silane coupling agent, 1 wt% nano silica, 0.1 wt% fluorocarbon surfactant and solvent, wherein the solvent is an ethanol / water mixture with a volume ratio of 1:1.

[0102] Step S200 specifically includes:

[0103] Step S201: Immerse the substrate 10 in the sealing liquid at 40°C for 10 minutes, and control the vacuum pressure to ≤10⁻² Pa for vacuum-assisted impregnation;

[0104] Step S202: Bake at 120℃ for 60 minutes to form a sealed pore layer 20, controlling the porosity to ≤2%.

[0105] Step S300: A second insulating layer 21 is formed on the first side of the substrate 10 using a magnetron sputtering method.

[0106] The magnetron sputtering method specifically includes: using silicon nitride (Si3N4) with a purity ≥99.99% and a thickness of 5μm as the target material, and performing magnetron sputtering under Ar / N2 mixed gas conditions, controlling the power at 500 W and the substrate temperature at ≤150℃; the breakdown field strength of the second insulating layer 21 needs to be controlled to be ≥10 MV / cm and the surface roughness Ra≤0.1μm.

[0107] Step S400: After forming a micro heat dissipation structure on the second side of the substrate 10, a packaging substrate is obtained. Specifically, the micro heat dissipation structure adopts a fin array structure 41, which includes a number of fins arranged in parallel and / or radially. The height of the fins is 100-500 μm and the spacing is 50-200 μm. The fin array structure 41 is formed by laser processing technology. The laser processing technology includes controlling the wavelength at 355nm, the power at 10W, and the scanning speed at 100mm / s. During laser processing, the structural size error is controlled to be ≤±5μm. The laser processing technology is more suitable for the processing and forming of the fin array structure 41 and the grooved mesh structure 42.

[0108] Step S500: Form an RDL wiring layer 30 on the second insulating layer 21. The RDL wiring layer 30 adopts an electroplated copper seed layer and controls the line width / line spacing to be ≤5μm. The bonding force between the RDL wiring layer 30 and the second insulating layer 21 is ≥50MPa. Example 2

[0109] A high thermal conductivity fan-out type packaging substrate is prepared by the following process:

[0110] Step S100: Perform micro-arc oxidation treatment on the first side of the substrate 10 to form a first insulating layer 11. The micro-arc oxidation electrolyte includes: 15 g / L sodium silicate, 8 g / L sodium phosphate and deionized water, and control the pH of the micro-arc oxidation electrolyte to be 10. The micro-arc oxidation treatment process conditions are: voltage 500V, pulse frequency 250Hz, pulse duty cycle 30%, and treatment time 25min. After micro-arc oxidation treatment, the thickness of the first insulating layer 11 needs to be controlled to be ≥20μm, porosity ≤15%, and breakdown voltage ≥700V.

[0111] Step S200: The substrate 10 is immersed in a sealing liquid and subjected to low-temperature sealing treatment at 50°C to form a sealed pore layer 20. The sealing liquid includes: 8 wt% silane coupling agent, 2 wt% nano silica, 0.35 wt% fluorocarbon surfactant and solvent, wherein the solvent is a 1:1 volume ratio of ethanol / water mixture.

[0112] Step S200 specifically includes:

[0113] Step S201: Immerse the substrate 10 in the sealing liquid at 50°C for 8 minutes, and control the vacuum pressure to ≤10⁻² Pa for vacuum-assisted impregnation;

[0114] Step S202: Bake at 135℃ for 45 minutes to form a sealed pore layer 20, controlling the porosity to ≤2%.

[0115] Step S300: A second insulating layer 21 is formed on the first side of the substrate 10 using a magnetron sputtering method.

[0116] The magnetron sputtering method specifically includes: using alumina (Al2O3) with a purity ≥99.99% and a thickness of 7μm as the target material, and performing magnetron sputtering under Ar / N2 mixed gas conditions, controlling the power at 1000 W and the substrate temperature at ≤150℃; the breakdown field strength of the second insulating layer 21 needs to be controlled to be ≥10 MV / cm and the surface roughness Ra≤0.1μm.

[0117] Step S400: After forming a micro heat dissipation structure on the second side of the substrate 10, a packaging substrate is obtained. Specifically, the micro heat dissipation structure adopts a grooved mesh structure 42 with a depth of 50-300μm, a width of 50-150μm, and a mesh density of 10-50 lines / cm. The grooved mesh structure 42 is formed by laser processing technology. The laser processing technology includes controlling the wavelength at 355nm, the power at 35W, and the scanning speed at 350mm / s for laser processing. During laser processing, the structural size error is controlled to be ≤±5μm.

[0118] Step S500: Form an RDL wiring layer 30 on the second insulating layer 21. The RDL wiring layer 30 adopts an electroplated copper seed layer and controls the line width / line spacing to be ≤5μm. The bonding force between the RDL wiring layer 30 and the second insulating layer 21 is ≥50MPa. Example 3

[0119] A high thermal conductivity fan-out type packaging substrate is prepared by the following process:

[0120] Step S100: Perform micro-arc oxidation treatment on the first side of the substrate 10 to form a first insulating layer 11. The micro-arc oxidation electrolyte includes: 20 g / L sodium silicate, 10 g / L sodium phosphate and deionized water, and control the pH of the micro-arc oxidation electrolyte to 10. The micro-arc oxidation treatment process conditions are: voltage 550V, pulse frequency 400Hz, pulse duty cycle 35%, and treatment time 25min. After micro-arc oxidation treatment, the thickness of the first insulating layer 11 needs to be controlled to be ≥20μm, the porosity ≤15%, and the breakdown voltage ≥700V.

[0121] Step S200: The substrate 10 is immersed in a sealing liquid and subjected to low-temperature sealing treatment at 50°C to form a sealed pore layer 20. The sealing liquid includes: 10wt% silane coupling agent, 2.5wt% nano silica, 0.4wt% fluorocarbon surfactant and solvent, wherein the solvent is an ethanol / water mixture with a volume ratio of 1:1.

[0122] Step S200 specifically includes:

[0123] Step S201: Immerse the substrate 10 in the sealing liquid at 50°C for 8 minutes, and control the vacuum pressure to ≤10⁻² Pa for vacuum-assisted impregnation;

[0124] Step S202: Bake at 140℃ for 40 minutes to form a sealed pore layer 20, controlling the porosity to ≤2%.

[0125] Step S300: A second insulating layer 21 is formed on the first side of the substrate 10 using a magnetron sputtering method.

[0126] The magnetron sputtering method specifically includes: using alumina (Al2O3) with a purity ≥99.99% and a thickness of 7μm as the target material, and performing magnetron sputtering under Ar / N2 mixed gas conditions, controlling the power at 2000 W and the substrate temperature at ≤150℃; the breakdown field strength of the second insulating layer 21 needs to be controlled to be ≥10 MV / cm and the surface roughness Ra≤0.1μm.

[0127] Step S400: After forming a micro heat dissipation structure on the second side of the substrate 10, a packaging substrate is obtained. Specifically, the micro heat dissipation structure adopts a grooved mesh structure 42 with a depth of 50-300μm, a width of 50-150μm, and a mesh density of 10-50 lines / cm. The grooved mesh structure 42 is formed by laser processing technology. The laser processing technology includes controlling the wavelength at 355nm, the power at 35W, and the scanning speed at 350mm / s for laser processing. During laser processing, the structural size error is controlled to be ≤±5μm.

[0128] Step S500: Form an RDL wiring layer 30 on the second insulating layer 21. The RDL wiring layer 30 adopts an electroplated copper seed layer and controls the line width / line spacing to be ≤5μm. The bonding force between the RDL wiring layer 30 and the second insulating layer 21 is ≥50MPa. Example 4

[0129] A high thermal conductivity fan-out type packaging substrate is prepared by the following process:

[0130] Step S100: Perform micro-arc oxidation treatment on the first side of the substrate 10 to form a first insulating layer 11. The micro-arc oxidation electrolyte includes: 20 g / L sodium silicate, 10 g / L sodium phosphate and deionized water, and control the pH of the micro-arc oxidation electrolyte to 11. The micro-arc oxidation treatment process conditions are: voltage 600V, pulse frequency 500Hz, pulse duty cycle 40%, and treatment time 10min. After micro-arc oxidation treatment, the thickness of the first insulating layer 11 needs to be controlled to be ≥20μm, the porosity ≤15%, and the breakdown voltage ≥700V.

[0131] Step S200: The substrate 10 is immersed in a sealing liquid and subjected to low-temperature sealing treatment at 60°C to form a sealed pore layer 20. The sealing liquid includes: 10wt% silane coupling agent, 3wt% nano silica, 0.5wt% fluorocarbon surfactant and solvent, wherein the solvent is a 1:1 volume ratio of ethanol / water mixture.

[0132] Step S200 specifically includes:

[0133] Step S201: Immerse the substrate 10 in the sealing liquid at 60°C for 5 minutes, and control the vacuum pressure to ≤10⁻² Pa for vacuum-assisted impregnation;

[0134] Step S202: Bake at 150℃ for 30 minutes to form a sealed pore layer 20, controlling the porosity to ≤2%.

[0135] Step S300: A second insulating layer 21 is formed on the first side of the substrate 10 using an atomic layer deposition method.

[0136] The atomic layer deposition method specifically includes: deposition using trimethylaluminum and H2O precursors at a temperature of 80°C.

[0137] Step S400: After forming a micro heat dissipation structure on the second side of the substrate 10, a packaging substrate is obtained. Specifically, the micro heat dissipation structure adopts a micropore array structure 43. The pore diameter of the micropore array structure 43 is 20-100μm, the pore depth is 50-200μm, and the porosity is 30-60%. The micropore array structure 43 is formed by imprinting. The imprinting process includes: controlling the pressure to 100 MPa, the temperature to 200℃, and the holding time to 3 min by imprinting with an imprinting mold. The imprinting mold is preferably made of hard alloy or ceramic with a temperature resistance of >300℃.

[0138] Step S500: Form an RDL wiring layer 30 on the second insulating layer 21. The RDL wiring layer 30 adopts an electroplated copper seed layer and controls the line width / line spacing to be ≤5μm. The bonding force between the RDL wiring layer 30 and the second insulating layer 21 is ≥50MPa. Example 5

[0139] A high thermal conductivity fan-out type packaging substrate is prepared by the following process:

[0140] Step S100: Perform micro-arc oxidation treatment on the first side of the substrate 10 to form a first insulating layer 11. The micro-arc oxidation electrolyte includes: 15 g / L sodium silicate, 10 g / L sodium phosphate and deionized water, and control the pH of the micro-arc oxidation electrolyte to be 10. The micro-arc oxidation treatment process conditions are: voltage 550V, pulse frequency 400Hz, pulse duty cycle 35%, and treatment time 15min. After micro-arc oxidation treatment, the thickness of the first insulating layer 11 needs to be controlled to be ≥20μm, the porosity ≤15%, and the breakdown voltage ≥700V.

[0141] Step S200: The substrate 10 is immersed in a sealing liquid and subjected to low-temperature sealing treatment at 50°C to form a sealed pore layer 20. The sealing liquid includes: 8 wt% silane coupling agent, 2.5 wt% nano silica, 0.4 wt% fluorocarbon surfactant and solvent, wherein the solvent is a 1:1 volume ratio of ethanol / water mixture.

[0142] Step S200 specifically includes:

[0143] Step S201: Immerse the substrate 10 in the sealing liquid at 50°C for 8 minutes, and control the vacuum pressure to ≤10⁻² Pa for vacuum-assisted impregnation;

[0144] Step S202: Bake at 140℃ for 40 minutes to form a sealed pore layer 20, controlling the porosity to ≤2%.

[0145] Step S300: A second insulating layer 21 is formed on the first side of the substrate 10 using an atomic layer deposition method.

[0146] The atomic layer deposition method specifically includes: deposition using trimethylaluminum and H2O precursors at a temperature of 120°C.

[0147] Step S400: After forming a micro heat dissipation structure on the second side of the substrate 10, a packaging substrate is obtained. Specifically, the micro heat dissipation structure adopts a fluid biomimetic structure 44, which includes a leaf vein-like structure. The fluid biomimetic structure 44 is formed by a chemical etching process. The chemical etching process includes etching with an etching solution at a temperature of 35°C and an etching rate of 7 μm / min for 10 min. The etching solution includes 15% hydrochloric acid, 8% nitric acid and 0.4% benzotriazole.

[0148] Step S500: Form an RDL wiring layer 30 on the second insulating layer 21. The RDL wiring layer 30 adopts an electroplated copper seed layer and controls the line width / line spacing to be ≤5μm. The bonding force between the RDL wiring layer 30 and the second insulating layer 21 is ≥50MPa. Example 6

[0149] A high thermal conductivity fan-out type packaging substrate is prepared by the following process:

[0150] Step S100: Perform micro-arc oxidation treatment on the first side of the substrate 10 to form a first insulating layer 11. The micro-arc oxidation electrolyte includes: 18 g / L sodium silicate, 8 g / L sodium phosphate and deionized water, and control the pH of the micro-arc oxidation electrolyte to be 10. The micro-arc oxidation treatment process conditions are: voltage 550V, pulse frequency 400Hz, pulse duty cycle 35%, and treatment time 15min. After micro-arc oxidation treatment, the thickness of the first insulating layer 11 needs to be controlled to be ≥20μm, the porosity ≤15%, and the breakdown voltage ≥700V.

[0151] Step S200: The substrate 10 is immersed in a sealing liquid and subjected to low-temperature sealing treatment at 55°C to form a sealed pore layer 20. The sealing liquid includes: 10wt% silane coupling agent, 2.5wt% nano silica, 0.2wt% fluorocarbon surfactant and solvent, wherein the solvent is an ethanol / water mixture with a volume ratio of 1:1.

[0152] Step S200 specifically includes:

[0153] Step S201: Immerse the substrate 10 in the sealing liquid at 55°C for 6 minutes, and control the vacuum pressure to ≤10⁻² Pa for vacuum-assisted impregnation;

[0154] Step S202: Bake at 138℃ for 35 minutes to form a sealed pore layer 20, controlling the porosity to ≤2%.

[0155] Step S300: A second insulating layer 21 is formed on the first side of the substrate 10 using an atomic layer deposition method.

[0156] The atomic layer deposition method specifically includes: deposition using trimethylaluminum and H2O precursors at a temperature of 100°C.

[0157] Step S400: After forming a micro heat dissipation structure on the second side of the substrate 10, a packaging substrate is obtained. Specifically, the micro heat dissipation structure adopts a grooved mesh structure 42. The grooved mesh structure 42 has a depth of 50-300μm, a width of 50-150μm, and a mesh density of 10-50 lines / cm. The grooved mesh structure 42 is formed by chemical etching process. The chemical etching process includes etching with etching solution for 5 minutes at a temperature of 25℃ and an etching rate of 5 μm / min. The etching solution includes 10% hydrochloric acid, 10% nitric acid, and 0.1% benzotriazole.

[0158] Step S500: Form an RDL wiring layer 30 on the second insulating layer 21. The RDL wiring layer 30 adopts an electroplated copper seed layer and controls the line width / line spacing to be ≤5μm. The bonding force between the RDL wiring layer 30 and the second insulating layer 21 is ≥50MPa.

[0159] The high thermal conductivity fan-out package substrates of the above embodiments were tested for bending strength according to ASTM C1341 standard, thermal performance according to JEDEC JESD51 standard, and breakdown voltage according to ASTM D149 standard.

[0160]

[0161] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention. These are all equivalent modifications and improvements made to the above embodiments based on the essential technology of the present invention, and all of these fall within the protection scope of the present invention.

Claims

1. A fabrication process for a high thermal conductivity fan-out type packaging substrate, characterized in that, include: Step S100: Perform micro-arc oxidation treatment on the first side of the substrate to form a first insulating layer; Step S200: Immerse the substrate in the sealing liquid and perform low-temperature sealing treatment at a temperature of 40-60°C to form a sealed pore layer; Step S300: Form a second insulating layer on the first side of the substrate using a magnetron sputtering method and / or an atomic layer deposition method; Step S400: After forming a micro heat dissipation structure on the second side of the substrate, a packaging substrate is obtained. In step S200, the sealing liquid includes: 5-10 wt% silane coupling agent, 1-3 wt% nano silica, 0.1-0.5 wt% fluorocarbon surfactant and solvent, wherein the solvent is an ethanol / water mixture with a volume ratio of 1:

1. Step S200 specifically includes: Step S201: Immerse the substrate in the sealing liquid at a temperature of 40-60℃ for 5-10 minutes, and control the vacuum pressure to ≤10⁻² Pa for vacuum-assisted impregnation; Step S202: Bake at 120-150℃ for 30-60 minutes to form a sealed pore layer, controlling the porosity to ≤2%.

2. The fabrication process of the high thermal conductivity fan-out type packaging substrate according to claim 1, characterized in that, In step S100, micro-arc oxidation treatment is performed in a micro-arc oxidation electrolyte, which includes: 10-20 g / L sodium silicate, 5-10 g / L sodium phosphate, and deionized water. The micro-arc oxidation process conditions are: voltage 400-600V, pulse frequency 100-500Hz, pulse duty cycle 20-40%, and processing time 10-30min. The thickness of the first insulating layer is ≥20μm, the porosity is ≤15%, and the breakdown voltage is ≥700V.

3. The fabrication process of the high thermal conductivity fan-out type packaging substrate according to claim 1, characterized in that, The magnetron sputtering method in step S300 specifically includes: Silicon nitride with a purity ≥99.99% and a thickness of 5-10 μm was used as the target material, and magnetron sputtering was performed under Ar / N2 mixed gas conditions, with a controlled power of 500-2000 W and a substrate temperature ≤150℃; or, Alumina with a purity of ≥99.99% and a thickness of 5-10 μm was used as the target material, and magnetron sputtering was performed under Ar atmosphere conditions with a power of 500-2000 W and a substrate temperature of ≤150℃.

4. The fabrication process of the high thermal conductivity fan-out type packaging substrate according to claim 1, characterized in that, The atomic layer deposition method in step S300 specifically includes: Deposition was carried out using trimethylaluminum and H2O precursors at temperatures of 80-120℃.

5. The fabrication process of the high thermal conductivity fan-out type packaging substrate according to claim 3 or 4, characterized in that, The second insulating layer has a breakdown field strength ≥ 10 MV / cm and a surface roughness Ra ≤ 0.1μm.

6. The fabrication process of the high thermal conductivity fan-out type packaging substrate according to claim 1, characterized in that, The micro heat dissipation structure includes one or more of the following: fin array structure, grooved mesh structure, microporous array structure, and fluid biomimetic structure; The fin array structure includes a plurality of fins arranged in parallel and / or radial patterns, wherein the fin height is 100-500 μm and the spacing is 50-200 μm; The grooved mesh structure has a depth of 50-300μm, a width of 50-150μm, and a mesh density of 10-50 lines / cm; The microporous array structure has a pore size of 20-100 μm, a pore depth of 50-200 μm, and a porosity of 30-60%. The fluid biomimetic structure includes a leaf vein-like structure or a shark skin-like texture structure.

7. The fabrication process of the high thermal conductivity fan-out type packaging substrate according to claim 6, characterized in that, The process for forming the micro heat dissipation structure includes: chemical etching process, laser processing process and imprinting process; The chemical etching process includes etching with an etching solution at a temperature of 25-40℃ and an etching rate of 5-10 μm / min for 5-15 minutes, wherein the etching solution includes 10-20% hydrochloric acid, 5-10% nitric acid and 0.1-0.5% benzotriazole. The laser processing technology includes: controlling the wavelength to be 355nm, the power to be 10-50W, and the scanning speed to be 100-500 mm / s for laser processing, and controlling the structural size error to be ≤±5μm during laser processing; The embossing process includes: embossing with an embossing mold while controlling the pressure to 50-200 MPa, the temperature to 150-250℃, and the holding time to 1-5 minutes.

8. The fabrication process of the high thermal conductivity fan-out type packaging substrate according to claim 1, characterized in that, It also includes: step S500, forming an RDL wiring layer on the second insulating layer.

9. The fabrication process of the high thermal conductivity fan-out type packaging substrate according to claim 8, characterized in that, The RDL wiring layer is made of electroplated copper or copper / titanium seed layer, and the line width / line spacing is controlled to be ≤5μm, and the bonding force between the RDL wiring layer and the second insulating layer is ≥50 MPa.

10. A high thermal conductivity fan-out type packaging substrate, characterized in that, Made by the preparation process described in any one of claims 1-9.

11. The application of the high thermal conductivity fan-out packaging substrate as described in claim 10 in semiconductor packaging.

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